xref: /original-bsd/sys/vax/include/mtpr.h (revision 5f783fcb)
1 /*-
2  * Copyright (c) 1982, 1986, 1988 The Regents of the University of California.
3  * All rights reserved.
4  *
5  * %sccs.include.proprietary.c%
6  *
7  *	@(#)mtpr.h	7.7 (Berkeley) 02/20/92
8  */
9 #ifndef _MTPR_H_
10 #define _MTPR_H_
11 
12 /*
13  * VAX processor register numbers
14  */
15 
16 #define	KSP	0x0		/* kernel stack pointer */
17 #define	ESP	0x1		/* exec stack pointer */
18 #define	SSP	0x2		/* supervisor stack pointer */
19 #define	USP	0x3		/* user stack pointer */
20 #define	ISP	0x4		/* interrupt stack pointer */
21 #define	P0BR	0x8		/* p0 base register */
22 #define	P0LR	0x9		/* p0 length register */
23 #define	P1BR	0xa		/* p1 base register */
24 #define	P1LR	0xb		/* p1 length register */
25 #define	SBR	0xc		/* system segment base register */
26 #define	SLR	0xd		/* system segment length register */
27 #define	PCBB	0x10		/* process control block base */
28 #define	SCBB	0x11		/* system control block base */
29 #define	IPL	0x12		/* interrupt priority level */
30 #define	ASTLVL	0x13		/* async. system trap level */
31 #define	SIRR	0x14		/* software interrupt request */
32 #define	SISR	0x15		/* software interrupt summary */
33 #if VAX8200
34 #define	IPIR	0x16		/* interprocessor interrupt register */
35 #endif
36 #if VAX750 || VAX730
37 #define	MCSR	0x17		/* machine check status register */
38 #endif
39 #define	ICCS	0x18		/* interval clock control */
40 #define	NICR	0x19		/* next interval count */
41 #define	ICR	0x1a		/* interval count */
42 #if VAX8600 || VAX8200 || VAX780 || VAX750 || VAX730 || VAX650
43 #define	TODR	0x1b		/* time of year (day) */
44 #endif
45 #if VAX750 || VAX730
46 #define	CSRS	0x1c		/* console storage receive status register */
47 #define	CSRD	0x1d		/* console storage receive data register */
48 #define	CSTS	0x1e		/* console storage transmit status register */
49 #define	CSTD	0x1f		/* console storage transmit data register */
50 #endif
51 #define	RXCS	0x20		/* console receiver control and status */
52 #define	RXDB	0x21		/* console receiver data buffer */
53 #define	TXCS	0x22		/* console transmitter control and status */
54 #define	TXDB	0x23		/* console transmitter data buffer */
55 #if VAX8200 || VAX750 || VAX730 || VAX650
56 #define	TBDR	0x24		/* translation buffer disable register */
57 #define	CADR	0x25		/* cache disable register */
58 #endif
59 #if VAX8200 || VAX750 || VAX730
60 #define	MCESR	0x26		/* machine check error summary register */
61 #endif
62 #if VAX750 || VAX730 || VAX650
63 #define	CAER	0x27		/* cache error */
64 #endif
65 #define	ACCS	0x28		/* accelerator control and status */
66 #if VAX780
67 #define	ACCR	0x29		/* accelerator maintenance */
68 #endif
69 #if VAX8200 || VAX780
70 #define	WCSA	0x2c		/* WCS address */
71 #define	WCSD	0x2d		/* WCS data */
72 #endif
73 #if VAX8200
74 #define	WCSL	0x2e		/* WCS load */
75 #endif
76 #if VAX8600 || VAX780
77 #define	SBIFS	0x30		/* SBI fault and status */
78 #define	SBIS	0x31		/* SBI silo */
79 #define	SBISC	0x32		/* SBI silo comparator */
80 #define	SBIMT	0x33		/* SBI maintenance */
81 #define	SBIER	0x34		/* SBI error register */
82 #define	SBITA	0x35		/* SBI timeout address */
83 #define	SBIQC	0x36		/* SBI quadword clear */
84 #endif
85 #if VAX750 || VAX730 || VAX630 || VAX650
86 #define	IUR	0x37		/* init unibus (Qbus on 6x0) register */
87 #endif
88 #define	MAPEN	0x38		/* memory management enable */
89 #define	TBIA	0x39		/* translation buffer invalidate all */
90 #define	TBIS	0x3a		/* translation buffer invalidate single */
91 #if VAX750 || VAX730
92 #define	TB	0x3b		/* translation buffer */
93 #endif
94 #if VAX780
95 #define	MBRK	0x3c		/* micro-program breakpoint */
96 #endif
97 #define	PMR	0x3d		/* performance monitor enable */
98 #define	SID	0x3e		/* system identification */
99 #if VAX8600 || VAX8200 || VAX650
100 #define TBCHK	0x3f		/* Translation Buffer Check */
101 #endif
102 #if VAX8600
103 #define PAMACC	0x40		/* PAMM access */
104 #define PAMLOC	0x41		/* PAMM location */
105 #define CSWP	0x42		/* Cache sweep */
106 #define MDECC	0x43		/* MBOX data ecc register */
107 #define MENA	0x44		/* MBOX error enable register */
108 #define MDCTL	0x45		/* MBOX data control register */
109 #define MCCTL	0x46		/* MBOX mcc control register */
110 #define MERG	0x47		/* MBOX	error generator register */
111 #define CRBT	0x48		/* Console reboot */
112 #define DFI	0x49		/* Diag fault insertion register */
113 #define EHSR	0x4a		/* Error handling status register */
114 #define STXCS	0x4c		/* Console block storage C/S */
115 #define STXDB	0x4d		/* Console block storage D/B */
116 #define ESPA	0x4e		/* EBOX scratchpad address */
117 #define ESPD	0x4f		/* EBOX sratchpad data */
118 #endif
119 #if VAX8200
120 #define	RXCS1	0x50		/* receive csr, console line 1 */
121 #define	RXDB1	0x51		/* receive data buffer, console line 1 */
122 #define	TXCS1	0x52		/* transmit csr, console line 1 */
123 #define	TXDB1	0x53		/* transmit data buffer, console line 1 */
124 #define	RXCS2	0x54		/* etc */
125 #define	RXDB2	0x55
126 #define	TXCS2	0x56
127 #define	TXDB2	0x57
128 #define	RXCS3	0x58
129 #define	RXDB3	0x59
130 #define	TXCS3	0x5a
131 #define	TXDB3	0x5b
132 #define	RXCD	0x5c		/* receive console data register */
133 #define	CACHEX	0x5d		/* cache invalidate register */
134 #define	BINID	0x5e		/* VAXBI node ID register */
135 #define	BISTOP	0x5f		/* VAXBI stop register */
136 #endif
137 #endif /*_MTPR_H_*/
138