1 /* $OpenBSD: if_ocereg.h,v 1.8 2022/01/09 05:42:54 jsg Exp $ */ 2 3 /*- 4 * Copyright (C) 2012 Emulex 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Emulex Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * Contact Information: 34 * freebsd-drivers@emulex.com 35 * 36 * Emulex 37 * 3333 Susan Street 38 * Costa Mesa, CA 92626 39 */ 40 41 #define OCE_BAR_CFG 0x10 42 #define OCE_BAR_CFG_BE2 0x14 43 #define OCE_BAR_CSR 0x18 44 #define OCE_BAR_DB 0x20 45 46 /* MPU semaphore */ 47 #define MPU_EP_SEM_BE 0x0ac 48 #define MPU_EP_SEM_XE201 0x400 49 #define MPU_EP_SEMAPHORE(sc) \ 50 ((IS_BE(sc)) ? MPU_EP_SEM_BE : MPU_EP_SEM_XE201) 51 #define MPU_EP_SEM_STAGE_MASK 0xffff 52 #define MPU_EP_SEM_ERROR (1<<31) 53 54 #define PCI_INTR_CTRL 0xfc 55 #define HOSTINTR_MASK (1<<29) 56 57 /* POST status reg struct */ 58 #define POST_STAGE_POWER_ON_RESET 0x00 59 #define POST_STAGE_AWAITING_HOST_RDY 0x01 60 #define POST_STAGE_HOST_RDY 0x02 61 #define POST_STAGE_CHIP_RESET 0x03 62 #define POST_STAGE_ARMFW_READY 0xc000 63 #define POST_STAGE_ARMFW_UE 0xf000 64 65 /* DOORBELL registers */ 66 #define PD_TXULP_DB 0x0060 67 #define PD_RXULP_DB 0x0100 68 #define PD_CQ_DB 0x0120 69 #define PD_EQ_DB 0x0120 /* same as CQ */ 70 #define PD_EQ_DB_EVENT (1<<10) 71 #define PD_MQ_DB 0x0140 72 #define PD_MPU_MBOX_DB 0x0160 73 74 /* Hardware Address types */ 75 #define MAC_ADDRESS_TYPE_STORAGE 0x0 /* (Storage MAC Address) */ 76 #define MAC_ADDRESS_TYPE_NETWORK 0x1 /* (Network MAC Address) */ 77 #define MAC_ADDRESS_TYPE_PD 0x2 /* (Protection Domain MAC Addr) */ 78 #define MAC_ADDRESS_TYPE_MANAGEMENT 0x3 /* (Management MAC Address) */ 79 #define MAC_ADDRESS_TYPE_FCOE 0x4 /* (FCoE MAC Address) */ 80 81 /* CREATE_IFACE capability and cap_en flags */ 82 #define MBX_RX_IFACE_RSS 0x000004 83 #define MBX_RX_IFACE_PROMISC 0x000008 84 #define MBX_RX_IFACE_BROADCAST 0x000010 85 #define MBX_RX_IFACE_UNTAGGED 0x000020 86 #define MBX_RX_IFACE_VLAN_PROMISC 0x000080 87 #define MBX_RX_IFACE_VLAN 0x000100 88 #define MBX_RX_IFACE_MCAST_PROMISC 0x000200 89 #define MBX_RX_IFACE_PASS_L2_ERR 0x000400 90 #define MBX_RX_IFACE_PASS_L3L4_ERR 0x000800 91 #define MBX_RX_IFACE_MCAST 0x001000 92 #define MBX_RX_IFACE_MCAST_HASH 0x002000 93 #define MBX_RX_IFACE_HDS 0x004000 94 #define MBX_RX_IFACE_DIRECTED 0x008000 95 #define MBX_RX_IFACE_VMQ 0x010000 96 #define MBX_RX_IFACE_NETQ 0x020000 97 #define MBX_RX_IFACE_QGROUPS 0x040000 98 #define MBX_RX_IFACE_LSO 0x080000 99 #define MBX_RX_IFACE_LRO 0x100000 100 101 #define ASYNC_EVENT_CODE_LINK_STATE 0x1 102 #define ASYNC_EVENT_LINK_UP 0x1 103 #define ASYNC_EVENT_LINK_DOWN 0x0 104 #define ASYNC_EVENT_GRP5 0x5 105 #define ASYNC_EVENT_PVID_STATE 0x3 106 #define VLAN_VID_MASK 0x0FFF 107 108 /* port link_status */ 109 #define ASYNC_EVENT_LOGICAL 0x02 110 111 /* Logical Link Status */ 112 #define NTWK_LOGICAL_LINK_DOWN 0 113 #define NTWK_LOGICAL_LINK_UP 1 114 115 /* max SGE per mbx */ 116 #define MAX_MBX_SGE 19 117 118 /* Max multicast filter size */ 119 #define OCE_MAX_MC_FILTER_SIZE 32 120 121 /* PCI SLI (Service Level Interface) capabilities register */ 122 #define OCE_INTF_REG_OFFSET 0x58 123 #define OCE_INTF_VALID_SIG 6 /* register's signature */ 124 #define OCE_INTF_FUNC_RESET_REQD 1 125 #define OCE_INTF_HINT1_NOHINT 0 126 #define OCE_INTF_HINT1_SEMAINIT 1 127 #define OCE_INTF_HINT1_STATCTRL 2 128 #define OCE_INTF_IF_TYPE_0 0 129 #define OCE_INTF_IF_TYPE_1 1 130 #define OCE_INTF_IF_TYPE_2 2 131 #define OCE_INTF_IF_TYPE_3 3 132 #define OCE_INTF_SLI_REV3 3 /* not supported by driver */ 133 #define OCE_INTF_SLI_REV4 4 /* driver supports SLI-4 */ 134 #define OCE_INTF_PHYS_FUNC 0 135 #define OCE_INTF_VIRT_FUNC 1 136 #define OCE_INTF_FAMILY_BE2 0 /* not supported by driver */ 137 #define OCE_INTF_FAMILY_BE3 1 /* driver supports BE3 */ 138 #define OCE_INTF_FAMILY_A0_CHIP 0xA /* Lancer A0 chip (supported) */ 139 #define OCE_INTF_FAMILY_B0_CHIP 0xB /* Lancer B0 chip (future) */ 140 141 #define NIC_WQE_SIZE 16 142 143 #define NIC_WQ_TYPE_FORWARDING 0x01 144 #define NIC_WQ_TYPE_STANDARD 0x02 145 #define NIC_WQ_TYPE_LOW_LATENCY 0x04 146 147 #define OCE_TXP_SW_SZ 48 148 149 #define OCE_SLI_FUNCTION(reg) ((reg) & 0x1) 150 #define OCE_SLI_REVISION(reg) (((reg) >> 4) & 0xf) 151 #define OCE_SLI_FAMILY(reg) (((reg) >> 8) & 0xf) 152 #define OCE_SLI_IFTYPE(reg) (((reg) >> 12) & 0xf) 153 #define OCE_SLI_HINT1(reg) (((reg) >> 16) & 0xff) 154 #define OCE_SLI_HINT2(reg) (((reg) >> 24) & 0x1f) 155 #define OCE_SLI_SIGNATURE(reg) (((reg) >> 29) & 0x7) 156 157 #define PD_MPU_MBOX_DB_READY (1<<0) 158 #define PD_MPU_MBOX_DB_HI (1<<1) 159 #define PD_MPU_MBOX_DB_ADDR_SHIFT 2 160 161 struct oce_pa { 162 uint64_t addr; 163 } __packed; 164 165 struct oce_sge { 166 uint64_t addr; 167 uint32_t length; 168 } __packed; 169 170 struct mbx_hdr { 171 uint8_t opcode; 172 uint8_t subsys; 173 uint8_t port; 174 uint8_t domain; 175 uint32_t timeout; 176 uint32_t length; 177 uint8_t version; 178 #define OCE_MBX_VER_V2 0x0002 179 #define OCE_MBX_VER_V1 0x0001 180 #define OCE_MBX_VER_V0 0x0000 181 uint8_t _rsvd[3]; 182 } __packed; 183 184 /* payload can contain an SGL or an embedded array of upto 59 dwords */ 185 #define OCE_MBX_PAYLOAD (59 * 4) 186 187 struct oce_mbx { 188 uint32_t flags; 189 #define OCE_MBX_F_EMBED (1<<0) 190 #define OCE_MBX_F_SGE (1<<3) 191 uint32_t payload_length; 192 uint32_t tag[2]; 193 uint32_t _rsvd; 194 union { 195 struct oce_sge sgl[MAX_MBX_SGE]; 196 uint8_t data[OCE_MBX_PAYLOAD]; 197 } pld; 198 } __packed; 199 200 /* completion queue entry for MQ */ 201 struct oce_mq_cqe { 202 union { 203 struct { 204 #if _BYTE_ORDER == BIG_ENDIAN 205 /* dw0 */ 206 uint32_t extended_status:16; 207 uint32_t completion_status:16; 208 /* dw1 dw2 */ 209 uint32_t mq_tag[2]; 210 /* dw3 */ 211 uint32_t valid:1; 212 uint32_t async_event:1; 213 uint32_t hpi_buffer_cmpl:1; 214 uint32_t completed:1; 215 uint32_t consumed:1; 216 uint32_t rsvd0:3; 217 uint32_t async_type:8; 218 uint32_t event_type:8; 219 uint32_t rsvd1:8; 220 #else 221 /* dw0 */ 222 uint32_t completion_status:16; 223 uint32_t extended_status:16; 224 /* dw1 dw2 */ 225 uint32_t mq_tag[2]; 226 /* dw3 */ 227 uint32_t rsvd1:8; 228 uint32_t event_type:8; 229 uint32_t async_type:8; 230 uint32_t rsvd0:3; 231 uint32_t consumed:1; 232 uint32_t completed:1; 233 uint32_t hpi_buffer_cmpl:1; 234 uint32_t async_event:1; 235 uint32_t valid:1; 236 #endif 237 } s; 238 uint32_t dw[4]; 239 } u0; 240 } __packed; 241 242 #define MQ_CQE_VALID(_cqe) ((_cqe)->u0.dw[3]) 243 #define MQ_CQE_INVALIDATE(_cqe) ((_cqe)->u0.dw[3] = 0) 244 245 /* Mailbox Completion Status Codes */ 246 enum MBX_COMPLETION_STATUS { 247 MBX_CQE_STATUS_SUCCESS = 0x00, 248 MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 0x01, 249 MBX_CQE_STATUS_INVALID_PARAMETER = 0x02, 250 MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 0x03, 251 MBX_CQE_STATUS_QUEUE_FLUSHING = 0x04, 252 MBX_CQE_STATUS_DMA_FAILED = 0x05 253 }; 254 255 struct oce_async_cqe_link_state { 256 union { 257 struct { 258 #if _BYTE_ORDER == BIG_ENDIAN 259 /* dw0 */ 260 uint8_t speed; 261 uint8_t duplex; 262 uint8_t link_status; 263 uint8_t phy_port; 264 /* dw1 */ 265 uint16_t qos_link_speed; 266 uint8_t rsvd0; 267 uint8_t fault; 268 /* dw2 */ 269 uint32_t event_tag; 270 /* dw3 */ 271 uint32_t valid:1; 272 uint32_t async_event:1; 273 uint32_t rsvd2:6; 274 uint32_t event_type:8; 275 uint32_t event_code:8; 276 uint32_t rsvd1:8; 277 #else 278 /* dw0 */ 279 uint8_t phy_port; 280 uint8_t link_status; 281 uint8_t duplex; 282 uint8_t speed; 283 /* dw1 */ 284 uint8_t fault; 285 uint8_t rsvd0; 286 uint16_t qos_link_speed; 287 /* dw2 */ 288 uint32_t event_tag; 289 /* dw3 */ 290 uint32_t rsvd1:8; 291 uint32_t event_code:8; 292 uint32_t event_type:8; 293 uint32_t rsvd2:6; 294 uint32_t async_event:1; 295 uint32_t valid:1; 296 #endif 297 } s; 298 uint32_t dw[4]; 299 } u0; 300 } __packed; 301 302 /* PVID aync event */ 303 struct oce_async_event_grp5_pvid_state { 304 uint8_t enabled; 305 uint8_t rsvd0; 306 uint16_t tag; 307 uint32_t event_tag; 308 uint32_t rsvd1; 309 uint32_t code; 310 } __packed; 311 312 union oce_mq_ext_ctx { 313 uint32_t dw[6]; 314 struct { 315 #if _BYTE_ORDER == BIG_ENDIAN 316 /* dw0 */ 317 uint32_t dw4rsvd1:16; 318 uint32_t num_pages:16; 319 /* dw1 */ 320 uint32_t async_evt_bitmap; 321 /* dw2 */ 322 uint32_t cq_id:10; 323 uint32_t dw5rsvd2:2; 324 uint32_t ring_size:4; 325 uint32_t dw5rsvd1:16; 326 /* dw3 */ 327 uint32_t valid:1; 328 uint32_t dw6rsvd1:31; 329 /* dw4 */ 330 uint32_t dw7rsvd1:21; 331 uint32_t async_cq_id:10; 332 uint32_t async_cq_valid:1; 333 #else 334 /* dw0 */ 335 uint32_t num_pages:16; 336 uint32_t dw4rsvd1:16; 337 /* dw1 */ 338 uint32_t async_evt_bitmap; 339 /* dw2 */ 340 uint32_t dw5rsvd1:16; 341 uint32_t ring_size:4; 342 uint32_t dw5rsvd2:2; 343 uint32_t cq_id:10; 344 /* dw3 */ 345 uint32_t dw6rsvd1:31; 346 uint32_t valid:1; 347 /* dw4 */ 348 uint32_t async_cq_valid:1; 349 uint32_t async_cq_id:10; 350 uint32_t dw7rsvd1:21; 351 #endif 352 /* dw5 */ 353 uint32_t dw8rsvd1; 354 } v0; 355 } __packed; 356 357 /* MQ mailbox structure */ 358 struct oce_bmbx { 359 struct oce_mbx mbx; 360 struct oce_mq_cqe cqe; 361 } __packed; 362 363 /* MBXs sub system codes */ 364 enum SUBSYS_CODES { 365 SUBSYS_RSVD = 0, 366 SUBSYS_COMMON = 1, 367 SUBSYS_COMMON_ISCSI = 2, 368 SUBSYS_NIC = 3, 369 SUBSYS_TOE = 4, 370 SUBSYS_PXE_UNDI = 5, 371 SUBSYS_ISCSI_INI = 6, 372 SUBSYS_ISCSI_TGT = 7, 373 SUBSYS_MILI_PTL = 8, 374 SUBSYS_MILI_TMD = 9, 375 SUBSYS_RDMA = 10, 376 SUBSYS_LOWLEVEL = 11, 377 SUBSYS_LRO = 13, 378 SUBSYS_DCBX = 15, 379 SUBSYS_DIAG = 16, 380 SUBSYS_VENDOR = 17 381 }; 382 383 /* common ioctl opcodes */ 384 enum COMMON_SUBSYS_OPCODES { 385 /* These opcodes are common to both networking and storage PCI functions 386 * They are used to reserve resources and configure CNA. These opcodes 387 * all use the SUBSYS_COMMON subsystem code. 388 */ 389 OPCODE_COMMON_QUERY_IFACE_MAC = 1, 390 OPCODE_COMMON_SET_IFACE_MAC = 2, 391 OPCODE_COMMON_SET_IFACE_MULTICAST = 3, 392 OPCODE_COMMON_CONFIG_IFACE_VLAN = 4, 393 OPCODE_COMMON_QUERY_LINK_CONFIG = 5, 394 OPCODE_COMMON_READ_FLASHROM = 6, 395 OPCODE_COMMON_WRITE_FLASHROM = 7, 396 OPCODE_COMMON_QUERY_MAX_MBX_BUFFER_SIZE = 8, 397 OPCODE_COMMON_CREATE_CQ = 12, 398 OPCODE_COMMON_CREATE_EQ = 13, 399 OPCODE_COMMON_CREATE_MQ = 21, 400 OPCODE_COMMON_GET_QOS = 27, 401 OPCODE_COMMON_SET_QOS = 28, 402 OPCODE_COMMON_READ_EPROM = 30, 403 OPCODE_COMMON_GET_CNTL_ATTRIBUTES = 32, 404 OPCODE_COMMON_NOP = 33, 405 OPCODE_COMMON_SET_IFACE_RX_FILTER = 34, 406 OPCODE_COMMON_GET_FW_VERSION = 35, 407 OPCODE_COMMON_SET_FLOW_CONTROL = 36, 408 OPCODE_COMMON_GET_FLOW_CONTROL = 37, 409 OPCODE_COMMON_SET_FRAME_SIZE = 39, 410 OPCODE_COMMON_MODIFY_EQ_DELAY = 41, 411 OPCODE_COMMON_CREATE_IFACE = 50, 412 OPCODE_COMMON_DESTROY_IFACE = 51, 413 OPCODE_COMMON_MODIFY_MSI_MESSAGES = 52, 414 OPCODE_COMMON_DESTROY_MQ = 53, 415 OPCODE_COMMON_DESTROY_CQ = 54, 416 OPCODE_COMMON_DESTROY_EQ = 55, 417 OPCODE_COMMON_UPLOAD_TCP = 56, 418 OPCODE_COMMON_SET_NTWK_LINK_SPEED = 57, 419 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG = 58, 420 OPCODE_COMMON_ADD_IFACE_MAC = 59, 421 OPCODE_COMMON_DEL_IFACE_MAC = 60, 422 OPCODE_COMMON_FUNCTION_RESET = 61, 423 OPCODE_COMMON_SET_PHYSICAL_LINK_CONFIG = 62, 424 OPCODE_COMMON_GET_BOOT_CONFIG = 66, 425 OPCPDE_COMMON_SET_BOOT_CONFIG = 67, 426 OPCODE_COMMON_SET_BEACON_CONFIG = 69, 427 OPCODE_COMMON_GET_BEACON_CONFIG = 70, 428 OPCODE_COMMON_GET_PHYSICAL_LINK_CONFIG = 71, 429 OPCODE_COMMON_GET_OEM_ATTRIBUTES = 76, 430 OPCODE_COMMON_GET_PORT_NAME = 77, 431 OPCODE_COMMON_GET_CONFIG_SIGNATURE = 78, 432 OPCODE_COMMON_SET_CONFIG_SIGNATURE = 79, 433 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG = 80, 434 OPCODE_COMMON_GET_BE_CONFIGURATION_RESOURCES = 81, 435 OPCODE_COMMON_SET_BE_CONFIGURATION_RESOURCES = 82, 436 OPCODE_COMMON_GET_RESET_NEEDED = 84, 437 OPCODE_COMMON_GET_SERIAL_NUMBER = 85, 438 OPCODE_COMMON_GET_NCSI_CONFIG = 86, 439 OPCODE_COMMON_SET_NCSI_CONFIG = 87, 440 OPCODE_COMMON_CREATE_MQ_EXT = 90, 441 OPCODE_COMMON_SET_FUNCTION_PRIVILEGES = 100, 442 OPCODE_COMMON_SET_VF_PORT_TYPE = 101, 443 OPCODE_COMMON_GET_PHY_CONFIG = 102, 444 OPCODE_COMMON_SET_FUNCTIONAL_CAPS = 103, 445 OPCODE_COMMON_GET_ADAPTER_ID = 110, 446 OPCODE_COMMON_GET_UPGRADE_FEATURES = 111, 447 OPCODE_COMMON_GET_INSTALLED_FEATURES = 112, 448 OPCODE_COMMON_GET_AVAIL_PERSONALITIES = 113, 449 OPCODE_COMMON_GET_CONFIG_PERSONALITIES = 114, 450 OPCODE_COMMON_SEND_ACTIVATION = 115, 451 OPCODE_COMMON_RESET_LICENSES = 116, 452 OPCODE_COMMON_GET_CNTL_ADDL_ATTRIBUTES = 121, 453 OPCODE_COMMON_QUERY_TCB = 144, 454 OPCODE_COMMON_ADD_IFACE_QUEUE_FILTER = 145, 455 OPCODE_COMMON_DEL_IFACE_QUEUE_FILTER = 146, 456 OPCODE_COMMON_GET_IFACE_MAC_LIST = 147, 457 OPCODE_COMMON_SET_IFACE_MAC_LIST = 148, 458 OPCODE_COMMON_MODIFY_CQ = 149, 459 OPCODE_COMMON_GET_IFACE_VLAN_LIST = 150, 460 OPCODE_COMMON_SET_IFACE_VLAN_LIST = 151, 461 OPCODE_COMMON_GET_HSW_CONFIG = 152, 462 OPCODE_COMMON_SET_HSW_CONFIG = 153, 463 OPCODE_COMMON_GET_RESOURCE_EXTENT_INFO = 154, 464 OPCODE_COMMON_GET_ALLOCATED_RESOURCE_EXTENTS = 155, 465 OPCODE_COMMON_ALLOC_RESOURCE_EXTENTS = 156, 466 OPCODE_COMMON_DEALLOC_RESOURCE_EXTENTS = 157, 467 OPCODE_COMMON_SET_DIAG_REGISTERS = 158, 468 OPCODE_COMMON_GET_FUNCTION_CONFIG = 160, 469 OPCODE_COMMON_GET_PROFILE_CAPACITIES = 161, 470 OPCODE_COMMON_GET_MR_PROFILE_CAPACITIES = 162, 471 OPCODE_COMMON_SET_MR_PROFILE_CAPACITIES = 163, 472 OPCODE_COMMON_GET_PROFILE_CONFIG = 164, 473 OPCODE_COMMON_SET_PROFILE_CONFIG = 165, 474 OPCODE_COMMON_GET_PROFILE_LIST = 166, 475 OPCODE_COMMON_GET_ACTIVE_PROFILE = 167, 476 OPCODE_COMMON_SET_ACTIVE_PROFILE = 168, 477 OPCODE_COMMON_GET_FUNCTION_PRIVILEGES = 170, 478 OPCODE_COMMON_READ_OBJECT = 171, 479 OPCODE_COMMON_WRITE_OBJECT = 172 480 }; 481 482 /* [05] OPCODE_COMMON_QUERY_LINK_CONFIG */ 483 struct mbx_query_common_link_config { 484 struct mbx_hdr hdr; 485 union { 486 struct { 487 uint32_t rsvd0; 488 } req; 489 490 struct { 491 /* dw 0 */ 492 uint8_t physical_port; 493 uint8_t mac_duplex; 494 uint8_t mac_speed; 495 uint8_t mac_fault; 496 /* dw 1 */ 497 uint8_t mgmt_mac_duplex; 498 uint8_t mgmt_mac_speed; 499 uint16_t qos_link_speed; 500 uint32_t logical_link_status; 501 } rsp; 502 } params; 503 } __packed; 504 505 /* [57] OPCODE_COMMON_SET_LINK_SPEED */ 506 struct mbx_set_common_link_speed { 507 struct mbx_hdr hdr; 508 union { 509 struct { 510 #if _BYTE_ORDER == BIG_ENDIAN 511 uint8_t rsvd0; 512 uint8_t mac_speed; 513 uint8_t virtual_port; 514 uint8_t physical_port; 515 #else 516 uint8_t physical_port; 517 uint8_t virtual_port; 518 uint8_t mac_speed; 519 uint8_t rsvd0; 520 #endif 521 } req; 522 523 struct { 524 uint32_t rsvd0; 525 } rsp; 526 527 uint32_t dw; 528 } params; 529 } __packed; 530 531 struct mac_address_format { 532 uint16_t size_of_struct; 533 uint8_t mac_addr[6]; 534 } __packed; 535 536 /* [01] OPCODE_COMMON_QUERY_IFACE_MAC */ 537 struct mbx_query_common_iface_mac { 538 struct mbx_hdr hdr; 539 union { 540 struct { 541 #if _BYTE_ORDER == BIG_ENDIAN 542 uint16_t if_id; 543 uint8_t permanent; 544 uint8_t type; 545 #else 546 uint8_t type; 547 uint8_t permanent; 548 uint16_t if_id; 549 #endif 550 551 } req; 552 553 struct { 554 struct mac_address_format mac; 555 } rsp; 556 } params; 557 } __packed; 558 559 /* [02] OPCODE_COMMON_SET_IFACE_MAC */ 560 struct mbx_set_common_iface_mac { 561 struct mbx_hdr hdr; 562 union { 563 struct { 564 #if _BYTE_ORDER == BIG_ENDIAN 565 /* dw 0 */ 566 uint16_t if_id; 567 uint8_t invalidate; 568 uint8_t type; 569 #else 570 /* dw 0 */ 571 uint8_t type; 572 uint8_t invalidate; 573 uint16_t if_id; 574 #endif 575 /* dw 1 */ 576 struct mac_address_format mac; 577 } req; 578 579 struct { 580 uint32_t rsvd0; 581 } rsp; 582 583 uint32_t dw[2]; 584 } params; 585 } __packed; 586 587 /* [03] OPCODE_COMMON_SET_IFACE_MULTICAST */ 588 struct mbx_set_common_iface_multicast { 589 struct mbx_hdr hdr; 590 union { 591 struct { 592 /* dw 0 */ 593 uint16_t num_mac; 594 uint8_t promiscuous; 595 uint8_t if_id; 596 /* dw 1-48 */ 597 struct { 598 uint8_t byte[6]; 599 } mac[32]; 600 601 } req; 602 603 struct { 604 uint32_t rsvd0; 605 } rsp; 606 607 uint32_t dw[49]; 608 } params; 609 } __packed; 610 611 struct qinq_vlan { 612 #if _BYTE_ORDER == BIG_ENDIAN 613 uint16_t inner; 614 uint16_t outer; 615 #else 616 uint16_t outer; 617 uint16_t inner; 618 #endif 619 } __packed; 620 621 struct normal_vlan { 622 uint16_t vtag; 623 } __packed; 624 625 struct ntwk_if_vlan_tag { 626 union { 627 struct normal_vlan normal; 628 struct qinq_vlan qinq; 629 } u0; 630 } __packed; 631 632 /* [50] OPCODE_COMMON_CREATE_IFACE */ 633 struct mbx_create_common_iface { 634 struct mbx_hdr hdr; 635 union { 636 struct { 637 uint32_t version; 638 uint32_t cap_flags; 639 uint32_t enable_flags; 640 uint8_t mac_addr[6]; 641 uint8_t rsvd0; 642 uint8_t mac_invalid; 643 struct ntwk_if_vlan_tag vlan_tag; 644 } req; 645 646 struct { 647 uint32_t if_id; 648 uint32_t pmac_id; 649 } rsp; 650 uint32_t dw[4]; 651 } params; 652 } __packed; 653 654 /* [51] OPCODE_COMMON_DESTROY_IFACE */ 655 struct mbx_destroy_common_iface { 656 struct mbx_hdr hdr; 657 union { 658 struct { 659 uint32_t if_id; 660 } req; 661 662 struct { 663 uint32_t rsvd0; 664 } rsp; 665 666 uint32_t dw; 667 } params; 668 } __packed; 669 670 /* 671 * Event Queue Entry 672 */ 673 struct oce_eqe { 674 uint32_t evnt; 675 } __packed; 676 677 /* event queue context structure */ 678 struct oce_eq_ctx { 679 #if _BYTE_ORDER == BIG_ENDIAN 680 uint32_t dw4rsvd1:16; 681 uint32_t num_pages:16; 682 683 uint32_t size:1; 684 uint32_t dw5rsvd2:1; 685 uint32_t valid:1; 686 uint32_t dw5rsvd1:29; 687 688 uint32_t armed:1; 689 uint32_t dw6rsvd2:2; 690 uint32_t count:3; 691 uint32_t dw6rsvd1:26; 692 693 uint32_t dw7rsvd2:9; 694 uint32_t delay_mult:10; 695 uint32_t dw7rsvd1:13; 696 697 uint32_t dw8rsvd1; 698 #else 699 uint32_t num_pages:16; 700 uint32_t dw4rsvd1:16; 701 702 uint32_t dw5rsvd1:29; 703 uint32_t valid:1; 704 uint32_t dw5rsvd2:1; 705 uint32_t size:1; 706 707 uint32_t dw6rsvd1:26; 708 uint32_t count:3; 709 uint32_t dw6rsvd2:2; 710 uint32_t armed:1; 711 712 uint32_t dw7rsvd1:13; 713 uint32_t delay_mult:10; 714 uint32_t dw7rsvd2:9; 715 716 uint32_t dw8rsvd1; 717 #endif 718 } __packed; 719 720 /* [13] OPCODE_COMMON_CREATE_EQ */ 721 struct mbx_create_common_eq { 722 struct mbx_hdr hdr; 723 union { 724 struct { 725 struct oce_eq_ctx ctx; 726 struct oce_pa pages[8]; 727 } req; 728 729 struct { 730 uint16_t eq_id; 731 uint16_t rsvd0; 732 } rsp; 733 } params; 734 } __packed; 735 736 /* [55] OPCODE_COMMON_DESTROY_EQ */ 737 struct mbx_destroy_common_eq { 738 struct mbx_hdr hdr; 739 union { 740 struct { 741 #if _BYTE_ORDER == BIG_ENDIAN 742 uint16_t rsvd0; 743 uint16_t id; 744 #else 745 uint16_t id; 746 uint16_t rsvd0; 747 #endif 748 } req; 749 750 struct { 751 uint32_t rsvd0; 752 } rsp; 753 } params; 754 } __packed; 755 756 /* SLI-4 CQ context - use version V0 for B3, version V2 for Lancer */ 757 union oce_cq_ctx { 758 uint32_t dw[5]; 759 struct { 760 #if _BYTE_ORDER == BIG_ENDIAN 761 /* dw4 */ 762 uint32_t dw4rsvd1:16; 763 uint32_t num_pages:16; 764 /* dw5 */ 765 uint32_t eventable:1; 766 uint32_t dw5rsvd3:1; 767 uint32_t valid:1; 768 uint32_t count:2; 769 uint32_t dw5rsvd2:12; 770 uint32_t nodelay:1; 771 uint32_t coalesce_wm:2; 772 uint32_t dw5rsvd1:12; 773 /* dw6 */ 774 uint32_t armed:1; 775 uint32_t dw6rsvd2:1; 776 uint32_t eq_id:8; 777 uint32_t dw6rsvd1:22; 778 #else 779 /* dw4 */ 780 uint32_t num_pages:16; 781 uint32_t dw4rsvd1:16; 782 /* dw5 */ 783 uint32_t dw5rsvd1:12; 784 uint32_t coalesce_wm:2; 785 uint32_t nodelay:1; 786 uint32_t dw5rsvd2:12; 787 uint32_t count:2; 788 uint32_t valid:1; 789 uint32_t dw5rsvd3:1; 790 uint32_t eventable:1; 791 /* dw6 */ 792 uint32_t dw6rsvd1:22; 793 uint32_t eq_id:8; 794 uint32_t dw6rsvd2:1; 795 uint32_t armed:1; 796 #endif 797 /* dw7 */ 798 uint32_t dw7rsvd1; 799 /* dw8 */ 800 uint32_t dw8rsvd1; 801 } v0; 802 struct { 803 #if _BYTE_ORDER == BIG_ENDIAN 804 /* dw4 */ 805 uint32_t dw4rsvd1:8; 806 uint32_t page_size:8; 807 uint32_t num_pages:16; 808 /* dw5 */ 809 uint32_t eventable:1; 810 uint32_t dw5rsvd3:1; 811 uint32_t valid:1; 812 uint32_t count:2; 813 uint32_t dw5rsvd2:11; 814 uint32_t autovalid:1; 815 uint32_t nodelay:1; 816 uint32_t coalesce_wm:2; 817 uint32_t dw5rsvd1:12; 818 /* dw6 */ 819 uint32_t armed:1; 820 uint32_t dw6rsvd1:15; 821 uint32_t eq_id:16; 822 /* dw7 */ 823 uint32_t dw7rsvd1:16; 824 uint32_t cqe_count:16; 825 #else 826 /* dw4 */ 827 uint32_t num_pages:16; 828 uint32_t page_size:8; 829 uint32_t dw4rsvd1:8; 830 /* dw5 */ 831 uint32_t dw5rsvd1:12; 832 uint32_t coalesce_wm:2; 833 uint32_t nodelay:1; 834 uint32_t autovalid:1; 835 uint32_t dw5rsvd2:11; 836 uint32_t count:2; 837 uint32_t valid:1; 838 uint32_t dw5rsvd3:1; 839 uint32_t eventable:1; 840 /* dw6 */ 841 uint32_t eq_id:8; 842 uint32_t dw6rsvd1:15; 843 uint32_t armed:1; 844 /* dw7 */ 845 uint32_t cqe_count:16; 846 uint32_t dw7rsvd1:16; 847 #endif 848 /* dw8 */ 849 uint32_t dw8rsvd1; 850 } v2; 851 } __packed; 852 853 /* [12] OPCODE_COMMON_CREATE_CQ */ 854 struct mbx_create_common_cq { 855 struct mbx_hdr hdr; 856 union { 857 struct { 858 union oce_cq_ctx cq_ctx; 859 struct oce_pa pages[4]; 860 } req; 861 862 struct { 863 uint16_t cq_id; 864 uint16_t rsvd0; 865 } rsp; 866 } params; 867 } __packed; 868 869 /* [54] OPCODE_COMMON_DESTROY_CQ */ 870 struct mbx_destroy_common_cq { 871 struct mbx_hdr hdr; 872 union { 873 struct { 874 #if _BYTE_ORDER == BIG_ENDIAN 875 uint16_t rsvd0; 876 uint16_t id; 877 #else 878 uint16_t id; 879 uint16_t rsvd0; 880 #endif 881 } req; 882 883 struct { 884 uint32_t rsvd0; 885 } rsp; 886 } params; 887 } __packed; 888 889 union oce_mq_ctx { 890 uint32_t dw[5]; 891 struct { 892 #if _BYTE_ORDER == BIG_ENDIAN 893 /* dw4 */ 894 uint32_t dw4rsvd1:16; 895 uint32_t num_pages:16; 896 /* dw5 */ 897 uint32_t cq_id:10; 898 uint32_t dw5rsvd2:2; 899 uint32_t ring_size:4; 900 uint32_t dw5rsvd1:16; 901 /* dw6 */ 902 uint32_t valid:1; 903 uint32_t dw6rsvd1:31; 904 /* dw7 */ 905 uint32_t dw7rsvd1:21; 906 uint32_t async_cq_id:10; 907 uint32_t async_cq_valid:1; 908 #else 909 /* dw4 */ 910 uint32_t num_pages:16; 911 uint32_t dw4rsvd1:16; 912 /* dw5 */ 913 uint32_t dw5rsvd1:16; 914 uint32_t ring_size:4; 915 uint32_t dw5rsvd2:2; 916 uint32_t cq_id:10; 917 /* dw6 */ 918 uint32_t dw6rsvd1:31; 919 uint32_t valid:1; 920 /* dw7 */ 921 uint32_t async_cq_valid:1; 922 uint32_t async_cq_id:10; 923 uint32_t dw7rsvd1:21; 924 #endif 925 /* dw8 */ 926 uint32_t dw8rsvd1; 927 } v0; 928 } __packed; 929 930 /** 931 * @brief [21] OPCODE_COMMON_CREATE_MQ 932 * A MQ must be at least 16 entries deep (corresponding to 1 page) and 933 * at most 128 entries deep (corresponding to 8 pages). 934 */ 935 struct mbx_create_common_mq { 936 struct mbx_hdr hdr; 937 union { 938 struct { 939 union oce_mq_ctx context; 940 struct oce_pa pages[8]; 941 } req; 942 943 struct { 944 uint32_t mq_id:16; 945 uint32_t rsvd0:16; 946 } rsp; 947 } params; 948 } __packed; 949 950 struct mbx_create_common_mq_ex { 951 struct mbx_hdr hdr; 952 union { 953 struct { 954 union oce_mq_ext_ctx context; 955 struct oce_pa pages[8]; 956 } req; 957 958 struct { 959 uint32_t mq_id:16; 960 uint32_t rsvd0:16; 961 } rsp; 962 } params; 963 } __packed; 964 965 /* [53] OPCODE_COMMON_DESTROY_MQ */ 966 struct mbx_destroy_common_mq { 967 struct mbx_hdr hdr; 968 union { 969 struct { 970 #if _BYTE_ORDER == BIG_ENDIAN 971 uint16_t rsvd0; 972 uint16_t id; 973 #else 974 uint16_t id; 975 uint16_t rsvd0; 976 #endif 977 } req; 978 979 struct { 980 uint32_t rsvd0; 981 } rsp; 982 } params; 983 } __packed; 984 985 /* [35] OPCODE_COMMON_GET_ FW_VERSION */ 986 struct mbx_get_common_fw_version { 987 struct mbx_hdr hdr; 988 union { 989 struct { 990 uint32_t rsvd0; 991 } req; 992 993 struct { 994 uint8_t fw_ver_str[32]; 995 uint8_t fw_on_flash_ver_str[32]; 996 } rsp; 997 } params; 998 } __packed; 999 1000 /* [52] OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES */ 1001 struct mbx_common_cev_modify_msi_messages { 1002 struct mbx_hdr hdr; 1003 union { 1004 struct { 1005 uint32_t num_msi_msgs; 1006 } req; 1007 1008 struct { 1009 uint32_t rsvd0; 1010 } rsp; 1011 } params; 1012 } __packed; 1013 1014 /* [36] OPCODE_COMMON_SET_FLOW_CONTROL */ 1015 /* [37] OPCODE_COMMON_GET_FLOW_CONTROL */ 1016 struct mbx_common_get_set_flow_control { 1017 struct mbx_hdr hdr; 1018 #if _BYTE_ORDER == BIG_ENDIAN 1019 uint16_t tx_flow_control; 1020 uint16_t rx_flow_control; 1021 #else 1022 uint16_t rx_flow_control; 1023 uint16_t tx_flow_control; 1024 #endif 1025 } __packed; 1026 1027 struct oce_phy_info { 1028 uint16_t phy_type; 1029 uint16_t interface_type; 1030 uint32_t misc_params; 1031 uint16_t ext_phy_details; 1032 uint16_t rsvd; 1033 uint16_t auto_speeds_supported; 1034 uint16_t fixed_speeds_supported; 1035 uint32_t future_use[2]; 1036 } __packed; 1037 1038 struct mbx_common_phy_info { 1039 struct mbx_hdr hdr; 1040 union { 1041 struct { 1042 uint32_t rsvd0[4]; 1043 } req; 1044 struct { 1045 struct oce_phy_info phy_info; 1046 } rsp; 1047 } params; 1048 } __packed; 1049 1050 /*Lancer firmware*/ 1051 1052 struct mbx_lancer_common_write_object { 1053 union { 1054 struct { 1055 struct mbx_hdr hdr; 1056 uint32_t write_length: 24; 1057 uint32_t rsvd: 7; 1058 uint32_t eof: 1; 1059 uint32_t write_offset; 1060 uint8_t object_name[104]; 1061 uint32_t descriptor_count; 1062 uint32_t buffer_length; 1063 uint32_t address_lower; 1064 uint32_t address_upper; 1065 } req; 1066 struct { 1067 uint8_t opcode; 1068 uint8_t subsystem; 1069 uint8_t rsvd1[2]; 1070 uint8_t status; 1071 uint8_t additional_status; 1072 uint8_t rsvd2[2]; 1073 uint32_t response_length; 1074 uint32_t actual_response_length; 1075 uint32_t actual_write_length; 1076 } rsp; 1077 } params; 1078 } __packed; 1079 1080 /** 1081 * @brief MBX Common Query Firmware Config 1082 * This command retrieves firmware configuration parameters and adapter 1083 * resources available to the driver originating the request. The firmware 1084 * configuration defines supported protocols by the installed adapter firmware. 1085 * This includes which ULP processors support the specified protocols and 1086 * the number of TCP connections allowed for that protocol. 1087 */ 1088 struct mbx_common_query_fw_config { 1089 struct mbx_hdr hdr; 1090 union { 1091 struct { 1092 uint32_t rsvd0[30]; 1093 } req; 1094 1095 struct { 1096 uint32_t config_number; 1097 uint32_t asic_revision; 1098 uint32_t port_id; /* used for stats retrieval */ 1099 uint32_t function_mode; 1100 struct { 1101 1102 uint32_t ulp_mode; 1103 uint32_t nic_wqid_base; 1104 uint32_t nic_wq_tot; 1105 uint32_t toe_wqid_base; 1106 uint32_t toe_wq_tot; 1107 uint32_t toe_rqid_base; 1108 uint32_t toe_rqid_tot; 1109 uint32_t toe_defrqid_base; 1110 uint32_t toe_defrqid_count; 1111 uint32_t lro_rqid_base; 1112 uint32_t lro_rqid_tot; 1113 uint32_t iscsi_icd_base; 1114 uint32_t iscsi_icd_count; 1115 } ulp[2]; 1116 uint32_t function_caps; 1117 uint32_t cqid_base; 1118 uint32_t cqid_tot; 1119 uint32_t eqid_base; 1120 uint32_t eqid_tot; 1121 } rsp; 1122 } params; 1123 } __packed; 1124 1125 enum CQFW_CONFIG_NUMBER { 1126 FCN_NIC_ISCSI_Initiator = 0x0, 1127 FCN_ISCSI_Target = 0x3, 1128 FCN_FCoE = 0x7, 1129 FCN_ISCSI_Initiator_Target = 0x9, 1130 FCN_NIC_RDMA_TOE = 0xA, 1131 FCN_NIC_RDMA_FCoE = 0xB, 1132 FCN_NIC_RDMA_iSCSI = 0xC, 1133 FCN_NIC_iSCSI_FCoE = 0xD 1134 }; 1135 1136 /** 1137 * @brief Function Capabilities 1138 * This field contains the flags indicating the capabilities of 1139 * the SLI Host’s PCI function. 1140 */ 1141 enum CQFW_FUNCTION_CAPABILITIES { 1142 FNC_UNCLASSIFIED_STATS = 0x1, 1143 FNC_RSS = 0x2, 1144 FNC_PROMISCUOUS = 0x4, 1145 FNC_LEGACY_MODE = 0x8, 1146 FNC_HDS = 0x4000, 1147 FNC_VMQ = 0x10000, 1148 FNC_NETQ = 0x20000, 1149 FNC_QGROUPS = 0x40000, 1150 FNC_LRO = 0x100000, 1151 FNC_VLAN_OFFLOAD = 0x800000 1152 }; 1153 1154 enum CQFW_ULP_MODES_SUPPORTED { 1155 ULP_TOE_MODE = 0x1, 1156 ULP_NIC_MODE = 0x2, 1157 ULP_RDMA_MODE = 0x4, 1158 ULP_ISCSI_INI_MODE = 0x10, 1159 ULP_ISCSI_TGT_MODE = 0x20, 1160 ULP_FCOE_INI_MODE = 0x40, 1161 ULP_FCOE_TGT_MODE = 0x80, 1162 ULP_DAL_MODE = 0x100, 1163 ULP_LRO_MODE = 0x200 1164 }; 1165 1166 /** 1167 * @brief Function Modes Supported 1168 * Valid function modes (or protocol-types) supported on the SLI-Host’s 1169 * PCIe function. This field is a logical OR of the following values: 1170 */ 1171 enum CQFW_FUNCTION_MODES_SUPPORTED { 1172 FNM_TOE_MODE = 0x1, /* TCP offload supported */ 1173 FNM_NIC_MODE = 0x2, /* Raw Ethernet supported */ 1174 FNM_RDMA_MODE = 0x4, /* RDMA protocol supported */ 1175 FNM_VM_MODE = 0x8, /* Virtual Machines supported */ 1176 FNM_ISCSI_INI_MODE = 0x10, /* iSCSI initiator supported */ 1177 FNM_ISCSI_TGT_MODE = 0x20, /* iSCSI target plus initiator */ 1178 FNM_FCOE_INI_MODE = 0x40, /* FCoE Initiator supported */ 1179 FNM_FCOE_TGT_MODE = 0x80, /* FCoE target supported */ 1180 FNM_DAL_MODE = 0x100, /* DAL supported */ 1181 FNM_LRO_MODE = 0x200, /* LRO supported */ 1182 FNM_FLEX10_MODE = 0x400, /* QinQ, FLEX-10 or VNIC */ 1183 FNM_NCSI_MODE = 0x800, /* NCSI supported */ 1184 FNM_IPV6_MODE = 0x1000, /* IPV6 stack enabled */ 1185 FNM_BE2_COMPAT_MODE = 0x2000, /* BE2 compatibility (BE3 disable)*/ 1186 FNM_INVALID_MODE = 0x8000, /* Invalid */ 1187 FNM_BE3_COMPAT_MODE = 0x10000, /* BE3 features */ 1188 FNM_VNIC_MODE = 0x20000, /* Set when IBM vNIC mode is set */ 1189 FNM_VNTAG_MODE = 0x40000, /* Set when VNTAG mode is set */ 1190 FNM_UMC_MODE = 0x1000000, /* Set when UMC mode is set */ 1191 FNM_UMC_DEF_EN = 0x100000, /* Set when UMC Default is set */ 1192 FNM_ONE_GB_EN = 0x200000, /* Set when 1GB Default is set */ 1193 FNM_VNIC_DEF_VALID = 0x400000, /* Set when VNIC_DEF_EN is valid */ 1194 FNM_VNIC_DEF_EN = 0x800000 /* Set when VNIC Default enabled */ 1195 }; 1196 1197 struct mbx_common_config_vlan { 1198 struct mbx_hdr hdr; 1199 union { 1200 struct { 1201 #if _BYTE_ORDER == BIG_ENDIAN 1202 uint8_t num_vlans; 1203 uint8_t untagged; 1204 uint8_t promisc; 1205 uint8_t if_id; 1206 #else 1207 uint8_t if_id; 1208 uint8_t promisc; 1209 uint8_t untagged; 1210 uint8_t num_vlans; 1211 #endif 1212 union { 1213 struct normal_vlan normal_vlans[64]; 1214 struct qinq_vlan qinq_vlans[32]; 1215 } tags; 1216 } req; 1217 1218 struct { 1219 uint32_t rsvd; 1220 } rsp; 1221 } params; 1222 } __packed; 1223 1224 struct iface_rx_filter_ctx { 1225 uint32_t global_flags_mask; 1226 uint32_t global_flags; 1227 uint32_t iface_flags_mask; 1228 uint32_t iface_flags; 1229 uint32_t if_id; 1230 #define IFACE_RX_NUM_MCAST_MAX 64 1231 uint32_t num_mcast; 1232 struct mbx_mcast_addr { 1233 uint8_t byte[6]; 1234 } mac[IFACE_RX_NUM_MCAST_MAX]; 1235 } __packed; 1236 1237 /* [34] OPCODE_COMMON_SET_IFACE_RX_FILTER */ 1238 struct mbx_set_common_iface_rx_filter { 1239 struct mbx_hdr hdr; 1240 union { 1241 struct iface_rx_filter_ctx req; 1242 struct iface_rx_filter_ctx rsp; 1243 } params; 1244 } __packed; 1245 1246 /* [41] OPCODE_COMMON_MODIFY_EQ_DELAY */ 1247 struct mbx_modify_common_eq_delay { 1248 struct mbx_hdr hdr; 1249 union { 1250 struct { 1251 uint32_t num_eq; 1252 struct { 1253 uint32_t eq_id; 1254 uint32_t phase; 1255 uint32_t dm; 1256 } delay[8]; 1257 } req; 1258 1259 struct { 1260 uint32_t rsvd0; 1261 } rsp; 1262 } params; 1263 } __packed; 1264 1265 /* [59] OPCODE_ADD_COMMON_IFACE_MAC */ 1266 struct mbx_add_common_iface_mac { 1267 struct mbx_hdr hdr; 1268 union { 1269 struct { 1270 uint32_t if_id; 1271 uint8_t mac_address[6]; 1272 uint8_t rsvd0[2]; 1273 } req; 1274 struct { 1275 uint32_t pmac_id; 1276 } rsp; 1277 } params; 1278 } __packed; 1279 1280 /* [60] OPCODE_DEL_COMMON_IFACE_MAC */ 1281 struct mbx_del_common_iface_mac { 1282 struct mbx_hdr hdr; 1283 union { 1284 struct { 1285 uint32_t if_id; 1286 uint32_t pmac_id; 1287 } req; 1288 struct { 1289 uint32_t rsvd0; 1290 } rsp; 1291 } params; 1292 } __packed; 1293 1294 /* [8] OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE */ 1295 struct mbx_query_common_max_mbx_buffer_size { 1296 struct mbx_hdr hdr; 1297 struct { 1298 uint32_t max_ioctl_bufsz; 1299 } rsp; 1300 } __packed; 1301 1302 /* [61] OPCODE_COMMON_FUNCTION_RESET */ 1303 struct ioctl_common_function_reset { 1304 struct mbx_hdr hdr; 1305 } __packed; 1306 1307 /* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */ 1308 struct mbx_common_func_link_cfg { 1309 struct mbx_hdr hdr; 1310 union { 1311 struct { 1312 uint32_t enable; 1313 } req; 1314 struct { 1315 uint32_t rsvd0; 1316 } rsp; 1317 } params; 1318 } __packed; 1319 1320 /* [103] OPCODE_COMMON_SET_FUNCTIONAL_CAPS */ 1321 #define CAP_SW_TIMESTAMPS 2 1322 #define CAP_BE3_NATIVE_ERX_API 4 1323 1324 struct mbx_common_set_function_cap { 1325 struct mbx_hdr hdr; 1326 union { 1327 struct { 1328 uint32_t valid_capability_flags; 1329 uint32_t capability_flags; 1330 uint8_t sbz[212]; 1331 } req; 1332 struct { 1333 uint32_t valid_capability_flags; 1334 uint32_t capability_flags; 1335 uint8_t sbz[212]; 1336 } rsp; 1337 } params; 1338 } __packed; 1339 struct mbx_lowlevel_test_loopback_mode { 1340 struct mbx_hdr hdr; 1341 union { 1342 struct { 1343 uint32_t loopback_type; 1344 uint32_t num_pkts; 1345 uint64_t pattern; 1346 uint32_t src_port; 1347 uint32_t dest_port; 1348 uint32_t pkt_size; 1349 }req; 1350 struct { 1351 uint32_t status; 1352 uint32_t num_txfer; 1353 uint32_t num_rx; 1354 uint32_t miscomp_off; 1355 uint32_t ticks_compl; 1356 }rsp; 1357 } params; 1358 } __packed; 1359 1360 struct mbx_lowlevel_set_loopback_mode { 1361 struct mbx_hdr hdr; 1362 union { 1363 struct { 1364 uint8_t src_port; 1365 uint8_t dest_port; 1366 uint8_t loopback_type; 1367 uint8_t loopback_state; 1368 } req; 1369 struct { 1370 uint8_t rsvd0[4]; 1371 } rsp; 1372 } params; 1373 } __packed; 1374 1375 enum LOWLEVEL_SUBSYS_OPCODES { 1376 /* Opcodes used for lowlevel functions common to many subsystems. 1377 * Some of these opcodes are used for diagnostic functions only. 1378 * These opcodes use the SUBSYS_LOWLEVEL subsystem code. 1379 */ 1380 OPCODE_LOWLEVEL_TEST_LOOPBACK = 18, 1381 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE = 19, 1382 OPCODE_LOWLEVEL_GET_LOOPBACK_MODE = 20 1383 }; 1384 1385 enum LLDP_SUBSYS_OPCODES { 1386 /* Opcodes used for LLDP subsystem for configuring the LLDP state machines. */ 1387 OPCODE_LLDP_GET_CFG = 1, 1388 OPCODE_LLDP_SET_CFG = 2, 1389 OPCODE_LLDP_GET_STATS = 3 1390 }; 1391 1392 enum DCBX_SUBSYS_OPCODES { 1393 /* Opcodes used for DCBX. */ 1394 OPCODE_DCBX_GET_CFG = 1, 1395 OPCODE_DCBX_SET_CFG = 2, 1396 OPCODE_DCBX_GET_MIB_INFO = 3, 1397 OPCODE_DCBX_GET_DCBX_MODE = 4, 1398 OPCODE_DCBX_SET_MODE = 5 1399 }; 1400 1401 enum DMTF_SUBSYS_OPCODES { 1402 /* Opcodes used for DCBX subsystem. */ 1403 OPCODE_DMTF_EXEC_CLP_CMD = 1 1404 }; 1405 1406 enum DIAG_SUBSYS_OPCODES { 1407 /* Opcodes used for diag functions common to many subsystems. */ 1408 OPCODE_DIAG_RUN_DMA_TEST = 1, 1409 OPCODE_DIAG_RUN_MDIO_TEST = 2, 1410 OPCODE_DIAG_RUN_NLB_TEST = 3, 1411 OPCODE_DIAG_RUN_ARM_TIMER_TEST = 4, 1412 OPCODE_DIAG_GET_MAC = 5 1413 }; 1414 1415 enum VENDOR_SUBSYS_OPCODES { 1416 /* Opcodes used for Vendor subsystem. */ 1417 OPCODE_VENDOR_SLI = 1 1418 }; 1419 1420 /* Management Status Codes */ 1421 enum MGMT_STATUS_SUCCESS { 1422 MGMT_SUCCESS = 0, 1423 MGMT_FAILED = 1, 1424 MGMT_ILLEGAL_REQUEST = 2, 1425 MGMT_ILLEGAL_FIELD = 3, 1426 MGMT_INSUFFICIENT_BUFFER = 4, 1427 MGMT_UNAUTHORIZED_REQUEST = 5, 1428 MGMT_INVALID_ISNS_ADDRESS = 10, 1429 MGMT_INVALID_IPADDR = 11, 1430 MGMT_INVALID_GATEWAY = 12, 1431 MGMT_INVALID_SUBNETMASK = 13, 1432 MGMT_INVALID_TARGET_IPADDR = 16, 1433 MGMT_TGTTBL_FULL = 20, 1434 MGMT_FLASHROM_SAVE_FAILED = 23, 1435 MGMT_IOCTLHANDLE_ALLOC_FAILED = 27, 1436 MGMT_INVALID_SESSION = 31, 1437 MGMT_INVALID_CONNECTION = 32, 1438 MGMT_BTL_PATH_EXCEEDS_OSM_LIMIT = 33, 1439 MGMT_BTL_TGTID_EXCEEDS_OSM_LIMIT = 34, 1440 MGMT_BTL_PATH_TGTID_OCCUPIED = 35, 1441 MGMT_BTL_NO_FREE_SLOT_PATH = 36, 1442 MGMT_BTL_NO_FREE_SLOT_TGTID = 37, 1443 MGMT_POLL_IOCTL_TIMEOUT = 40, 1444 MGMT_ERROR_ACITISCSI = 41, 1445 MGMT_BUFFER_SIZE_EXCEED_OSM_OR_OS_LIMIT = 43, 1446 MGMT_REBOOT_REQUIRED = 44, 1447 MGMT_INSUFFICIENT_TIMEOUT = 45, 1448 MGMT_IPADDR_NOT_SET = 46, 1449 MGMT_IPADDR_DUP_DETECTED = 47, 1450 MGMT_CANT_REMOVE_LAST_CONNECTION = 48, 1451 MGMT_TARGET_BUSY = 49, 1452 MGMT_TGT_ERR_LISTEN_SOCKET = 50, 1453 MGMT_TGT_ERR_BIND_SOCKET = 51, 1454 MGMT_TGT_ERR_NO_SOCKET = 52, 1455 MGMT_TGT_ERR_ISNS_COMM_FAILED = 55, 1456 MGMT_CANNOT_DELETE_BOOT_TARGET = 56, 1457 MGMT_TGT_PORTAL_MODE_IN_LISTEN = 57, 1458 MGMT_FCF_IN_USE = 58 , 1459 MGMT_NO_CQE = 59, 1460 MGMT_TARGET_NOT_FOUND = 65, 1461 MGMT_NOT_SUPPORTED = 66, 1462 MGMT_NO_FCF_RECORDS = 67, 1463 MGMT_FEATURE_NOT_SUPPORTED = 68, 1464 MGMT_VPD_FUNCTION_OUT_OF_RANGE = 69, 1465 MGMT_VPD_FUNCTION_TYPE_INCORRECT = 70, 1466 MGMT_INVALID_NON_EMBEDDED_WRB = 71, 1467 MGMT_OOR = 100, 1468 MGMT_INVALID_PD = 101, 1469 MGMT_STATUS_PD_INUSE = 102, 1470 MGMT_INVALID_CQ = 103, 1471 MGMT_INVALID_QP = 104, 1472 MGMT_INVALID_STAG = 105, 1473 MGMT_ORD_EXCEEDS = 106, 1474 MGMT_IRD_EXCEEDS = 107, 1475 MGMT_SENDQ_WQE_EXCEEDS = 108, 1476 MGMT_RECVQ_RQE_EXCEEDS = 109, 1477 MGMT_SGE_SEND_EXCEEDS = 110, 1478 MGMT_SGE_WRITE_EXCEEDS = 111, 1479 MGMT_SGE_RECV_EXCEEDS = 112, 1480 MGMT_INVALID_STATE_CHANGE = 113, 1481 MGMT_MW_BOUND = 114, 1482 MGMT_INVALID_VA = 115, 1483 MGMT_INVALID_LENGTH = 116, 1484 MGMT_INVALID_FBO = 117, 1485 MGMT_INVALID_ACC_RIGHTS = 118, 1486 MGMT_INVALID_PBE_SIZE = 119, 1487 MGMT_INVALID_PBL_ENTRY = 120, 1488 MGMT_INVALID_PBL_OFFSET = 121, 1489 MGMT_ADDR_NON_EXIST = 122, 1490 MGMT_INVALID_VLANID = 123, 1491 MGMT_INVALID_MTU = 124, 1492 MGMT_INVALID_BACKLOG = 125, 1493 MGMT_CONNECTION_INPROGRESS = 126, 1494 MGMT_INVALID_RQE_SIZE = 127, 1495 MGMT_INVALID_RQE_ENTRY = 128 1496 }; 1497 1498 /* Additional Management Status Codes */ 1499 enum MGMT_ADDI_STATUS { 1500 MGMT_ADDI_NO_STATUS = 0, 1501 MGMT_ADDI_INVALID_IPTYPE = 1, 1502 MGMT_ADDI_TARGET_HANDLE_NOT_FOUND = 9, 1503 MGMT_ADDI_SESSION_HANDLE_NOT_FOUND = 10, 1504 MGMT_ADDI_CONNECTION_HANDLE_NOT_FOUND = 11, 1505 MGMT_ADDI_ACTIVE_SESSIONS_PRESENT = 16, 1506 MGMT_ADDI_SESSION_ALREADY_OPENED = 17, 1507 MGMT_ADDI_SESSION_ALREADY_CLOSED = 18, 1508 MGMT_ADDI_DEST_HOST_UNREACHABLE = 19, 1509 MGMT_ADDI_LOGIN_IN_PROGRESS = 20, 1510 MGMT_ADDI_TCP_CONNECT_FAILED = 21, 1511 MGMT_ADDI_INSUFFICIENT_RESOURCES = 22, 1512 MGMT_ADDI_LINK_DOWN = 23, 1513 MGMT_ADDI_DHCP_ERROR = 24, 1514 MGMT_ADDI_CONNECTION_OFFLOADED = 25, 1515 MGMT_ADDI_CONNECTION_NOT_OFFLOADED = 26, 1516 MGMT_ADDI_CONNECTION_UPLOAD_IN_PROGRESS = 27, 1517 MGMT_ADDI_REQUEST_REJECTED = 28, 1518 MGMT_ADDI_INVALID_SUBSYSTEM = 29, 1519 MGMT_ADDI_INVALID_OPCODE = 30, 1520 MGMT_ADDI_INVALID_MAXCONNECTION_PARAM = 31, 1521 MGMT_ADDI_INVALID_KEY = 32, 1522 MGMT_ADDI_INVALID_DOMAIN = 35, 1523 MGMT_ADDI_LOGIN_INITIATOR_ERROR = 43, 1524 MGMT_ADDI_LOGIN_AUTHENTICATION_ERROR = 44, 1525 MGMT_ADDI_LOGIN_AUTHORIZATION_ERROR = 45, 1526 MGMT_ADDI_LOGIN_NOT_FOUND = 46, 1527 MGMT_ADDI_LOGIN_TARGET_REMOVED = 47, 1528 MGMT_ADDI_LOGIN_UNSUPPORTED_VERSION = 48, 1529 MGMT_ADDI_LOGIN_TOO_MANY_CONNECTIONS = 49, 1530 MGMT_ADDI_LOGIN_MISSING_PARAMETER = 50, 1531 MGMT_ADDI_LOGIN_NO_SESSION_SPANNING = 51, 1532 MGMT_ADDI_LOGIN_SESSION_TYPE_NOT_SUPPORTED = 52, 1533 MGMT_ADDI_LOGIN_SESSION_DOES_NOT_EXIST = 53, 1534 MGMT_ADDI_LOGIN_INVALID_DURING_LOGIN = 54, 1535 MGMT_ADDI_LOGIN_TARGET_ERROR = 55, 1536 MGMT_ADDI_LOGIN_SERVICE_UNAVAILABLE = 56, 1537 MGMT_ADDI_LOGIN_OUT_OF_RESOURCES = 57, 1538 MGMT_ADDI_SAME_CHAP_SECRET = 58, 1539 MGMT_ADDI_INVALID_SECRET_LENGTH = 59, 1540 MGMT_ADDI_DUPLICATE_ENTRY = 60, 1541 MGMT_ADDI_SETTINGS_MODIFIED_REBOOT_REQD = 63, 1542 MGMT_ADDI_INVALID_EXTENDED_TIMEOUT = 64, 1543 MGMT_ADDI_INVALID_INTERFACE_HANDLE = 65, 1544 MGMT_ADDI_ERR_VLAN_ON_DEF_INTERFACE = 66, 1545 MGMT_ADDI_INTERFACE_DOES_NOT_EXIST = 67, 1546 MGMT_ADDI_INTERFACE_ALREADY_EXISTS = 68, 1547 MGMT_ADDI_INVALID_VLAN_RANGE = 69, 1548 MGMT_ADDI_ERR_SET_VLAN = 70, 1549 MGMT_ADDI_ERR_DEL_VLAN = 71, 1550 MGMT_ADDI_CANNOT_DEL_DEF_INTERFACE = 72, 1551 MGMT_ADDI_DHCP_REQ_ALREADY_PENDING = 73, 1552 MGMT_ADDI_TOO_MANY_INTERFACES = 74, 1553 MGMT_ADDI_INVALID_REQUEST = 75 1554 }; 1555 1556 enum NIC_SUBSYS_OPCODES { 1557 /** 1558 * @brief NIC Subsystem Opcodes (see Network SLI-4 manual >= Rev4, v21-2) 1559 * These opcodes are used for configuring the Ethernet interfaces. 1560 * These opcodes all use the SUBSYS_NIC subsystem code. 1561 */ 1562 OPCODE_NIC_CONFIG_RSS = 1, 1563 OPCODE_NIC_CONFIG_ACPI = 2, 1564 OPCODE_NIC_CONFIG_PROMISCUOUS = 3, 1565 OPCODE_NIC_GET_STATS = 4, 1566 OPCODE_NIC_CREATE_WQ = 7, 1567 OPCODE_NIC_CREATE_RQ = 8, 1568 OPCODE_NIC_DELETE_WQ = 9, 1569 OPCODE_NIC_DELETE_RQ = 10, 1570 OPCODE_NIC_CONFIG_ACPI_WOL_MAGIC = 12, 1571 OPCODE_NIC_GET_NETWORK_STATS = 13, 1572 OPCODE_NIC_CREATE_HDS_RQ = 16, 1573 OPCODE_NIC_DELETE_HDS_RQ = 17, 1574 OPCODE_NIC_GET_PPORT_STATS = 18, 1575 OPCODE_NIC_GET_VPORT_STATS = 19, 1576 OPCODE_NIC_GET_QUEUE_STATS = 20 1577 }; 1578 1579 /* NIC header WQE */ 1580 struct oce_nic_hdr_wqe { 1581 union { 1582 struct { 1583 #if _BYTE_ORDER == BIG_ENDIAN 1584 /* dw0 */ 1585 uint32_t rsvd0; 1586 1587 /* dw1 */ 1588 uint32_t last_seg_udp_len:14; 1589 uint32_t rsvd1:18; 1590 1591 /* dw2 */ 1592 uint32_t lso_mss:14; 1593 uint32_t num_wqe:5; 1594 uint32_t rsvd4:2; 1595 uint32_t vlan:1; 1596 uint32_t lso:1; 1597 uint32_t tcpcs:1; 1598 uint32_t udpcs:1; 1599 uint32_t ipcs:1; 1600 uint32_t rsvd3:1; 1601 uint32_t rsvd2:1; 1602 uint32_t forward:1; 1603 uint32_t crc:1; 1604 uint32_t event:1; 1605 uint32_t complete:1; 1606 1607 /* dw3 */ 1608 uint32_t vlan_tag:16; 1609 uint32_t total_length:16; 1610 #else 1611 /* dw0 */ 1612 uint32_t rsvd0; 1613 1614 /* dw1 */ 1615 uint32_t rsvd1:18; 1616 uint32_t last_seg_udp_len:14; 1617 1618 /* dw2 */ 1619 uint32_t complete:1; 1620 uint32_t event:1; 1621 uint32_t crc:1; 1622 uint32_t forward:1; 1623 uint32_t rsvd2:1; 1624 uint32_t rsvd3:1; 1625 uint32_t ipcs:1; 1626 uint32_t udpcs:1; 1627 uint32_t tcpcs:1; 1628 uint32_t lso:1; 1629 uint32_t vlan:1; 1630 uint32_t rsvd4:2; 1631 uint32_t num_wqe:5; 1632 uint32_t lso_mss:14; 1633 1634 /* dw3 */ 1635 uint32_t total_length:16; 1636 uint32_t vlan_tag:16; 1637 #endif 1638 } s; 1639 uint32_t dw[4]; 1640 } u0; 1641 } __packed; 1642 1643 /* NIC fragment WQE */ 1644 struct oce_nic_frag_wqe { 1645 union { 1646 struct { 1647 /* dw0 */ 1648 uint32_t frag_pa_hi; 1649 /* dw1 */ 1650 uint32_t frag_pa_lo; 1651 /* dw2 */ 1652 uint32_t rsvd0; 1653 uint32_t frag_len; 1654 } s; 1655 uint32_t dw[4]; 1656 } u0; 1657 } __packed; 1658 1659 /* Ethernet Tx Completion Descriptor */ 1660 struct oce_nic_tx_cqe { 1661 union { 1662 struct { 1663 #if _BYTE_ORDER == BIG_ENDIAN 1664 /* dw 0 */ 1665 uint32_t status:4; 1666 uint32_t rsvd0:8; 1667 uint32_t port:2; 1668 uint32_t ct:2; 1669 uint32_t wqe_index:16; 1670 /* dw 1 */ 1671 uint32_t rsvd1:5; 1672 uint32_t cast_enc:2; 1673 uint32_t lso:1; 1674 uint32_t nwh_bytes:8; 1675 uint32_t user_bytes:16; 1676 /* dw 2 */ 1677 uint32_t rsvd2; 1678 /* dw 3 */ 1679 uint32_t valid:1; 1680 uint32_t rsvd3:4; 1681 uint32_t wq_id:11; 1682 uint32_t num_pkts:16; 1683 #else 1684 /* dw 0 */ 1685 uint32_t wqe_index:16; 1686 uint32_t ct:2; 1687 uint32_t port:2; 1688 uint32_t rsvd0:8; 1689 uint32_t status:4; 1690 /* dw 1 */ 1691 uint32_t user_bytes:16; 1692 uint32_t nwh_bytes:8; 1693 uint32_t lso:1; 1694 uint32_t cast_enc:2; 1695 uint32_t rsvd1:5; 1696 /* dw 2 */ 1697 uint32_t rsvd2; 1698 /* dw 3 */ 1699 uint32_t num_pkts:16; 1700 uint32_t wq_id:11; 1701 uint32_t rsvd3:4; 1702 uint32_t valid:1; 1703 #endif 1704 } s; 1705 uint32_t dw[4]; 1706 } u0; 1707 } __packed; 1708 #define WQ_CQE_VALID(_cqe) ((_cqe)->u0.dw[3]) 1709 #define WQ_CQE_INVALIDATE(_cqe) ((_cqe)->u0.dw[3] = 0) 1710 1711 /* Receive Queue Entry (RQE) */ 1712 struct oce_nic_rqe { 1713 union { 1714 struct { 1715 uint32_t frag_pa_hi; 1716 uint32_t frag_pa_lo; 1717 } s; 1718 uint32_t dw[2]; 1719 } u0; 1720 } __packed; 1721 1722 /* NIC Receive CQE */ 1723 struct oce_nic_rx_cqe { 1724 union { 1725 struct { 1726 #if _BYTE_ORDER == BIG_ENDIAN 1727 /* dw 0 */ 1728 uint32_t ip_options:1; 1729 uint32_t port:1; 1730 uint32_t pkt_size:14; 1731 uint32_t vlan_tag:16; 1732 /* dw 1 */ 1733 uint32_t num_fragments:3; 1734 uint32_t switched:1; 1735 uint32_t ct:2; 1736 uint32_t frag_index:10; 1737 uint32_t rsvd0:1; 1738 uint32_t vlan_tag_present:1; 1739 uint32_t mac_dst:6; 1740 uint32_t ip_ver:1; 1741 uint32_t l4_cksum_pass:1; 1742 uint32_t ip_cksum_pass:1; 1743 uint32_t udpframe:1; 1744 uint32_t tcpframe:1; 1745 uint32_t ipframe:1; 1746 uint32_t rss_hp:1; 1747 uint32_t error:1; 1748 /* dw 2 */ 1749 uint32_t valid:1; 1750 uint32_t hds_type:2; 1751 uint32_t lro_pkt:1; 1752 uint32_t rsvd4:1; 1753 uint32_t hds_hdr_size:12; 1754 uint32_t hds_hdr_frag_index:10; 1755 uint32_t rss_bank:1; 1756 uint32_t qnq:1; 1757 uint32_t pkt_type:2; 1758 uint32_t rss_flush:1; 1759 /* dw 3 */ 1760 uint32_t rss_hash_value; 1761 #else 1762 /* dw 0 */ 1763 uint32_t vlan_tag:16; 1764 uint32_t pkt_size:14; 1765 uint32_t port:1; 1766 uint32_t ip_options:1; 1767 /* dw 1 */ 1768 uint32_t error:1; 1769 uint32_t rss_hp:1; 1770 uint32_t ipframe:1; 1771 uint32_t tcpframe:1; 1772 uint32_t udpframe:1; 1773 uint32_t ip_cksum_pass:1; 1774 uint32_t l4_cksum_pass:1; 1775 uint32_t ip_ver:1; 1776 uint32_t mac_dst:6; 1777 uint32_t vlan_tag_present:1; 1778 uint32_t rsvd0:1; 1779 uint32_t frag_index:10; 1780 uint32_t ct:2; 1781 uint32_t switched:1; 1782 uint32_t num_fragments:3; 1783 /* dw 2 */ 1784 uint32_t rss_flush:1; 1785 uint32_t pkt_type:2; 1786 uint32_t qnq:1; 1787 uint32_t rss_bank:1; 1788 uint32_t hds_hdr_frag_index:10; 1789 uint32_t hds_hdr_size:12; 1790 uint32_t rsvd4:1; 1791 uint32_t lro_pkt:1; 1792 uint32_t hds_type:2; 1793 uint32_t valid:1; 1794 /* dw 3 */ 1795 uint32_t rss_hash_value; 1796 #endif 1797 } s; 1798 uint32_t dw[4]; 1799 } u0; 1800 } __packed; 1801 1802 /* NIC Receive CQE_v1 */ 1803 struct oce_nic_rx_cqe_v1 { 1804 union { 1805 struct { 1806 #if _BYTE_ORDER == BIG_ENDIAN 1807 /* dw 0 */ 1808 uint32_t ip_options:1; 1809 uint32_t vlan_tag_present:1; 1810 uint32_t pkt_size:14; 1811 uint32_t vlan_tag:16; 1812 /* dw 1 */ 1813 uint32_t num_fragments:3; 1814 uint32_t switched:1; 1815 uint32_t ct:2; 1816 uint32_t frag_index:10; 1817 uint32_t rsvd0:1; 1818 uint32_t mac_dst:7; 1819 uint32_t ip_ver:1; 1820 uint32_t l4_cksum_pass:1; 1821 uint32_t ip_cksum_pass:1; 1822 uint32_t udpframe:1; 1823 uint32_t tcpframe:1; 1824 uint32_t ipframe:1; 1825 uint32_t rss_hp:1; 1826 uint32_t error:1; 1827 /* dw 2 */ 1828 uint32_t valid:1; 1829 uint32_t rsvd4:13; 1830 uint32_t hds_hdr_size:2; 1831 uint32_t hds_hdr_frag_index:8; 1832 uint32_t vlantag:1; 1833 uint32_t port:2; 1834 uint32_t rss_bank:1; 1835 uint32_t qnq:1; 1836 uint32_t pkt_type:2; 1837 uint32_t rss_flush:1; 1838 /* dw 3 */ 1839 uint32_t rss_hash_value; 1840 #else 1841 /* dw 0 */ 1842 uint32_t vlan_tag:16; 1843 uint32_t pkt_size:14; 1844 uint32_t vlan_tag_present:1; 1845 uint32_t ip_options:1; 1846 /* dw 1 */ 1847 uint32_t error:1; 1848 uint32_t rss_hp:1; 1849 uint32_t ipframe:1; 1850 uint32_t tcpframe:1; 1851 uint32_t udpframe:1; 1852 uint32_t ip_cksum_pass:1; 1853 uint32_t l4_cksum_pass:1; 1854 uint32_t ip_ver:1; 1855 uint32_t mac_dst:7; 1856 uint32_t rsvd0:1; 1857 uint32_t frag_index:10; 1858 uint32_t ct:2; 1859 uint32_t switched:1; 1860 uint32_t num_fragments:3; 1861 /* dw 2 */ 1862 uint32_t rss_flush:1; 1863 uint32_t pkt_type:2; 1864 uint32_t qnq:1; 1865 uint32_t rss_bank:1; 1866 uint32_t port:2; 1867 uint32_t vlantag:1; 1868 uint32_t hds_hdr_frag_index:8; 1869 uint32_t hds_hdr_size:2; 1870 uint32_t rsvd4:13; 1871 uint32_t valid:1; 1872 /* dw 3 */ 1873 uint32_t rss_hash_value; 1874 #endif 1875 } s; 1876 uint32_t dw[4]; 1877 } u0; 1878 } __packed; 1879 1880 #define RQ_CQE_VALID(_cqe) ((_cqe)->u0.dw[2]) 1881 #define RQ_CQE_INVALIDATE(_cqe) ((_cqe)->u0.dw[2] = 0) 1882 1883 struct mbx_config_nic_promiscuous { 1884 struct mbx_hdr hdr; 1885 union { 1886 struct { 1887 #if _BYTE_ORDER == BIG_ENDIAN 1888 uint16_t rsvd0; 1889 uint8_t port1_promisc; 1890 uint8_t port0_promisc; 1891 #else 1892 uint8_t port0_promisc; 1893 uint8_t port1_promisc; 1894 uint16_t rsvd0; 1895 #endif 1896 } req; 1897 1898 struct { 1899 uint32_t rsvd0; 1900 } rsp; 1901 } params; 1902 } __packed; 1903 1904 union oce_wq_ctx { 1905 uint32_t dw[17]; 1906 struct { 1907 #if _BYTE_ORDER == BIG_ENDIAN 1908 /* dw4 */ 1909 uint32_t dw4rsvd2:8; 1910 uint32_t nic_wq_type:8; 1911 uint32_t dw4rsvd1:8; 1912 uint32_t num_pages:8; 1913 /* dw5 */ 1914 uint32_t dw5rsvd2:12; 1915 uint32_t wq_size:4; 1916 uint32_t dw5rsvd1:16; 1917 /* dw6 */ 1918 uint32_t valid:1; 1919 uint32_t dw6rsvd1:31; 1920 /* dw7 */ 1921 uint32_t dw7rsvd1:16; 1922 uint32_t cq_id:16; 1923 #else 1924 /* dw4 */ 1925 uint32_t num_pages:8; 1926 #if 0 1927 uint32_t dw4rsvd1:8; 1928 #else 1929 /* PSP: this workaround is not documented: fill 0x01 for ulp_mask */ 1930 uint32_t ulp_mask:8; 1931 #endif 1932 uint32_t nic_wq_type:8; 1933 uint32_t dw4rsvd2:8; 1934 /* dw5 */ 1935 uint32_t dw5rsvd1:16; 1936 uint32_t wq_size:4; 1937 uint32_t dw5rsvd2:12; 1938 /* dw6 */ 1939 uint32_t dw6rsvd1:31; 1940 uint32_t valid:1; 1941 /* dw7 */ 1942 uint32_t cq_id:16; 1943 uint32_t dw7rsvd1:16; 1944 #endif 1945 /* dw8 - dw20 */ 1946 uint32_t dw8_20rsvd1[13]; 1947 } v0; 1948 struct { 1949 #if _BYTE_ORDER == BIG_ENDIAN 1950 /* dw4 */ 1951 uint32_t dw4rsvd2:8; 1952 uint32_t nic_wq_type:8; 1953 uint32_t dw4rsvd1:8; 1954 uint32_t num_pages:8; 1955 /* dw5 */ 1956 uint32_t dw5rsvd2:12; 1957 uint32_t wq_size:4; 1958 uint32_t iface_id:16; 1959 /* dw6 */ 1960 uint32_t valid:1; 1961 uint32_t dw6rsvd1:31; 1962 /* dw7 */ 1963 uint32_t dw7rsvd1:16; 1964 uint32_t cq_id:16; 1965 #else 1966 /* dw4 */ 1967 uint32_t num_pages:8; 1968 uint32_t dw4rsvd1:8; 1969 uint32_t nic_wq_type:8; 1970 uint32_t dw4rsvd2:8; 1971 /* dw5 */ 1972 uint32_t iface_id:16; 1973 uint32_t wq_size:4; 1974 uint32_t dw5rsvd2:12; 1975 /* dw6 */ 1976 uint32_t dw6rsvd1:31; 1977 uint32_t valid:1; 1978 /* dw7 */ 1979 uint32_t cq_id:16; 1980 uint32_t dw7rsvd1:16; 1981 #endif 1982 /* dw8 - dw20 */ 1983 uint32_t dw8_20rsvd1[13]; 1984 } v1; 1985 } __packed; 1986 1987 /** 1988 * @brief [07] NIC_CREATE_WQ 1989 * @note 1990 * Lancer requires an InterfaceID to be specified with every WQ. This 1991 * is the basis for NIC IOV where the Interface maps to a vPort and maps 1992 * to both Tx and Rx sides. 1993 */ 1994 #define OCE_WQ_TYPE_FORWARDING 0x1 /* wq forwards pkts to TOE */ 1995 #define OCE_WQ_TYPE_STANDARD 0x2 /* wq sends network pkts */ 1996 struct mbx_create_nic_wq { 1997 struct mbx_hdr hdr; 1998 union { 1999 struct { 2000 uint8_t num_pages; 2001 uint8_t ulp_num; 2002 uint16_t nic_wq_type; 2003 uint16_t if_id; 2004 uint8_t wq_size; 2005 uint8_t rsvd1; 2006 uint32_t rsvd2; 2007 uint16_t cq_id; 2008 uint16_t rsvd3; 2009 uint32_t rsvd4[13]; 2010 struct oce_pa pages[8]; 2011 } req; 2012 2013 struct { 2014 uint16_t wq_id; 2015 uint16_t rid; 2016 uint32_t db_offset; 2017 uint8_t tc_id; 2018 uint8_t rsvd0[3]; 2019 } rsp; 2020 } params; 2021 } __packed; 2022 2023 /* [09] NIC_DELETE_WQ */ 2024 struct mbx_delete_nic_wq { 2025 /* dw0 - dw3 */ 2026 struct mbx_hdr hdr; 2027 union { 2028 struct { 2029 #if _BYTE_ORDER == BIG_ENDIAN 2030 /* dw4 */ 2031 uint16_t rsvd0; 2032 uint16_t wq_id; 2033 #else 2034 /* dw4 */ 2035 uint16_t wq_id; 2036 uint16_t rsvd0; 2037 #endif 2038 } req; 2039 struct { 2040 uint32_t rsvd0; 2041 } rsp; 2042 } params; 2043 } __packed; 2044 2045 struct mbx_create_nic_rq { 2046 struct mbx_hdr hdr; 2047 union { 2048 struct { 2049 uint16_t cq_id; 2050 uint8_t frag_size; 2051 uint8_t num_pages; 2052 struct oce_pa pages[2]; 2053 uint32_t if_id; 2054 uint16_t max_frame_size; 2055 uint16_t page_size; 2056 uint32_t is_rss_queue; 2057 } req; 2058 2059 struct { 2060 uint16_t rq_id; 2061 uint8_t rss_cpuid; 2062 uint8_t rsvd0; 2063 } rsp; 2064 } params; 2065 } __packed; 2066 2067 /* [10] NIC_DELETE_RQ */ 2068 struct mbx_delete_nic_rq { 2069 /* dw0 - dw3 */ 2070 struct mbx_hdr hdr; 2071 union { 2072 struct { 2073 #if _BYTE_ORDER == BIG_ENDIAN 2074 /* dw4 */ 2075 uint16_t bypass_flush; 2076 uint16_t rq_id; 2077 #else 2078 /* dw4 */ 2079 uint16_t rq_id; 2080 uint16_t bypass_flush; 2081 #endif 2082 } req; 2083 2084 struct { 2085 /* dw4 */ 2086 uint32_t rsvd0; 2087 } rsp; 2088 } params; 2089 } __packed; 2090 2091 struct oce_port_rxf_stats_v0 { 2092 uint32_t rx_bytes_lsd; /* dword 0*/ 2093 uint32_t rx_bytes_msd; /* dword 1*/ 2094 uint32_t rx_total_frames; /* dword 2*/ 2095 uint32_t rx_unicast_frames; /* dword 3*/ 2096 uint32_t rx_multicast_frames; /* dword 4*/ 2097 uint32_t rx_broadcast_frames; /* dword 5*/ 2098 uint32_t rx_crc_errors; /* dword 6*/ 2099 uint32_t rx_alignment_symbol_errors; /* dword 7*/ 2100 uint32_t rx_pause_frames; /* dword 8*/ 2101 uint32_t rx_control_frames; /* dword 9*/ 2102 uint32_t rx_in_range_errors; /* dword 10*/ 2103 uint32_t rx_out_range_errors; /* dword 11*/ 2104 uint32_t rx_frame_too_long; /* dword 12*/ 2105 uint32_t rx_address_match_errors; /* dword 13*/ 2106 uint32_t rx_vlan_mismatch; /* dword 14*/ 2107 uint32_t rx_dropped_too_small; /* dword 15*/ 2108 uint32_t rx_dropped_too_short; /* dword 16*/ 2109 uint32_t rx_dropped_header_too_small; /* dword 17*/ 2110 uint32_t rx_dropped_tcp_length; /* dword 18*/ 2111 uint32_t rx_dropped_runt; /* dword 19*/ 2112 uint32_t rx_64_byte_packets; /* dword 20*/ 2113 uint32_t rx_65_127_byte_packets; /* dword 21*/ 2114 uint32_t rx_128_256_byte_packets; /* dword 22*/ 2115 uint32_t rx_256_511_byte_packets; /* dword 23*/ 2116 uint32_t rx_512_1023_byte_packets; /* dword 24*/ 2117 uint32_t rx_1024_1518_byte_packets; /* dword 25*/ 2118 uint32_t rx_1519_2047_byte_packets; /* dword 26*/ 2119 uint32_t rx_2048_4095_byte_packets; /* dword 27*/ 2120 uint32_t rx_4096_8191_byte_packets; /* dword 28*/ 2121 uint32_t rx_8192_9216_byte_packets; /* dword 29*/ 2122 uint32_t rx_ip_checksum_errs; /* dword 30*/ 2123 uint32_t rx_tcp_checksum_errs; /* dword 31*/ 2124 uint32_t rx_udp_checksum_errs; /* dword 32*/ 2125 uint32_t rx_non_rss_packets; /* dword 33*/ 2126 uint32_t rx_ipv4_packets; /* dword 34*/ 2127 uint32_t rx_ipv6_packets; /* dword 35*/ 2128 uint32_t rx_ipv4_bytes_lsd; /* dword 36*/ 2129 uint32_t rx_ipv4_bytes_msd; /* dword 37*/ 2130 uint32_t rx_ipv6_bytes_lsd; /* dword 38*/ 2131 uint32_t rx_ipv6_bytes_msd; /* dword 39*/ 2132 uint32_t rx_chute1_packets; /* dword 40*/ 2133 uint32_t rx_chute2_packets; /* dword 41*/ 2134 uint32_t rx_chute3_packets; /* dword 42*/ 2135 uint32_t rx_management_packets; /* dword 43*/ 2136 uint32_t rx_switched_unicast_packets; /* dword 44*/ 2137 uint32_t rx_switched_multicast_packets; /* dword 45*/ 2138 uint32_t rx_switched_broadcast_packets; /* dword 46*/ 2139 uint32_t tx_bytes_lsd; /* dword 47*/ 2140 uint32_t tx_bytes_msd; /* dword 48*/ 2141 uint32_t tx_unicastframes; /* dword 49*/ 2142 uint32_t tx_multicastframes; /* dword 50*/ 2143 uint32_t tx_broadcastframes; /* dword 51*/ 2144 uint32_t tx_pauseframes; /* dword 52*/ 2145 uint32_t tx_controlframes; /* dword 53*/ 2146 uint32_t tx_64_byte_packets; /* dword 54*/ 2147 uint32_t tx_65_127_byte_packets; /* dword 55*/ 2148 uint32_t tx_128_256_byte_packets; /* dword 56*/ 2149 uint32_t tx_256_511_byte_packets; /* dword 57*/ 2150 uint32_t tx_512_1023_byte_packets; /* dword 58*/ 2151 uint32_t tx_1024_1518_byte_packets; /* dword 59*/ 2152 uint32_t tx_1519_2047_byte_packets; /* dword 60*/ 2153 uint32_t tx_2048_4095_byte_packets; /* dword 61*/ 2154 uint32_t tx_4096_8191_byte_packets; /* dword 62*/ 2155 uint32_t tx_8192_9216_byte_packets; /* dword 63*/ 2156 uint32_t rxpp_fifo_overflow_drop; /* dword 64*/ 2157 uint32_t rx_input_fifo_overflow_drop; /* dword 65*/ 2158 } __packed; 2159 2160 struct oce_rxf_stats_v0 { 2161 struct oce_port_rxf_stats_v0 port[2]; 2162 uint32_t rx_drops_no_pbuf; /* dword 132*/ 2163 uint32_t rx_drops_no_txpb; /* dword 133*/ 2164 uint32_t rx_drops_no_erx_descr; /* dword 134*/ 2165 uint32_t rx_drops_no_tpre_descr; /* dword 135*/ 2166 uint32_t management_rx_port_packets; /* dword 136*/ 2167 uint32_t management_rx_port_bytes; /* dword 137*/ 2168 uint32_t management_rx_port_pause_frames;/* dword 138*/ 2169 uint32_t management_rx_port_errors; /* dword 139*/ 2170 uint32_t management_tx_port_packets; /* dword 140*/ 2171 uint32_t management_tx_port_bytes; /* dword 141*/ 2172 uint32_t management_tx_port_pause; /* dword 142*/ 2173 uint32_t management_rx_port_rxfifo_overflow; /* dword 143*/ 2174 uint32_t rx_drops_too_many_frags; /* dword 144*/ 2175 uint32_t rx_drops_invalid_ring; /* dword 145*/ 2176 uint32_t forwarded_packets; /* dword 146*/ 2177 uint32_t rx_drops_mtu; /* dword 147*/ 2178 uint32_t rsvd0[7]; 2179 uint32_t port0_jabber_events; 2180 uint32_t port1_jabber_events; 2181 uint32_t rsvd1[6]; 2182 } __packed; 2183 2184 struct oce_port_rxf_stats_v1 { 2185 uint32_t rsvd0[12]; 2186 uint32_t rx_crc_errors; 2187 uint32_t rx_alignment_symbol_errors; 2188 uint32_t rx_pause_frames; 2189 uint32_t rx_priority_pause_frames; 2190 uint32_t rx_control_frames; 2191 uint32_t rx_in_range_errors; 2192 uint32_t rx_out_range_errors; 2193 uint32_t rx_frame_too_long; 2194 uint32_t rx_address_match_errors; 2195 uint32_t rx_dropped_too_small; 2196 uint32_t rx_dropped_too_short; 2197 uint32_t rx_dropped_header_too_small; 2198 uint32_t rx_dropped_tcp_length; 2199 uint32_t rx_dropped_runt; 2200 uint32_t rsvd1[10]; 2201 uint32_t rx_ip_checksum_errs; 2202 uint32_t rx_tcp_checksum_errs; 2203 uint32_t rx_udp_checksum_errs; 2204 uint32_t rsvd2[7]; 2205 uint32_t rx_switched_unicast_packets; 2206 uint32_t rx_switched_multicast_packets; 2207 uint32_t rx_switched_broadcast_packets; 2208 uint32_t rsvd3[3]; 2209 uint32_t tx_pauseframes; 2210 uint32_t tx_priority_pauseframes; 2211 uint32_t tx_controlframes; 2212 uint32_t rsvd4[10]; 2213 uint32_t rxpp_fifo_overflow_drop; 2214 uint32_t rx_input_fifo_overflow_drop; 2215 uint32_t pmem_fifo_overflow_drop; 2216 uint32_t jabber_events; 2217 uint32_t rsvd5[3]; 2218 } __packed; 2219 2220 struct oce_rxf_stats_v1 { 2221 struct oce_port_rxf_stats_v1 port[4]; 2222 uint32_t rsvd0[2]; 2223 uint32_t rx_drops_no_pbuf; 2224 uint32_t rx_drops_no_txpb; 2225 uint32_t rx_drops_no_erx_descr; 2226 uint32_t rx_drops_no_tpre_descr; 2227 uint32_t rsvd1[6]; 2228 uint32_t rx_drops_too_many_frags; 2229 uint32_t rx_drops_invalid_ring; 2230 uint32_t forwarded_packets; 2231 uint32_t rx_drops_mtu; 2232 uint32_t rsvd2[14]; 2233 } __packed; 2234 2235 struct oce_erx_stats_v1 { 2236 uint32_t rx_drops_no_fragments[68]; 2237 uint32_t rsvd[4]; 2238 } __packed; 2239 2240 2241 struct oce_erx_stats_v0 { 2242 uint32_t rx_drops_no_fragments[44]; 2243 uint32_t rsvd[4]; 2244 } __packed; 2245 2246 struct oce_pmem_stats { 2247 uint32_t eth_red_drops; 2248 uint32_t rsvd[5]; 2249 } __packed; 2250 2251 struct oce_hw_stats_v1 { 2252 struct oce_rxf_stats_v1 rxf; 2253 uint32_t rsvd0[OCE_TXP_SW_SZ]; 2254 struct oce_erx_stats_v1 erx; 2255 struct oce_pmem_stats pmem; 2256 uint32_t rsvd1[18]; 2257 } __packed; 2258 2259 struct oce_hw_stats_v0 { 2260 struct oce_rxf_stats_v0 rxf; 2261 uint32_t rsvd[48]; 2262 struct oce_erx_stats_v0 erx; 2263 struct oce_pmem_stats pmem; 2264 } __packed; 2265 2266 struct mbx_get_nic_stats_v0 { 2267 struct mbx_hdr hdr; 2268 union { 2269 struct { 2270 uint32_t rsvd0; 2271 } req; 2272 2273 union { 2274 struct oce_hw_stats_v0 stats; 2275 } rsp; 2276 } params; 2277 } __packed; 2278 2279 struct mbx_get_nic_stats { 2280 struct mbx_hdr hdr; 2281 union { 2282 struct { 2283 uint32_t rsvd0; 2284 } req; 2285 2286 struct { 2287 struct oce_hw_stats_v1 stats; 2288 } rsp; 2289 } params; 2290 } __packed; 2291 2292 /* [18(0x12)] NIC_GET_PPORT_STATS */ 2293 struct oce_pport_stats { 2294 uint64_t tx_pkts; 2295 uint64_t tx_unicast_pkts; 2296 uint64_t tx_multicast_pkts; 2297 uint64_t tx_broadcast_pkts; 2298 uint64_t tx_bytes; 2299 uint64_t tx_unicast_bytes; 2300 uint64_t tx_multicast_bytes; 2301 uint64_t tx_broadcast_bytes; 2302 uint64_t tx_discards; 2303 uint64_t tx_errors; 2304 uint64_t tx_pause_frames; 2305 uint64_t tx_pause_on_frames; 2306 uint64_t tx_pause_off_frames; 2307 uint64_t tx_internal_mac_errors; 2308 uint64_t tx_control_frames; 2309 uint64_t tx_pkts_64_bytes; 2310 uint64_t tx_pkts_65_to_127_bytes; 2311 uint64_t tx_pkts_128_to_255_bytes; 2312 uint64_t tx_pkts_256_to_511_bytes; 2313 uint64_t tx_pkts_512_to_1023_bytes; 2314 uint64_t tx_pkts_1024_to_1518_bytes; 2315 uint64_t tx_pkts_1519_to_2047_bytes; 2316 uint64_t tx_pkts_2048_to_4095_bytes; 2317 uint64_t tx_pkts_4096_to_8191_bytes; 2318 uint64_t tx_pkts_8192_to_9216_bytes; 2319 uint64_t tx_lso_pkts; 2320 uint64_t rx_pkts; 2321 uint64_t rx_unicast_pkts; 2322 uint64_t rx_multicast_pkts; 2323 uint64_t rx_broadcast_pkts; 2324 uint64_t rx_bytes; 2325 uint64_t rx_unicast_bytes; 2326 uint64_t rx_multicast_bytes; 2327 uint64_t rx_broadcast_bytes; 2328 uint32_t rx_unknown_protos; 2329 uint32_t reserved_word69; 2330 uint64_t rx_discards; 2331 uint64_t rx_errors; 2332 uint64_t rx_crc_errors; 2333 uint64_t rx_alignment_errors; 2334 uint64_t rx_symbol_errors; 2335 uint64_t rx_pause_frames; 2336 uint64_t rx_pause_on_frames; 2337 uint64_t rx_pause_off_frames; 2338 uint64_t rx_frames_too_long; 2339 uint64_t rx_internal_mac_errors; 2340 uint32_t rx_undersize_pkts; 2341 uint32_t rx_oversize_pkts; 2342 uint32_t rx_fragment_pkts; 2343 uint32_t rx_jabbers; 2344 uint64_t rx_control_frames; 2345 uint64_t rx_control_frames_unknown_opcode; 2346 uint32_t rx_in_range_errors; 2347 uint32_t rx_out_of_range_errors; 2348 uint32_t rx_address_match_errors; 2349 uint32_t rx_vlan_mismatch_errors; 2350 uint32_t rx_dropped_too_small; 2351 uint32_t rx_dropped_too_short; 2352 uint32_t rx_dropped_header_too_small; 2353 uint32_t rx_dropped_invalid_tcp_length; 2354 uint32_t rx_dropped_runt; 2355 uint32_t rx_ip_checksum_errors; 2356 uint32_t rx_tcp_checksum_errors; 2357 uint32_t rx_udp_checksum_errors; 2358 uint32_t rx_non_rss_pkts; 2359 uint64_t reserved_word111; 2360 uint64_t rx_ipv4_pkts; 2361 uint64_t rx_ipv6_pkts; 2362 uint64_t rx_ipv4_bytes; 2363 uint64_t rx_ipv6_bytes; 2364 uint64_t rx_nic_pkts; 2365 uint64_t rx_tcp_pkts; 2366 uint64_t rx_iscsi_pkts; 2367 uint64_t rx_management_pkts; 2368 uint64_t rx_switched_unicast_pkts; 2369 uint64_t rx_switched_multicast_pkts; 2370 uint64_t rx_switched_broadcast_pkts; 2371 uint64_t num_forwards; 2372 uint32_t rx_fifo_overflow; 2373 uint32_t rx_input_fifo_overflow; 2374 uint64_t rx_drops_too_many_frags; 2375 uint32_t rx_drops_invalid_queue; 2376 uint32_t reserved_word141; 2377 uint64_t rx_drops_mtu; 2378 uint64_t rx_pkts_64_bytes; 2379 uint64_t rx_pkts_65_to_127_bytes; 2380 uint64_t rx_pkts_128_to_255_bytes; 2381 uint64_t rx_pkts_256_to_511_bytes; 2382 uint64_t rx_pkts_512_to_1023_bytes; 2383 uint64_t rx_pkts_1024_to_1518_bytes; 2384 uint64_t rx_pkts_1519_to_2047_bytes; 2385 uint64_t rx_pkts_2048_to_4095_bytes; 2386 uint64_t rx_pkts_4096_to_8191_bytes; 2387 uint64_t rx_pkts_8192_to_9216_bytes; 2388 } __packed; 2389 2390 struct mbx_get_pport_stats { 2391 /* dw0 - dw3 */ 2392 struct mbx_hdr hdr; 2393 union { 2394 struct { 2395 /* dw4 */ 2396 #if _BYTE_ORDER == BIG_ENDIAN 2397 uint32_t reset_stats:8; 2398 uint32_t rsvd0:8; 2399 uint32_t port_number:16; 2400 #else 2401 uint32_t port_number:16; 2402 uint32_t rsvd0:8; 2403 uint32_t reset_stats:8; 2404 #endif 2405 } req; 2406 2407 union { 2408 struct oce_pport_stats pps; 2409 uint32_t pport_stats[164 - 4 + 1]; 2410 } rsp; 2411 } params; 2412 } __packed; 2413 2414 /* [19(0x13)] NIC_GET_VPORT_STATS */ 2415 struct oce_vport_stats { 2416 uint64_t tx_pkts; 2417 uint64_t tx_unicast_pkts; 2418 uint64_t tx_multicast_pkts; 2419 uint64_t tx_broadcast_pkts; 2420 uint64_t tx_bytes; 2421 uint64_t tx_unicast_bytes; 2422 uint64_t tx_multicast_bytes; 2423 uint64_t tx_broadcast_bytes; 2424 uint64_t tx_discards; 2425 uint64_t tx_errors; 2426 uint64_t tx_pkts_64_bytes; 2427 uint64_t tx_pkts_65_to_127_bytes; 2428 uint64_t tx_pkts_128_to_255_bytes; 2429 uint64_t tx_pkts_256_to_511_bytes; 2430 uint64_t tx_pkts_512_to_1023_bytes; 2431 uint64_t tx_pkts_1024_to_1518_bytes; 2432 uint64_t tx_pkts_1519_to_9699_bytes; 2433 uint64_t tx_pkts_over_9699_bytes; 2434 uint64_t rx_pkts; 2435 uint64_t rx_unicast_pkts; 2436 uint64_t rx_multicast_pkts; 2437 uint64_t rx_broadcast_pkts; 2438 uint64_t rx_bytes; 2439 uint64_t rx_unicast_bytes; 2440 uint64_t rx_multicast_bytes; 2441 uint64_t rx_broadcast_bytes; 2442 uint64_t rx_discards; 2443 uint64_t rx_errors; 2444 uint64_t rx_pkts_64_bytes; 2445 uint64_t rx_pkts_65_to_127_bytes; 2446 uint64_t rx_pkts_128_to_255_bytes; 2447 uint64_t rx_pkts_256_to_511_bytes; 2448 uint64_t rx_pkts_512_to_1023_bytes; 2449 uint64_t rx_pkts_1024_to_1518_bytes; 2450 uint64_t rx_pkts_1519_to_9699_bytes; 2451 uint64_t rx_pkts_gt_9699_bytes; 2452 } __packed; 2453 struct mbx_get_vport_stats { 2454 /* dw0 - dw3 */ 2455 struct mbx_hdr hdr; 2456 union { 2457 struct { 2458 /* dw4 */ 2459 #if _BYTE_ORDER == BIG_ENDIAN 2460 uint32_t reset_stats:8; 2461 uint32_t rsvd0:8; 2462 uint32_t vport_number:16; 2463 #else 2464 uint32_t vport_number:16; 2465 uint32_t rsvd0:8; 2466 uint32_t reset_stats:8; 2467 #endif 2468 } req; 2469 2470 union { 2471 struct oce_vport_stats vps; 2472 uint32_t vport_stats[75 - 4 + 1]; 2473 } rsp; 2474 } params; 2475 } __packed; 2476 2477 /* Hash option flags for RSS enable */ 2478 enum RSS_ENABLE_FLAGS { 2479 RSS_ENABLE_NONE = 0x0, /* (No RSS) */ 2480 RSS_ENABLE_IPV4 = 0x1, /* (IPV4 HASH enabled ) */ 2481 RSS_ENABLE_TCP_IPV4 = 0x2, /* (TCP IPV4 Hash enabled) */ 2482 RSS_ENABLE_IPV6 = 0x4, /* (IPV6 HASH enabled) */ 2483 RSS_ENABLE_TCP_IPV6 = 0x8 /* (TCP IPV6 HASH */ 2484 }; 2485 2486 /* [01] NIC_CONFIG_RSS */ 2487 #define OCE_HASH_TBL_SZ 10 2488 #define OCE_CPU_TBL_SZ 128 2489 #define OCE_FLUSH 1 /* RSS flush completion per CQ port */ 2490 struct mbx_config_nic_rss { 2491 struct mbx_hdr hdr; 2492 union { 2493 struct { 2494 #if _BYTE_ORDER == BIG_ENDIAN 2495 uint32_t if_id; 2496 uint16_t cpu_tbl_sz_log2; 2497 uint16_t enable_rss; 2498 uint32_t hash[OCE_HASH_TBL_SZ]; 2499 uint8_t cputable[OCE_CPU_TBL_SZ]; 2500 uint8_t rsvd[3]; 2501 uint8_t flush; 2502 #else 2503 uint32_t if_id; 2504 uint16_t enable_rss; 2505 uint16_t cpu_tbl_sz_log2; 2506 uint32_t hash[OCE_HASH_TBL_SZ]; 2507 uint8_t cputable[OCE_CPU_TBL_SZ]; 2508 uint8_t flush; 2509 uint8_t rsvd[3]; 2510 #endif 2511 } req; 2512 struct { 2513 uint8_t rsvd[3]; 2514 uint8_t rss_bank; 2515 } rsp; 2516 } params; 2517 } __packed; 2518