1 /* $OpenBSD: db_instruction.h,v 1.2 2021/05/12 01:24:32 jsg Exp $ */ 2 3 /* 4 * https://github.com/riscv/riscv-opcodes 5 * 7d1a0e3153c37cd180be9e95f331f32c225d9257 6 * 7 * db_instruction.h: $(ALL_OPCODES) parse_opcodes 8 * cat $(ALL_OPCODES) | python3 ./parse_opcodes -c > $@ 9 */ 10 11 /* Automatically generated by parse_opcodes. */ 12 #ifndef RISCV_ENCODING_H 13 #define RISCV_ENCODING_H 14 #define MATCH_SLLI_RV32 0x1013 15 #define MASK_SLLI_RV32 0xfe00707f 16 #define MATCH_SRLI_RV32 0x5013 17 #define MASK_SRLI_RV32 0xfe00707f 18 #define MATCH_SRAI_RV32 0x40005013 19 #define MASK_SRAI_RV32 0xfe00707f 20 #define MATCH_FRFLAGS 0x102073 21 #define MASK_FRFLAGS 0xfffff07f 22 #define MATCH_FSFLAGS 0x101073 23 #define MASK_FSFLAGS 0xfff0707f 24 #define MATCH_FSFLAGSI 0x105073 25 #define MASK_FSFLAGSI 0xfff0707f 26 #define MATCH_FRRM 0x202073 27 #define MASK_FRRM 0xfffff07f 28 #define MATCH_FSRM 0x201073 29 #define MASK_FSRM 0xfff0707f 30 #define MATCH_FSRMI 0x205073 31 #define MASK_FSRMI 0xfff0707f 32 #define MATCH_FSCSR 0x301073 33 #define MASK_FSCSR 0xfff0707f 34 #define MATCH_FRCSR 0x302073 35 #define MASK_FRCSR 0xfffff07f 36 #define MATCH_RDCYCLE 0xc0002073 37 #define MASK_RDCYCLE 0xfffff07f 38 #define MATCH_RDTIME 0xc0102073 39 #define MASK_RDTIME 0xfffff07f 40 #define MATCH_RDINSTRET 0xc0202073 41 #define MASK_RDINSTRET 0xfffff07f 42 #define MATCH_RDCYCLEH 0xc8002073 43 #define MASK_RDCYCLEH 0xfffff07f 44 #define MATCH_RDTIMEH 0xc8102073 45 #define MASK_RDTIMEH 0xfffff07f 46 #define MATCH_RDINSTRETH 0xc8202073 47 #define MASK_RDINSTRETH 0xfffff07f 48 #define MATCH_SCALL 0x73 49 #define MASK_SCALL 0xffffffff 50 #define MATCH_SBREAK 0x100073 51 #define MASK_SBREAK 0xffffffff 52 #define MATCH_FMV_X_S 0xe0000053 53 #define MASK_FMV_X_S 0xfff0707f 54 #define MATCH_FMV_S_X 0xf0000053 55 #define MASK_FMV_S_X 0xfff0707f 56 #define MATCH_FENCE_TSO 0x8330000f 57 #define MASK_FENCE_TSO 0xfff0707f 58 #define MATCH_PAUSE 0x100000f 59 #define MASK_PAUSE 0xffffffff 60 #define MATCH_BEQ 0x63 61 #define MASK_BEQ 0x707f 62 #define MATCH_BNE 0x1063 63 #define MASK_BNE 0x707f 64 #define MATCH_BLT 0x4063 65 #define MASK_BLT 0x707f 66 #define MATCH_BGE 0x5063 67 #define MASK_BGE 0x707f 68 #define MATCH_BLTU 0x6063 69 #define MASK_BLTU 0x707f 70 #define MATCH_BGEU 0x7063 71 #define MASK_BGEU 0x707f 72 #define MATCH_JALR 0x67 73 #define MASK_JALR 0x707f 74 #define MATCH_JAL 0x6f 75 #define MASK_JAL 0x7f 76 #define MATCH_LUI 0x37 77 #define MASK_LUI 0x7f 78 #define MATCH_AUIPC 0x17 79 #define MASK_AUIPC 0x7f 80 #define MATCH_ADDI 0x13 81 #define MASK_ADDI 0x707f 82 #define MATCH_SLLI 0x1013 83 #define MASK_SLLI 0xfc00707f 84 #define MATCH_SLTI 0x2013 85 #define MASK_SLTI 0x707f 86 #define MATCH_SLTIU 0x3013 87 #define MASK_SLTIU 0x707f 88 #define MATCH_XORI 0x4013 89 #define MASK_XORI 0x707f 90 #define MATCH_SRLI 0x5013 91 #define MASK_SRLI 0xfc00707f 92 #define MATCH_SRAI 0x40005013 93 #define MASK_SRAI 0xfc00707f 94 #define MATCH_ORI 0x6013 95 #define MASK_ORI 0x707f 96 #define MATCH_ANDI 0x7013 97 #define MASK_ANDI 0x707f 98 #define MATCH_ADD 0x33 99 #define MASK_ADD 0xfe00707f 100 #define MATCH_SUB 0x40000033 101 #define MASK_SUB 0xfe00707f 102 #define MATCH_SLL 0x1033 103 #define MASK_SLL 0xfe00707f 104 #define MATCH_SLT 0x2033 105 #define MASK_SLT 0xfe00707f 106 #define MATCH_SLTU 0x3033 107 #define MASK_SLTU 0xfe00707f 108 #define MATCH_XOR 0x4033 109 #define MASK_XOR 0xfe00707f 110 #define MATCH_SRL 0x5033 111 #define MASK_SRL 0xfe00707f 112 #define MATCH_SRA 0x40005033 113 #define MASK_SRA 0xfe00707f 114 #define MATCH_OR 0x6033 115 #define MASK_OR 0xfe00707f 116 #define MATCH_AND 0x7033 117 #define MASK_AND 0xfe00707f 118 #define MATCH_LB 0x3 119 #define MASK_LB 0x707f 120 #define MATCH_LH 0x1003 121 #define MASK_LH 0x707f 122 #define MATCH_LW 0x2003 123 #define MASK_LW 0x707f 124 #define MATCH_LBU 0x4003 125 #define MASK_LBU 0x707f 126 #define MATCH_LHU 0x5003 127 #define MASK_LHU 0x707f 128 #define MATCH_SB 0x23 129 #define MASK_SB 0x707f 130 #define MATCH_SH 0x1023 131 #define MASK_SH 0x707f 132 #define MATCH_SW 0x2023 133 #define MASK_SW 0x707f 134 #define MATCH_FENCE 0xf 135 #define MASK_FENCE 0x707f 136 #define MATCH_FENCE_I 0x100f 137 #define MASK_FENCE_I 0x707f 138 #define MATCH_ADDIW 0x1b 139 #define MASK_ADDIW 0x707f 140 #define MATCH_SLLIW 0x101b 141 #define MASK_SLLIW 0xfe00707f 142 #define MATCH_SRLIW 0x501b 143 #define MASK_SRLIW 0xfe00707f 144 #define MATCH_SRAIW 0x4000501b 145 #define MASK_SRAIW 0xfe00707f 146 #define MATCH_ADDW 0x3b 147 #define MASK_ADDW 0xfe00707f 148 #define MATCH_SUBW 0x4000003b 149 #define MASK_SUBW 0xfe00707f 150 #define MATCH_SLLW 0x103b 151 #define MASK_SLLW 0xfe00707f 152 #define MATCH_SRLW 0x503b 153 #define MASK_SRLW 0xfe00707f 154 #define MATCH_SRAW 0x4000503b 155 #define MASK_SRAW 0xfe00707f 156 #define MATCH_LD 0x3003 157 #define MASK_LD 0x707f 158 #define MATCH_LWU 0x6003 159 #define MASK_LWU 0x707f 160 #define MATCH_SD 0x3023 161 #define MASK_SD 0x707f 162 #define MATCH_MUL 0x2000033 163 #define MASK_MUL 0xfe00707f 164 #define MATCH_MULH 0x2001033 165 #define MASK_MULH 0xfe00707f 166 #define MATCH_MULHSU 0x2002033 167 #define MASK_MULHSU 0xfe00707f 168 #define MATCH_MULHU 0x2003033 169 #define MASK_MULHU 0xfe00707f 170 #define MATCH_DIV 0x2004033 171 #define MASK_DIV 0xfe00707f 172 #define MATCH_DIVU 0x2005033 173 #define MASK_DIVU 0xfe00707f 174 #define MATCH_REM 0x2006033 175 #define MASK_REM 0xfe00707f 176 #define MATCH_REMU 0x2007033 177 #define MASK_REMU 0xfe00707f 178 #define MATCH_MULW 0x200003b 179 #define MASK_MULW 0xfe00707f 180 #define MATCH_DIVW 0x200403b 181 #define MASK_DIVW 0xfe00707f 182 #define MATCH_DIVUW 0x200503b 183 #define MASK_DIVUW 0xfe00707f 184 #define MATCH_REMW 0x200603b 185 #define MASK_REMW 0xfe00707f 186 #define MATCH_REMUW 0x200703b 187 #define MASK_REMUW 0xfe00707f 188 #define MATCH_AMOADD_W 0x202f 189 #define MASK_AMOADD_W 0xf800707f 190 #define MATCH_AMOXOR_W 0x2000202f 191 #define MASK_AMOXOR_W 0xf800707f 192 #define MATCH_AMOOR_W 0x4000202f 193 #define MASK_AMOOR_W 0xf800707f 194 #define MATCH_AMOAND_W 0x6000202f 195 #define MASK_AMOAND_W 0xf800707f 196 #define MATCH_AMOMIN_W 0x8000202f 197 #define MASK_AMOMIN_W 0xf800707f 198 #define MATCH_AMOMAX_W 0xa000202f 199 #define MASK_AMOMAX_W 0xf800707f 200 #define MATCH_AMOMINU_W 0xc000202f 201 #define MASK_AMOMINU_W 0xf800707f 202 #define MATCH_AMOMAXU_W 0xe000202f 203 #define MASK_AMOMAXU_W 0xf800707f 204 #define MATCH_AMOSWAP_W 0x800202f 205 #define MASK_AMOSWAP_W 0xf800707f 206 #define MATCH_LR_W 0x1000202f 207 #define MASK_LR_W 0xf9f0707f 208 #define MATCH_SC_W 0x1800202f 209 #define MASK_SC_W 0xf800707f 210 #define MATCH_AMOADD_D 0x302f 211 #define MASK_AMOADD_D 0xf800707f 212 #define MATCH_AMOXOR_D 0x2000302f 213 #define MASK_AMOXOR_D 0xf800707f 214 #define MATCH_AMOOR_D 0x4000302f 215 #define MASK_AMOOR_D 0xf800707f 216 #define MATCH_AMOAND_D 0x6000302f 217 #define MASK_AMOAND_D 0xf800707f 218 #define MATCH_AMOMIN_D 0x8000302f 219 #define MASK_AMOMIN_D 0xf800707f 220 #define MATCH_AMOMAX_D 0xa000302f 221 #define MASK_AMOMAX_D 0xf800707f 222 #define MATCH_AMOMINU_D 0xc000302f 223 #define MASK_AMOMINU_D 0xf800707f 224 #define MATCH_AMOMAXU_D 0xe000302f 225 #define MASK_AMOMAXU_D 0xf800707f 226 #define MATCH_AMOSWAP_D 0x800302f 227 #define MASK_AMOSWAP_D 0xf800707f 228 #define MATCH_LR_D 0x1000302f 229 #define MASK_LR_D 0xf9f0707f 230 #define MATCH_SC_D 0x1800302f 231 #define MASK_SC_D 0xf800707f 232 #define MATCH_HFENCE_VVMA 0x22000073 233 #define MASK_HFENCE_VVMA 0xfe007fff 234 #define MATCH_HFENCE_GVMA 0x62000073 235 #define MASK_HFENCE_GVMA 0xfe007fff 236 #define MATCH_HLV_B 0x60004073 237 #define MASK_HLV_B 0xfff0707f 238 #define MATCH_HLV_BU 0x60104073 239 #define MASK_HLV_BU 0xfff0707f 240 #define MATCH_HLV_H 0x64004073 241 #define MASK_HLV_H 0xfff0707f 242 #define MATCH_HLV_HU 0x64104073 243 #define MASK_HLV_HU 0xfff0707f 244 #define MATCH_HLVX_HU 0x64304073 245 #define MASK_HLVX_HU 0xfff0707f 246 #define MATCH_HLV_W 0x68004073 247 #define MASK_HLV_W 0xfff0707f 248 #define MATCH_HLVX_WU 0x68304073 249 #define MASK_HLVX_WU 0xfff0707f 250 #define MATCH_HSV_B 0x62004073 251 #define MASK_HSV_B 0xfe007fff 252 #define MATCH_HSV_H 0x66004073 253 #define MASK_HSV_H 0xfe007fff 254 #define MATCH_HSV_W 0x6a004073 255 #define MASK_HSV_W 0xfe007fff 256 #define MATCH_HLV_WU 0x68104073 257 #define MASK_HLV_WU 0xfff0707f 258 #define MATCH_HLV_D 0x6c004073 259 #define MASK_HLV_D 0xfff0707f 260 #define MATCH_HSV_D 0x6e004073 261 #define MASK_HSV_D 0xfe007fff 262 #define MATCH_FADD_S 0x53 263 #define MASK_FADD_S 0xfe00007f 264 #define MATCH_FSUB_S 0x8000053 265 #define MASK_FSUB_S 0xfe00007f 266 #define MATCH_FMUL_S 0x10000053 267 #define MASK_FMUL_S 0xfe00007f 268 #define MATCH_FDIV_S 0x18000053 269 #define MASK_FDIV_S 0xfe00007f 270 #define MATCH_FSGNJ_S 0x20000053 271 #define MASK_FSGNJ_S 0xfe00707f 272 #define MATCH_FSGNJN_S 0x20001053 273 #define MASK_FSGNJN_S 0xfe00707f 274 #define MATCH_FSGNJX_S 0x20002053 275 #define MASK_FSGNJX_S 0xfe00707f 276 #define MATCH_FMIN_S 0x28000053 277 #define MASK_FMIN_S 0xfe00707f 278 #define MATCH_FMAX_S 0x28001053 279 #define MASK_FMAX_S 0xfe00707f 280 #define MATCH_FSQRT_S 0x58000053 281 #define MASK_FSQRT_S 0xfff0007f 282 #define MATCH_FLE_S 0xa0000053 283 #define MASK_FLE_S 0xfe00707f 284 #define MATCH_FLT_S 0xa0001053 285 #define MASK_FLT_S 0xfe00707f 286 #define MATCH_FEQ_S 0xa0002053 287 #define MASK_FEQ_S 0xfe00707f 288 #define MATCH_FCVT_W_S 0xc0000053 289 #define MASK_FCVT_W_S 0xfff0007f 290 #define MATCH_FCVT_WU_S 0xc0100053 291 #define MASK_FCVT_WU_S 0xfff0007f 292 #define MATCH_FMV_X_W 0xe0000053 293 #define MASK_FMV_X_W 0xfff0707f 294 #define MATCH_FCLASS_S 0xe0001053 295 #define MASK_FCLASS_S 0xfff0707f 296 #define MATCH_FCVT_S_W 0xd0000053 297 #define MASK_FCVT_S_W 0xfff0007f 298 #define MATCH_FCVT_S_WU 0xd0100053 299 #define MASK_FCVT_S_WU 0xfff0007f 300 #define MATCH_FMV_W_X 0xf0000053 301 #define MASK_FMV_W_X 0xfff0707f 302 #define MATCH_FLW 0x2007 303 #define MASK_FLW 0x707f 304 #define MATCH_FSW 0x2027 305 #define MASK_FSW 0x707f 306 #define MATCH_FMADD_S 0x43 307 #define MASK_FMADD_S 0x600007f 308 #define MATCH_FMSUB_S 0x47 309 #define MASK_FMSUB_S 0x600007f 310 #define MATCH_FNMSUB_S 0x4b 311 #define MASK_FNMSUB_S 0x600007f 312 #define MATCH_FNMADD_S 0x4f 313 #define MASK_FNMADD_S 0x600007f 314 #define MATCH_FCVT_L_S 0xc0200053 315 #define MASK_FCVT_L_S 0xfff0007f 316 #define MATCH_FCVT_LU_S 0xc0300053 317 #define MASK_FCVT_LU_S 0xfff0007f 318 #define MATCH_FCVT_S_L 0xd0200053 319 #define MASK_FCVT_S_L 0xfff0007f 320 #define MATCH_FCVT_S_LU 0xd0300053 321 #define MASK_FCVT_S_LU 0xfff0007f 322 #define MATCH_FADD_D 0x2000053 323 #define MASK_FADD_D 0xfe00007f 324 #define MATCH_FSUB_D 0xa000053 325 #define MASK_FSUB_D 0xfe00007f 326 #define MATCH_FMUL_D 0x12000053 327 #define MASK_FMUL_D 0xfe00007f 328 #define MATCH_FDIV_D 0x1a000053 329 #define MASK_FDIV_D 0xfe00007f 330 #define MATCH_FSGNJ_D 0x22000053 331 #define MASK_FSGNJ_D 0xfe00707f 332 #define MATCH_FSGNJN_D 0x22001053 333 #define MASK_FSGNJN_D 0xfe00707f 334 #define MATCH_FSGNJX_D 0x22002053 335 #define MASK_FSGNJX_D 0xfe00707f 336 #define MATCH_FMIN_D 0x2a000053 337 #define MASK_FMIN_D 0xfe00707f 338 #define MATCH_FMAX_D 0x2a001053 339 #define MASK_FMAX_D 0xfe00707f 340 #define MATCH_FCVT_S_D 0x40100053 341 #define MASK_FCVT_S_D 0xfff0007f 342 #define MATCH_FCVT_D_S 0x42000053 343 #define MASK_FCVT_D_S 0xfff0007f 344 #define MATCH_FSQRT_D 0x5a000053 345 #define MASK_FSQRT_D 0xfff0007f 346 #define MATCH_FLE_D 0xa2000053 347 #define MASK_FLE_D 0xfe00707f 348 #define MATCH_FLT_D 0xa2001053 349 #define MASK_FLT_D 0xfe00707f 350 #define MATCH_FEQ_D 0xa2002053 351 #define MASK_FEQ_D 0xfe00707f 352 #define MATCH_FCVT_W_D 0xc2000053 353 #define MASK_FCVT_W_D 0xfff0007f 354 #define MATCH_FCVT_WU_D 0xc2100053 355 #define MASK_FCVT_WU_D 0xfff0007f 356 #define MATCH_FCLASS_D 0xe2001053 357 #define MASK_FCLASS_D 0xfff0707f 358 #define MATCH_FCVT_D_W 0xd2000053 359 #define MASK_FCVT_D_W 0xfff0007f 360 #define MATCH_FCVT_D_WU 0xd2100053 361 #define MASK_FCVT_D_WU 0xfff0007f 362 #define MATCH_FLD 0x3007 363 #define MASK_FLD 0x707f 364 #define MATCH_FSD 0x3027 365 #define MASK_FSD 0x707f 366 #define MATCH_FMADD_D 0x2000043 367 #define MASK_FMADD_D 0x600007f 368 #define MATCH_FMSUB_D 0x2000047 369 #define MASK_FMSUB_D 0x600007f 370 #define MATCH_FNMSUB_D 0x200004b 371 #define MASK_FNMSUB_D 0x600007f 372 #define MATCH_FNMADD_D 0x200004f 373 #define MASK_FNMADD_D 0x600007f 374 #define MATCH_FCVT_L_D 0xc2200053 375 #define MASK_FCVT_L_D 0xfff0007f 376 #define MATCH_FCVT_LU_D 0xc2300053 377 #define MASK_FCVT_LU_D 0xfff0007f 378 #define MATCH_FMV_X_D 0xe2000053 379 #define MASK_FMV_X_D 0xfff0707f 380 #define MATCH_FCVT_D_L 0xd2200053 381 #define MASK_FCVT_D_L 0xfff0007f 382 #define MATCH_FCVT_D_LU 0xd2300053 383 #define MASK_FCVT_D_LU 0xfff0007f 384 #define MATCH_FMV_D_X 0xf2000053 385 #define MASK_FMV_D_X 0xfff0707f 386 #define MATCH_FADD_Q 0x6000053 387 #define MASK_FADD_Q 0xfe00007f 388 #define MATCH_FSUB_Q 0xe000053 389 #define MASK_FSUB_Q 0xfe00007f 390 #define MATCH_FMUL_Q 0x16000053 391 #define MASK_FMUL_Q 0xfe00007f 392 #define MATCH_FDIV_Q 0x1e000053 393 #define MASK_FDIV_Q 0xfe00007f 394 #define MATCH_FSGNJ_Q 0x26000053 395 #define MASK_FSGNJ_Q 0xfe00707f 396 #define MATCH_FSGNJN_Q 0x26001053 397 #define MASK_FSGNJN_Q 0xfe00707f 398 #define MATCH_FSGNJX_Q 0x26002053 399 #define MASK_FSGNJX_Q 0xfe00707f 400 #define MATCH_FMIN_Q 0x2e000053 401 #define MASK_FMIN_Q 0xfe00707f 402 #define MATCH_FMAX_Q 0x2e001053 403 #define MASK_FMAX_Q 0xfe00707f 404 #define MATCH_FCVT_S_Q 0x40300053 405 #define MASK_FCVT_S_Q 0xfff0007f 406 #define MATCH_FCVT_Q_S 0x46000053 407 #define MASK_FCVT_Q_S 0xfff0007f 408 #define MATCH_FCVT_D_Q 0x42300053 409 #define MASK_FCVT_D_Q 0xfff0007f 410 #define MATCH_FCVT_Q_D 0x46100053 411 #define MASK_FCVT_Q_D 0xfff0007f 412 #define MATCH_FSQRT_Q 0x5e000053 413 #define MASK_FSQRT_Q 0xfff0007f 414 #define MATCH_FLE_Q 0xa6000053 415 #define MASK_FLE_Q 0xfe00707f 416 #define MATCH_FLT_Q 0xa6001053 417 #define MASK_FLT_Q 0xfe00707f 418 #define MATCH_FEQ_Q 0xa6002053 419 #define MASK_FEQ_Q 0xfe00707f 420 #define MATCH_FCVT_W_Q 0xc6000053 421 #define MASK_FCVT_W_Q 0xfff0007f 422 #define MATCH_FCVT_WU_Q 0xc6100053 423 #define MASK_FCVT_WU_Q 0xfff0007f 424 #define MATCH_FCLASS_Q 0xe6001053 425 #define MASK_FCLASS_Q 0xfff0707f 426 #define MATCH_FCVT_Q_W 0xd6000053 427 #define MASK_FCVT_Q_W 0xfff0007f 428 #define MATCH_FCVT_Q_WU 0xd6100053 429 #define MASK_FCVT_Q_WU 0xfff0007f 430 #define MATCH_FLQ 0x4007 431 #define MASK_FLQ 0x707f 432 #define MATCH_FSQ 0x4027 433 #define MASK_FSQ 0x707f 434 #define MATCH_FMADD_Q 0x6000043 435 #define MASK_FMADD_Q 0x600007f 436 #define MATCH_FMSUB_Q 0x6000047 437 #define MASK_FMSUB_Q 0x600007f 438 #define MATCH_FNMSUB_Q 0x600004b 439 #define MASK_FNMSUB_Q 0x600007f 440 #define MATCH_FNMADD_Q 0x600004f 441 #define MASK_FNMADD_Q 0x600007f 442 #define MATCH_FCVT_L_Q 0xc6200053 443 #define MASK_FCVT_L_Q 0xfff0007f 444 #define MATCH_FCVT_LU_Q 0xc6300053 445 #define MASK_FCVT_LU_Q 0xfff0007f 446 #define MATCH_FCVT_Q_L 0xd6200053 447 #define MASK_FCVT_Q_L 0xfff0007f 448 #define MATCH_FCVT_Q_LU 0xd6300053 449 #define MASK_FCVT_Q_LU 0xfff0007f 450 #define MATCH_ANDN 0x40007033 451 #define MASK_ANDN 0xfe00707f 452 #define MATCH_ORN 0x40006033 453 #define MASK_ORN 0xfe00707f 454 #define MATCH_XNOR 0x40004033 455 #define MASK_XNOR 0xfe00707f 456 #define MATCH_SLO 0x20001033 457 #define MASK_SLO 0xfe00707f 458 #define MATCH_SRO 0x20005033 459 #define MASK_SRO 0xfe00707f 460 #define MATCH_ROL 0x60001033 461 #define MASK_ROL 0xfe00707f 462 #define MATCH_ROR 0x60005033 463 #define MASK_ROR 0xfe00707f 464 #define MATCH_BCLR 0x48001033 465 #define MASK_BCLR 0xfe00707f 466 #define MATCH_BSET 0x28001033 467 #define MASK_BSET 0xfe00707f 468 #define MATCH_BINV 0x68001033 469 #define MASK_BINV 0xfe00707f 470 #define MATCH_BEXT 0x48005033 471 #define MASK_BEXT 0xfe00707f 472 #define MATCH_GORC 0x28005033 473 #define MASK_GORC 0xfe00707f 474 #define MATCH_GREV 0x68005033 475 #define MASK_GREV 0xfe00707f 476 #define MATCH_SLOI 0x20001013 477 #define MASK_SLOI 0xfc00707f 478 #define MATCH_SROI 0x20005013 479 #define MASK_SROI 0xfc00707f 480 #define MATCH_RORI 0x60005013 481 #define MASK_RORI 0xfc00707f 482 #define MATCH_BCLRI 0x48001013 483 #define MASK_BCLRI 0xfc00707f 484 #define MATCH_BSETI 0x28001013 485 #define MASK_BSETI 0xfc00707f 486 #define MATCH_BINVI 0x68001013 487 #define MASK_BINVI 0xfc00707f 488 #define MATCH_BEXTI 0x48005013 489 #define MASK_BEXTI 0xfc00707f 490 #define MATCH_GORCI 0x28005013 491 #define MASK_GORCI 0xfc00707f 492 #define MATCH_GREVI 0x68005013 493 #define MASK_GREVI 0xfc00707f 494 #define MATCH_CMIX 0x6001033 495 #define MASK_CMIX 0x600707f 496 #define MATCH_CMOV 0x6005033 497 #define MASK_CMOV 0x600707f 498 #define MATCH_FSL 0x4001033 499 #define MASK_FSL 0x600707f 500 #define MATCH_FSR 0x4005033 501 #define MASK_FSR 0x600707f 502 #define MATCH_FSRI 0x4005013 503 #define MASK_FSRI 0x400707f 504 #define MATCH_CLZ 0x60001013 505 #define MASK_CLZ 0xfff0707f 506 #define MATCH_CTZ 0x60101013 507 #define MASK_CTZ 0xfff0707f 508 #define MATCH_CPOP 0x60201013 509 #define MASK_CPOP 0xfff0707f 510 #define MATCH_SEXT_B 0x60401013 511 #define MASK_SEXT_B 0xfff0707f 512 #define MATCH_SEXT_H 0x60501013 513 #define MASK_SEXT_H 0xfff0707f 514 #define MATCH_CRC32_B 0x61001013 515 #define MASK_CRC32_B 0xfff0707f 516 #define MATCH_CRC32_H 0x61101013 517 #define MASK_CRC32_H 0xfff0707f 518 #define MATCH_CRC32_W 0x61201013 519 #define MASK_CRC32_W 0xfff0707f 520 #define MATCH_CRC32C_B 0x61801013 521 #define MASK_CRC32C_B 0xfff0707f 522 #define MATCH_CRC32C_H 0x61901013 523 #define MASK_CRC32C_H 0xfff0707f 524 #define MATCH_CRC32C_W 0x61a01013 525 #define MASK_CRC32C_W 0xfff0707f 526 #define MATCH_SH1ADD 0x20002033 527 #define MASK_SH1ADD 0xfe00707f 528 #define MATCH_SH2ADD 0x20004033 529 #define MASK_SH2ADD 0xfe00707f 530 #define MATCH_SH3ADD 0x20006033 531 #define MASK_SH3ADD 0xfe00707f 532 #define MATCH_CLMUL 0xa001033 533 #define MASK_CLMUL 0xfe00707f 534 #define MATCH_CLMULR 0xa002033 535 #define MASK_CLMULR 0xfe00707f 536 #define MATCH_CLMULH 0xa003033 537 #define MASK_CLMULH 0xfe00707f 538 #define MATCH_MIN 0xa004033 539 #define MASK_MIN 0xfe00707f 540 #define MATCH_MINU 0xa005033 541 #define MASK_MINU 0xfe00707f 542 #define MATCH_MAX 0xa006033 543 #define MASK_MAX 0xfe00707f 544 #define MATCH_MAXU 0xa007033 545 #define MASK_MAXU 0xfe00707f 546 #define MATCH_SHFL 0x8001033 547 #define MASK_SHFL 0xfe00707f 548 #define MATCH_UNSHFL 0x8005033 549 #define MASK_UNSHFL 0xfe00707f 550 #define MATCH_BCOMPRESS 0x8006033 551 #define MASK_BCOMPRESS 0xfe00707f 552 #define MATCH_BDECOMPRESS 0x48006033 553 #define MASK_BDECOMPRESS 0xfe00707f 554 #define MATCH_PACK 0x8004033 555 #define MASK_PACK 0xfe00707f 556 #define MATCH_PACKU 0x48004033 557 #define MASK_PACKU 0xfe00707f 558 #define MATCH_PACKH 0x8007033 559 #define MASK_PACKH 0xfe00707f 560 #define MATCH_BFP 0x48007033 561 #define MASK_BFP 0xfe00707f 562 #define MATCH_SHFLI 0x8001013 563 #define MASK_SHFLI 0xfe00707f 564 #define MATCH_UNSHFLI 0x8005013 565 #define MASK_UNSHFLI 0xfe00707f 566 #define MATCH_XPERM_N 0x28002033 567 #define MASK_XPERM_N 0xfe00707f 568 #define MATCH_XPERM_B 0x28004033 569 #define MASK_XPERM_B 0xfe00707f 570 #define MATCH_XPERM_H 0x28006033 571 #define MASK_XPERM_H 0xfe00707f 572 #define MATCH_BMATFLIP 0x60301013 573 #define MASK_BMATFLIP 0xfff0707f 574 #define MATCH_CRC32_D 0x61301013 575 #define MASK_CRC32_D 0xfff0707f 576 #define MATCH_CRC32C_D 0x61b01013 577 #define MASK_CRC32C_D 0xfff0707f 578 #define MATCH_BMATOR 0x8003033 579 #define MASK_BMATOR 0xfe00707f 580 #define MATCH_BMATXOR 0x48003033 581 #define MASK_BMATXOR 0xfe00707f 582 #define MATCH_SLLI_UW 0x800101b 583 #define MASK_SLLI_UW 0xfc00707f 584 #define MATCH_ADD_UW 0x800003b 585 #define MASK_ADD_UW 0xfe00707f 586 #define MATCH_SLOW 0x2000103b 587 #define MASK_SLOW 0xfe00707f 588 #define MATCH_SROW 0x2000503b 589 #define MASK_SROW 0xfe00707f 590 #define MATCH_ROLW 0x6000103b 591 #define MASK_ROLW 0xfe00707f 592 #define MATCH_RORW 0x6000503b 593 #define MASK_RORW 0xfe00707f 594 #define MATCH_SBCLRW 0x4800103b 595 #define MASK_SBCLRW 0xfe00707f 596 #define MATCH_SBSETW 0x2800103b 597 #define MASK_SBSETW 0xfe00707f 598 #define MATCH_SBINVW 0x6800103b 599 #define MASK_SBINVW 0xfe00707f 600 #define MATCH_SBEXTW 0x4800503b 601 #define MASK_SBEXTW 0xfe00707f 602 #define MATCH_GORCW 0x2800503b 603 #define MASK_GORCW 0xfe00707f 604 #define MATCH_GREVW 0x6800503b 605 #define MASK_GREVW 0xfe00707f 606 #define MATCH_SLOIW 0x2000101b 607 #define MASK_SLOIW 0xfe00707f 608 #define MATCH_SROIW 0x2000501b 609 #define MASK_SROIW 0xfe00707f 610 #define MATCH_RORIW 0x6000501b 611 #define MASK_RORIW 0xfe00707f 612 #define MATCH_SBCLRIW 0x4800101b 613 #define MASK_SBCLRIW 0xfe00707f 614 #define MATCH_SBSETIW 0x2800101b 615 #define MASK_SBSETIW 0xfe00707f 616 #define MATCH_SBINVIW 0x6800101b 617 #define MASK_SBINVIW 0xfe00707f 618 #define MATCH_GORCIW 0x2800501b 619 #define MASK_GORCIW 0xfe00707f 620 #define MATCH_GREVIW 0x6800501b 621 #define MASK_GREVIW 0xfe00707f 622 #define MATCH_FSLW 0x400103b 623 #define MASK_FSLW 0x600707f 624 #define MATCH_FSRW 0x400503b 625 #define MASK_FSRW 0x600707f 626 #define MATCH_FSRIW 0x400501b 627 #define MASK_FSRIW 0x600707f 628 #define MATCH_CLZW 0x6000101b 629 #define MASK_CLZW 0xfff0707f 630 #define MATCH_CTZW 0x6010101b 631 #define MASK_CTZW 0xfff0707f 632 #define MATCH_CPOPW 0x6020101b 633 #define MASK_CPOPW 0xfff0707f 634 #define MATCH_SH1ADD_UW 0x2000203b 635 #define MASK_SH1ADD_UW 0xfe00707f 636 #define MATCH_SH2ADD_UW 0x2000403b 637 #define MASK_SH2ADD_UW 0xfe00707f 638 #define MATCH_SH3ADD_UW 0x2000603b 639 #define MASK_SH3ADD_UW 0xfe00707f 640 #define MATCH_SHFLW 0x800103b 641 #define MASK_SHFLW 0xfe00707f 642 #define MATCH_UNSHFLW 0x800503b 643 #define MASK_UNSHFLW 0xfe00707f 644 #define MATCH_BCOMPRESSW 0x800603b 645 #define MASK_BCOMPRESSW 0xfe00707f 646 #define MATCH_BDECOMPRESSW 0x4800603b 647 #define MASK_BDECOMPRESSW 0xfe00707f 648 #define MATCH_PACKW 0x800403b 649 #define MASK_PACKW 0xfe00707f 650 #define MATCH_PACKUW 0x4800403b 651 #define MASK_PACKUW 0xfe00707f 652 #define MATCH_BFPW 0x4800703b 653 #define MASK_BFPW 0xfe00707f 654 #define MATCH_XPERM_W 0x28000033 655 #define MASK_XPERM_W 0xfe00707f 656 #define MATCH_ECALL 0x73 657 #define MASK_ECALL 0xffffffff 658 #define MATCH_EBREAK 0x100073 659 #define MASK_EBREAK 0xffffffff 660 #define MATCH_URET 0x200073 661 #define MASK_URET 0xffffffff 662 #define MATCH_SRET 0x10200073 663 #define MASK_SRET 0xffffffff 664 #define MATCH_MRET 0x30200073 665 #define MASK_MRET 0xffffffff 666 #define MATCH_DRET 0x7b200073 667 #define MASK_DRET 0xffffffff 668 #define MATCH_SFENCE_VMA 0x12000073 669 #define MASK_SFENCE_VMA 0xfe007fff 670 #define MATCH_WFI 0x10500073 671 #define MASK_WFI 0xffffffff 672 #define MATCH_CSRRW 0x1073 673 #define MASK_CSRRW 0x707f 674 #define MATCH_CSRRS 0x2073 675 #define MASK_CSRRS 0x707f 676 #define MATCH_CSRRC 0x3073 677 #define MASK_CSRRC 0x707f 678 #define MATCH_CSRRWI 0x5073 679 #define MASK_CSRRWI 0x707f 680 #define MATCH_CSRRSI 0x6073 681 #define MASK_CSRRSI 0x707f 682 #define MATCH_CSRRCI 0x7073 683 #define MASK_CSRRCI 0x707f 684 #define MATCH_FADD_H 0x4000053 685 #define MASK_FADD_H 0xfe00007f 686 #define MATCH_FSUB_H 0xc000053 687 #define MASK_FSUB_H 0xfe00007f 688 #define MATCH_FMUL_H 0x14000053 689 #define MASK_FMUL_H 0xfe00007f 690 #define MATCH_FDIV_H 0x1c000053 691 #define MASK_FDIV_H 0xfe00007f 692 #define MATCH_FSGNJ_H 0x24000053 693 #define MASK_FSGNJ_H 0xfe00707f 694 #define MATCH_FSGNJN_H 0x24001053 695 #define MASK_FSGNJN_H 0xfe00707f 696 #define MATCH_FSGNJX_H 0x24002053 697 #define MASK_FSGNJX_H 0xfe00707f 698 #define MATCH_FMIN_H 0x2c000053 699 #define MASK_FMIN_H 0xfe00707f 700 #define MATCH_FMAX_H 0x2c001053 701 #define MASK_FMAX_H 0xfe00707f 702 #define MATCH_FCVT_H_S 0x44000053 703 #define MASK_FCVT_H_S 0xfff0007f 704 #define MATCH_FCVT_S_H 0x40200053 705 #define MASK_FCVT_S_H 0xfff0007f 706 #define MATCH_FSQRT_H 0x5c000053 707 #define MASK_FSQRT_H 0xfff0007f 708 #define MATCH_FLE_H 0xa4000053 709 #define MASK_FLE_H 0xfe00707f 710 #define MATCH_FLT_H 0xa4001053 711 #define MASK_FLT_H 0xfe00707f 712 #define MATCH_FEQ_H 0xa4002053 713 #define MASK_FEQ_H 0xfe00707f 714 #define MATCH_FCVT_W_H 0xc4000053 715 #define MASK_FCVT_W_H 0xfff0007f 716 #define MATCH_FCVT_WU_H 0xc4100053 717 #define MASK_FCVT_WU_H 0xfff0007f 718 #define MATCH_FMV_X_H 0xe4000053 719 #define MASK_FMV_X_H 0xfff0707f 720 #define MATCH_FCLASS_H 0xe4001053 721 #define MASK_FCLASS_H 0xfff0707f 722 #define MATCH_FCVT_H_W 0xd4000053 723 #define MASK_FCVT_H_W 0xfff0007f 724 #define MATCH_FCVT_H_WU 0xd4100053 725 #define MASK_FCVT_H_WU 0xfff0007f 726 #define MATCH_FMV_H_X 0xf4000053 727 #define MASK_FMV_H_X 0xfff0707f 728 #define MATCH_FLH 0x1007 729 #define MASK_FLH 0x707f 730 #define MATCH_FSH 0x1027 731 #define MASK_FSH 0x707f 732 #define MATCH_FMADD_H 0x4000043 733 #define MASK_FMADD_H 0x600007f 734 #define MATCH_FMSUB_H 0x4000047 735 #define MASK_FMSUB_H 0x600007f 736 #define MATCH_FNMSUB_H 0x400004b 737 #define MASK_FNMSUB_H 0x600007f 738 #define MATCH_FNMADD_H 0x400004f 739 #define MASK_FNMADD_H 0x600007f 740 #define MATCH_FCVT_H_D 0x44100053 741 #define MASK_FCVT_H_D 0xfff0007f 742 #define MATCH_FCVT_D_H 0x42200053 743 #define MASK_FCVT_D_H 0xfff0007f 744 #define MATCH_FCVT_H_Q 0x44300053 745 #define MASK_FCVT_H_Q 0xfff0007f 746 #define MATCH_FCVT_Q_H 0x46200053 747 #define MASK_FCVT_Q_H 0xfff0007f 748 #define MATCH_FCVT_L_H 0xc4200053 749 #define MASK_FCVT_L_H 0xfff0007f 750 #define MATCH_FCVT_LU_H 0xc4300053 751 #define MASK_FCVT_LU_H 0xfff0007f 752 #define MATCH_FCVT_H_L 0xd4200053 753 #define MASK_FCVT_H_L 0xfff0007f 754 #define MATCH_FCVT_H_LU 0xd4300053 755 #define MASK_FCVT_H_LU 0xfff0007f 756 #define MATCH_POLLENTROPY 0xf1500073 757 #define MASK_POLLENTROPY 0xfffff07f 758 #define MATCH_GETNOISE 0x7a900073 759 #define MASK_GETNOISE 0xfffff07f 760 #define MATCH_SM4ED 0x30000033 761 #define MASK_SM4ED 0x3e007fff 762 #define MATCH_SM4KS 0x34000033 763 #define MASK_SM4KS 0x3e007fff 764 #define MATCH_SM3P0 0x10801013 765 #define MASK_SM3P0 0xfff0707f 766 #define MATCH_SM3P1 0x10901013 767 #define MASK_SM3P1 0xfff0707f 768 #define MATCH_SHA256SUM0 0x10001013 769 #define MASK_SHA256SUM0 0xfff0707f 770 #define MATCH_SHA256SUM1 0x10101013 771 #define MASK_SHA256SUM1 0xfff0707f 772 #define MATCH_SHA256SIG0 0x10201013 773 #define MASK_SHA256SIG0 0xfff0707f 774 #define MATCH_SHA256SIG1 0x10301013 775 #define MASK_SHA256SIG1 0xfff0707f 776 #define MATCH_AES32ESMI 0x36000033 777 #define MASK_AES32ESMI 0x3e007fff 778 #define MATCH_AES32ESI 0x32000033 779 #define MASK_AES32ESI 0x3e007fff 780 #define MATCH_AES32DSMI 0x3e000033 781 #define MASK_AES32DSMI 0x3e007fff 782 #define MATCH_AES32DSI 0x3a000033 783 #define MASK_AES32DSI 0x3e007fff 784 #define MATCH_SHA512SUM0R 0x50000033 785 #define MASK_SHA512SUM0R 0xfe00707f 786 #define MATCH_SHA512SUM1R 0x52000033 787 #define MASK_SHA512SUM1R 0xfe00707f 788 #define MATCH_SHA512SIG0L 0x54000033 789 #define MASK_SHA512SIG0L 0xfe00707f 790 #define MATCH_SHA512SIG0H 0x5c000033 791 #define MASK_SHA512SIG0H 0xfe00707f 792 #define MATCH_SHA512SIG1L 0x56000033 793 #define MASK_SHA512SIG1L 0xfe00707f 794 #define MATCH_SHA512SIG1H 0x5e000033 795 #define MASK_SHA512SIG1H 0xfe00707f 796 #define MATCH_AES64KS1I 0x31001013 797 #define MASK_AES64KS1I 0xff00707f 798 #define MATCH_AES64IM 0x30001013 799 #define MASK_AES64IM 0xfff0707f 800 #define MATCH_AES64KS2 0x7e000033 801 #define MASK_AES64KS2 0xfe00707f 802 #define MATCH_AES64ESM 0x36000033 803 #define MASK_AES64ESM 0xfe00707f 804 #define MATCH_AES64ES 0x32000033 805 #define MASK_AES64ES 0xfe00707f 806 #define MATCH_AES64DSM 0x3e000033 807 #define MASK_AES64DSM 0xfe00707f 808 #define MATCH_AES64DS 0x3a000033 809 #define MASK_AES64DS 0xfe00707f 810 #define MATCH_SHA512SUM0 0x10401013 811 #define MASK_SHA512SUM0 0xfff0707f 812 #define MATCH_SHA512SUM1 0x10501013 813 #define MASK_SHA512SUM1 0xfff0707f 814 #define MATCH_SHA512SIG0 0x10601013 815 #define MASK_SHA512SIG0 0xfff0707f 816 #define MATCH_SHA512SIG1 0x10701013 817 #define MASK_SHA512SIG1 0xfff0707f 818 #define MATCH_C_NOP 0x1 819 #define MASK_C_NOP 0xffff 820 #define MATCH_C_ADDI16SP 0x6101 821 #define MASK_C_ADDI16SP 0xef83 822 #define MATCH_C_JR 0x8002 823 #define MASK_C_JR 0xf07f 824 #define MATCH_C_JALR 0x9002 825 #define MASK_C_JALR 0xf07f 826 #define MATCH_C_EBREAK 0x9002 827 #define MASK_C_EBREAK 0xffff 828 #define MATCH_C_ADDI4SPN 0x0 829 #define MASK_C_ADDI4SPN 0xe003 830 #define MATCH_C_FLD 0x2000 831 #define MASK_C_FLD 0xe003 832 #define MATCH_C_LW 0x4000 833 #define MASK_C_LW 0xe003 834 #define MATCH_C_FLW 0x6000 835 #define MASK_C_FLW 0xe003 836 #define MATCH_C_FSD 0xa000 837 #define MASK_C_FSD 0xe003 838 #define MATCH_C_SW 0xc000 839 #define MASK_C_SW 0xe003 840 #define MATCH_C_FSW 0xe000 841 #define MASK_C_FSW 0xe003 842 #define MATCH_C_ADDI 0x1 843 #define MASK_C_ADDI 0xe003 844 #define MATCH_C_JAL 0x2001 845 #define MASK_C_JAL 0xe003 846 #define MATCH_C_LI 0x4001 847 #define MASK_C_LI 0xe003 848 #define MATCH_C_LUI 0x6001 849 #define MASK_C_LUI 0xe003 850 #define MATCH_C_SRLI 0x8001 851 #define MASK_C_SRLI 0xec03 852 #define MATCH_C_SRAI 0x8401 853 #define MASK_C_SRAI 0xec03 854 #define MATCH_C_ANDI 0x8801 855 #define MASK_C_ANDI 0xec03 856 #define MATCH_C_SUB 0x8c01 857 #define MASK_C_SUB 0xfc63 858 #define MATCH_C_XOR 0x8c21 859 #define MASK_C_XOR 0xfc63 860 #define MATCH_C_OR 0x8c41 861 #define MASK_C_OR 0xfc63 862 #define MATCH_C_AND 0x8c61 863 #define MASK_C_AND 0xfc63 864 #define MATCH_C_J 0xa001 865 #define MASK_C_J 0xe003 866 #define MATCH_C_BEQZ 0xc001 867 #define MASK_C_BEQZ 0xe003 868 #define MATCH_C_BNEZ 0xe001 869 #define MASK_C_BNEZ 0xe003 870 #define MATCH_C_SLLI 0x2 871 #define MASK_C_SLLI 0xe003 872 #define MATCH_C_FLDSP 0x2002 873 #define MASK_C_FLDSP 0xe003 874 #define MATCH_C_LWSP 0x4002 875 #define MASK_C_LWSP 0xe003 876 #define MATCH_C_FLWSP 0x6002 877 #define MASK_C_FLWSP 0xe003 878 #define MATCH_C_MV 0x8002 879 #define MASK_C_MV 0xf003 880 #define MATCH_C_ADD 0x9002 881 #define MASK_C_ADD 0xf003 882 #define MATCH_C_FSDSP 0xa002 883 #define MASK_C_FSDSP 0xe003 884 #define MATCH_C_SWSP 0xc002 885 #define MASK_C_SWSP 0xe003 886 #define MATCH_C_FSWSP 0xe002 887 #define MASK_C_FSWSP 0xe003 888 #define MATCH_C_SRLI_RV32 0x8001 889 #define MASK_C_SRLI_RV32 0xfc03 890 #define MATCH_C_SRAI_RV32 0x8401 891 #define MASK_C_SRAI_RV32 0xfc03 892 #define MATCH_C_SLLI_RV32 0x2 893 #define MASK_C_SLLI_RV32 0xf003 894 #define MATCH_C_LD 0x6000 895 #define MASK_C_LD 0xe003 896 #define MATCH_C_SD 0xe000 897 #define MASK_C_SD 0xe003 898 #define MATCH_C_SUBW 0x9c01 899 #define MASK_C_SUBW 0xfc63 900 #define MATCH_C_ADDW 0x9c21 901 #define MASK_C_ADDW 0xfc63 902 #define MATCH_C_ADDIW 0x2001 903 #define MASK_C_ADDIW 0xe003 904 #define MATCH_C_LDSP 0x6002 905 #define MASK_C_LDSP 0xe003 906 #define MATCH_C_SDSP 0xe002 907 #define MASK_C_SDSP 0xe003 908 #define MATCH_CUSTOM0 0xb 909 #define MASK_CUSTOM0 0x707f 910 #define MATCH_CUSTOM0_RS1 0x200b 911 #define MASK_CUSTOM0_RS1 0x707f 912 #define MATCH_CUSTOM0_RS1_RS2 0x300b 913 #define MASK_CUSTOM0_RS1_RS2 0x707f 914 #define MATCH_CUSTOM0_RD 0x400b 915 #define MASK_CUSTOM0_RD 0x707f 916 #define MATCH_CUSTOM0_RD_RS1 0x600b 917 #define MASK_CUSTOM0_RD_RS1 0x707f 918 #define MATCH_CUSTOM0_RD_RS1_RS2 0x700b 919 #define MASK_CUSTOM0_RD_RS1_RS2 0x707f 920 #define MATCH_CUSTOM1 0x2b 921 #define MASK_CUSTOM1 0x707f 922 #define MATCH_CUSTOM1_RS1 0x202b 923 #define MASK_CUSTOM1_RS1 0x707f 924 #define MATCH_CUSTOM1_RS1_RS2 0x302b 925 #define MASK_CUSTOM1_RS1_RS2 0x707f 926 #define MATCH_CUSTOM1_RD 0x402b 927 #define MASK_CUSTOM1_RD 0x707f 928 #define MATCH_CUSTOM1_RD_RS1 0x602b 929 #define MASK_CUSTOM1_RD_RS1 0x707f 930 #define MATCH_CUSTOM1_RD_RS1_RS2 0x702b 931 #define MASK_CUSTOM1_RD_RS1_RS2 0x707f 932 #define MATCH_CUSTOM2 0x5b 933 #define MASK_CUSTOM2 0x707f 934 #define MATCH_CUSTOM2_RS1 0x205b 935 #define MASK_CUSTOM2_RS1 0x707f 936 #define MATCH_CUSTOM2_RS1_RS2 0x305b 937 #define MASK_CUSTOM2_RS1_RS2 0x707f 938 #define MATCH_CUSTOM2_RD 0x405b 939 #define MASK_CUSTOM2_RD 0x707f 940 #define MATCH_CUSTOM2_RD_RS1 0x605b 941 #define MASK_CUSTOM2_RD_RS1 0x707f 942 #define MATCH_CUSTOM2_RD_RS1_RS2 0x705b 943 #define MASK_CUSTOM2_RD_RS1_RS2 0x707f 944 #define MATCH_CUSTOM3 0x7b 945 #define MASK_CUSTOM3 0x707f 946 #define MATCH_CUSTOM3_RS1 0x207b 947 #define MASK_CUSTOM3_RS1 0x707f 948 #define MATCH_CUSTOM3_RS1_RS2 0x307b 949 #define MASK_CUSTOM3_RS1_RS2 0x707f 950 #define MATCH_CUSTOM3_RD 0x407b 951 #define MASK_CUSTOM3_RD 0x707f 952 #define MATCH_CUSTOM3_RD_RS1 0x607b 953 #define MASK_CUSTOM3_RD_RS1 0x707f 954 #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b 955 #define MASK_CUSTOM3_RD_RS1_RS2 0x707f 956 #define MATCH_VSETIVLI 0xc0007057 957 #define MASK_VSETIVLI 0xc000707f 958 #define MATCH_VSETVLI 0x7057 959 #define MASK_VSETVLI 0x8000707f 960 #define MATCH_VSETVL 0x80007057 961 #define MASK_VSETVL 0xfe00707f 962 #define MATCH_VLE1_V 0x2b00007 963 #define MASK_VLE1_V 0xfff0707f 964 #define MATCH_VSE1_V 0x2b00027 965 #define MASK_VSE1_V 0xfff0707f 966 #define MATCH_VLE8_V 0x7 967 #define MASK_VLE8_V 0x1df0707f 968 #define MATCH_VLE16_V 0x5007 969 #define MASK_VLE16_V 0x1df0707f 970 #define MATCH_VLE32_V 0x6007 971 #define MASK_VLE32_V 0x1df0707f 972 #define MATCH_VLE64_V 0x7007 973 #define MASK_VLE64_V 0x1df0707f 974 #define MATCH_VLE128_V 0x10000007 975 #define MASK_VLE128_V 0x1df0707f 976 #define MATCH_VLE256_V 0x10005007 977 #define MASK_VLE256_V 0x1df0707f 978 #define MATCH_VLE512_V 0x10006007 979 #define MASK_VLE512_V 0x1df0707f 980 #define MATCH_VLE1024_V 0x10007007 981 #define MASK_VLE1024_V 0x1df0707f 982 #define MATCH_VSE8_V 0x27 983 #define MASK_VSE8_V 0x1df0707f 984 #define MATCH_VSE16_V 0x5027 985 #define MASK_VSE16_V 0x1df0707f 986 #define MATCH_VSE32_V 0x6027 987 #define MASK_VSE32_V 0x1df0707f 988 #define MATCH_VSE64_V 0x7027 989 #define MASK_VSE64_V 0x1df0707f 990 #define MATCH_VSE128_V 0x10000027 991 #define MASK_VSE128_V 0x1df0707f 992 #define MATCH_VSE256_V 0x10005027 993 #define MASK_VSE256_V 0x1df0707f 994 #define MATCH_VSE512_V 0x10006027 995 #define MASK_VSE512_V 0x1df0707f 996 #define MATCH_VSE1024_V 0x10007027 997 #define MASK_VSE1024_V 0x1df0707f 998 #define MATCH_VLUXEI8_V 0x4000007 999 #define MASK_VLUXEI8_V 0x1c00707f 1000 #define MATCH_VLUXEI16_V 0x4005007 1001 #define MASK_VLUXEI16_V 0x1c00707f 1002 #define MATCH_VLUXEI32_V 0x4006007 1003 #define MASK_VLUXEI32_V 0x1c00707f 1004 #define MATCH_VLUXEI64_V 0x4007007 1005 #define MASK_VLUXEI64_V 0x1c00707f 1006 #define MATCH_VLUXEI128_V 0x14000007 1007 #define MASK_VLUXEI128_V 0x1c00707f 1008 #define MATCH_VLUXEI256_V 0x14005007 1009 #define MASK_VLUXEI256_V 0x1c00707f 1010 #define MATCH_VLUXEI512_V 0x14006007 1011 #define MASK_VLUXEI512_V 0x1c00707f 1012 #define MATCH_VLUXEI1024_V 0x14007007 1013 #define MASK_VLUXEI1024_V 0x1c00707f 1014 #define MATCH_VSUXEI8_V 0x4000027 1015 #define MASK_VSUXEI8_V 0x1c00707f 1016 #define MATCH_VSUXEI16_V 0x4005027 1017 #define MASK_VSUXEI16_V 0x1c00707f 1018 #define MATCH_VSUXEI32_V 0x4006027 1019 #define MASK_VSUXEI32_V 0x1c00707f 1020 #define MATCH_VSUXEI64_V 0x4007027 1021 #define MASK_VSUXEI64_V 0x1c00707f 1022 #define MATCH_VSUXEI128_V 0x14000027 1023 #define MASK_VSUXEI128_V 0x1c00707f 1024 #define MATCH_VSUXEI256_V 0x14005027 1025 #define MASK_VSUXEI256_V 0x1c00707f 1026 #define MATCH_VSUXEI512_V 0x14006027 1027 #define MASK_VSUXEI512_V 0x1c00707f 1028 #define MATCH_VSUXEI1024_V 0x14007027 1029 #define MASK_VSUXEI1024_V 0x1c00707f 1030 #define MATCH_VLSE8_V 0x8000007 1031 #define MASK_VLSE8_V 0x1c00707f 1032 #define MATCH_VLSE16_V 0x8005007 1033 #define MASK_VLSE16_V 0x1c00707f 1034 #define MATCH_VLSE32_V 0x8006007 1035 #define MASK_VLSE32_V 0x1c00707f 1036 #define MATCH_VLSE64_V 0x8007007 1037 #define MASK_VLSE64_V 0x1c00707f 1038 #define MATCH_VLSE128_V 0x18000007 1039 #define MASK_VLSE128_V 0x1c00707f 1040 #define MATCH_VLSE256_V 0x18005007 1041 #define MASK_VLSE256_V 0x1c00707f 1042 #define MATCH_VLSE512_V 0x18006007 1043 #define MASK_VLSE512_V 0x1c00707f 1044 #define MATCH_VLSE1024_V 0x18007007 1045 #define MASK_VLSE1024_V 0x1c00707f 1046 #define MATCH_VSSE8_V 0x8000027 1047 #define MASK_VSSE8_V 0x1c00707f 1048 #define MATCH_VSSE16_V 0x8005027 1049 #define MASK_VSSE16_V 0x1c00707f 1050 #define MATCH_VSSE32_V 0x8006027 1051 #define MASK_VSSE32_V 0x1c00707f 1052 #define MATCH_VSSE64_V 0x8007027 1053 #define MASK_VSSE64_V 0x1c00707f 1054 #define MATCH_VSSE128_V 0x18000027 1055 #define MASK_VSSE128_V 0x1c00707f 1056 #define MATCH_VSSE256_V 0x18005027 1057 #define MASK_VSSE256_V 0x1c00707f 1058 #define MATCH_VSSE512_V 0x18006027 1059 #define MASK_VSSE512_V 0x1c00707f 1060 #define MATCH_VSSE1024_V 0x18007027 1061 #define MASK_VSSE1024_V 0x1c00707f 1062 #define MATCH_VLOXEI8_V 0xc000007 1063 #define MASK_VLOXEI8_V 0x1c00707f 1064 #define MATCH_VLOXEI16_V 0xc005007 1065 #define MASK_VLOXEI16_V 0x1c00707f 1066 #define MATCH_VLOXEI32_V 0xc006007 1067 #define MASK_VLOXEI32_V 0x1c00707f 1068 #define MATCH_VLOXEI64_V 0xc007007 1069 #define MASK_VLOXEI64_V 0x1c00707f 1070 #define MATCH_VLOXEI128_V 0x1c000007 1071 #define MASK_VLOXEI128_V 0x1c00707f 1072 #define MATCH_VLOXEI256_V 0x1c005007 1073 #define MASK_VLOXEI256_V 0x1c00707f 1074 #define MATCH_VLOXEI512_V 0x1c006007 1075 #define MASK_VLOXEI512_V 0x1c00707f 1076 #define MATCH_VLOXEI1024_V 0x1c007007 1077 #define MASK_VLOXEI1024_V 0x1c00707f 1078 #define MATCH_VSOXEI8_V 0xc000027 1079 #define MASK_VSOXEI8_V 0x1c00707f 1080 #define MATCH_VSOXEI16_V 0xc005027 1081 #define MASK_VSOXEI16_V 0x1c00707f 1082 #define MATCH_VSOXEI32_V 0xc006027 1083 #define MASK_VSOXEI32_V 0x1c00707f 1084 #define MATCH_VSOXEI64_V 0xc007027 1085 #define MASK_VSOXEI64_V 0x1c00707f 1086 #define MATCH_VSOXEI128_V 0x1c000027 1087 #define MASK_VSOXEI128_V 0x1c00707f 1088 #define MATCH_VSOXEI256_V 0x1c005027 1089 #define MASK_VSOXEI256_V 0x1c00707f 1090 #define MATCH_VSOXEI512_V 0x1c006027 1091 #define MASK_VSOXEI512_V 0x1c00707f 1092 #define MATCH_VSOXEI1024_V 0x1c007027 1093 #define MASK_VSOXEI1024_V 0x1c00707f 1094 #define MATCH_VLE8FF_V 0x1000007 1095 #define MASK_VLE8FF_V 0x1df0707f 1096 #define MATCH_VLE16FF_V 0x1005007 1097 #define MASK_VLE16FF_V 0x1df0707f 1098 #define MATCH_VLE32FF_V 0x1006007 1099 #define MASK_VLE32FF_V 0x1df0707f 1100 #define MATCH_VLE64FF_V 0x1007007 1101 #define MASK_VLE64FF_V 0x1df0707f 1102 #define MATCH_VLE128FF_V 0x11000007 1103 #define MASK_VLE128FF_V 0x1df0707f 1104 #define MATCH_VLE256FF_V 0x11005007 1105 #define MASK_VLE256FF_V 0x1df0707f 1106 #define MATCH_VLE512FF_V 0x11006007 1107 #define MASK_VLE512FF_V 0x1df0707f 1108 #define MATCH_VLE1024FF_V 0x11007007 1109 #define MASK_VLE1024FF_V 0x1df0707f 1110 #define MATCH_VL1RE8_V 0x2800007 1111 #define MASK_VL1RE8_V 0xfff0707f 1112 #define MATCH_VL1RE16_V 0x2805007 1113 #define MASK_VL1RE16_V 0xfff0707f 1114 #define MATCH_VL1RE32_V 0x2806007 1115 #define MASK_VL1RE32_V 0xfff0707f 1116 #define MATCH_VL1RE64_V 0x2807007 1117 #define MASK_VL1RE64_V 0xfff0707f 1118 #define MATCH_VL2RE8_V 0x22800007 1119 #define MASK_VL2RE8_V 0xfff0707f 1120 #define MATCH_VL2RE16_V 0x22805007 1121 #define MASK_VL2RE16_V 0xfff0707f 1122 #define MATCH_VL2RE32_V 0x22806007 1123 #define MASK_VL2RE32_V 0xfff0707f 1124 #define MATCH_VL2RE64_V 0x22807007 1125 #define MASK_VL2RE64_V 0xfff0707f 1126 #define MATCH_VL4RE8_V 0x62800007 1127 #define MASK_VL4RE8_V 0xfff0707f 1128 #define MATCH_VL4RE16_V 0x62805007 1129 #define MASK_VL4RE16_V 0xfff0707f 1130 #define MATCH_VL4RE32_V 0x62806007 1131 #define MASK_VL4RE32_V 0xfff0707f 1132 #define MATCH_VL4RE64_V 0x62807007 1133 #define MASK_VL4RE64_V 0xfff0707f 1134 #define MATCH_VL8RE8_V 0xe2800007 1135 #define MASK_VL8RE8_V 0xfff0707f 1136 #define MATCH_VL8RE16_V 0xe2805007 1137 #define MASK_VL8RE16_V 0xfff0707f 1138 #define MATCH_VL8RE32_V 0xe2806007 1139 #define MASK_VL8RE32_V 0xfff0707f 1140 #define MATCH_VL8RE64_V 0xe2807007 1141 #define MASK_VL8RE64_V 0xfff0707f 1142 #define MATCH_VS1R_V 0x2800027 1143 #define MASK_VS1R_V 0xfff0707f 1144 #define MATCH_VS2R_V 0x22800027 1145 #define MASK_VS2R_V 0xfff0707f 1146 #define MATCH_VS4R_V 0x62800027 1147 #define MASK_VS4R_V 0xfff0707f 1148 #define MATCH_VS8R_V 0xe2800027 1149 #define MASK_VS8R_V 0xfff0707f 1150 #define MATCH_VFADD_VF 0x5057 1151 #define MASK_VFADD_VF 0xfc00707f 1152 #define MATCH_VFSUB_VF 0x8005057 1153 #define MASK_VFSUB_VF 0xfc00707f 1154 #define MATCH_VFMIN_VF 0x10005057 1155 #define MASK_VFMIN_VF 0xfc00707f 1156 #define MATCH_VFMAX_VF 0x18005057 1157 #define MASK_VFMAX_VF 0xfc00707f 1158 #define MATCH_VFSGNJ_VF 0x20005057 1159 #define MASK_VFSGNJ_VF 0xfc00707f 1160 #define MATCH_VFSGNJN_VF 0x24005057 1161 #define MASK_VFSGNJN_VF 0xfc00707f 1162 #define MATCH_VFSGNJX_VF 0x28005057 1163 #define MASK_VFSGNJX_VF 0xfc00707f 1164 #define MATCH_VFSLIDE1UP_VF 0x38005057 1165 #define MASK_VFSLIDE1UP_VF 0xfc00707f 1166 #define MATCH_VFSLIDE1DOWN_VF 0x3c005057 1167 #define MASK_VFSLIDE1DOWN_VF 0xfc00707f 1168 #define MATCH_VFMV_S_F 0x42005057 1169 #define MASK_VFMV_S_F 0xfff0707f 1170 #define MATCH_VFMERGE_VFM 0x5c005057 1171 #define MASK_VFMERGE_VFM 0xfe00707f 1172 #define MATCH_VFMV_V_F 0x5e005057 1173 #define MASK_VFMV_V_F 0xfff0707f 1174 #define MATCH_VMFEQ_VF 0x60005057 1175 #define MASK_VMFEQ_VF 0xfc00707f 1176 #define MATCH_VMFLE_VF 0x64005057 1177 #define MASK_VMFLE_VF 0xfc00707f 1178 #define MATCH_VMFLT_VF 0x6c005057 1179 #define MASK_VMFLT_VF 0xfc00707f 1180 #define MATCH_VMFNE_VF 0x70005057 1181 #define MASK_VMFNE_VF 0xfc00707f 1182 #define MATCH_VMFGT_VF 0x74005057 1183 #define MASK_VMFGT_VF 0xfc00707f 1184 #define MATCH_VMFGE_VF 0x7c005057 1185 #define MASK_VMFGE_VF 0xfc00707f 1186 #define MATCH_VFDIV_VF 0x80005057 1187 #define MASK_VFDIV_VF 0xfc00707f 1188 #define MATCH_VFRDIV_VF 0x84005057 1189 #define MASK_VFRDIV_VF 0xfc00707f 1190 #define MATCH_VFMUL_VF 0x90005057 1191 #define MASK_VFMUL_VF 0xfc00707f 1192 #define MATCH_VFRSUB_VF 0x9c005057 1193 #define MASK_VFRSUB_VF 0xfc00707f 1194 #define MATCH_VFMADD_VF 0xa0005057 1195 #define MASK_VFMADD_VF 0xfc00707f 1196 #define MATCH_VFNMADD_VF 0xa4005057 1197 #define MASK_VFNMADD_VF 0xfc00707f 1198 #define MATCH_VFMSUB_VF 0xa8005057 1199 #define MASK_VFMSUB_VF 0xfc00707f 1200 #define MATCH_VFNMSUB_VF 0xac005057 1201 #define MASK_VFNMSUB_VF 0xfc00707f 1202 #define MATCH_VFMACC_VF 0xb0005057 1203 #define MASK_VFMACC_VF 0xfc00707f 1204 #define MATCH_VFNMACC_VF 0xb4005057 1205 #define MASK_VFNMACC_VF 0xfc00707f 1206 #define MATCH_VFMSAC_VF 0xb8005057 1207 #define MASK_VFMSAC_VF 0xfc00707f 1208 #define MATCH_VFNMSAC_VF 0xbc005057 1209 #define MASK_VFNMSAC_VF 0xfc00707f 1210 #define MATCH_VFWADD_VF 0xc0005057 1211 #define MASK_VFWADD_VF 0xfc00707f 1212 #define MATCH_VFWSUB_VF 0xc8005057 1213 #define MASK_VFWSUB_VF 0xfc00707f 1214 #define MATCH_VFWADD_WF 0xd0005057 1215 #define MASK_VFWADD_WF 0xfc00707f 1216 #define MATCH_VFWSUB_WF 0xd8005057 1217 #define MASK_VFWSUB_WF 0xfc00707f 1218 #define MATCH_VFWMUL_VF 0xe0005057 1219 #define MASK_VFWMUL_VF 0xfc00707f 1220 #define MATCH_VFWMACC_VF 0xf0005057 1221 #define MASK_VFWMACC_VF 0xfc00707f 1222 #define MATCH_VFWNMACC_VF 0xf4005057 1223 #define MASK_VFWNMACC_VF 0xfc00707f 1224 #define MATCH_VFWMSAC_VF 0xf8005057 1225 #define MASK_VFWMSAC_VF 0xfc00707f 1226 #define MATCH_VFWNMSAC_VF 0xfc005057 1227 #define MASK_VFWNMSAC_VF 0xfc00707f 1228 #define MATCH_VFADD_VV 0x1057 1229 #define MASK_VFADD_VV 0xfc00707f 1230 #define MATCH_VFREDSUM_VS 0x4001057 1231 #define MASK_VFREDSUM_VS 0xfc00707f 1232 #define MATCH_VFSUB_VV 0x8001057 1233 #define MASK_VFSUB_VV 0xfc00707f 1234 #define MATCH_VFREDOSUM_VS 0xc001057 1235 #define MASK_VFREDOSUM_VS 0xfc00707f 1236 #define MATCH_VFMIN_VV 0x10001057 1237 #define MASK_VFMIN_VV 0xfc00707f 1238 #define MATCH_VFREDMIN_VS 0x14001057 1239 #define MASK_VFREDMIN_VS 0xfc00707f 1240 #define MATCH_VFMAX_VV 0x18001057 1241 #define MASK_VFMAX_VV 0xfc00707f 1242 #define MATCH_VFREDMAX_VS 0x1c001057 1243 #define MASK_VFREDMAX_VS 0xfc00707f 1244 #define MATCH_VFSGNJ_VV 0x20001057 1245 #define MASK_VFSGNJ_VV 0xfc00707f 1246 #define MATCH_VFSGNJN_VV 0x24001057 1247 #define MASK_VFSGNJN_VV 0xfc00707f 1248 #define MATCH_VFSGNJX_VV 0x28001057 1249 #define MASK_VFSGNJX_VV 0xfc00707f 1250 #define MATCH_VFMV_F_S 0x42001057 1251 #define MASK_VFMV_F_S 0xfe0ff07f 1252 #define MATCH_VMFEQ_VV 0x60001057 1253 #define MASK_VMFEQ_VV 0xfc00707f 1254 #define MATCH_VMFLE_VV 0x64001057 1255 #define MASK_VMFLE_VV 0xfc00707f 1256 #define MATCH_VMFLT_VV 0x6c001057 1257 #define MASK_VMFLT_VV 0xfc00707f 1258 #define MATCH_VMFNE_VV 0x70001057 1259 #define MASK_VMFNE_VV 0xfc00707f 1260 #define MATCH_VFDIV_VV 0x80001057 1261 #define MASK_VFDIV_VV 0xfc00707f 1262 #define MATCH_VFMUL_VV 0x90001057 1263 #define MASK_VFMUL_VV 0xfc00707f 1264 #define MATCH_VFMADD_VV 0xa0001057 1265 #define MASK_VFMADD_VV 0xfc00707f 1266 #define MATCH_VFNMADD_VV 0xa4001057 1267 #define MASK_VFNMADD_VV 0xfc00707f 1268 #define MATCH_VFMSUB_VV 0xa8001057 1269 #define MASK_VFMSUB_VV 0xfc00707f 1270 #define MATCH_VFNMSUB_VV 0xac001057 1271 #define MASK_VFNMSUB_VV 0xfc00707f 1272 #define MATCH_VFMACC_VV 0xb0001057 1273 #define MASK_VFMACC_VV 0xfc00707f 1274 #define MATCH_VFNMACC_VV 0xb4001057 1275 #define MASK_VFNMACC_VV 0xfc00707f 1276 #define MATCH_VFMSAC_VV 0xb8001057 1277 #define MASK_VFMSAC_VV 0xfc00707f 1278 #define MATCH_VFNMSAC_VV 0xbc001057 1279 #define MASK_VFNMSAC_VV 0xfc00707f 1280 #define MATCH_VFCVT_XU_F_V 0x48001057 1281 #define MASK_VFCVT_XU_F_V 0xfc0ff07f 1282 #define MATCH_VFCVT_X_F_V 0x48009057 1283 #define MASK_VFCVT_X_F_V 0xfc0ff07f 1284 #define MATCH_VFCVT_F_XU_V 0x48011057 1285 #define MASK_VFCVT_F_XU_V 0xfc0ff07f 1286 #define MATCH_VFCVT_F_X_V 0x48019057 1287 #define MASK_VFCVT_F_X_V 0xfc0ff07f 1288 #define MATCH_VFCVT_RTZ_XU_F_V 0x48031057 1289 #define MASK_VFCVT_RTZ_XU_F_V 0xfc0ff07f 1290 #define MATCH_VFCVT_RTZ_X_F_V 0x48039057 1291 #define MASK_VFCVT_RTZ_X_F_V 0xfc0ff07f 1292 #define MATCH_VFWCVT_XU_F_V 0x48041057 1293 #define MASK_VFWCVT_XU_F_V 0xfc0ff07f 1294 #define MATCH_VFWCVT_X_F_V 0x48049057 1295 #define MASK_VFWCVT_X_F_V 0xfc0ff07f 1296 #define MATCH_VFWCVT_F_XU_V 0x48051057 1297 #define MASK_VFWCVT_F_XU_V 0xfc0ff07f 1298 #define MATCH_VFWCVT_F_X_V 0x48059057 1299 #define MASK_VFWCVT_F_X_V 0xfc0ff07f 1300 #define MATCH_VFWCVT_F_F_V 0x48061057 1301 #define MASK_VFWCVT_F_F_V 0xfc0ff07f 1302 #define MATCH_VFWCVT_RTZ_XU_F_V 0x48071057 1303 #define MASK_VFWCVT_RTZ_XU_F_V 0xfc0ff07f 1304 #define MATCH_VFWCVT_RTZ_X_F_V 0x48079057 1305 #define MASK_VFWCVT_RTZ_X_F_V 0xfc0ff07f 1306 #define MATCH_VFNCVT_XU_F_W 0x48081057 1307 #define MASK_VFNCVT_XU_F_W 0xfc0ff07f 1308 #define MATCH_VFNCVT_X_F_W 0x48089057 1309 #define MASK_VFNCVT_X_F_W 0xfc0ff07f 1310 #define MATCH_VFNCVT_F_XU_W 0x48091057 1311 #define MASK_VFNCVT_F_XU_W 0xfc0ff07f 1312 #define MATCH_VFNCVT_F_X_W 0x48099057 1313 #define MASK_VFNCVT_F_X_W 0xfc0ff07f 1314 #define MATCH_VFNCVT_F_F_W 0x480a1057 1315 #define MASK_VFNCVT_F_F_W 0xfc0ff07f 1316 #define MATCH_VFNCVT_ROD_F_F_W 0x480a9057 1317 #define MASK_VFNCVT_ROD_F_F_W 0xfc0ff07f 1318 #define MATCH_VFNCVT_RTZ_XU_F_W 0x480b1057 1319 #define MASK_VFNCVT_RTZ_XU_F_W 0xfc0ff07f 1320 #define MATCH_VFNCVT_RTZ_X_F_W 0x480b9057 1321 #define MASK_VFNCVT_RTZ_X_F_W 0xfc0ff07f 1322 #define MATCH_VFSQRT_V 0x4c001057 1323 #define MASK_VFSQRT_V 0xfc0ff07f 1324 #define MATCH_VFRSQRT7_V 0x4c021057 1325 #define MASK_VFRSQRT7_V 0xfc0ff07f 1326 #define MATCH_VFREC7_V 0x4c029057 1327 #define MASK_VFREC7_V 0xfc0ff07f 1328 #define MATCH_VFCLASS_V 0x4c081057 1329 #define MASK_VFCLASS_V 0xfc0ff07f 1330 #define MATCH_VFWADD_VV 0xc0001057 1331 #define MASK_VFWADD_VV 0xfc00707f 1332 #define MATCH_VFWREDSUM_VS 0xc4001057 1333 #define MASK_VFWREDSUM_VS 0xfc00707f 1334 #define MATCH_VFWSUB_VV 0xc8001057 1335 #define MASK_VFWSUB_VV 0xfc00707f 1336 #define MATCH_VFWREDOSUM_VS 0xcc001057 1337 #define MASK_VFWREDOSUM_VS 0xfc00707f 1338 #define MATCH_VFWADD_WV 0xd0001057 1339 #define MASK_VFWADD_WV 0xfc00707f 1340 #define MATCH_VFWSUB_WV 0xd8001057 1341 #define MASK_VFWSUB_WV 0xfc00707f 1342 #define MATCH_VFWMUL_VV 0xe0001057 1343 #define MASK_VFWMUL_VV 0xfc00707f 1344 #define MATCH_VFDOT_VV 0xe4001057 1345 #define MASK_VFDOT_VV 0xfc00707f 1346 #define MATCH_VFWMACC_VV 0xf0001057 1347 #define MASK_VFWMACC_VV 0xfc00707f 1348 #define MATCH_VFWNMACC_VV 0xf4001057 1349 #define MASK_VFWNMACC_VV 0xfc00707f 1350 #define MATCH_VFWMSAC_VV 0xf8001057 1351 #define MASK_VFWMSAC_VV 0xfc00707f 1352 #define MATCH_VFWNMSAC_VV 0xfc001057 1353 #define MASK_VFWNMSAC_VV 0xfc00707f 1354 #define MATCH_VADD_VX 0x4057 1355 #define MASK_VADD_VX 0xfc00707f 1356 #define MATCH_VSUB_VX 0x8004057 1357 #define MASK_VSUB_VX 0xfc00707f 1358 #define MATCH_VRSUB_VX 0xc004057 1359 #define MASK_VRSUB_VX 0xfc00707f 1360 #define MATCH_VMINU_VX 0x10004057 1361 #define MASK_VMINU_VX 0xfc00707f 1362 #define MATCH_VMIN_VX 0x14004057 1363 #define MASK_VMIN_VX 0xfc00707f 1364 #define MATCH_VMAXU_VX 0x18004057 1365 #define MASK_VMAXU_VX 0xfc00707f 1366 #define MATCH_VMAX_VX 0x1c004057 1367 #define MASK_VMAX_VX 0xfc00707f 1368 #define MATCH_VAND_VX 0x24004057 1369 #define MASK_VAND_VX 0xfc00707f 1370 #define MATCH_VOR_VX 0x28004057 1371 #define MASK_VOR_VX 0xfc00707f 1372 #define MATCH_VXOR_VX 0x2c004057 1373 #define MASK_VXOR_VX 0xfc00707f 1374 #define MATCH_VRGATHER_VX 0x30004057 1375 #define MASK_VRGATHER_VX 0xfc00707f 1376 #define MATCH_VSLIDEUP_VX 0x38004057 1377 #define MASK_VSLIDEUP_VX 0xfc00707f 1378 #define MATCH_VSLIDEDOWN_VX 0x3c004057 1379 #define MASK_VSLIDEDOWN_VX 0xfc00707f 1380 #define MATCH_VADC_VXM 0x40004057 1381 #define MASK_VADC_VXM 0xfe00707f 1382 #define MATCH_VMADC_VXM 0x44004057 1383 #define MASK_VMADC_VXM 0xfc00707f 1384 #define MATCH_VSBC_VXM 0x48004057 1385 #define MASK_VSBC_VXM 0xfe00707f 1386 #define MATCH_VMSBC_VXM 0x4c004057 1387 #define MASK_VMSBC_VXM 0xfc00707f 1388 #define MATCH_VMERGE_VXM 0x5c004057 1389 #define MASK_VMERGE_VXM 0xfe00707f 1390 #define MATCH_VMV_V_X 0x5e004057 1391 #define MASK_VMV_V_X 0xfff0707f 1392 #define MATCH_VMSEQ_VX 0x60004057 1393 #define MASK_VMSEQ_VX 0xfc00707f 1394 #define MATCH_VMSNE_VX 0x64004057 1395 #define MASK_VMSNE_VX 0xfc00707f 1396 #define MATCH_VMSLTU_VX 0x68004057 1397 #define MASK_VMSLTU_VX 0xfc00707f 1398 #define MATCH_VMSLT_VX 0x6c004057 1399 #define MASK_VMSLT_VX 0xfc00707f 1400 #define MATCH_VMSLEU_VX 0x70004057 1401 #define MASK_VMSLEU_VX 0xfc00707f 1402 #define MATCH_VMSLE_VX 0x74004057 1403 #define MASK_VMSLE_VX 0xfc00707f 1404 #define MATCH_VMSGTU_VX 0x78004057 1405 #define MASK_VMSGTU_VX 0xfc00707f 1406 #define MATCH_VMSGT_VX 0x7c004057 1407 #define MASK_VMSGT_VX 0xfc00707f 1408 #define MATCH_VSADDU_VX 0x80004057 1409 #define MASK_VSADDU_VX 0xfc00707f 1410 #define MATCH_VSADD_VX 0x84004057 1411 #define MASK_VSADD_VX 0xfc00707f 1412 #define MATCH_VSSUBU_VX 0x88004057 1413 #define MASK_VSSUBU_VX 0xfc00707f 1414 #define MATCH_VSSUB_VX 0x8c004057 1415 #define MASK_VSSUB_VX 0xfc00707f 1416 #define MATCH_VSLL_VX 0x94004057 1417 #define MASK_VSLL_VX 0xfc00707f 1418 #define MATCH_VSMUL_VX 0x9c004057 1419 #define MASK_VSMUL_VX 0xfc00707f 1420 #define MATCH_VSRL_VX 0xa0004057 1421 #define MASK_VSRL_VX 0xfc00707f 1422 #define MATCH_VSRA_VX 0xa4004057 1423 #define MASK_VSRA_VX 0xfc00707f 1424 #define MATCH_VSSRL_VX 0xa8004057 1425 #define MASK_VSSRL_VX 0xfc00707f 1426 #define MATCH_VSSRA_VX 0xac004057 1427 #define MASK_VSSRA_VX 0xfc00707f 1428 #define MATCH_VNSRL_WX 0xb0004057 1429 #define MASK_VNSRL_WX 0xfc00707f 1430 #define MATCH_VNSRA_WX 0xb4004057 1431 #define MASK_VNSRA_WX 0xfc00707f 1432 #define MATCH_VNCLIPU_WX 0xb8004057 1433 #define MASK_VNCLIPU_WX 0xfc00707f 1434 #define MATCH_VNCLIP_WX 0xbc004057 1435 #define MASK_VNCLIP_WX 0xfc00707f 1436 #define MATCH_VADD_VV 0x57 1437 #define MASK_VADD_VV 0xfc00707f 1438 #define MATCH_VSUB_VV 0x8000057 1439 #define MASK_VSUB_VV 0xfc00707f 1440 #define MATCH_VMINU_VV 0x10000057 1441 #define MASK_VMINU_VV 0xfc00707f 1442 #define MATCH_VMIN_VV 0x14000057 1443 #define MASK_VMIN_VV 0xfc00707f 1444 #define MATCH_VMAXU_VV 0x18000057 1445 #define MASK_VMAXU_VV 0xfc00707f 1446 #define MATCH_VMAX_VV 0x1c000057 1447 #define MASK_VMAX_VV 0xfc00707f 1448 #define MATCH_VAND_VV 0x24000057 1449 #define MASK_VAND_VV 0xfc00707f 1450 #define MATCH_VOR_VV 0x28000057 1451 #define MASK_VOR_VV 0xfc00707f 1452 #define MATCH_VXOR_VV 0x2c000057 1453 #define MASK_VXOR_VV 0xfc00707f 1454 #define MATCH_VRGATHER_VV 0x30000057 1455 #define MASK_VRGATHER_VV 0xfc00707f 1456 #define MATCH_VRGATHEREI16_VV 0x38000057 1457 #define MASK_VRGATHEREI16_VV 0xfc00707f 1458 #define MATCH_VADC_VVM 0x40000057 1459 #define MASK_VADC_VVM 0xfe00707f 1460 #define MATCH_VMADC_VVM 0x44000057 1461 #define MASK_VMADC_VVM 0xfc00707f 1462 #define MATCH_VSBC_VVM 0x48000057 1463 #define MASK_VSBC_VVM 0xfe00707f 1464 #define MATCH_VMSBC_VVM 0x4c000057 1465 #define MASK_VMSBC_VVM 0xfc00707f 1466 #define MATCH_VMERGE_VVM 0x5c000057 1467 #define MASK_VMERGE_VVM 0xfe00707f 1468 #define MATCH_VMV_V_V 0x5e000057 1469 #define MASK_VMV_V_V 0xfff0707f 1470 #define MATCH_VMSEQ_VV 0x60000057 1471 #define MASK_VMSEQ_VV 0xfc00707f 1472 #define MATCH_VMSNE_VV 0x64000057 1473 #define MASK_VMSNE_VV 0xfc00707f 1474 #define MATCH_VMSLTU_VV 0x68000057 1475 #define MASK_VMSLTU_VV 0xfc00707f 1476 #define MATCH_VMSLT_VV 0x6c000057 1477 #define MASK_VMSLT_VV 0xfc00707f 1478 #define MATCH_VMSLEU_VV 0x70000057 1479 #define MASK_VMSLEU_VV 0xfc00707f 1480 #define MATCH_VMSLE_VV 0x74000057 1481 #define MASK_VMSLE_VV 0xfc00707f 1482 #define MATCH_VSADDU_VV 0x80000057 1483 #define MASK_VSADDU_VV 0xfc00707f 1484 #define MATCH_VSADD_VV 0x84000057 1485 #define MASK_VSADD_VV 0xfc00707f 1486 #define MATCH_VSSUBU_VV 0x88000057 1487 #define MASK_VSSUBU_VV 0xfc00707f 1488 #define MATCH_VSSUB_VV 0x8c000057 1489 #define MASK_VSSUB_VV 0xfc00707f 1490 #define MATCH_VSLL_VV 0x94000057 1491 #define MASK_VSLL_VV 0xfc00707f 1492 #define MATCH_VSMUL_VV 0x9c000057 1493 #define MASK_VSMUL_VV 0xfc00707f 1494 #define MATCH_VSRL_VV 0xa0000057 1495 #define MASK_VSRL_VV 0xfc00707f 1496 #define MATCH_VSRA_VV 0xa4000057 1497 #define MASK_VSRA_VV 0xfc00707f 1498 #define MATCH_VSSRL_VV 0xa8000057 1499 #define MASK_VSSRL_VV 0xfc00707f 1500 #define MATCH_VSSRA_VV 0xac000057 1501 #define MASK_VSSRA_VV 0xfc00707f 1502 #define MATCH_VNSRL_WV 0xb0000057 1503 #define MASK_VNSRL_WV 0xfc00707f 1504 #define MATCH_VNSRA_WV 0xb4000057 1505 #define MASK_VNSRA_WV 0xfc00707f 1506 #define MATCH_VNCLIPU_WV 0xb8000057 1507 #define MASK_VNCLIPU_WV 0xfc00707f 1508 #define MATCH_VNCLIP_WV 0xbc000057 1509 #define MASK_VNCLIP_WV 0xfc00707f 1510 #define MATCH_VWREDSUMU_VS 0xc0000057 1511 #define MASK_VWREDSUMU_VS 0xfc00707f 1512 #define MATCH_VWREDSUM_VS 0xc4000057 1513 #define MASK_VWREDSUM_VS 0xfc00707f 1514 #define MATCH_VDOTU_VV 0xe0000057 1515 #define MASK_VDOTU_VV 0xfc00707f 1516 #define MATCH_VDOT_VV 0xe4000057 1517 #define MASK_VDOT_VV 0xfc00707f 1518 #define MATCH_VQMACCU_VV 0xf0000057 1519 #define MASK_VQMACCU_VV 0xfc00707f 1520 #define MATCH_VQMACC_VV 0xf4000057 1521 #define MASK_VQMACC_VV 0xfc00707f 1522 #define MATCH_VQMACCSU_VV 0xfc000057 1523 #define MASK_VQMACCSU_VV 0xfc00707f 1524 #define MATCH_VADD_VI 0x3057 1525 #define MASK_VADD_VI 0xfc00707f 1526 #define MATCH_VRSUB_VI 0xc003057 1527 #define MASK_VRSUB_VI 0xfc00707f 1528 #define MATCH_VAND_VI 0x24003057 1529 #define MASK_VAND_VI 0xfc00707f 1530 #define MATCH_VOR_VI 0x28003057 1531 #define MASK_VOR_VI 0xfc00707f 1532 #define MATCH_VXOR_VI 0x2c003057 1533 #define MASK_VXOR_VI 0xfc00707f 1534 #define MATCH_VRGATHER_VI 0x30003057 1535 #define MASK_VRGATHER_VI 0xfc00707f 1536 #define MATCH_VSLIDEUP_VI 0x38003057 1537 #define MASK_VSLIDEUP_VI 0xfc00707f 1538 #define MATCH_VSLIDEDOWN_VI 0x3c003057 1539 #define MASK_VSLIDEDOWN_VI 0xfc00707f 1540 #define MATCH_VADC_VIM 0x40003057 1541 #define MASK_VADC_VIM 0xfe00707f 1542 #define MATCH_VMADC_VIM 0x44003057 1543 #define MASK_VMADC_VIM 0xfc00707f 1544 #define MATCH_VMERGE_VIM 0x5c003057 1545 #define MASK_VMERGE_VIM 0xfe00707f 1546 #define MATCH_VMV_V_I 0x5e003057 1547 #define MASK_VMV_V_I 0xfff0707f 1548 #define MATCH_VMSEQ_VI 0x60003057 1549 #define MASK_VMSEQ_VI 0xfc00707f 1550 #define MATCH_VMSNE_VI 0x64003057 1551 #define MASK_VMSNE_VI 0xfc00707f 1552 #define MATCH_VMSLEU_VI 0x70003057 1553 #define MASK_VMSLEU_VI 0xfc00707f 1554 #define MATCH_VMSLE_VI 0x74003057 1555 #define MASK_VMSLE_VI 0xfc00707f 1556 #define MATCH_VMSGTU_VI 0x78003057 1557 #define MASK_VMSGTU_VI 0xfc00707f 1558 #define MATCH_VMSGT_VI 0x7c003057 1559 #define MASK_VMSGT_VI 0xfc00707f 1560 #define MATCH_VSADDU_VI 0x80003057 1561 #define MASK_VSADDU_VI 0xfc00707f 1562 #define MATCH_VSADD_VI 0x84003057 1563 #define MASK_VSADD_VI 0xfc00707f 1564 #define MATCH_VSLL_VI 0x94003057 1565 #define MASK_VSLL_VI 0xfc00707f 1566 #define MATCH_VMV1R_V 0x9e003057 1567 #define MASK_VMV1R_V 0xfe0ff07f 1568 #define MATCH_VMV2R_V 0x9e00b057 1569 #define MASK_VMV2R_V 0xfe0ff07f 1570 #define MATCH_VMV4R_V 0x9e01b057 1571 #define MASK_VMV4R_V 0xfe0ff07f 1572 #define MATCH_VMV8R_V 0x9e03b057 1573 #define MASK_VMV8R_V 0xfe0ff07f 1574 #define MATCH_VSRL_VI 0xa0003057 1575 #define MASK_VSRL_VI 0xfc00707f 1576 #define MATCH_VSRA_VI 0xa4003057 1577 #define MASK_VSRA_VI 0xfc00707f 1578 #define MATCH_VSSRL_VI 0xa8003057 1579 #define MASK_VSSRL_VI 0xfc00707f 1580 #define MATCH_VSSRA_VI 0xac003057 1581 #define MASK_VSSRA_VI 0xfc00707f 1582 #define MATCH_VNSRL_WI 0xb0003057 1583 #define MASK_VNSRL_WI 0xfc00707f 1584 #define MATCH_VNSRA_WI 0xb4003057 1585 #define MASK_VNSRA_WI 0xfc00707f 1586 #define MATCH_VNCLIPU_WI 0xb8003057 1587 #define MASK_VNCLIPU_WI 0xfc00707f 1588 #define MATCH_VNCLIP_WI 0xbc003057 1589 #define MASK_VNCLIP_WI 0xfc00707f 1590 #define MATCH_VREDSUM_VS 0x2057 1591 #define MASK_VREDSUM_VS 0xfc00707f 1592 #define MATCH_VREDAND_VS 0x4002057 1593 #define MASK_VREDAND_VS 0xfc00707f 1594 #define MATCH_VREDOR_VS 0x8002057 1595 #define MASK_VREDOR_VS 0xfc00707f 1596 #define MATCH_VREDXOR_VS 0xc002057 1597 #define MASK_VREDXOR_VS 0xfc00707f 1598 #define MATCH_VREDMINU_VS 0x10002057 1599 #define MASK_VREDMINU_VS 0xfc00707f 1600 #define MATCH_VREDMIN_VS 0x14002057 1601 #define MASK_VREDMIN_VS 0xfc00707f 1602 #define MATCH_VREDMAXU_VS 0x18002057 1603 #define MASK_VREDMAXU_VS 0xfc00707f 1604 #define MATCH_VREDMAX_VS 0x1c002057 1605 #define MASK_VREDMAX_VS 0xfc00707f 1606 #define MATCH_VAADDU_VV 0x20002057 1607 #define MASK_VAADDU_VV 0xfc00707f 1608 #define MATCH_VAADD_VV 0x24002057 1609 #define MASK_VAADD_VV 0xfc00707f 1610 #define MATCH_VASUBU_VV 0x28002057 1611 #define MASK_VASUBU_VV 0xfc00707f 1612 #define MATCH_VASUB_VV 0x2c002057 1613 #define MASK_VASUB_VV 0xfc00707f 1614 #define MATCH_VMV_X_S 0x42002057 1615 #define MASK_VMV_X_S 0xfe0ff07f 1616 #define MATCH_VZEXT_VF8 0x48012057 1617 #define MASK_VZEXT_VF8 0xfc0ff07f 1618 #define MATCH_VSEXT_VF8 0x4801a057 1619 #define MASK_VSEXT_VF8 0xfc0ff07f 1620 #define MATCH_VZEXT_VF4 0x48022057 1621 #define MASK_VZEXT_VF4 0xfc0ff07f 1622 #define MATCH_VSEXT_VF4 0x4802a057 1623 #define MASK_VSEXT_VF4 0xfc0ff07f 1624 #define MATCH_VZEXT_VF2 0x48032057 1625 #define MASK_VZEXT_VF2 0xfc0ff07f 1626 #define MATCH_VSEXT_VF2 0x4803a057 1627 #define MASK_VSEXT_VF2 0xfc0ff07f 1628 #define MATCH_VCOMPRESS_VM 0x5e002057 1629 #define MASK_VCOMPRESS_VM 0xfe00707f 1630 #define MATCH_VMANDNOT_MM 0x60002057 1631 #define MASK_VMANDNOT_MM 0xfc00707f 1632 #define MATCH_VMAND_MM 0x64002057 1633 #define MASK_VMAND_MM 0xfc00707f 1634 #define MATCH_VMOR_MM 0x68002057 1635 #define MASK_VMOR_MM 0xfc00707f 1636 #define MATCH_VMXOR_MM 0x6c002057 1637 #define MASK_VMXOR_MM 0xfc00707f 1638 #define MATCH_VMORNOT_MM 0x70002057 1639 #define MASK_VMORNOT_MM 0xfc00707f 1640 #define MATCH_VMNAND_MM 0x74002057 1641 #define MASK_VMNAND_MM 0xfc00707f 1642 #define MATCH_VMNOR_MM 0x78002057 1643 #define MASK_VMNOR_MM 0xfc00707f 1644 #define MATCH_VMXNOR_MM 0x7c002057 1645 #define MASK_VMXNOR_MM 0xfc00707f 1646 #define MATCH_VMSBF_M 0x5000a057 1647 #define MASK_VMSBF_M 0xfc0ff07f 1648 #define MATCH_VMSOF_M 0x50012057 1649 #define MASK_VMSOF_M 0xfc0ff07f 1650 #define MATCH_VMSIF_M 0x5001a057 1651 #define MASK_VMSIF_M 0xfc0ff07f 1652 #define MATCH_VIOTA_M 0x50082057 1653 #define MASK_VIOTA_M 0xfc0ff07f 1654 #define MATCH_VID_V 0x5008a057 1655 #define MASK_VID_V 0xfdfff07f 1656 #define MATCH_VPOPC_M 0x40082057 1657 #define MASK_VPOPC_M 0xfc0ff07f 1658 #define MATCH_VFIRST_M 0x4008a057 1659 #define MASK_VFIRST_M 0xfc0ff07f 1660 #define MATCH_VDIVU_VV 0x80002057 1661 #define MASK_VDIVU_VV 0xfc00707f 1662 #define MATCH_VDIV_VV 0x84002057 1663 #define MASK_VDIV_VV 0xfc00707f 1664 #define MATCH_VREMU_VV 0x88002057 1665 #define MASK_VREMU_VV 0xfc00707f 1666 #define MATCH_VREM_VV 0x8c002057 1667 #define MASK_VREM_VV 0xfc00707f 1668 #define MATCH_VMULHU_VV 0x90002057 1669 #define MASK_VMULHU_VV 0xfc00707f 1670 #define MATCH_VMUL_VV 0x94002057 1671 #define MASK_VMUL_VV 0xfc00707f 1672 #define MATCH_VMULHSU_VV 0x98002057 1673 #define MASK_VMULHSU_VV 0xfc00707f 1674 #define MATCH_VMULH_VV 0x9c002057 1675 #define MASK_VMULH_VV 0xfc00707f 1676 #define MATCH_VMADD_VV 0xa4002057 1677 #define MASK_VMADD_VV 0xfc00707f 1678 #define MATCH_VNMSUB_VV 0xac002057 1679 #define MASK_VNMSUB_VV 0xfc00707f 1680 #define MATCH_VMACC_VV 0xb4002057 1681 #define MASK_VMACC_VV 0xfc00707f 1682 #define MATCH_VNMSAC_VV 0xbc002057 1683 #define MASK_VNMSAC_VV 0xfc00707f 1684 #define MATCH_VWADDU_VV 0xc0002057 1685 #define MASK_VWADDU_VV 0xfc00707f 1686 #define MATCH_VWADD_VV 0xc4002057 1687 #define MASK_VWADD_VV 0xfc00707f 1688 #define MATCH_VWSUBU_VV 0xc8002057 1689 #define MASK_VWSUBU_VV 0xfc00707f 1690 #define MATCH_VWSUB_VV 0xcc002057 1691 #define MASK_VWSUB_VV 0xfc00707f 1692 #define MATCH_VWADDU_WV 0xd0002057 1693 #define MASK_VWADDU_WV 0xfc00707f 1694 #define MATCH_VWADD_WV 0xd4002057 1695 #define MASK_VWADD_WV 0xfc00707f 1696 #define MATCH_VWSUBU_WV 0xd8002057 1697 #define MASK_VWSUBU_WV 0xfc00707f 1698 #define MATCH_VWSUB_WV 0xdc002057 1699 #define MASK_VWSUB_WV 0xfc00707f 1700 #define MATCH_VWMULU_VV 0xe0002057 1701 #define MASK_VWMULU_VV 0xfc00707f 1702 #define MATCH_VWMULSU_VV 0xe8002057 1703 #define MASK_VWMULSU_VV 0xfc00707f 1704 #define MATCH_VWMUL_VV 0xec002057 1705 #define MASK_VWMUL_VV 0xfc00707f 1706 #define MATCH_VWMACCU_VV 0xf0002057 1707 #define MASK_VWMACCU_VV 0xfc00707f 1708 #define MATCH_VWMACC_VV 0xf4002057 1709 #define MASK_VWMACC_VV 0xfc00707f 1710 #define MATCH_VWMACCSU_VV 0xfc002057 1711 #define MASK_VWMACCSU_VV 0xfc00707f 1712 #define MATCH_VAADDU_VX 0x20006057 1713 #define MASK_VAADDU_VX 0xfc00707f 1714 #define MATCH_VAADD_VX 0x24006057 1715 #define MASK_VAADD_VX 0xfc00707f 1716 #define MATCH_VASUBU_VX 0x28006057 1717 #define MASK_VASUBU_VX 0xfc00707f 1718 #define MATCH_VASUB_VX 0x2c006057 1719 #define MASK_VASUB_VX 0xfc00707f 1720 #define MATCH_VMV_S_X 0x42006057 1721 #define MASK_VMV_S_X 0xfff0707f 1722 #define MATCH_VSLIDE1UP_VX 0x38006057 1723 #define MASK_VSLIDE1UP_VX 0xfc00707f 1724 #define MATCH_VSLIDE1DOWN_VX 0x3c006057 1725 #define MASK_VSLIDE1DOWN_VX 0xfc00707f 1726 #define MATCH_VDIVU_VX 0x80006057 1727 #define MASK_VDIVU_VX 0xfc00707f 1728 #define MATCH_VDIV_VX 0x84006057 1729 #define MASK_VDIV_VX 0xfc00707f 1730 #define MATCH_VREMU_VX 0x88006057 1731 #define MASK_VREMU_VX 0xfc00707f 1732 #define MATCH_VREM_VX 0x8c006057 1733 #define MASK_VREM_VX 0xfc00707f 1734 #define MATCH_VMULHU_VX 0x90006057 1735 #define MASK_VMULHU_VX 0xfc00707f 1736 #define MATCH_VMUL_VX 0x94006057 1737 #define MASK_VMUL_VX 0xfc00707f 1738 #define MATCH_VMULHSU_VX 0x98006057 1739 #define MASK_VMULHSU_VX 0xfc00707f 1740 #define MATCH_VMULH_VX 0x9c006057 1741 #define MASK_VMULH_VX 0xfc00707f 1742 #define MATCH_VMADD_VX 0xa4006057 1743 #define MASK_VMADD_VX 0xfc00707f 1744 #define MATCH_VNMSUB_VX 0xac006057 1745 #define MASK_VNMSUB_VX 0xfc00707f 1746 #define MATCH_VMACC_VX 0xb4006057 1747 #define MASK_VMACC_VX 0xfc00707f 1748 #define MATCH_VNMSAC_VX 0xbc006057 1749 #define MASK_VNMSAC_VX 0xfc00707f 1750 #define MATCH_VWADDU_VX 0xc0006057 1751 #define MASK_VWADDU_VX 0xfc00707f 1752 #define MATCH_VWADD_VX 0xc4006057 1753 #define MASK_VWADD_VX 0xfc00707f 1754 #define MATCH_VWSUBU_VX 0xc8006057 1755 #define MASK_VWSUBU_VX 0xfc00707f 1756 #define MATCH_VWSUB_VX 0xcc006057 1757 #define MASK_VWSUB_VX 0xfc00707f 1758 #define MATCH_VWADDU_WX 0xd0006057 1759 #define MASK_VWADDU_WX 0xfc00707f 1760 #define MATCH_VWADD_WX 0xd4006057 1761 #define MASK_VWADD_WX 0xfc00707f 1762 #define MATCH_VWSUBU_WX 0xd8006057 1763 #define MASK_VWSUBU_WX 0xfc00707f 1764 #define MATCH_VWSUB_WX 0xdc006057 1765 #define MASK_VWSUB_WX 0xfc00707f 1766 #define MATCH_VWMULU_VX 0xe0006057 1767 #define MASK_VWMULU_VX 0xfc00707f 1768 #define MATCH_VWMULSU_VX 0xe8006057 1769 #define MASK_VWMULSU_VX 0xfc00707f 1770 #define MATCH_VWMUL_VX 0xec006057 1771 #define MASK_VWMUL_VX 0xfc00707f 1772 #define MATCH_VWMACCU_VX 0xf0006057 1773 #define MASK_VWMACCU_VX 0xfc00707f 1774 #define MATCH_VWMACC_VX 0xf4006057 1775 #define MASK_VWMACC_VX 0xfc00707f 1776 #define MATCH_VWMACCUS_VX 0xf8006057 1777 #define MASK_VWMACCUS_VX 0xfc00707f 1778 #define MATCH_VWMACCSU_VX 0xfc006057 1779 #define MASK_VWMACCSU_VX 0xfc00707f 1780 #define MATCH_VAMOSWAPEI8_V 0x800002f 1781 #define MASK_VAMOSWAPEI8_V 0xf800707f 1782 #define MATCH_VAMOADDEI8_V 0x2f 1783 #define MASK_VAMOADDEI8_V 0xf800707f 1784 #define MATCH_VAMOXOREI8_V 0x2000002f 1785 #define MASK_VAMOXOREI8_V 0xf800707f 1786 #define MATCH_VAMOANDEI8_V 0x6000002f 1787 #define MASK_VAMOANDEI8_V 0xf800707f 1788 #define MATCH_VAMOOREI8_V 0x4000002f 1789 #define MASK_VAMOOREI8_V 0xf800707f 1790 #define MATCH_VAMOMINEI8_V 0x8000002f 1791 #define MASK_VAMOMINEI8_V 0xf800707f 1792 #define MATCH_VAMOMAXEI8_V 0xa000002f 1793 #define MASK_VAMOMAXEI8_V 0xf800707f 1794 #define MATCH_VAMOMINUEI8_V 0xc000002f 1795 #define MASK_VAMOMINUEI8_V 0xf800707f 1796 #define MATCH_VAMOMAXUEI8_V 0xe000002f 1797 #define MASK_VAMOMAXUEI8_V 0xf800707f 1798 #define MATCH_VAMOSWAPEI16_V 0x800502f 1799 #define MASK_VAMOSWAPEI16_V 0xf800707f 1800 #define MATCH_VAMOADDEI16_V 0x502f 1801 #define MASK_VAMOADDEI16_V 0xf800707f 1802 #define MATCH_VAMOXOREI16_V 0x2000502f 1803 #define MASK_VAMOXOREI16_V 0xf800707f 1804 #define MATCH_VAMOANDEI16_V 0x6000502f 1805 #define MASK_VAMOANDEI16_V 0xf800707f 1806 #define MATCH_VAMOOREI16_V 0x4000502f 1807 #define MASK_VAMOOREI16_V 0xf800707f 1808 #define MATCH_VAMOMINEI16_V 0x8000502f 1809 #define MASK_VAMOMINEI16_V 0xf800707f 1810 #define MATCH_VAMOMAXEI16_V 0xa000502f 1811 #define MASK_VAMOMAXEI16_V 0xf800707f 1812 #define MATCH_VAMOMINUEI16_V 0xc000502f 1813 #define MASK_VAMOMINUEI16_V 0xf800707f 1814 #define MATCH_VAMOMAXUEI16_V 0xe000502f 1815 #define MASK_VAMOMAXUEI16_V 0xf800707f 1816 #define MATCH_VAMOSWAPEI32_V 0x800602f 1817 #define MASK_VAMOSWAPEI32_V 0xf800707f 1818 #define MATCH_VAMOADDEI32_V 0x602f 1819 #define MASK_VAMOADDEI32_V 0xf800707f 1820 #define MATCH_VAMOXOREI32_V 0x2000602f 1821 #define MASK_VAMOXOREI32_V 0xf800707f 1822 #define MATCH_VAMOANDEI32_V 0x6000602f 1823 #define MASK_VAMOANDEI32_V 0xf800707f 1824 #define MATCH_VAMOOREI32_V 0x4000602f 1825 #define MASK_VAMOOREI32_V 0xf800707f 1826 #define MATCH_VAMOMINEI32_V 0x8000602f 1827 #define MASK_VAMOMINEI32_V 0xf800707f 1828 #define MATCH_VAMOMAXEI32_V 0xa000602f 1829 #define MASK_VAMOMAXEI32_V 0xf800707f 1830 #define MATCH_VAMOMINUEI32_V 0xc000602f 1831 #define MASK_VAMOMINUEI32_V 0xf800707f 1832 #define MATCH_VAMOMAXUEI32_V 0xe000602f 1833 #define MASK_VAMOMAXUEI32_V 0xf800707f 1834 #define MATCH_VAMOSWAPEI64_V 0x800702f 1835 #define MASK_VAMOSWAPEI64_V 0xf800707f 1836 #define MATCH_VAMOADDEI64_V 0x702f 1837 #define MASK_VAMOADDEI64_V 0xf800707f 1838 #define MATCH_VAMOXOREI64_V 0x2000702f 1839 #define MASK_VAMOXOREI64_V 0xf800707f 1840 #define MATCH_VAMOANDEI64_V 0x6000702f 1841 #define MASK_VAMOANDEI64_V 0xf800707f 1842 #define MATCH_VAMOOREI64_V 0x4000702f 1843 #define MASK_VAMOOREI64_V 0xf800707f 1844 #define MATCH_VAMOMINEI64_V 0x8000702f 1845 #define MASK_VAMOMINEI64_V 0xf800707f 1846 #define MATCH_VAMOMAXEI64_V 0xa000702f 1847 #define MASK_VAMOMAXEI64_V 0xf800707f 1848 #define MATCH_VAMOMINUEI64_V 0xc000702f 1849 #define MASK_VAMOMINUEI64_V 0xf800707f 1850 #define MATCH_VAMOMAXUEI64_V 0xe000702f 1851 #define MASK_VAMOMAXUEI64_V 0xf800707f 1852 #define MATCH_VMVNFR_V 0x9e003057 1853 #define MASK_VMVNFR_V 0xfe00707f 1854 #define MATCH_VL1R_V 0x2800007 1855 #define MASK_VL1R_V 0xfff0707f 1856 #define MATCH_VL2R_V 0x6805007 1857 #define MASK_VL2R_V 0xfff0707f 1858 #define MATCH_VL4R_V 0xe806007 1859 #define MASK_VL4R_V 0xfff0707f 1860 #define MATCH_VL8R_V 0x1e807007 1861 #define MASK_VL8R_V 0xfff0707f 1862 #define CSR_FFLAGS 0x1 1863 #define CSR_FRM 0x2 1864 #define CSR_FCSR 0x3 1865 #define CSR_USTATUS 0x0 1866 #define CSR_UIE 0x4 1867 #define CSR_UTVEC 0x5 1868 #define CSR_VSTART 0x8 1869 #define CSR_VXSAT 0x9 1870 #define CSR_VXRM 0xa 1871 #define CSR_VCSR 0xf 1872 #define CSR_USCRATCH 0x40 1873 #define CSR_UEPC 0x41 1874 #define CSR_UCAUSE 0x42 1875 #define CSR_UTVAL 0x43 1876 #define CSR_UIP 0x44 1877 #define CSR_CYCLE 0xc00 1878 #define CSR_TIME 0xc01 1879 #define CSR_INSTRET 0xc02 1880 #define CSR_HPMCOUNTER3 0xc03 1881 #define CSR_HPMCOUNTER4 0xc04 1882 #define CSR_HPMCOUNTER5 0xc05 1883 #define CSR_HPMCOUNTER6 0xc06 1884 #define CSR_HPMCOUNTER7 0xc07 1885 #define CSR_HPMCOUNTER8 0xc08 1886 #define CSR_HPMCOUNTER9 0xc09 1887 #define CSR_HPMCOUNTER10 0xc0a 1888 #define CSR_HPMCOUNTER11 0xc0b 1889 #define CSR_HPMCOUNTER12 0xc0c 1890 #define CSR_HPMCOUNTER13 0xc0d 1891 #define CSR_HPMCOUNTER14 0xc0e 1892 #define CSR_HPMCOUNTER15 0xc0f 1893 #define CSR_HPMCOUNTER16 0xc10 1894 #define CSR_HPMCOUNTER17 0xc11 1895 #define CSR_HPMCOUNTER18 0xc12 1896 #define CSR_HPMCOUNTER19 0xc13 1897 #define CSR_HPMCOUNTER20 0xc14 1898 #define CSR_HPMCOUNTER21 0xc15 1899 #define CSR_HPMCOUNTER22 0xc16 1900 #define CSR_HPMCOUNTER23 0xc17 1901 #define CSR_HPMCOUNTER24 0xc18 1902 #define CSR_HPMCOUNTER25 0xc19 1903 #define CSR_HPMCOUNTER26 0xc1a 1904 #define CSR_HPMCOUNTER27 0xc1b 1905 #define CSR_HPMCOUNTER28 0xc1c 1906 #define CSR_HPMCOUNTER29 0xc1d 1907 #define CSR_HPMCOUNTER30 0xc1e 1908 #define CSR_HPMCOUNTER31 0xc1f 1909 #define CSR_VL 0xc20 1910 #define CSR_VTYPE 0xc21 1911 #define CSR_VLENB 0xc22 1912 #define CSR_SSTATUS 0x100 1913 #define CSR_SEDELEG 0x102 1914 #define CSR_SIDELEG 0x103 1915 #define CSR_SIE 0x104 1916 #define CSR_STVEC 0x105 1917 #define CSR_SCOUNTEREN 0x106 1918 #define CSR_SSCRATCH 0x140 1919 #define CSR_SEPC 0x141 1920 #define CSR_SCAUSE 0x142 1921 #define CSR_STVAL 0x143 1922 #define CSR_SIP 0x144 1923 #define CSR_SATP 0x180 1924 #define CSR_VSSTATUS 0x200 1925 #define CSR_VSIE 0x204 1926 #define CSR_VSTVEC 0x205 1927 #define CSR_VSSCRATCH 0x240 1928 #define CSR_VSEPC 0x241 1929 #define CSR_VSCAUSE 0x242 1930 #define CSR_VSTVAL 0x243 1931 #define CSR_VSIP 0x244 1932 #define CSR_VSATP 0x280 1933 #define CSR_HSTATUS 0x600 1934 #define CSR_HEDELEG 0x602 1935 #define CSR_HIDELEG 0x603 1936 #define CSR_HIE 0x604 1937 #define CSR_HTIMEDELTA 0x605 1938 #define CSR_HCOUNTEREN 0x606 1939 #define CSR_HGEIE 0x607 1940 #define CSR_HTVAL 0x643 1941 #define CSR_HIP 0x644 1942 #define CSR_HVIP 0x645 1943 #define CSR_HTINST 0x64a 1944 #define CSR_HGATP 0x680 1945 #define CSR_HGEIP 0xe12 1946 #define CSR_UTVT 0x7 1947 #define CSR_UNXTI 0x45 1948 #define CSR_UINTSTATUS 0x46 1949 #define CSR_USCRATCHCSW 0x48 1950 #define CSR_USCRATCHCSWL 0x49 1951 #define CSR_STVT 0x107 1952 #define CSR_SNXTI 0x145 1953 #define CSR_SINTSTATUS 0x146 1954 #define CSR_SSCRATCHCSW 0x148 1955 #define CSR_SSCRATCHCSWL 0x149 1956 #define CSR_MTVT 0x307 1957 #define CSR_MNXTI 0x345 1958 #define CSR_MINTSTATUS 0x346 1959 #define CSR_MSCRATCHCSW 0x348 1960 #define CSR_MSCRATCHCSWL 0x349 1961 #define CSR_MSTATUS 0x300 1962 #define CSR_MISA 0x301 1963 #define CSR_MEDELEG 0x302 1964 #define CSR_MIDELEG 0x303 1965 #define CSR_MIE 0x304 1966 #define CSR_MTVEC 0x305 1967 #define CSR_MCOUNTEREN 0x306 1968 #define CSR_MCOUNTINHIBIT 0x320 1969 #define CSR_MSCRATCH 0x340 1970 #define CSR_MEPC 0x341 1971 #define CSR_MCAUSE 0x342 1972 #define CSR_MTVAL 0x343 1973 #define CSR_MIP 0x344 1974 #define CSR_MTINST 0x34a 1975 #define CSR_MTVAL2 0x34b 1976 #define CSR_PMPCFG0 0x3a0 1977 #define CSR_PMPCFG1 0x3a1 1978 #define CSR_PMPCFG2 0x3a2 1979 #define CSR_PMPCFG3 0x3a3 1980 #define CSR_PMPADDR0 0x3b0 1981 #define CSR_PMPADDR1 0x3b1 1982 #define CSR_PMPADDR2 0x3b2 1983 #define CSR_PMPADDR3 0x3b3 1984 #define CSR_PMPADDR4 0x3b4 1985 #define CSR_PMPADDR5 0x3b5 1986 #define CSR_PMPADDR6 0x3b6 1987 #define CSR_PMPADDR7 0x3b7 1988 #define CSR_PMPADDR8 0x3b8 1989 #define CSR_PMPADDR9 0x3b9 1990 #define CSR_PMPADDR10 0x3ba 1991 #define CSR_PMPADDR11 0x3bb 1992 #define CSR_PMPADDR12 0x3bc 1993 #define CSR_PMPADDR13 0x3bd 1994 #define CSR_PMPADDR14 0x3be 1995 #define CSR_PMPADDR15 0x3bf 1996 #define CSR_TSELECT 0x7a0 1997 #define CSR_TDATA1 0x7a1 1998 #define CSR_TDATA2 0x7a2 1999 #define CSR_TDATA3 0x7a3 2000 #define CSR_TINFO 0x7a4 2001 #define CSR_TCONTROL 0x7a5 2002 #define CSR_MCONTEXT 0x7a8 2003 #define CSR_SCONTEXT 0x7aa 2004 #define CSR_DCSR 0x7b0 2005 #define CSR_DPC 0x7b1 2006 #define CSR_DSCRATCH0 0x7b2 2007 #define CSR_DSCRATCH1 0x7b3 2008 #define CSR_MCYCLE 0xb00 2009 #define CSR_MINSTRET 0xb02 2010 #define CSR_MHPMCOUNTER3 0xb03 2011 #define CSR_MHPMCOUNTER4 0xb04 2012 #define CSR_MHPMCOUNTER5 0xb05 2013 #define CSR_MHPMCOUNTER6 0xb06 2014 #define CSR_MHPMCOUNTER7 0xb07 2015 #define CSR_MHPMCOUNTER8 0xb08 2016 #define CSR_MHPMCOUNTER9 0xb09 2017 #define CSR_MHPMCOUNTER10 0xb0a 2018 #define CSR_MHPMCOUNTER11 0xb0b 2019 #define CSR_MHPMCOUNTER12 0xb0c 2020 #define CSR_MHPMCOUNTER13 0xb0d 2021 #define CSR_MHPMCOUNTER14 0xb0e 2022 #define CSR_MHPMCOUNTER15 0xb0f 2023 #define CSR_MHPMCOUNTER16 0xb10 2024 #define CSR_MHPMCOUNTER17 0xb11 2025 #define CSR_MHPMCOUNTER18 0xb12 2026 #define CSR_MHPMCOUNTER19 0xb13 2027 #define CSR_MHPMCOUNTER20 0xb14 2028 #define CSR_MHPMCOUNTER21 0xb15 2029 #define CSR_MHPMCOUNTER22 0xb16 2030 #define CSR_MHPMCOUNTER23 0xb17 2031 #define CSR_MHPMCOUNTER24 0xb18 2032 #define CSR_MHPMCOUNTER25 0xb19 2033 #define CSR_MHPMCOUNTER26 0xb1a 2034 #define CSR_MHPMCOUNTER27 0xb1b 2035 #define CSR_MHPMCOUNTER28 0xb1c 2036 #define CSR_MHPMCOUNTER29 0xb1d 2037 #define CSR_MHPMCOUNTER30 0xb1e 2038 #define CSR_MHPMCOUNTER31 0xb1f 2039 #define CSR_MHPMEVENT3 0x323 2040 #define CSR_MHPMEVENT4 0x324 2041 #define CSR_MHPMEVENT5 0x325 2042 #define CSR_MHPMEVENT6 0x326 2043 #define CSR_MHPMEVENT7 0x327 2044 #define CSR_MHPMEVENT8 0x328 2045 #define CSR_MHPMEVENT9 0x329 2046 #define CSR_MHPMEVENT10 0x32a 2047 #define CSR_MHPMEVENT11 0x32b 2048 #define CSR_MHPMEVENT12 0x32c 2049 #define CSR_MHPMEVENT13 0x32d 2050 #define CSR_MHPMEVENT14 0x32e 2051 #define CSR_MHPMEVENT15 0x32f 2052 #define CSR_MHPMEVENT16 0x330 2053 #define CSR_MHPMEVENT17 0x331 2054 #define CSR_MHPMEVENT18 0x332 2055 #define CSR_MHPMEVENT19 0x333 2056 #define CSR_MHPMEVENT20 0x334 2057 #define CSR_MHPMEVENT21 0x335 2058 #define CSR_MHPMEVENT22 0x336 2059 #define CSR_MHPMEVENT23 0x337 2060 #define CSR_MHPMEVENT24 0x338 2061 #define CSR_MHPMEVENT25 0x339 2062 #define CSR_MHPMEVENT26 0x33a 2063 #define CSR_MHPMEVENT27 0x33b 2064 #define CSR_MHPMEVENT28 0x33c 2065 #define CSR_MHPMEVENT29 0x33d 2066 #define CSR_MHPMEVENT30 0x33e 2067 #define CSR_MHPMEVENT31 0x33f 2068 #define CSR_MVENDORID 0xf11 2069 #define CSR_MARCHID 0xf12 2070 #define CSR_MIMPID 0xf13 2071 #define CSR_MHARTID 0xf14 2072 #define CSR_MENTROPY 0xf15 2073 #define CSR_MNOISE 0x7a9 2074 #define CSR_HTIMEDELTAH 0x615 2075 #define CSR_CYCLEH 0xc80 2076 #define CSR_TIMEH 0xc81 2077 #define CSR_INSTRETH 0xc82 2078 #define CSR_HPMCOUNTER3H 0xc83 2079 #define CSR_HPMCOUNTER4H 0xc84 2080 #define CSR_HPMCOUNTER5H 0xc85 2081 #define CSR_HPMCOUNTER6H 0xc86 2082 #define CSR_HPMCOUNTER7H 0xc87 2083 #define CSR_HPMCOUNTER8H 0xc88 2084 #define CSR_HPMCOUNTER9H 0xc89 2085 #define CSR_HPMCOUNTER10H 0xc8a 2086 #define CSR_HPMCOUNTER11H 0xc8b 2087 #define CSR_HPMCOUNTER12H 0xc8c 2088 #define CSR_HPMCOUNTER13H 0xc8d 2089 #define CSR_HPMCOUNTER14H 0xc8e 2090 #define CSR_HPMCOUNTER15H 0xc8f 2091 #define CSR_HPMCOUNTER16H 0xc90 2092 #define CSR_HPMCOUNTER17H 0xc91 2093 #define CSR_HPMCOUNTER18H 0xc92 2094 #define CSR_HPMCOUNTER19H 0xc93 2095 #define CSR_HPMCOUNTER20H 0xc94 2096 #define CSR_HPMCOUNTER21H 0xc95 2097 #define CSR_HPMCOUNTER22H 0xc96 2098 #define CSR_HPMCOUNTER23H 0xc97 2099 #define CSR_HPMCOUNTER24H 0xc98 2100 #define CSR_HPMCOUNTER25H 0xc99 2101 #define CSR_HPMCOUNTER26H 0xc9a 2102 #define CSR_HPMCOUNTER27H 0xc9b 2103 #define CSR_HPMCOUNTER28H 0xc9c 2104 #define CSR_HPMCOUNTER29H 0xc9d 2105 #define CSR_HPMCOUNTER30H 0xc9e 2106 #define CSR_HPMCOUNTER31H 0xc9f 2107 #define CSR_MSTATUSH 0x310 2108 #define CSR_MCYCLEH 0xb80 2109 #define CSR_MINSTRETH 0xb82 2110 #define CSR_MHPMCOUNTER3H 0xb83 2111 #define CSR_MHPMCOUNTER4H 0xb84 2112 #define CSR_MHPMCOUNTER5H 0xb85 2113 #define CSR_MHPMCOUNTER6H 0xb86 2114 #define CSR_MHPMCOUNTER7H 0xb87 2115 #define CSR_MHPMCOUNTER8H 0xb88 2116 #define CSR_MHPMCOUNTER9H 0xb89 2117 #define CSR_MHPMCOUNTER10H 0xb8a 2118 #define CSR_MHPMCOUNTER11H 0xb8b 2119 #define CSR_MHPMCOUNTER12H 0xb8c 2120 #define CSR_MHPMCOUNTER13H 0xb8d 2121 #define CSR_MHPMCOUNTER14H 0xb8e 2122 #define CSR_MHPMCOUNTER15H 0xb8f 2123 #define CSR_MHPMCOUNTER16H 0xb90 2124 #define CSR_MHPMCOUNTER17H 0xb91 2125 #define CSR_MHPMCOUNTER18H 0xb92 2126 #define CSR_MHPMCOUNTER19H 0xb93 2127 #define CSR_MHPMCOUNTER20H 0xb94 2128 #define CSR_MHPMCOUNTER21H 0xb95 2129 #define CSR_MHPMCOUNTER22H 0xb96 2130 #define CSR_MHPMCOUNTER23H 0xb97 2131 #define CSR_MHPMCOUNTER24H 0xb98 2132 #define CSR_MHPMCOUNTER25H 0xb99 2133 #define CSR_MHPMCOUNTER26H 0xb9a 2134 #define CSR_MHPMCOUNTER27H 0xb9b 2135 #define CSR_MHPMCOUNTER28H 0xb9c 2136 #define CSR_MHPMCOUNTER29H 0xb9d 2137 #define CSR_MHPMCOUNTER30H 0xb9e 2138 #define CSR_MHPMCOUNTER31H 0xb9f 2139 #define CAUSE_MISALIGNED_FETCH 0x0 2140 #define CAUSE_FETCH_ACCESS 0x1 2141 #define CAUSE_ILLEGAL_INSTRUCTION 0x2 2142 #define CAUSE_BREAKPOINT 0x3 2143 #define CAUSE_MISALIGNED_LOAD 0x4 2144 #define CAUSE_LOAD_ACCESS 0x5 2145 #define CAUSE_MISALIGNED_STORE 0x6 2146 #define CAUSE_STORE_ACCESS 0x7 2147 #define CAUSE_USER_ECALL 0x8 2148 #define CAUSE_SUPERVISOR_ECALL 0x9 2149 #define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa 2150 #define CAUSE_MACHINE_ECALL 0xb 2151 #define CAUSE_FETCH_PAGE_FAULT 0xc 2152 #define CAUSE_LOAD_PAGE_FAULT 0xd 2153 #define CAUSE_STORE_PAGE_FAULT 0xf 2154 #define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 2155 #define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 2156 #define CAUSE_VIRTUAL_INSTRUCTION 0x16 2157 #define CAUSE_STORE_GUEST_PAGE_FAULT 0x17 2158 #endif 2159 #ifdef DECLARE_INSN 2160 DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) 2161 DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32) 2162 DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32) 2163 DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS) 2164 DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS) 2165 DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI) 2166 DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM) 2167 DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM) 2168 DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI) 2169 DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR) 2170 DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR) 2171 DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE) 2172 DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME) 2173 DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET) 2174 DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH) 2175 DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH) 2176 DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH) 2177 DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL) 2178 DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK) 2179 DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) 2180 DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) 2181 DECLARE_INSN(fence_tso, MATCH_FENCE_TSO, MASK_FENCE_TSO) 2182 DECLARE_INSN(pause, MATCH_PAUSE, MASK_PAUSE) 2183 DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) 2184 DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) 2185 DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) 2186 DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) 2187 DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) 2188 DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) 2189 DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) 2190 DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) 2191 DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) 2192 DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) 2193 DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) 2194 DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) 2195 DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) 2196 DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) 2197 DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) 2198 DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) 2199 DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) 2200 DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) 2201 DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) 2202 DECLARE_INSN(add, MATCH_ADD, MASK_ADD) 2203 DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) 2204 DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) 2205 DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) 2206 DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) 2207 DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) 2208 DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) 2209 DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) 2210 DECLARE_INSN(or, MATCH_OR, MASK_OR) 2211 DECLARE_INSN(and, MATCH_AND, MASK_AND) 2212 DECLARE_INSN(lb, MATCH_LB, MASK_LB) 2213 DECLARE_INSN(lh, MATCH_LH, MASK_LH) 2214 DECLARE_INSN(lw, MATCH_LW, MASK_LW) 2215 DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) 2216 DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) 2217 DECLARE_INSN(sb, MATCH_SB, MASK_SB) 2218 DECLARE_INSN(sh, MATCH_SH, MASK_SH) 2219 DECLARE_INSN(sw, MATCH_SW, MASK_SW) 2220 DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) 2221 DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) 2222 DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) 2223 DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) 2224 DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) 2225 DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) 2226 DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) 2227 DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) 2228 DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) 2229 DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) 2230 DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) 2231 DECLARE_INSN(ld, MATCH_LD, MASK_LD) 2232 DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) 2233 DECLARE_INSN(sd, MATCH_SD, MASK_SD) 2234 DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) 2235 DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) 2236 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) 2237 DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) 2238 DECLARE_INSN(div, MATCH_DIV, MASK_DIV) 2239 DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) 2240 DECLARE_INSN(rem, MATCH_REM, MASK_REM) 2241 DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) 2242 DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) 2243 DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) 2244 DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) 2245 DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) 2246 DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) 2247 DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) 2248 DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) 2249 DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) 2250 DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) 2251 DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) 2252 DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) 2253 DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) 2254 DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) 2255 DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) 2256 DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) 2257 DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) 2258 DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) 2259 DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) 2260 DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) 2261 DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) 2262 DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) 2263 DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) 2264 DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) 2265 DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) 2266 DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) 2267 DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) 2268 DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) 2269 DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA) 2270 DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA) 2271 DECLARE_INSN(hlv_b, MATCH_HLV_B, MASK_HLV_B) 2272 DECLARE_INSN(hlv_bu, MATCH_HLV_BU, MASK_HLV_BU) 2273 DECLARE_INSN(hlv_h, MATCH_HLV_H, MASK_HLV_H) 2274 DECLARE_INSN(hlv_hu, MATCH_HLV_HU, MASK_HLV_HU) 2275 DECLARE_INSN(hlvx_hu, MATCH_HLVX_HU, MASK_HLVX_HU) 2276 DECLARE_INSN(hlv_w, MATCH_HLV_W, MASK_HLV_W) 2277 DECLARE_INSN(hlvx_wu, MATCH_HLVX_WU, MASK_HLVX_WU) 2278 DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B) 2279 DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H) 2280 DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W) 2281 DECLARE_INSN(hlv_wu, MATCH_HLV_WU, MASK_HLV_WU) 2282 DECLARE_INSN(hlv_d, MATCH_HLV_D, MASK_HLV_D) 2283 DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D) 2284 DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) 2285 DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) 2286 DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) 2287 DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) 2288 DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) 2289 DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) 2290 DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) 2291 DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) 2292 DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) 2293 DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) 2294 DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) 2295 DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) 2296 DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) 2297 DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) 2298 DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) 2299 DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) 2300 DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) 2301 DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) 2302 DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) 2303 DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) 2304 DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) 2305 DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) 2306 DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) 2307 DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) 2308 DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) 2309 DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) 2310 DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) 2311 DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) 2312 DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) 2313 DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) 2314 DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) 2315 DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) 2316 DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) 2317 DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) 2318 DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) 2319 DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) 2320 DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) 2321 DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) 2322 DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) 2323 DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) 2324 DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) 2325 DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) 2326 DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) 2327 DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) 2328 DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) 2329 DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) 2330 DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) 2331 DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) 2332 DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) 2333 DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) 2334 DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) 2335 DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) 2336 DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) 2337 DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) 2338 DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) 2339 DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) 2340 DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) 2341 DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) 2342 DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) 2343 DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) 2344 DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) 2345 DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) 2346 DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) 2347 DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) 2348 DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) 2349 DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) 2350 DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) 2351 DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) 2352 DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) 2353 DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) 2354 DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) 2355 DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) 2356 DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) 2357 DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) 2358 DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) 2359 DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) 2360 DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) 2361 DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) 2362 DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) 2363 DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) 2364 DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) 2365 DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) 2366 DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) 2367 DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) 2368 DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) 2369 DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) 2370 DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) 2371 DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) 2372 DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) 2373 DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) 2374 DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) 2375 DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) 2376 DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) 2377 DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) 2378 DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN) 2379 DECLARE_INSN(orn, MATCH_ORN, MASK_ORN) 2380 DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR) 2381 DECLARE_INSN(slo, MATCH_SLO, MASK_SLO) 2382 DECLARE_INSN(sro, MATCH_SRO, MASK_SRO) 2383 DECLARE_INSN(rol, MATCH_ROL, MASK_ROL) 2384 DECLARE_INSN(ror, MATCH_ROR, MASK_ROR) 2385 DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR) 2386 DECLARE_INSN(bset, MATCH_BSET, MASK_BSET) 2387 DECLARE_INSN(binv, MATCH_BINV, MASK_BINV) 2388 DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT) 2389 DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC) 2390 DECLARE_INSN(grev, MATCH_GREV, MASK_GREV) 2391 DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI) 2392 DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI) 2393 DECLARE_INSN(rori, MATCH_RORI, MASK_RORI) 2394 DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI) 2395 DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI) 2396 DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI) 2397 DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI) 2398 DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI) 2399 DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI) 2400 DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX) 2401 DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV) 2402 DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL) 2403 DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR) 2404 DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI) 2405 DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ) 2406 DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ) 2407 DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP) 2408 DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B) 2409 DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H) 2410 DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B) 2411 DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H) 2412 DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W) 2413 DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B) 2414 DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H) 2415 DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W) 2416 DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD) 2417 DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD) 2418 DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD) 2419 DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL) 2420 DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR) 2421 DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH) 2422 DECLARE_INSN(min, MATCH_MIN, MASK_MIN) 2423 DECLARE_INSN(minu, MATCH_MINU, MASK_MINU) 2424 DECLARE_INSN(max, MATCH_MAX, MASK_MAX) 2425 DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU) 2426 DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL) 2427 DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL) 2428 DECLARE_INSN(bcompress, MATCH_BCOMPRESS, MASK_BCOMPRESS) 2429 DECLARE_INSN(bdecompress, MATCH_BDECOMPRESS, MASK_BDECOMPRESS) 2430 DECLARE_INSN(pack, MATCH_PACK, MASK_PACK) 2431 DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU) 2432 DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH) 2433 DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP) 2434 DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI) 2435 DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI) 2436 DECLARE_INSN(xperm_n, MATCH_XPERM_N, MASK_XPERM_N) 2437 DECLARE_INSN(xperm_b, MATCH_XPERM_B, MASK_XPERM_B) 2438 DECLARE_INSN(xperm_h, MATCH_XPERM_H, MASK_XPERM_H) 2439 DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP) 2440 DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D) 2441 DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D) 2442 DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR) 2443 DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR) 2444 DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW) 2445 DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW) 2446 DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW) 2447 DECLARE_INSN(srow, MATCH_SROW, MASK_SROW) 2448 DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW) 2449 DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW) 2450 DECLARE_INSN(sbclrw, MATCH_SBCLRW, MASK_SBCLRW) 2451 DECLARE_INSN(sbsetw, MATCH_SBSETW, MASK_SBSETW) 2452 DECLARE_INSN(sbinvw, MATCH_SBINVW, MASK_SBINVW) 2453 DECLARE_INSN(sbextw, MATCH_SBEXTW, MASK_SBEXTW) 2454 DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW) 2455 DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW) 2456 DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW) 2457 DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW) 2458 DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW) 2459 DECLARE_INSN(sbclriw, MATCH_SBCLRIW, MASK_SBCLRIW) 2460 DECLARE_INSN(sbsetiw, MATCH_SBSETIW, MASK_SBSETIW) 2461 DECLARE_INSN(sbinviw, MATCH_SBINVIW, MASK_SBINVIW) 2462 DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW) 2463 DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW) 2464 DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW) 2465 DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW) 2466 DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW) 2467 DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW) 2468 DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW) 2469 DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW) 2470 DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW) 2471 DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW) 2472 DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW) 2473 DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW) 2474 DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW) 2475 DECLARE_INSN(bcompressw, MATCH_BCOMPRESSW, MASK_BCOMPRESSW) 2476 DECLARE_INSN(bdecompressw, MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW) 2477 DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW) 2478 DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW) 2479 DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW) 2480 DECLARE_INSN(xperm_w, MATCH_XPERM_W, MASK_XPERM_W) 2481 DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) 2482 DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) 2483 DECLARE_INSN(uret, MATCH_URET, MASK_URET) 2484 DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) 2485 DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) 2486 DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) 2487 DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) 2488 DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) 2489 DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) 2490 DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) 2491 DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) 2492 DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) 2493 DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) 2494 DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) 2495 DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H) 2496 DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H) 2497 DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H) 2498 DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H) 2499 DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H) 2500 DECLARE_INSN(fsgnjn_h, MATCH_FSGNJN_H, MASK_FSGNJN_H) 2501 DECLARE_INSN(fsgnjx_h, MATCH_FSGNJX_H, MASK_FSGNJX_H) 2502 DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H) 2503 DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H) 2504 DECLARE_INSN(fcvt_h_s, MATCH_FCVT_H_S, MASK_FCVT_H_S) 2505 DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H) 2506 DECLARE_INSN(fsqrt_h, MATCH_FSQRT_H, MASK_FSQRT_H) 2507 DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H) 2508 DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H) 2509 DECLARE_INSN(feq_h, MATCH_FEQ_H, MASK_FEQ_H) 2510 DECLARE_INSN(fcvt_w_h, MATCH_FCVT_W_H, MASK_FCVT_W_H) 2511 DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H) 2512 DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H) 2513 DECLARE_INSN(fclass_h, MATCH_FCLASS_H, MASK_FCLASS_H) 2514 DECLARE_INSN(fcvt_h_w, MATCH_FCVT_H_W, MASK_FCVT_H_W) 2515 DECLARE_INSN(fcvt_h_wu, MATCH_FCVT_H_WU, MASK_FCVT_H_WU) 2516 DECLARE_INSN(fmv_h_x, MATCH_FMV_H_X, MASK_FMV_H_X) 2517 DECLARE_INSN(flh, MATCH_FLH, MASK_FLH) 2518 DECLARE_INSN(fsh, MATCH_FSH, MASK_FSH) 2519 DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H) 2520 DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H) 2521 DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H) 2522 DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H) 2523 DECLARE_INSN(fcvt_h_d, MATCH_FCVT_H_D, MASK_FCVT_H_D) 2524 DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H) 2525 DECLARE_INSN(fcvt_h_q, MATCH_FCVT_H_Q, MASK_FCVT_H_Q) 2526 DECLARE_INSN(fcvt_q_h, MATCH_FCVT_Q_H, MASK_FCVT_Q_H) 2527 DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H) 2528 DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H) 2529 DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L) 2530 DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU) 2531 DECLARE_INSN(pollentropy, MATCH_POLLENTROPY, MASK_POLLENTROPY) 2532 DECLARE_INSN(getnoise, MATCH_GETNOISE, MASK_GETNOISE) 2533 DECLARE_INSN(sm4ed, MATCH_SM4ED, MASK_SM4ED) 2534 DECLARE_INSN(sm4ks, MATCH_SM4KS, MASK_SM4KS) 2535 DECLARE_INSN(sm3p0, MATCH_SM3P0, MASK_SM3P0) 2536 DECLARE_INSN(sm3p1, MATCH_SM3P1, MASK_SM3P1) 2537 DECLARE_INSN(sha256sum0, MATCH_SHA256SUM0, MASK_SHA256SUM0) 2538 DECLARE_INSN(sha256sum1, MATCH_SHA256SUM1, MASK_SHA256SUM1) 2539 DECLARE_INSN(sha256sig0, MATCH_SHA256SIG0, MASK_SHA256SIG0) 2540 DECLARE_INSN(sha256sig1, MATCH_SHA256SIG1, MASK_SHA256SIG1) 2541 DECLARE_INSN(aes32esmi, MATCH_AES32ESMI, MASK_AES32ESMI) 2542 DECLARE_INSN(aes32esi, MATCH_AES32ESI, MASK_AES32ESI) 2543 DECLARE_INSN(aes32dsmi, MATCH_AES32DSMI, MASK_AES32DSMI) 2544 DECLARE_INSN(aes32dsi, MATCH_AES32DSI, MASK_AES32DSI) 2545 DECLARE_INSN(sha512sum0r, MATCH_SHA512SUM0R, MASK_SHA512SUM0R) 2546 DECLARE_INSN(sha512sum1r, MATCH_SHA512SUM1R, MASK_SHA512SUM1R) 2547 DECLARE_INSN(sha512sig0l, MATCH_SHA512SIG0L, MASK_SHA512SIG0L) 2548 DECLARE_INSN(sha512sig0h, MATCH_SHA512SIG0H, MASK_SHA512SIG0H) 2549 DECLARE_INSN(sha512sig1l, MATCH_SHA512SIG1L, MASK_SHA512SIG1L) 2550 DECLARE_INSN(sha512sig1h, MATCH_SHA512SIG1H, MASK_SHA512SIG1H) 2551 DECLARE_INSN(aes64ks1i, MATCH_AES64KS1I, MASK_AES64KS1I) 2552 DECLARE_INSN(aes64im, MATCH_AES64IM, MASK_AES64IM) 2553 DECLARE_INSN(aes64ks2, MATCH_AES64KS2, MASK_AES64KS2) 2554 DECLARE_INSN(aes64esm, MATCH_AES64ESM, MASK_AES64ESM) 2555 DECLARE_INSN(aes64es, MATCH_AES64ES, MASK_AES64ES) 2556 DECLARE_INSN(aes64dsm, MATCH_AES64DSM, MASK_AES64DSM) 2557 DECLARE_INSN(aes64ds, MATCH_AES64DS, MASK_AES64DS) 2558 DECLARE_INSN(sha512sum0, MATCH_SHA512SUM0, MASK_SHA512SUM0) 2559 DECLARE_INSN(sha512sum1, MATCH_SHA512SUM1, MASK_SHA512SUM1) 2560 DECLARE_INSN(sha512sig0, MATCH_SHA512SIG0, MASK_SHA512SIG0) 2561 DECLARE_INSN(sha512sig1, MATCH_SHA512SIG1, MASK_SHA512SIG1) 2562 DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) 2563 DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) 2564 DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) 2565 DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) 2566 DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) 2567 DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) 2568 DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) 2569 DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) 2570 DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) 2571 DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) 2572 DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) 2573 DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) 2574 DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) 2575 DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) 2576 DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) 2577 DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) 2578 DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) 2579 DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) 2580 DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) 2581 DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) 2582 DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) 2583 DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) 2584 DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) 2585 DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) 2586 DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) 2587 DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) 2588 DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) 2589 DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) 2590 DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) 2591 DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) 2592 DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) 2593 DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) 2594 DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) 2595 DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) 2596 DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) 2597 DECLARE_INSN(c_srli_rv32, MATCH_C_SRLI_RV32, MASK_C_SRLI_RV32) 2598 DECLARE_INSN(c_srai_rv32, MATCH_C_SRAI_RV32, MASK_C_SRAI_RV32) 2599 DECLARE_INSN(c_slli_rv32, MATCH_C_SLLI_RV32, MASK_C_SLLI_RV32) 2600 DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) 2601 DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) 2602 DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) 2603 DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) 2604 DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) 2605 DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) 2606 DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) 2607 DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) 2608 DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) 2609 DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) 2610 DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) 2611 DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) 2612 DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) 2613 DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) 2614 DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) 2615 DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) 2616 DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) 2617 DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) 2618 DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) 2619 DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) 2620 DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) 2621 DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) 2622 DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) 2623 DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) 2624 DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) 2625 DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) 2626 DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) 2627 DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) 2628 DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) 2629 DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) 2630 DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) 2631 DECLARE_INSN(vsetivli, MATCH_VSETIVLI, MASK_VSETIVLI) 2632 DECLARE_INSN(vsetvli, MATCH_VSETVLI, MASK_VSETVLI) 2633 DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL) 2634 DECLARE_INSN(vle1_v, MATCH_VLE1_V, MASK_VLE1_V) 2635 DECLARE_INSN(vse1_v, MATCH_VSE1_V, MASK_VSE1_V) 2636 DECLARE_INSN(vle8_v, MATCH_VLE8_V, MASK_VLE8_V) 2637 DECLARE_INSN(vle16_v, MATCH_VLE16_V, MASK_VLE16_V) 2638 DECLARE_INSN(vle32_v, MATCH_VLE32_V, MASK_VLE32_V) 2639 DECLARE_INSN(vle64_v, MATCH_VLE64_V, MASK_VLE64_V) 2640 DECLARE_INSN(vle128_v, MATCH_VLE128_V, MASK_VLE128_V) 2641 DECLARE_INSN(vle256_v, MATCH_VLE256_V, MASK_VLE256_V) 2642 DECLARE_INSN(vle512_v, MATCH_VLE512_V, MASK_VLE512_V) 2643 DECLARE_INSN(vle1024_v, MATCH_VLE1024_V, MASK_VLE1024_V) 2644 DECLARE_INSN(vse8_v, MATCH_VSE8_V, MASK_VSE8_V) 2645 DECLARE_INSN(vse16_v, MATCH_VSE16_V, MASK_VSE16_V) 2646 DECLARE_INSN(vse32_v, MATCH_VSE32_V, MASK_VSE32_V) 2647 DECLARE_INSN(vse64_v, MATCH_VSE64_V, MASK_VSE64_V) 2648 DECLARE_INSN(vse128_v, MATCH_VSE128_V, MASK_VSE128_V) 2649 DECLARE_INSN(vse256_v, MATCH_VSE256_V, MASK_VSE256_V) 2650 DECLARE_INSN(vse512_v, MATCH_VSE512_V, MASK_VSE512_V) 2651 DECLARE_INSN(vse1024_v, MATCH_VSE1024_V, MASK_VSE1024_V) 2652 DECLARE_INSN(vluxei8_v, MATCH_VLUXEI8_V, MASK_VLUXEI8_V) 2653 DECLARE_INSN(vluxei16_v, MATCH_VLUXEI16_V, MASK_VLUXEI16_V) 2654 DECLARE_INSN(vluxei32_v, MATCH_VLUXEI32_V, MASK_VLUXEI32_V) 2655 DECLARE_INSN(vluxei64_v, MATCH_VLUXEI64_V, MASK_VLUXEI64_V) 2656 DECLARE_INSN(vluxei128_v, MATCH_VLUXEI128_V, MASK_VLUXEI128_V) 2657 DECLARE_INSN(vluxei256_v, MATCH_VLUXEI256_V, MASK_VLUXEI256_V) 2658 DECLARE_INSN(vluxei512_v, MATCH_VLUXEI512_V, MASK_VLUXEI512_V) 2659 DECLARE_INSN(vluxei1024_v, MATCH_VLUXEI1024_V, MASK_VLUXEI1024_V) 2660 DECLARE_INSN(vsuxei8_v, MATCH_VSUXEI8_V, MASK_VSUXEI8_V) 2661 DECLARE_INSN(vsuxei16_v, MATCH_VSUXEI16_V, MASK_VSUXEI16_V) 2662 DECLARE_INSN(vsuxei32_v, MATCH_VSUXEI32_V, MASK_VSUXEI32_V) 2663 DECLARE_INSN(vsuxei64_v, MATCH_VSUXEI64_V, MASK_VSUXEI64_V) 2664 DECLARE_INSN(vsuxei128_v, MATCH_VSUXEI128_V, MASK_VSUXEI128_V) 2665 DECLARE_INSN(vsuxei256_v, MATCH_VSUXEI256_V, MASK_VSUXEI256_V) 2666 DECLARE_INSN(vsuxei512_v, MATCH_VSUXEI512_V, MASK_VSUXEI512_V) 2667 DECLARE_INSN(vsuxei1024_v, MATCH_VSUXEI1024_V, MASK_VSUXEI1024_V) 2668 DECLARE_INSN(vlse8_v, MATCH_VLSE8_V, MASK_VLSE8_V) 2669 DECLARE_INSN(vlse16_v, MATCH_VLSE16_V, MASK_VLSE16_V) 2670 DECLARE_INSN(vlse32_v, MATCH_VLSE32_V, MASK_VLSE32_V) 2671 DECLARE_INSN(vlse64_v, MATCH_VLSE64_V, MASK_VLSE64_V) 2672 DECLARE_INSN(vlse128_v, MATCH_VLSE128_V, MASK_VLSE128_V) 2673 DECLARE_INSN(vlse256_v, MATCH_VLSE256_V, MASK_VLSE256_V) 2674 DECLARE_INSN(vlse512_v, MATCH_VLSE512_V, MASK_VLSE512_V) 2675 DECLARE_INSN(vlse1024_v, MATCH_VLSE1024_V, MASK_VLSE1024_V) 2676 DECLARE_INSN(vsse8_v, MATCH_VSSE8_V, MASK_VSSE8_V) 2677 DECLARE_INSN(vsse16_v, MATCH_VSSE16_V, MASK_VSSE16_V) 2678 DECLARE_INSN(vsse32_v, MATCH_VSSE32_V, MASK_VSSE32_V) 2679 DECLARE_INSN(vsse64_v, MATCH_VSSE64_V, MASK_VSSE64_V) 2680 DECLARE_INSN(vsse128_v, MATCH_VSSE128_V, MASK_VSSE128_V) 2681 DECLARE_INSN(vsse256_v, MATCH_VSSE256_V, MASK_VSSE256_V) 2682 DECLARE_INSN(vsse512_v, MATCH_VSSE512_V, MASK_VSSE512_V) 2683 DECLARE_INSN(vsse1024_v, MATCH_VSSE1024_V, MASK_VSSE1024_V) 2684 DECLARE_INSN(vloxei8_v, MATCH_VLOXEI8_V, MASK_VLOXEI8_V) 2685 DECLARE_INSN(vloxei16_v, MATCH_VLOXEI16_V, MASK_VLOXEI16_V) 2686 DECLARE_INSN(vloxei32_v, MATCH_VLOXEI32_V, MASK_VLOXEI32_V) 2687 DECLARE_INSN(vloxei64_v, MATCH_VLOXEI64_V, MASK_VLOXEI64_V) 2688 DECLARE_INSN(vloxei128_v, MATCH_VLOXEI128_V, MASK_VLOXEI128_V) 2689 DECLARE_INSN(vloxei256_v, MATCH_VLOXEI256_V, MASK_VLOXEI256_V) 2690 DECLARE_INSN(vloxei512_v, MATCH_VLOXEI512_V, MASK_VLOXEI512_V) 2691 DECLARE_INSN(vloxei1024_v, MATCH_VLOXEI1024_V, MASK_VLOXEI1024_V) 2692 DECLARE_INSN(vsoxei8_v, MATCH_VSOXEI8_V, MASK_VSOXEI8_V) 2693 DECLARE_INSN(vsoxei16_v, MATCH_VSOXEI16_V, MASK_VSOXEI16_V) 2694 DECLARE_INSN(vsoxei32_v, MATCH_VSOXEI32_V, MASK_VSOXEI32_V) 2695 DECLARE_INSN(vsoxei64_v, MATCH_VSOXEI64_V, MASK_VSOXEI64_V) 2696 DECLARE_INSN(vsoxei128_v, MATCH_VSOXEI128_V, MASK_VSOXEI128_V) 2697 DECLARE_INSN(vsoxei256_v, MATCH_VSOXEI256_V, MASK_VSOXEI256_V) 2698 DECLARE_INSN(vsoxei512_v, MATCH_VSOXEI512_V, MASK_VSOXEI512_V) 2699 DECLARE_INSN(vsoxei1024_v, MATCH_VSOXEI1024_V, MASK_VSOXEI1024_V) 2700 DECLARE_INSN(vle8ff_v, MATCH_VLE8FF_V, MASK_VLE8FF_V) 2701 DECLARE_INSN(vle16ff_v, MATCH_VLE16FF_V, MASK_VLE16FF_V) 2702 DECLARE_INSN(vle32ff_v, MATCH_VLE32FF_V, MASK_VLE32FF_V) 2703 DECLARE_INSN(vle64ff_v, MATCH_VLE64FF_V, MASK_VLE64FF_V) 2704 DECLARE_INSN(vle128ff_v, MATCH_VLE128FF_V, MASK_VLE128FF_V) 2705 DECLARE_INSN(vle256ff_v, MATCH_VLE256FF_V, MASK_VLE256FF_V) 2706 DECLARE_INSN(vle512ff_v, MATCH_VLE512FF_V, MASK_VLE512FF_V) 2707 DECLARE_INSN(vle1024ff_v, MATCH_VLE1024FF_V, MASK_VLE1024FF_V) 2708 DECLARE_INSN(vl1re8_v, MATCH_VL1RE8_V, MASK_VL1RE8_V) 2709 DECLARE_INSN(vl1re16_v, MATCH_VL1RE16_V, MASK_VL1RE16_V) 2710 DECLARE_INSN(vl1re32_v, MATCH_VL1RE32_V, MASK_VL1RE32_V) 2711 DECLARE_INSN(vl1re64_v, MATCH_VL1RE64_V, MASK_VL1RE64_V) 2712 DECLARE_INSN(vl2re8_v, MATCH_VL2RE8_V, MASK_VL2RE8_V) 2713 DECLARE_INSN(vl2re16_v, MATCH_VL2RE16_V, MASK_VL2RE16_V) 2714 DECLARE_INSN(vl2re32_v, MATCH_VL2RE32_V, MASK_VL2RE32_V) 2715 DECLARE_INSN(vl2re64_v, MATCH_VL2RE64_V, MASK_VL2RE64_V) 2716 DECLARE_INSN(vl4re8_v, MATCH_VL4RE8_V, MASK_VL4RE8_V) 2717 DECLARE_INSN(vl4re16_v, MATCH_VL4RE16_V, MASK_VL4RE16_V) 2718 DECLARE_INSN(vl4re32_v, MATCH_VL4RE32_V, MASK_VL4RE32_V) 2719 DECLARE_INSN(vl4re64_v, MATCH_VL4RE64_V, MASK_VL4RE64_V) 2720 DECLARE_INSN(vl8re8_v, MATCH_VL8RE8_V, MASK_VL8RE8_V) 2721 DECLARE_INSN(vl8re16_v, MATCH_VL8RE16_V, MASK_VL8RE16_V) 2722 DECLARE_INSN(vl8re32_v, MATCH_VL8RE32_V, MASK_VL8RE32_V) 2723 DECLARE_INSN(vl8re64_v, MATCH_VL8RE64_V, MASK_VL8RE64_V) 2724 DECLARE_INSN(vs1r_v, MATCH_VS1R_V, MASK_VS1R_V) 2725 DECLARE_INSN(vs2r_v, MATCH_VS2R_V, MASK_VS2R_V) 2726 DECLARE_INSN(vs4r_v, MATCH_VS4R_V, MASK_VS4R_V) 2727 DECLARE_INSN(vs8r_v, MATCH_VS8R_V, MASK_VS8R_V) 2728 DECLARE_INSN(vfadd_vf, MATCH_VFADD_VF, MASK_VFADD_VF) 2729 DECLARE_INSN(vfsub_vf, MATCH_VFSUB_VF, MASK_VFSUB_VF) 2730 DECLARE_INSN(vfmin_vf, MATCH_VFMIN_VF, MASK_VFMIN_VF) 2731 DECLARE_INSN(vfmax_vf, MATCH_VFMAX_VF, MASK_VFMAX_VF) 2732 DECLARE_INSN(vfsgnj_vf, MATCH_VFSGNJ_VF, MASK_VFSGNJ_VF) 2733 DECLARE_INSN(vfsgnjn_vf, MATCH_VFSGNJN_VF, MASK_VFSGNJN_VF) 2734 DECLARE_INSN(vfsgnjx_vf, MATCH_VFSGNJX_VF, MASK_VFSGNJX_VF) 2735 DECLARE_INSN(vfslide1up_vf, MATCH_VFSLIDE1UP_VF, MASK_VFSLIDE1UP_VF) 2736 DECLARE_INSN(vfslide1down_vf, MATCH_VFSLIDE1DOWN_VF, MASK_VFSLIDE1DOWN_VF) 2737 DECLARE_INSN(vfmv_s_f, MATCH_VFMV_S_F, MASK_VFMV_S_F) 2738 DECLARE_INSN(vfmerge_vfm, MATCH_VFMERGE_VFM, MASK_VFMERGE_VFM) 2739 DECLARE_INSN(vfmv_v_f, MATCH_VFMV_V_F, MASK_VFMV_V_F) 2740 DECLARE_INSN(vmfeq_vf, MATCH_VMFEQ_VF, MASK_VMFEQ_VF) 2741 DECLARE_INSN(vmfle_vf, MATCH_VMFLE_VF, MASK_VMFLE_VF) 2742 DECLARE_INSN(vmflt_vf, MATCH_VMFLT_VF, MASK_VMFLT_VF) 2743 DECLARE_INSN(vmfne_vf, MATCH_VMFNE_VF, MASK_VMFNE_VF) 2744 DECLARE_INSN(vmfgt_vf, MATCH_VMFGT_VF, MASK_VMFGT_VF) 2745 DECLARE_INSN(vmfge_vf, MATCH_VMFGE_VF, MASK_VMFGE_VF) 2746 DECLARE_INSN(vfdiv_vf, MATCH_VFDIV_VF, MASK_VFDIV_VF) 2747 DECLARE_INSN(vfrdiv_vf, MATCH_VFRDIV_VF, MASK_VFRDIV_VF) 2748 DECLARE_INSN(vfmul_vf, MATCH_VFMUL_VF, MASK_VFMUL_VF) 2749 DECLARE_INSN(vfrsub_vf, MATCH_VFRSUB_VF, MASK_VFRSUB_VF) 2750 DECLARE_INSN(vfmadd_vf, MATCH_VFMADD_VF, MASK_VFMADD_VF) 2751 DECLARE_INSN(vfnmadd_vf, MATCH_VFNMADD_VF, MASK_VFNMADD_VF) 2752 DECLARE_INSN(vfmsub_vf, MATCH_VFMSUB_VF, MASK_VFMSUB_VF) 2753 DECLARE_INSN(vfnmsub_vf, MATCH_VFNMSUB_VF, MASK_VFNMSUB_VF) 2754 DECLARE_INSN(vfmacc_vf, MATCH_VFMACC_VF, MASK_VFMACC_VF) 2755 DECLARE_INSN(vfnmacc_vf, MATCH_VFNMACC_VF, MASK_VFNMACC_VF) 2756 DECLARE_INSN(vfmsac_vf, MATCH_VFMSAC_VF, MASK_VFMSAC_VF) 2757 DECLARE_INSN(vfnmsac_vf, MATCH_VFNMSAC_VF, MASK_VFNMSAC_VF) 2758 DECLARE_INSN(vfwadd_vf, MATCH_VFWADD_VF, MASK_VFWADD_VF) 2759 DECLARE_INSN(vfwsub_vf, MATCH_VFWSUB_VF, MASK_VFWSUB_VF) 2760 DECLARE_INSN(vfwadd_wf, MATCH_VFWADD_WF, MASK_VFWADD_WF) 2761 DECLARE_INSN(vfwsub_wf, MATCH_VFWSUB_WF, MASK_VFWSUB_WF) 2762 DECLARE_INSN(vfwmul_vf, MATCH_VFWMUL_VF, MASK_VFWMUL_VF) 2763 DECLARE_INSN(vfwmacc_vf, MATCH_VFWMACC_VF, MASK_VFWMACC_VF) 2764 DECLARE_INSN(vfwnmacc_vf, MATCH_VFWNMACC_VF, MASK_VFWNMACC_VF) 2765 DECLARE_INSN(vfwmsac_vf, MATCH_VFWMSAC_VF, MASK_VFWMSAC_VF) 2766 DECLARE_INSN(vfwnmsac_vf, MATCH_VFWNMSAC_VF, MASK_VFWNMSAC_VF) 2767 DECLARE_INSN(vfadd_vv, MATCH_VFADD_VV, MASK_VFADD_VV) 2768 DECLARE_INSN(vfredsum_vs, MATCH_VFREDSUM_VS, MASK_VFREDSUM_VS) 2769 DECLARE_INSN(vfsub_vv, MATCH_VFSUB_VV, MASK_VFSUB_VV) 2770 DECLARE_INSN(vfredosum_vs, MATCH_VFREDOSUM_VS, MASK_VFREDOSUM_VS) 2771 DECLARE_INSN(vfmin_vv, MATCH_VFMIN_VV, MASK_VFMIN_VV) 2772 DECLARE_INSN(vfredmin_vs, MATCH_VFREDMIN_VS, MASK_VFREDMIN_VS) 2773 DECLARE_INSN(vfmax_vv, MATCH_VFMAX_VV, MASK_VFMAX_VV) 2774 DECLARE_INSN(vfredmax_vs, MATCH_VFREDMAX_VS, MASK_VFREDMAX_VS) 2775 DECLARE_INSN(vfsgnj_vv, MATCH_VFSGNJ_VV, MASK_VFSGNJ_VV) 2776 DECLARE_INSN(vfsgnjn_vv, MATCH_VFSGNJN_VV, MASK_VFSGNJN_VV) 2777 DECLARE_INSN(vfsgnjx_vv, MATCH_VFSGNJX_VV, MASK_VFSGNJX_VV) 2778 DECLARE_INSN(vfmv_f_s, MATCH_VFMV_F_S, MASK_VFMV_F_S) 2779 DECLARE_INSN(vmfeq_vv, MATCH_VMFEQ_VV, MASK_VMFEQ_VV) 2780 DECLARE_INSN(vmfle_vv, MATCH_VMFLE_VV, MASK_VMFLE_VV) 2781 DECLARE_INSN(vmflt_vv, MATCH_VMFLT_VV, MASK_VMFLT_VV) 2782 DECLARE_INSN(vmfne_vv, MATCH_VMFNE_VV, MASK_VMFNE_VV) 2783 DECLARE_INSN(vfdiv_vv, MATCH_VFDIV_VV, MASK_VFDIV_VV) 2784 DECLARE_INSN(vfmul_vv, MATCH_VFMUL_VV, MASK_VFMUL_VV) 2785 DECLARE_INSN(vfmadd_vv, MATCH_VFMADD_VV, MASK_VFMADD_VV) 2786 DECLARE_INSN(vfnmadd_vv, MATCH_VFNMADD_VV, MASK_VFNMADD_VV) 2787 DECLARE_INSN(vfmsub_vv, MATCH_VFMSUB_VV, MASK_VFMSUB_VV) 2788 DECLARE_INSN(vfnmsub_vv, MATCH_VFNMSUB_VV, MASK_VFNMSUB_VV) 2789 DECLARE_INSN(vfmacc_vv, MATCH_VFMACC_VV, MASK_VFMACC_VV) 2790 DECLARE_INSN(vfnmacc_vv, MATCH_VFNMACC_VV, MASK_VFNMACC_VV) 2791 DECLARE_INSN(vfmsac_vv, MATCH_VFMSAC_VV, MASK_VFMSAC_VV) 2792 DECLARE_INSN(vfnmsac_vv, MATCH_VFNMSAC_VV, MASK_VFNMSAC_VV) 2793 DECLARE_INSN(vfcvt_xu_f_v, MATCH_VFCVT_XU_F_V, MASK_VFCVT_XU_F_V) 2794 DECLARE_INSN(vfcvt_x_f_v, MATCH_VFCVT_X_F_V, MASK_VFCVT_X_F_V) 2795 DECLARE_INSN(vfcvt_f_xu_v, MATCH_VFCVT_F_XU_V, MASK_VFCVT_F_XU_V) 2796 DECLARE_INSN(vfcvt_f_x_v, MATCH_VFCVT_F_X_V, MASK_VFCVT_F_X_V) 2797 DECLARE_INSN(vfcvt_rtz_xu_f_v, MATCH_VFCVT_RTZ_XU_F_V, MASK_VFCVT_RTZ_XU_F_V) 2798 DECLARE_INSN(vfcvt_rtz_x_f_v, MATCH_VFCVT_RTZ_X_F_V, MASK_VFCVT_RTZ_X_F_V) 2799 DECLARE_INSN(vfwcvt_xu_f_v, MATCH_VFWCVT_XU_F_V, MASK_VFWCVT_XU_F_V) 2800 DECLARE_INSN(vfwcvt_x_f_v, MATCH_VFWCVT_X_F_V, MASK_VFWCVT_X_F_V) 2801 DECLARE_INSN(vfwcvt_f_xu_v, MATCH_VFWCVT_F_XU_V, MASK_VFWCVT_F_XU_V) 2802 DECLARE_INSN(vfwcvt_f_x_v, MATCH_VFWCVT_F_X_V, MASK_VFWCVT_F_X_V) 2803 DECLARE_INSN(vfwcvt_f_f_v, MATCH_VFWCVT_F_F_V, MASK_VFWCVT_F_F_V) 2804 DECLARE_INSN(vfwcvt_rtz_xu_f_v, MATCH_VFWCVT_RTZ_XU_F_V, MASK_VFWCVT_RTZ_XU_F_V) 2805 DECLARE_INSN(vfwcvt_rtz_x_f_v, MATCH_VFWCVT_RTZ_X_F_V, MASK_VFWCVT_RTZ_X_F_V) 2806 DECLARE_INSN(vfncvt_xu_f_w, MATCH_VFNCVT_XU_F_W, MASK_VFNCVT_XU_F_W) 2807 DECLARE_INSN(vfncvt_x_f_w, MATCH_VFNCVT_X_F_W, MASK_VFNCVT_X_F_W) 2808 DECLARE_INSN(vfncvt_f_xu_w, MATCH_VFNCVT_F_XU_W, MASK_VFNCVT_F_XU_W) 2809 DECLARE_INSN(vfncvt_f_x_w, MATCH_VFNCVT_F_X_W, MASK_VFNCVT_F_X_W) 2810 DECLARE_INSN(vfncvt_f_f_w, MATCH_VFNCVT_F_F_W, MASK_VFNCVT_F_F_W) 2811 DECLARE_INSN(vfncvt_rod_f_f_w, MATCH_VFNCVT_ROD_F_F_W, MASK_VFNCVT_ROD_F_F_W) 2812 DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W) 2813 DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W) 2814 DECLARE_INSN(vfsqrt_v, MATCH_VFSQRT_V, MASK_VFSQRT_V) 2815 DECLARE_INSN(vfrsqrt7_v, MATCH_VFRSQRT7_V, MASK_VFRSQRT7_V) 2816 DECLARE_INSN(vfrec7_v, MATCH_VFREC7_V, MASK_VFREC7_V) 2817 DECLARE_INSN(vfclass_v, MATCH_VFCLASS_V, MASK_VFCLASS_V) 2818 DECLARE_INSN(vfwadd_vv, MATCH_VFWADD_VV, MASK_VFWADD_VV) 2819 DECLARE_INSN(vfwredsum_vs, MATCH_VFWREDSUM_VS, MASK_VFWREDSUM_VS) 2820 DECLARE_INSN(vfwsub_vv, MATCH_VFWSUB_VV, MASK_VFWSUB_VV) 2821 DECLARE_INSN(vfwredosum_vs, MATCH_VFWREDOSUM_VS, MASK_VFWREDOSUM_VS) 2822 DECLARE_INSN(vfwadd_wv, MATCH_VFWADD_WV, MASK_VFWADD_WV) 2823 DECLARE_INSN(vfwsub_wv, MATCH_VFWSUB_WV, MASK_VFWSUB_WV) 2824 DECLARE_INSN(vfwmul_vv, MATCH_VFWMUL_VV, MASK_VFWMUL_VV) 2825 DECLARE_INSN(vfdot_vv, MATCH_VFDOT_VV, MASK_VFDOT_VV) 2826 DECLARE_INSN(vfwmacc_vv, MATCH_VFWMACC_VV, MASK_VFWMACC_VV) 2827 DECLARE_INSN(vfwnmacc_vv, MATCH_VFWNMACC_VV, MASK_VFWNMACC_VV) 2828 DECLARE_INSN(vfwmsac_vv, MATCH_VFWMSAC_VV, MASK_VFWMSAC_VV) 2829 DECLARE_INSN(vfwnmsac_vv, MATCH_VFWNMSAC_VV, MASK_VFWNMSAC_VV) 2830 DECLARE_INSN(vadd_vx, MATCH_VADD_VX, MASK_VADD_VX) 2831 DECLARE_INSN(vsub_vx, MATCH_VSUB_VX, MASK_VSUB_VX) 2832 DECLARE_INSN(vrsub_vx, MATCH_VRSUB_VX, MASK_VRSUB_VX) 2833 DECLARE_INSN(vminu_vx, MATCH_VMINU_VX, MASK_VMINU_VX) 2834 DECLARE_INSN(vmin_vx, MATCH_VMIN_VX, MASK_VMIN_VX) 2835 DECLARE_INSN(vmaxu_vx, MATCH_VMAXU_VX, MASK_VMAXU_VX) 2836 DECLARE_INSN(vmax_vx, MATCH_VMAX_VX, MASK_VMAX_VX) 2837 DECLARE_INSN(vand_vx, MATCH_VAND_VX, MASK_VAND_VX) 2838 DECLARE_INSN(vor_vx, MATCH_VOR_VX, MASK_VOR_VX) 2839 DECLARE_INSN(vxor_vx, MATCH_VXOR_VX, MASK_VXOR_VX) 2840 DECLARE_INSN(vrgather_vx, MATCH_VRGATHER_VX, MASK_VRGATHER_VX) 2841 DECLARE_INSN(vslideup_vx, MATCH_VSLIDEUP_VX, MASK_VSLIDEUP_VX) 2842 DECLARE_INSN(vslidedown_vx, MATCH_VSLIDEDOWN_VX, MASK_VSLIDEDOWN_VX) 2843 DECLARE_INSN(vadc_vxm, MATCH_VADC_VXM, MASK_VADC_VXM) 2844 DECLARE_INSN(vmadc_vxm, MATCH_VMADC_VXM, MASK_VMADC_VXM) 2845 DECLARE_INSN(vsbc_vxm, MATCH_VSBC_VXM, MASK_VSBC_VXM) 2846 DECLARE_INSN(vmsbc_vxm, MATCH_VMSBC_VXM, MASK_VMSBC_VXM) 2847 DECLARE_INSN(vmerge_vxm, MATCH_VMERGE_VXM, MASK_VMERGE_VXM) 2848 DECLARE_INSN(vmv_v_x, MATCH_VMV_V_X, MASK_VMV_V_X) 2849 DECLARE_INSN(vmseq_vx, MATCH_VMSEQ_VX, MASK_VMSEQ_VX) 2850 DECLARE_INSN(vmsne_vx, MATCH_VMSNE_VX, MASK_VMSNE_VX) 2851 DECLARE_INSN(vmsltu_vx, MATCH_VMSLTU_VX, MASK_VMSLTU_VX) 2852 DECLARE_INSN(vmslt_vx, MATCH_VMSLT_VX, MASK_VMSLT_VX) 2853 DECLARE_INSN(vmsleu_vx, MATCH_VMSLEU_VX, MASK_VMSLEU_VX) 2854 DECLARE_INSN(vmsle_vx, MATCH_VMSLE_VX, MASK_VMSLE_VX) 2855 DECLARE_INSN(vmsgtu_vx, MATCH_VMSGTU_VX, MASK_VMSGTU_VX) 2856 DECLARE_INSN(vmsgt_vx, MATCH_VMSGT_VX, MASK_VMSGT_VX) 2857 DECLARE_INSN(vsaddu_vx, MATCH_VSADDU_VX, MASK_VSADDU_VX) 2858 DECLARE_INSN(vsadd_vx, MATCH_VSADD_VX, MASK_VSADD_VX) 2859 DECLARE_INSN(vssubu_vx, MATCH_VSSUBU_VX, MASK_VSSUBU_VX) 2860 DECLARE_INSN(vssub_vx, MATCH_VSSUB_VX, MASK_VSSUB_VX) 2861 DECLARE_INSN(vsll_vx, MATCH_VSLL_VX, MASK_VSLL_VX) 2862 DECLARE_INSN(vsmul_vx, MATCH_VSMUL_VX, MASK_VSMUL_VX) 2863 DECLARE_INSN(vsrl_vx, MATCH_VSRL_VX, MASK_VSRL_VX) 2864 DECLARE_INSN(vsra_vx, MATCH_VSRA_VX, MASK_VSRA_VX) 2865 DECLARE_INSN(vssrl_vx, MATCH_VSSRL_VX, MASK_VSSRL_VX) 2866 DECLARE_INSN(vssra_vx, MATCH_VSSRA_VX, MASK_VSSRA_VX) 2867 DECLARE_INSN(vnsrl_wx, MATCH_VNSRL_WX, MASK_VNSRL_WX) 2868 DECLARE_INSN(vnsra_wx, MATCH_VNSRA_WX, MASK_VNSRA_WX) 2869 DECLARE_INSN(vnclipu_wx, MATCH_VNCLIPU_WX, MASK_VNCLIPU_WX) 2870 DECLARE_INSN(vnclip_wx, MATCH_VNCLIP_WX, MASK_VNCLIP_WX) 2871 DECLARE_INSN(vadd_vv, MATCH_VADD_VV, MASK_VADD_VV) 2872 DECLARE_INSN(vsub_vv, MATCH_VSUB_VV, MASK_VSUB_VV) 2873 DECLARE_INSN(vminu_vv, MATCH_VMINU_VV, MASK_VMINU_VV) 2874 DECLARE_INSN(vmin_vv, MATCH_VMIN_VV, MASK_VMIN_VV) 2875 DECLARE_INSN(vmaxu_vv, MATCH_VMAXU_VV, MASK_VMAXU_VV) 2876 DECLARE_INSN(vmax_vv, MATCH_VMAX_VV, MASK_VMAX_VV) 2877 DECLARE_INSN(vand_vv, MATCH_VAND_VV, MASK_VAND_VV) 2878 DECLARE_INSN(vor_vv, MATCH_VOR_VV, MASK_VOR_VV) 2879 DECLARE_INSN(vxor_vv, MATCH_VXOR_VV, MASK_VXOR_VV) 2880 DECLARE_INSN(vrgather_vv, MATCH_VRGATHER_VV, MASK_VRGATHER_VV) 2881 DECLARE_INSN(vrgatherei16_vv, MATCH_VRGATHEREI16_VV, MASK_VRGATHEREI16_VV) 2882 DECLARE_INSN(vadc_vvm, MATCH_VADC_VVM, MASK_VADC_VVM) 2883 DECLARE_INSN(vmadc_vvm, MATCH_VMADC_VVM, MASK_VMADC_VVM) 2884 DECLARE_INSN(vsbc_vvm, MATCH_VSBC_VVM, MASK_VSBC_VVM) 2885 DECLARE_INSN(vmsbc_vvm, MATCH_VMSBC_VVM, MASK_VMSBC_VVM) 2886 DECLARE_INSN(vmerge_vvm, MATCH_VMERGE_VVM, MASK_VMERGE_VVM) 2887 DECLARE_INSN(vmv_v_v, MATCH_VMV_V_V, MASK_VMV_V_V) 2888 DECLARE_INSN(vmseq_vv, MATCH_VMSEQ_VV, MASK_VMSEQ_VV) 2889 DECLARE_INSN(vmsne_vv, MATCH_VMSNE_VV, MASK_VMSNE_VV) 2890 DECLARE_INSN(vmsltu_vv, MATCH_VMSLTU_VV, MASK_VMSLTU_VV) 2891 DECLARE_INSN(vmslt_vv, MATCH_VMSLT_VV, MASK_VMSLT_VV) 2892 DECLARE_INSN(vmsleu_vv, MATCH_VMSLEU_VV, MASK_VMSLEU_VV) 2893 DECLARE_INSN(vmsle_vv, MATCH_VMSLE_VV, MASK_VMSLE_VV) 2894 DECLARE_INSN(vsaddu_vv, MATCH_VSADDU_VV, MASK_VSADDU_VV) 2895 DECLARE_INSN(vsadd_vv, MATCH_VSADD_VV, MASK_VSADD_VV) 2896 DECLARE_INSN(vssubu_vv, MATCH_VSSUBU_VV, MASK_VSSUBU_VV) 2897 DECLARE_INSN(vssub_vv, MATCH_VSSUB_VV, MASK_VSSUB_VV) 2898 DECLARE_INSN(vsll_vv, MATCH_VSLL_VV, MASK_VSLL_VV) 2899 DECLARE_INSN(vsmul_vv, MATCH_VSMUL_VV, MASK_VSMUL_VV) 2900 DECLARE_INSN(vsrl_vv, MATCH_VSRL_VV, MASK_VSRL_VV) 2901 DECLARE_INSN(vsra_vv, MATCH_VSRA_VV, MASK_VSRA_VV) 2902 DECLARE_INSN(vssrl_vv, MATCH_VSSRL_VV, MASK_VSSRL_VV) 2903 DECLARE_INSN(vssra_vv, MATCH_VSSRA_VV, MASK_VSSRA_VV) 2904 DECLARE_INSN(vnsrl_wv, MATCH_VNSRL_WV, MASK_VNSRL_WV) 2905 DECLARE_INSN(vnsra_wv, MATCH_VNSRA_WV, MASK_VNSRA_WV) 2906 DECLARE_INSN(vnclipu_wv, MATCH_VNCLIPU_WV, MASK_VNCLIPU_WV) 2907 DECLARE_INSN(vnclip_wv, MATCH_VNCLIP_WV, MASK_VNCLIP_WV) 2908 DECLARE_INSN(vwredsumu_vs, MATCH_VWREDSUMU_VS, MASK_VWREDSUMU_VS) 2909 DECLARE_INSN(vwredsum_vs, MATCH_VWREDSUM_VS, MASK_VWREDSUM_VS) 2910 DECLARE_INSN(vdotu_vv, MATCH_VDOTU_VV, MASK_VDOTU_VV) 2911 DECLARE_INSN(vdot_vv, MATCH_VDOT_VV, MASK_VDOT_VV) 2912 DECLARE_INSN(vqmaccu_vv, MATCH_VQMACCU_VV, MASK_VQMACCU_VV) 2913 DECLARE_INSN(vqmacc_vv, MATCH_VQMACC_VV, MASK_VQMACC_VV) 2914 DECLARE_INSN(vqmaccsu_vv, MATCH_VQMACCSU_VV, MASK_VQMACCSU_VV) 2915 DECLARE_INSN(vadd_vi, MATCH_VADD_VI, MASK_VADD_VI) 2916 DECLARE_INSN(vrsub_vi, MATCH_VRSUB_VI, MASK_VRSUB_VI) 2917 DECLARE_INSN(vand_vi, MATCH_VAND_VI, MASK_VAND_VI) 2918 DECLARE_INSN(vor_vi, MATCH_VOR_VI, MASK_VOR_VI) 2919 DECLARE_INSN(vxor_vi, MATCH_VXOR_VI, MASK_VXOR_VI) 2920 DECLARE_INSN(vrgather_vi, MATCH_VRGATHER_VI, MASK_VRGATHER_VI) 2921 DECLARE_INSN(vslideup_vi, MATCH_VSLIDEUP_VI, MASK_VSLIDEUP_VI) 2922 DECLARE_INSN(vslidedown_vi, MATCH_VSLIDEDOWN_VI, MASK_VSLIDEDOWN_VI) 2923 DECLARE_INSN(vadc_vim, MATCH_VADC_VIM, MASK_VADC_VIM) 2924 DECLARE_INSN(vmadc_vim, MATCH_VMADC_VIM, MASK_VMADC_VIM) 2925 DECLARE_INSN(vmerge_vim, MATCH_VMERGE_VIM, MASK_VMERGE_VIM) 2926 DECLARE_INSN(vmv_v_i, MATCH_VMV_V_I, MASK_VMV_V_I) 2927 DECLARE_INSN(vmseq_vi, MATCH_VMSEQ_VI, MASK_VMSEQ_VI) 2928 DECLARE_INSN(vmsne_vi, MATCH_VMSNE_VI, MASK_VMSNE_VI) 2929 DECLARE_INSN(vmsleu_vi, MATCH_VMSLEU_VI, MASK_VMSLEU_VI) 2930 DECLARE_INSN(vmsle_vi, MATCH_VMSLE_VI, MASK_VMSLE_VI) 2931 DECLARE_INSN(vmsgtu_vi, MATCH_VMSGTU_VI, MASK_VMSGTU_VI) 2932 DECLARE_INSN(vmsgt_vi, MATCH_VMSGT_VI, MASK_VMSGT_VI) 2933 DECLARE_INSN(vsaddu_vi, MATCH_VSADDU_VI, MASK_VSADDU_VI) 2934 DECLARE_INSN(vsadd_vi, MATCH_VSADD_VI, MASK_VSADD_VI) 2935 DECLARE_INSN(vsll_vi, MATCH_VSLL_VI, MASK_VSLL_VI) 2936 DECLARE_INSN(vmv1r_v, MATCH_VMV1R_V, MASK_VMV1R_V) 2937 DECLARE_INSN(vmv2r_v, MATCH_VMV2R_V, MASK_VMV2R_V) 2938 DECLARE_INSN(vmv4r_v, MATCH_VMV4R_V, MASK_VMV4R_V) 2939 DECLARE_INSN(vmv8r_v, MATCH_VMV8R_V, MASK_VMV8R_V) 2940 DECLARE_INSN(vsrl_vi, MATCH_VSRL_VI, MASK_VSRL_VI) 2941 DECLARE_INSN(vsra_vi, MATCH_VSRA_VI, MASK_VSRA_VI) 2942 DECLARE_INSN(vssrl_vi, MATCH_VSSRL_VI, MASK_VSSRL_VI) 2943 DECLARE_INSN(vssra_vi, MATCH_VSSRA_VI, MASK_VSSRA_VI) 2944 DECLARE_INSN(vnsrl_wi, MATCH_VNSRL_WI, MASK_VNSRL_WI) 2945 DECLARE_INSN(vnsra_wi, MATCH_VNSRA_WI, MASK_VNSRA_WI) 2946 DECLARE_INSN(vnclipu_wi, MATCH_VNCLIPU_WI, MASK_VNCLIPU_WI) 2947 DECLARE_INSN(vnclip_wi, MATCH_VNCLIP_WI, MASK_VNCLIP_WI) 2948 DECLARE_INSN(vredsum_vs, MATCH_VREDSUM_VS, MASK_VREDSUM_VS) 2949 DECLARE_INSN(vredand_vs, MATCH_VREDAND_VS, MASK_VREDAND_VS) 2950 DECLARE_INSN(vredor_vs, MATCH_VREDOR_VS, MASK_VREDOR_VS) 2951 DECLARE_INSN(vredxor_vs, MATCH_VREDXOR_VS, MASK_VREDXOR_VS) 2952 DECLARE_INSN(vredminu_vs, MATCH_VREDMINU_VS, MASK_VREDMINU_VS) 2953 DECLARE_INSN(vredmin_vs, MATCH_VREDMIN_VS, MASK_VREDMIN_VS) 2954 DECLARE_INSN(vredmaxu_vs, MATCH_VREDMAXU_VS, MASK_VREDMAXU_VS) 2955 DECLARE_INSN(vredmax_vs, MATCH_VREDMAX_VS, MASK_VREDMAX_VS) 2956 DECLARE_INSN(vaaddu_vv, MATCH_VAADDU_VV, MASK_VAADDU_VV) 2957 DECLARE_INSN(vaadd_vv, MATCH_VAADD_VV, MASK_VAADD_VV) 2958 DECLARE_INSN(vasubu_vv, MATCH_VASUBU_VV, MASK_VASUBU_VV) 2959 DECLARE_INSN(vasub_vv, MATCH_VASUB_VV, MASK_VASUB_VV) 2960 DECLARE_INSN(vmv_x_s, MATCH_VMV_X_S, MASK_VMV_X_S) 2961 DECLARE_INSN(vzext_vf8, MATCH_VZEXT_VF8, MASK_VZEXT_VF8) 2962 DECLARE_INSN(vsext_vf8, MATCH_VSEXT_VF8, MASK_VSEXT_VF8) 2963 DECLARE_INSN(vzext_vf4, MATCH_VZEXT_VF4, MASK_VZEXT_VF4) 2964 DECLARE_INSN(vsext_vf4, MATCH_VSEXT_VF4, MASK_VSEXT_VF4) 2965 DECLARE_INSN(vzext_vf2, MATCH_VZEXT_VF2, MASK_VZEXT_VF2) 2966 DECLARE_INSN(vsext_vf2, MATCH_VSEXT_VF2, MASK_VSEXT_VF2) 2967 DECLARE_INSN(vcompress_vm, MATCH_VCOMPRESS_VM, MASK_VCOMPRESS_VM) 2968 DECLARE_INSN(vmandnot_mm, MATCH_VMANDNOT_MM, MASK_VMANDNOT_MM) 2969 DECLARE_INSN(vmand_mm, MATCH_VMAND_MM, MASK_VMAND_MM) 2970 DECLARE_INSN(vmor_mm, MATCH_VMOR_MM, MASK_VMOR_MM) 2971 DECLARE_INSN(vmxor_mm, MATCH_VMXOR_MM, MASK_VMXOR_MM) 2972 DECLARE_INSN(vmornot_mm, MATCH_VMORNOT_MM, MASK_VMORNOT_MM) 2973 DECLARE_INSN(vmnand_mm, MATCH_VMNAND_MM, MASK_VMNAND_MM) 2974 DECLARE_INSN(vmnor_mm, MATCH_VMNOR_MM, MASK_VMNOR_MM) 2975 DECLARE_INSN(vmxnor_mm, MATCH_VMXNOR_MM, MASK_VMXNOR_MM) 2976 DECLARE_INSN(vmsbf_m, MATCH_VMSBF_M, MASK_VMSBF_M) 2977 DECLARE_INSN(vmsof_m, MATCH_VMSOF_M, MASK_VMSOF_M) 2978 DECLARE_INSN(vmsif_m, MATCH_VMSIF_M, MASK_VMSIF_M) 2979 DECLARE_INSN(viota_m, MATCH_VIOTA_M, MASK_VIOTA_M) 2980 DECLARE_INSN(vid_v, MATCH_VID_V, MASK_VID_V) 2981 DECLARE_INSN(vpopc_m, MATCH_VPOPC_M, MASK_VPOPC_M) 2982 DECLARE_INSN(vfirst_m, MATCH_VFIRST_M, MASK_VFIRST_M) 2983 DECLARE_INSN(vdivu_vv, MATCH_VDIVU_VV, MASK_VDIVU_VV) 2984 DECLARE_INSN(vdiv_vv, MATCH_VDIV_VV, MASK_VDIV_VV) 2985 DECLARE_INSN(vremu_vv, MATCH_VREMU_VV, MASK_VREMU_VV) 2986 DECLARE_INSN(vrem_vv, MATCH_VREM_VV, MASK_VREM_VV) 2987 DECLARE_INSN(vmulhu_vv, MATCH_VMULHU_VV, MASK_VMULHU_VV) 2988 DECLARE_INSN(vmul_vv, MATCH_VMUL_VV, MASK_VMUL_VV) 2989 DECLARE_INSN(vmulhsu_vv, MATCH_VMULHSU_VV, MASK_VMULHSU_VV) 2990 DECLARE_INSN(vmulh_vv, MATCH_VMULH_VV, MASK_VMULH_VV) 2991 DECLARE_INSN(vmadd_vv, MATCH_VMADD_VV, MASK_VMADD_VV) 2992 DECLARE_INSN(vnmsub_vv, MATCH_VNMSUB_VV, MASK_VNMSUB_VV) 2993 DECLARE_INSN(vmacc_vv, MATCH_VMACC_VV, MASK_VMACC_VV) 2994 DECLARE_INSN(vnmsac_vv, MATCH_VNMSAC_VV, MASK_VNMSAC_VV) 2995 DECLARE_INSN(vwaddu_vv, MATCH_VWADDU_VV, MASK_VWADDU_VV) 2996 DECLARE_INSN(vwadd_vv, MATCH_VWADD_VV, MASK_VWADD_VV) 2997 DECLARE_INSN(vwsubu_vv, MATCH_VWSUBU_VV, MASK_VWSUBU_VV) 2998 DECLARE_INSN(vwsub_vv, MATCH_VWSUB_VV, MASK_VWSUB_VV) 2999 DECLARE_INSN(vwaddu_wv, MATCH_VWADDU_WV, MASK_VWADDU_WV) 3000 DECLARE_INSN(vwadd_wv, MATCH_VWADD_WV, MASK_VWADD_WV) 3001 DECLARE_INSN(vwsubu_wv, MATCH_VWSUBU_WV, MASK_VWSUBU_WV) 3002 DECLARE_INSN(vwsub_wv, MATCH_VWSUB_WV, MASK_VWSUB_WV) 3003 DECLARE_INSN(vwmulu_vv, MATCH_VWMULU_VV, MASK_VWMULU_VV) 3004 DECLARE_INSN(vwmulsu_vv, MATCH_VWMULSU_VV, MASK_VWMULSU_VV) 3005 DECLARE_INSN(vwmul_vv, MATCH_VWMUL_VV, MASK_VWMUL_VV) 3006 DECLARE_INSN(vwmaccu_vv, MATCH_VWMACCU_VV, MASK_VWMACCU_VV) 3007 DECLARE_INSN(vwmacc_vv, MATCH_VWMACC_VV, MASK_VWMACC_VV) 3008 DECLARE_INSN(vwmaccsu_vv, MATCH_VWMACCSU_VV, MASK_VWMACCSU_VV) 3009 DECLARE_INSN(vaaddu_vx, MATCH_VAADDU_VX, MASK_VAADDU_VX) 3010 DECLARE_INSN(vaadd_vx, MATCH_VAADD_VX, MASK_VAADD_VX) 3011 DECLARE_INSN(vasubu_vx, MATCH_VASUBU_VX, MASK_VASUBU_VX) 3012 DECLARE_INSN(vasub_vx, MATCH_VASUB_VX, MASK_VASUB_VX) 3013 DECLARE_INSN(vmv_s_x, MATCH_VMV_S_X, MASK_VMV_S_X) 3014 DECLARE_INSN(vslide1up_vx, MATCH_VSLIDE1UP_VX, MASK_VSLIDE1UP_VX) 3015 DECLARE_INSN(vslide1down_vx, MATCH_VSLIDE1DOWN_VX, MASK_VSLIDE1DOWN_VX) 3016 DECLARE_INSN(vdivu_vx, MATCH_VDIVU_VX, MASK_VDIVU_VX) 3017 DECLARE_INSN(vdiv_vx, MATCH_VDIV_VX, MASK_VDIV_VX) 3018 DECLARE_INSN(vremu_vx, MATCH_VREMU_VX, MASK_VREMU_VX) 3019 DECLARE_INSN(vrem_vx, MATCH_VREM_VX, MASK_VREM_VX) 3020 DECLARE_INSN(vmulhu_vx, MATCH_VMULHU_VX, MASK_VMULHU_VX) 3021 DECLARE_INSN(vmul_vx, MATCH_VMUL_VX, MASK_VMUL_VX) 3022 DECLARE_INSN(vmulhsu_vx, MATCH_VMULHSU_VX, MASK_VMULHSU_VX) 3023 DECLARE_INSN(vmulh_vx, MATCH_VMULH_VX, MASK_VMULH_VX) 3024 DECLARE_INSN(vmadd_vx, MATCH_VMADD_VX, MASK_VMADD_VX) 3025 DECLARE_INSN(vnmsub_vx, MATCH_VNMSUB_VX, MASK_VNMSUB_VX) 3026 DECLARE_INSN(vmacc_vx, MATCH_VMACC_VX, MASK_VMACC_VX) 3027 DECLARE_INSN(vnmsac_vx, MATCH_VNMSAC_VX, MASK_VNMSAC_VX) 3028 DECLARE_INSN(vwaddu_vx, MATCH_VWADDU_VX, MASK_VWADDU_VX) 3029 DECLARE_INSN(vwadd_vx, MATCH_VWADD_VX, MASK_VWADD_VX) 3030 DECLARE_INSN(vwsubu_vx, MATCH_VWSUBU_VX, MASK_VWSUBU_VX) 3031 DECLARE_INSN(vwsub_vx, MATCH_VWSUB_VX, MASK_VWSUB_VX) 3032 DECLARE_INSN(vwaddu_wx, MATCH_VWADDU_WX, MASK_VWADDU_WX) 3033 DECLARE_INSN(vwadd_wx, MATCH_VWADD_WX, MASK_VWADD_WX) 3034 DECLARE_INSN(vwsubu_wx, MATCH_VWSUBU_WX, MASK_VWSUBU_WX) 3035 DECLARE_INSN(vwsub_wx, MATCH_VWSUB_WX, MASK_VWSUB_WX) 3036 DECLARE_INSN(vwmulu_vx, MATCH_VWMULU_VX, MASK_VWMULU_VX) 3037 DECLARE_INSN(vwmulsu_vx, MATCH_VWMULSU_VX, MASK_VWMULSU_VX) 3038 DECLARE_INSN(vwmul_vx, MATCH_VWMUL_VX, MASK_VWMUL_VX) 3039 DECLARE_INSN(vwmaccu_vx, MATCH_VWMACCU_VX, MASK_VWMACCU_VX) 3040 DECLARE_INSN(vwmacc_vx, MATCH_VWMACC_VX, MASK_VWMACC_VX) 3041 DECLARE_INSN(vwmaccus_vx, MATCH_VWMACCUS_VX, MASK_VWMACCUS_VX) 3042 DECLARE_INSN(vwmaccsu_vx, MATCH_VWMACCSU_VX, MASK_VWMACCSU_VX) 3043 DECLARE_INSN(vamoswapei8_v, MATCH_VAMOSWAPEI8_V, MASK_VAMOSWAPEI8_V) 3044 DECLARE_INSN(vamoaddei8_v, MATCH_VAMOADDEI8_V, MASK_VAMOADDEI8_V) 3045 DECLARE_INSN(vamoxorei8_v, MATCH_VAMOXOREI8_V, MASK_VAMOXOREI8_V) 3046 DECLARE_INSN(vamoandei8_v, MATCH_VAMOANDEI8_V, MASK_VAMOANDEI8_V) 3047 DECLARE_INSN(vamoorei8_v, MATCH_VAMOOREI8_V, MASK_VAMOOREI8_V) 3048 DECLARE_INSN(vamominei8_v, MATCH_VAMOMINEI8_V, MASK_VAMOMINEI8_V) 3049 DECLARE_INSN(vamomaxei8_v, MATCH_VAMOMAXEI8_V, MASK_VAMOMAXEI8_V) 3050 DECLARE_INSN(vamominuei8_v, MATCH_VAMOMINUEI8_V, MASK_VAMOMINUEI8_V) 3051 DECLARE_INSN(vamomaxuei8_v, MATCH_VAMOMAXUEI8_V, MASK_VAMOMAXUEI8_V) 3052 DECLARE_INSN(vamoswapei16_v, MATCH_VAMOSWAPEI16_V, MASK_VAMOSWAPEI16_V) 3053 DECLARE_INSN(vamoaddei16_v, MATCH_VAMOADDEI16_V, MASK_VAMOADDEI16_V) 3054 DECLARE_INSN(vamoxorei16_v, MATCH_VAMOXOREI16_V, MASK_VAMOXOREI16_V) 3055 DECLARE_INSN(vamoandei16_v, MATCH_VAMOANDEI16_V, MASK_VAMOANDEI16_V) 3056 DECLARE_INSN(vamoorei16_v, MATCH_VAMOOREI16_V, MASK_VAMOOREI16_V) 3057 DECLARE_INSN(vamominei16_v, MATCH_VAMOMINEI16_V, MASK_VAMOMINEI16_V) 3058 DECLARE_INSN(vamomaxei16_v, MATCH_VAMOMAXEI16_V, MASK_VAMOMAXEI16_V) 3059 DECLARE_INSN(vamominuei16_v, MATCH_VAMOMINUEI16_V, MASK_VAMOMINUEI16_V) 3060 DECLARE_INSN(vamomaxuei16_v, MATCH_VAMOMAXUEI16_V, MASK_VAMOMAXUEI16_V) 3061 DECLARE_INSN(vamoswapei32_v, MATCH_VAMOSWAPEI32_V, MASK_VAMOSWAPEI32_V) 3062 DECLARE_INSN(vamoaddei32_v, MATCH_VAMOADDEI32_V, MASK_VAMOADDEI32_V) 3063 DECLARE_INSN(vamoxorei32_v, MATCH_VAMOXOREI32_V, MASK_VAMOXOREI32_V) 3064 DECLARE_INSN(vamoandei32_v, MATCH_VAMOANDEI32_V, MASK_VAMOANDEI32_V) 3065 DECLARE_INSN(vamoorei32_v, MATCH_VAMOOREI32_V, MASK_VAMOOREI32_V) 3066 DECLARE_INSN(vamominei32_v, MATCH_VAMOMINEI32_V, MASK_VAMOMINEI32_V) 3067 DECLARE_INSN(vamomaxei32_v, MATCH_VAMOMAXEI32_V, MASK_VAMOMAXEI32_V) 3068 DECLARE_INSN(vamominuei32_v, MATCH_VAMOMINUEI32_V, MASK_VAMOMINUEI32_V) 3069 DECLARE_INSN(vamomaxuei32_v, MATCH_VAMOMAXUEI32_V, MASK_VAMOMAXUEI32_V) 3070 DECLARE_INSN(vamoswapei64_v, MATCH_VAMOSWAPEI64_V, MASK_VAMOSWAPEI64_V) 3071 DECLARE_INSN(vamoaddei64_v, MATCH_VAMOADDEI64_V, MASK_VAMOADDEI64_V) 3072 DECLARE_INSN(vamoxorei64_v, MATCH_VAMOXOREI64_V, MASK_VAMOXOREI64_V) 3073 DECLARE_INSN(vamoandei64_v, MATCH_VAMOANDEI64_V, MASK_VAMOANDEI64_V) 3074 DECLARE_INSN(vamoorei64_v, MATCH_VAMOOREI64_V, MASK_VAMOOREI64_V) 3075 DECLARE_INSN(vamominei64_v, MATCH_VAMOMINEI64_V, MASK_VAMOMINEI64_V) 3076 DECLARE_INSN(vamomaxei64_v, MATCH_VAMOMAXEI64_V, MASK_VAMOMAXEI64_V) 3077 DECLARE_INSN(vamominuei64_v, MATCH_VAMOMINUEI64_V, MASK_VAMOMINUEI64_V) 3078 DECLARE_INSN(vamomaxuei64_v, MATCH_VAMOMAXUEI64_V, MASK_VAMOMAXUEI64_V) 3079 DECLARE_INSN(vmvnfr_v, MATCH_VMVNFR_V, MASK_VMVNFR_V) 3080 DECLARE_INSN(vl1r_v, MATCH_VL1R_V, MASK_VL1R_V) 3081 DECLARE_INSN(vl2r_v, MATCH_VL2R_V, MASK_VL2R_V) 3082 DECLARE_INSN(vl4r_v, MATCH_VL4R_V, MASK_VL4R_V) 3083 DECLARE_INSN(vl8r_v, MATCH_VL8R_V, MASK_VL8R_V) 3084 #ifdef DECLARE_RV32_ONLY 3085 DECLARE_RV32_ONLY(aes32esmi) 3086 DECLARE_RV32_ONLY(aes32esi) 3087 DECLARE_RV32_ONLY(aes32dsmi) 3088 DECLARE_RV32_ONLY(aes32dsi) 3089 DECLARE_RV32_ONLY(sha512sum0r) 3090 DECLARE_RV32_ONLY(sha512sum1r) 3091 DECLARE_RV32_ONLY(sha512sig0l) 3092 DECLARE_RV32_ONLY(sha512sig0h) 3093 DECLARE_RV32_ONLY(sha512sig1l) 3094 DECLARE_RV32_ONLY(sha512sig1h) 3095 #endif 3096 #ifdef DECLARE_RV64_ONLY 3097 DECLARE_RV64_ONLY(aes64ks1i) 3098 DECLARE_RV64_ONLY(aes64im) 3099 DECLARE_RV64_ONLY(aes64ks2) 3100 DECLARE_RV64_ONLY(aes64esm) 3101 DECLARE_RV64_ONLY(aes64es) 3102 DECLARE_RV64_ONLY(aes64dsm) 3103 DECLARE_RV64_ONLY(aes64ds) 3104 DECLARE_RV64_ONLY(sha512sum0) 3105 DECLARE_RV64_ONLY(sha512sum1) 3106 DECLARE_RV64_ONLY(sha512sig0) 3107 DECLARE_RV64_ONLY(sha512sig1) 3108 #endif 3109 #endif 3110 #ifdef DECLARE_CSR 3111 DECLARE_CSR(fflags, CSR_FFLAGS) 3112 DECLARE_CSR(frm, CSR_FRM) 3113 DECLARE_CSR(fcsr, CSR_FCSR) 3114 DECLARE_CSR(ustatus, CSR_USTATUS) 3115 DECLARE_CSR(uie, CSR_UIE) 3116 DECLARE_CSR(utvec, CSR_UTVEC) 3117 DECLARE_CSR(vstart, CSR_VSTART) 3118 DECLARE_CSR(vxsat, CSR_VXSAT) 3119 DECLARE_CSR(vxrm, CSR_VXRM) 3120 DECLARE_CSR(vcsr, CSR_VCSR) 3121 DECLARE_CSR(uscratch, CSR_USCRATCH) 3122 DECLARE_CSR(uepc, CSR_UEPC) 3123 DECLARE_CSR(ucause, CSR_UCAUSE) 3124 DECLARE_CSR(utval, CSR_UTVAL) 3125 DECLARE_CSR(uip, CSR_UIP) 3126 DECLARE_CSR(cycle, CSR_CYCLE) 3127 DECLARE_CSR(time, CSR_TIME) 3128 DECLARE_CSR(instret, CSR_INSTRET) 3129 DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) 3130 DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) 3131 DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) 3132 DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) 3133 DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) 3134 DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) 3135 DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) 3136 DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) 3137 DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) 3138 DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) 3139 DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) 3140 DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) 3141 DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) 3142 DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) 3143 DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) 3144 DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) 3145 DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) 3146 DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) 3147 DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) 3148 DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) 3149 DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) 3150 DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) 3151 DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) 3152 DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) 3153 DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) 3154 DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) 3155 DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) 3156 DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) 3157 DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) 3158 DECLARE_CSR(vl, CSR_VL) 3159 DECLARE_CSR(vtype, CSR_VTYPE) 3160 DECLARE_CSR(vlenb, CSR_VLENB) 3161 DECLARE_CSR(sstatus, CSR_SSTATUS) 3162 DECLARE_CSR(sedeleg, CSR_SEDELEG) 3163 DECLARE_CSR(sideleg, CSR_SIDELEG) 3164 DECLARE_CSR(sie, CSR_SIE) 3165 DECLARE_CSR(stvec, CSR_STVEC) 3166 DECLARE_CSR(scounteren, CSR_SCOUNTEREN) 3167 DECLARE_CSR(sscratch, CSR_SSCRATCH) 3168 DECLARE_CSR(sepc, CSR_SEPC) 3169 DECLARE_CSR(scause, CSR_SCAUSE) 3170 DECLARE_CSR(stval, CSR_STVAL) 3171 DECLARE_CSR(sip, CSR_SIP) 3172 DECLARE_CSR(satp, CSR_SATP) 3173 DECLARE_CSR(vsstatus, CSR_VSSTATUS) 3174 DECLARE_CSR(vsie, CSR_VSIE) 3175 DECLARE_CSR(vstvec, CSR_VSTVEC) 3176 DECLARE_CSR(vsscratch, CSR_VSSCRATCH) 3177 DECLARE_CSR(vsepc, CSR_VSEPC) 3178 DECLARE_CSR(vscause, CSR_VSCAUSE) 3179 DECLARE_CSR(vstval, CSR_VSTVAL) 3180 DECLARE_CSR(vsip, CSR_VSIP) 3181 DECLARE_CSR(vsatp, CSR_VSATP) 3182 DECLARE_CSR(hstatus, CSR_HSTATUS) 3183 DECLARE_CSR(hedeleg, CSR_HEDELEG) 3184 DECLARE_CSR(hideleg, CSR_HIDELEG) 3185 DECLARE_CSR(hie, CSR_HIE) 3186 DECLARE_CSR(htimedelta, CSR_HTIMEDELTA) 3187 DECLARE_CSR(hcounteren, CSR_HCOUNTEREN) 3188 DECLARE_CSR(hgeie, CSR_HGEIE) 3189 DECLARE_CSR(htval, CSR_HTVAL) 3190 DECLARE_CSR(hip, CSR_HIP) 3191 DECLARE_CSR(hvip, CSR_HVIP) 3192 DECLARE_CSR(htinst, CSR_HTINST) 3193 DECLARE_CSR(hgatp, CSR_HGATP) 3194 DECLARE_CSR(hgeip, CSR_HGEIP) 3195 DECLARE_CSR(utvt, CSR_UTVT) 3196 DECLARE_CSR(unxti, CSR_UNXTI) 3197 DECLARE_CSR(uintstatus, CSR_UINTSTATUS) 3198 DECLARE_CSR(uscratchcsw, CSR_USCRATCHCSW) 3199 DECLARE_CSR(uscratchcswl, CSR_USCRATCHCSWL) 3200 DECLARE_CSR(stvt, CSR_STVT) 3201 DECLARE_CSR(snxti, CSR_SNXTI) 3202 DECLARE_CSR(sintstatus, CSR_SINTSTATUS) 3203 DECLARE_CSR(sscratchcsw, CSR_SSCRATCHCSW) 3204 DECLARE_CSR(sscratchcswl, CSR_SSCRATCHCSWL) 3205 DECLARE_CSR(mtvt, CSR_MTVT) 3206 DECLARE_CSR(mnxti, CSR_MNXTI) 3207 DECLARE_CSR(mintstatus, CSR_MINTSTATUS) 3208 DECLARE_CSR(mscratchcsw, CSR_MSCRATCHCSW) 3209 DECLARE_CSR(mscratchcswl, CSR_MSCRATCHCSWL) 3210 DECLARE_CSR(mstatus, CSR_MSTATUS) 3211 DECLARE_CSR(misa, CSR_MISA) 3212 DECLARE_CSR(medeleg, CSR_MEDELEG) 3213 DECLARE_CSR(mideleg, CSR_MIDELEG) 3214 DECLARE_CSR(mie, CSR_MIE) 3215 DECLARE_CSR(mtvec, CSR_MTVEC) 3216 DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) 3217 DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT) 3218 DECLARE_CSR(mscratch, CSR_MSCRATCH) 3219 DECLARE_CSR(mepc, CSR_MEPC) 3220 DECLARE_CSR(mcause, CSR_MCAUSE) 3221 DECLARE_CSR(mtval, CSR_MTVAL) 3222 DECLARE_CSR(mip, CSR_MIP) 3223 DECLARE_CSR(mtinst, CSR_MTINST) 3224 DECLARE_CSR(mtval2, CSR_MTVAL2) 3225 DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) 3226 DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) 3227 DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) 3228 DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) 3229 DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) 3230 DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) 3231 DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) 3232 DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) 3233 DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) 3234 DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) 3235 DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) 3236 DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) 3237 DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) 3238 DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) 3239 DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) 3240 DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) 3241 DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) 3242 DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) 3243 DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) 3244 DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) 3245 DECLARE_CSR(tselect, CSR_TSELECT) 3246 DECLARE_CSR(tdata1, CSR_TDATA1) 3247 DECLARE_CSR(tdata2, CSR_TDATA2) 3248 DECLARE_CSR(tdata3, CSR_TDATA3) 3249 DECLARE_CSR(tinfo, CSR_TINFO) 3250 DECLARE_CSR(tcontrol, CSR_TCONTROL) 3251 DECLARE_CSR(mcontext, CSR_MCONTEXT) 3252 DECLARE_CSR(scontext, CSR_SCONTEXT) 3253 DECLARE_CSR(dcsr, CSR_DCSR) 3254 DECLARE_CSR(dpc, CSR_DPC) 3255 DECLARE_CSR(dscratch0, CSR_DSCRATCH0) 3256 DECLARE_CSR(dscratch1, CSR_DSCRATCH1) 3257 DECLARE_CSR(mcycle, CSR_MCYCLE) 3258 DECLARE_CSR(minstret, CSR_MINSTRET) 3259 DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) 3260 DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) 3261 DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) 3262 DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) 3263 DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) 3264 DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) 3265 DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) 3266 DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) 3267 DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) 3268 DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) 3269 DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) 3270 DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) 3271 DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) 3272 DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) 3273 DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) 3274 DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) 3275 DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) 3276 DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) 3277 DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) 3278 DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) 3279 DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) 3280 DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) 3281 DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) 3282 DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) 3283 DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) 3284 DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) 3285 DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) 3286 DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) 3287 DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) 3288 DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) 3289 DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) 3290 DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) 3291 DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) 3292 DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) 3293 DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) 3294 DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) 3295 DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) 3296 DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) 3297 DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) 3298 DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) 3299 DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) 3300 DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) 3301 DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) 3302 DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) 3303 DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) 3304 DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) 3305 DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) 3306 DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) 3307 DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) 3308 DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) 3309 DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) 3310 DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) 3311 DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) 3312 DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) 3313 DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) 3314 DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) 3315 DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) 3316 DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) 3317 DECLARE_CSR(mvendorid, CSR_MVENDORID) 3318 DECLARE_CSR(marchid, CSR_MARCHID) 3319 DECLARE_CSR(mimpid, CSR_MIMPID) 3320 DECLARE_CSR(mhartid, CSR_MHARTID) 3321 DECLARE_CSR(mentropy, CSR_MENTROPY) 3322 DECLARE_CSR(mnoise, CSR_MNOISE) 3323 DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH) 3324 DECLARE_CSR(cycleh, CSR_CYCLEH) 3325 DECLARE_CSR(timeh, CSR_TIMEH) 3326 DECLARE_CSR(instreth, CSR_INSTRETH) 3327 DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) 3328 DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) 3329 DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) 3330 DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) 3331 DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) 3332 DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) 3333 DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) 3334 DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) 3335 DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) 3336 DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) 3337 DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) 3338 DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) 3339 DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) 3340 DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) 3341 DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) 3342 DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) 3343 DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) 3344 DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) 3345 DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) 3346 DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) 3347 DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) 3348 DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) 3349 DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) 3350 DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) 3351 DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) 3352 DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) 3353 DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) 3354 DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) 3355 DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) 3356 DECLARE_CSR(mstatush, CSR_MSTATUSH) 3357 DECLARE_CSR(mcycleh, CSR_MCYCLEH) 3358 DECLARE_CSR(minstreth, CSR_MINSTRETH) 3359 DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) 3360 DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) 3361 DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) 3362 DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) 3363 DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) 3364 DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) 3365 DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) 3366 DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) 3367 DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) 3368 DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) 3369 DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) 3370 DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) 3371 DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) 3372 DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) 3373 DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) 3374 DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) 3375 DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) 3376 DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) 3377 DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) 3378 DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) 3379 DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) 3380 DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) 3381 DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) 3382 DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) 3383 DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) 3384 DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) 3385 DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) 3386 DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) 3387 DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) 3388 #endif 3389 #ifdef DECLARE_CAUSE 3390 DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) 3391 DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) 3392 DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) 3393 DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) 3394 DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) 3395 DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) 3396 DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) 3397 DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) 3398 DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) 3399 DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) 3400 DECLARE_CAUSE("virtual_supervisor_ecall", CAUSE_VIRTUAL_SUPERVISOR_ECALL) 3401 DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) 3402 DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) 3403 DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) 3404 DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) 3405 DECLARE_CAUSE("fetch guest page fault", CAUSE_FETCH_GUEST_PAGE_FAULT) 3406 DECLARE_CAUSE("load guest page fault", CAUSE_LOAD_GUEST_PAGE_FAULT) 3407 DECLARE_CAUSE("virtual instruction", CAUSE_VIRTUAL_INSTRUCTION) 3408 DECLARE_CAUSE("store guest page fault", CAUSE_STORE_GUEST_PAGE_FAULT) 3409 #endif 3410