1 /*-------------------------------------------------------------------------- 2 P89c51RD2.H 3 (English) 4 This header allows to use the microcontroler Philips P89c51RD2 5 with the compiler SDCC. 6 7 Copyright (c) 2005 Omar Espinosa--e-mail: opiedrahita2003 AT yahoo.com. 8 9 This library is free software; you can redistribute it and/or 10 modify it under the terms of the GNU Lesser General Public 11 License as published by the Free Software Foundation; either 12 version 2.1 of the License, or (at your option) any later version. 13 14 This library is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 Lesser General Public License for more details. 18 19 You should have received a copy of the GNU Lesser General Public 20 License along with this library; if not, write to the Free Software 21 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 23 (Spanish-Espa�ol) 24 Archivo encabezador para el ucontrolador Philips P89c51RD2. 25 Derechos de copy (DC) 2005. OMAR ESPINOSA P. E-mail: opiedrahita2003 AT yahoo.com 26 Uso libre 27 --------------------------------------------------------------------------*/ 28 29 #ifndef __P89c51RD2_H__ 30 #define __P89c51RD2_H__ 31 32 /* BYTE Registers */ 33 __sfr __at (0x80) P0 ; 34 __sfr __at (0x90) P1 ; 35 __sfr __at (0xA0) P2 ; 36 __sfr __at (0xB0) P3 ; 37 __sfr __at (0xD0) PSW ; 38 __sfr __at (0xE0) ACC ; 39 __sfr __at (0xF0) B ; 40 __sfr __at (0x81) SP ; 41 __sfr __at (0x82) DPL ; 42 __sfr __at (0x83) DPH ; 43 __sfr __at (0x87) PCON ; 44 __sfr __at (0x88) TCON ; 45 __sfr __at (0x89) TMOD ; 46 __sfr __at (0x8A) TL0 ; 47 __sfr __at (0x8B) TL1 ; 48 __sfr __at (0x8C) TH0 ; 49 __sfr __at (0x8D) TH1 ; 50 __sfr __at (0xA8) IE ; 51 __sfr __at (0xB8) IP ; 52 __sfr __at (0x98) SCON ; 53 __sfr __at (0x99) SBUF ; 54 55 /* 80C51Fx/Rx Extensions */ 56 __sfr __at (0x8E) AUXR ; 57 __sfr __at (0xA2) AUXR1 ; 58 __sfr __at (0xA9) SADDR ; 59 __sfr __at (0xB7) IPH ; 60 __sfr __at (0xB9) SADEN ; 61 __sfr __at (0xC8) T2CON ; 62 __sfr __at (0xC9) T2MOD ; 63 __sfr __at (0xCA) RCAP2L ; 64 __sfr __at (0xCB) RCAP2H ; 65 __sfr __at (0xCC) TL2 ; 66 __sfr __at (0xCD) TH2 ; 67 __sfr __at (0xD8) CCON ; 68 __sfr __at (0xD9) CMOD ; 69 __sfr __at (0xDA) CCAPM0 ; 70 __sfr __at (0xDB) CCAPM1 ; 71 __sfr __at (0xDC) CCAPM2 ; 72 __sfr __at (0xDD) CCAPM3 ; 73 __sfr __at (0xDE) CCAPM4 ; 74 __sfr __at (0xE9) CL ; 75 __sfr __at (0xEA) CCAP0L ; 76 __sfr __at (0xEB) CCAP1L ; 77 __sfr __at (0xEC) CCAP2L ; 78 __sfr __at (0xED) CCAP3L ; 79 __sfr __at (0xEE) CCAP4L ; 80 __sfr __at (0xF9) CH ; 81 __sfr __at (0xFA) CCAP0H ; 82 __sfr __at (0xFB) CCAP1H ; 83 __sfr __at (0xFC) CCAP2H ; 84 __sfr __at (0xFD) CCAP3H ; 85 __sfr __at (0xFE) CCAP4H ; 86 87 88 /* BIT Registers */ 89 /* PSW */ 90 91 __sbit __at (0xD7) PSW_7; 92 __sbit __at (0xD6) PSW_6; 93 __sbit __at (0xD5) PSW_5; 94 __sbit __at (0xD4) PSW_4; 95 __sbit __at (0xD3) PSW_3; 96 __sbit __at (0xD2) PSW_2; 97 __sbit __at (0xD0) PSW_0; 98 99 #define CY PSW_7 100 #define AC PSW_6 101 #define F0 PSW_5 102 #define RS1 PSW_4 103 #define RS0 PSW_3 104 #define OV PSW_2 105 #define P PSW_0 106 107 /* TCON */ 108 __sbit __at (0x8F) TCON_7; 109 __sbit __at (0x8E) TCON_6; 110 __sbit __at (0x8D) TCON_5; 111 __sbit __at (0x8C) TCON_4; 112 __sbit __at (0x8B) TCON_3; 113 __sbit __at (0x8A) TCON_2; 114 __sbit __at (0x89) TCON_1; 115 __sbit __at (0x88) TCON_0; 116 117 #define TF1 TCON_7 118 #define TR1 TCON_6 119 #define TF0 TCON_5 120 #define TR0 TCON_4 121 #define IE1 TCON_3 122 #define IT1 TCON_2 123 #define IE0 TCON_1 124 #define IT0 TCON_0 125 126 /* IE */ 127 __sbit __at (0xAF) IE_7; 128 __sbit __at (0xAE) IE_6; 129 __sbit __at (0xAD) IE_5; 130 __sbit __at (0xAC) IE_4; 131 __sbit __at (0xAB) IE_3; 132 __sbit __at (0xAA) IE_2; 133 __sbit __at (0xA9) IE_1; 134 __sbit __at (0xA8) IE_0; 135 136 #define EA IE_7 137 #define EC IE_6 138 #define ET2 IE_5 139 #define ES IE_4 140 #define ET1 IE_3 141 #define EX1 IE_2 142 #define ET0 IE_1 143 #define EX0 IE_0 144 145 /* IP */ 146 __sbit __at (0xBE) IP_6; 147 __sbit __at (0xBD) IP_5; 148 __sbit __at (0xBC) IP_4; 149 __sbit __at (0xBB) IP_3; 150 __sbit __at (0xBA) IP_2; 151 __sbit __at (0xB9) IP_1; 152 __sbit __at (0xB8) IP_0; 153 154 #define PPC IP_6 155 #define PT2 IP_5 156 #define PS IP_4 157 #define PT1 IP_3 158 #define PX1 IP_2 159 #define PT0 IP_1 160 #define PX0 IP_0 161 162 /* P3 */ 163 __sbit __at (0xB7) P3_7; 164 __sbit __at (0xB6) P3_6; 165 __sbit __at (0xB5) P3_5; 166 __sbit __at (0xB4) P3_4; 167 __sbit __at (0xB3) P3_3; 168 __sbit __at (0xB2) P3_2; 169 __sbit __at (0xB1) P3_1; 170 __sbit __at (0xB0) P3_0; 171 172 #define RD P3_7 173 #define WR P3_6 174 #define T1 P3_5 175 #define T0 P3_4 176 #define INT1 P3_3 177 #define INT0 P3_2 178 #define TXD P3_1 179 #define RXD P3_0 180 181 /* SCON */ 182 __sbit __at (0x9F) SCON_7; // alternatively "FE" 183 __sbit __at (0x9E) SCON_6; 184 __sbit __at (0x9D) SCON_5; 185 __sbit __at (0x9C) SCON_4; 186 __sbit __at (0x9B) SCON_3; 187 __sbit __at (0x9A) SCON_2; 188 __sbit __at (0x99) SCON_1; 189 __sbit __at (0x98) SCON_0; 190 191 #define SM0 SCON_7 // alternatively "FE" 192 #define FE SCON_7 193 #define SM1 SCON_6 194 #define SM2 SCON_5 195 #define REN SCON_4 196 #define TB8 SCON_3 197 #define RB8 SCON_2 198 #define TI SCON_1 199 #define RI SCON_0 200 201 /* P1 */ 202 __sbit __at (0x97) P1_7; 203 __sbit __at (0x96) P1_6; 204 __sbit __at (0x95) P1_5; 205 __sbit __at (0x94) P1_4; 206 __sbit __at (0x93) P1_3; 207 __sbit __at (0x92) P1_2; 208 __sbit __at (0x91) P1_1; 209 __sbit __at (0x90) P1_0; 210 211 #define CEX4 P1_7 212 #define CEX3 P1_6 213 #define CEX2 P1_5 214 #define CEX1 P1_4 215 #define CEX0 P1_3 216 #define ECI P1_2 217 #define T2EX P1_1 218 #define T2 P1_0 219 220 /* T2CON */ 221 __sbit __at (0xCF) T2CON_7; 222 __sbit __at (0xCE) T2CON_6; 223 __sbit __at (0xCD) T2CON_5; 224 __sbit __at (0xCC) T2CON_4; 225 __sbit __at (0xCB) T2CON_3; 226 __sbit __at (0xCA) T2CON_2; 227 __sbit __at (0xC9) T2CON_1; 228 __sbit __at (0xC8) T2CON_0; 229 230 #define TF2 T2CON_7 231 #define EXF2 T2CON_6 232 #define RCLK T2CON_5 233 #define TCLK T2CON_4 234 #define EXEN2 T2CON_3 235 #define TR2 T2CON_2 236 #define C_T2 T2CON_1 237 #define CP_RL2 T2CON_0 238 239 /* CCON */ 240 __sbit __at (0xDF) CCON_7; 241 __sbit __at (0xDE) CCON_6; 242 __sbit __at (0xDC) CCON_4; 243 __sbit __at (0xDB) CCON_3; 244 __sbit __at (0xDA) CCON_2; 245 __sbit __at (0xD9) CCON_1; 246 __sbit __at (0xD8) CCON_0; 247 248 #define CF CCON_7 249 #define CR CCON_6 250 #define CCF4 CCON_4 251 #define CCF3 CCON_3 252 #define CCF2 CCON_2 253 #define CCF1 CCON_1 254 #define CCF0 CCON_0 255 256 #endif 257