1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the SystemZ implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
14 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
15 
16 #include "SystemZ.h"
17 #include "SystemZRegisterInfo.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include <cstdint>
24 
25 #define GET_INSTRINFO_HEADER
26 #include "SystemZGenInstrInfo.inc"
27 
28 namespace llvm {
29 
30 class SystemZSubtarget;
31 
32 namespace SystemZII {
33 
34 enum {
35   // See comments in SystemZInstrFormats.td.
36   SimpleBDXLoad          = (1 << 0),
37   SimpleBDXStore         = (1 << 1),
38   Has20BitOffset         = (1 << 2),
39   HasIndex               = (1 << 3),
40   Is128Bit               = (1 << 4),
41   AccessSizeMask         = (31 << 5),
42   AccessSizeShift        = 5,
43   CCValuesMask           = (15 << 10),
44   CCValuesShift          = 10,
45   CompareZeroCCMaskMask  = (15 << 14),
46   CompareZeroCCMaskShift = 14,
47   CCMaskFirst            = (1 << 18),
48   CCMaskLast             = (1 << 19),
49   IsLogical              = (1 << 20),
50   CCIfNoSignedWrap       = (1 << 21)
51 };
52 
getAccessSize(unsigned int Flags)53 static inline unsigned getAccessSize(unsigned int Flags) {
54   return (Flags & AccessSizeMask) >> AccessSizeShift;
55 }
56 
getCCValues(unsigned int Flags)57 static inline unsigned getCCValues(unsigned int Flags) {
58   return (Flags & CCValuesMask) >> CCValuesShift;
59 }
60 
getCompareZeroCCMask(unsigned int Flags)61 static inline unsigned getCompareZeroCCMask(unsigned int Flags) {
62   return (Flags & CompareZeroCCMaskMask) >> CompareZeroCCMaskShift;
63 }
64 
65 // SystemZ MachineOperand target flags.
66 enum {
67   // Masks out the bits for the access model.
68   MO_SYMBOL_MODIFIER = (3 << 0),
69 
70   // @GOT (aka @GOTENT)
71   MO_GOT = (1 << 0),
72 
73   // @INDNTPOFF
74   MO_INDNTPOFF = (2 << 0)
75 };
76 
77 // Classifies a branch.
78 enum BranchType {
79   // An instruction that branches on the current value of CC.
80   BranchNormal,
81 
82   // An instruction that peforms a 32-bit signed comparison and branches
83   // on the result.
84   BranchC,
85 
86   // An instruction that peforms a 32-bit unsigned comparison and branches
87   // on the result.
88   BranchCL,
89 
90   // An instruction that peforms a 64-bit signed comparison and branches
91   // on the result.
92   BranchCG,
93 
94   // An instruction that peforms a 64-bit unsigned comparison and branches
95   // on the result.
96   BranchCLG,
97 
98   // An instruction that decrements a 32-bit register and branches if
99   // the result is nonzero.
100   BranchCT,
101 
102   // An instruction that decrements a 64-bit register and branches if
103   // the result is nonzero.
104   BranchCTG,
105 
106   // An instruction representing an asm goto statement.
107   AsmGoto
108 };
109 
110 // Information about a branch instruction.
111 class Branch {
112   // The target of the branch. In case of INLINEASM_BR, this is nullptr.
113   const MachineOperand *Target;
114 
115 public:
116   // The type of the branch.
117   BranchType Type;
118 
119   // CCMASK_<N> is set if CC might be equal to N.
120   unsigned CCValid;
121 
122   // CCMASK_<N> is set if the branch should be taken when CC == N.
123   unsigned CCMask;
124 
Branch(BranchType type,unsigned ccValid,unsigned ccMask,const MachineOperand * target)125   Branch(BranchType type, unsigned ccValid, unsigned ccMask,
126          const MachineOperand *target)
127     : Target(target), Type(type), CCValid(ccValid), CCMask(ccMask) {}
128 
isIndirect()129   bool isIndirect() { return Target != nullptr && Target->isReg(); }
hasMBBTarget()130   bool hasMBBTarget() { return Target != nullptr && Target->isMBB(); }
getMBBTarget()131   MachineBasicBlock *getMBBTarget() {
132     return hasMBBTarget() ? Target->getMBB() : nullptr;
133   }
134 };
135 
136 // Kinds of fused compares in compare-and-* instructions.  Together with type
137 // of the converted compare, this identifies the compare-and-*
138 // instruction.
139 enum FusedCompareType {
140   // Relative branch - CRJ etc.
141   CompareAndBranch,
142 
143   // Indirect branch, used for return - CRBReturn etc.
144   CompareAndReturn,
145 
146   // Indirect branch, used for sibcall - CRBCall etc.
147   CompareAndSibcall,
148 
149   // Trap
150   CompareAndTrap
151 };
152 
153 } // end namespace SystemZII
154 
155 namespace SystemZ {
156 int getTwoOperandOpcode(uint16_t Opcode);
157 int getTargetMemOpcode(uint16_t Opcode);
158 
159 // Return a version of comparison CC mask CCMask in which the LT and GT
160 // actions are swapped.
161 unsigned reverseCCMask(unsigned CCMask);
162 
163 // Create a new basic block after MBB.
164 MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB);
165 // Split MBB after MI and return the new block (the one that contains
166 // instructions after MI).
167 MachineBasicBlock *splitBlockAfter(MachineBasicBlock::iterator MI,
168                                    MachineBasicBlock *MBB);
169 // Split MBB before MI and return the new block (the one that contains MI).
170 MachineBasicBlock *splitBlockBefore(MachineBasicBlock::iterator MI,
171                                     MachineBasicBlock *MBB);
172 }
173 
174 class SystemZInstrInfo : public SystemZGenInstrInfo {
175   const SystemZRegisterInfo RI;
176   SystemZSubtarget &STI;
177 
178   void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
179   void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
180   void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode,
181                       bool ConvertHigh) const;
182   void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
183                        unsigned LowOpcodeK, unsigned HighOpcode) const;
184   void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
185                        unsigned HighOpcode) const;
186   void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
187                        unsigned HighOpcode) const;
188   void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
189                         unsigned Size) const;
190   void expandLoadStackGuard(MachineInstr *MI) const;
191 
192   MachineInstrBuilder
193   emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
194                 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
195                 unsigned LowLowOpcode, unsigned Size, bool KillSrc,
196                 bool UndefSrc) const;
197 
198   virtual void anchor();
199 
200 protected:
201   /// Commutes the operands in the given instruction by changing the operands
202   /// order and/or changing the instruction's opcode and/or the immediate value
203   /// operand.
204   ///
205   /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
206   /// to be commuted.
207   ///
208   /// Do not call this method for a non-commutable instruction or
209   /// non-commutable operands.
210   /// Even though the instruction is commutable, the method may still
211   /// fail to commute the operands, null pointer is returned in such cases.
212   MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
213                                        unsigned CommuteOpIdx1,
214                                        unsigned CommuteOpIdx2) const override;
215 
216 public:
217   explicit SystemZInstrInfo(SystemZSubtarget &STI);
218 
219   // Override TargetInstrInfo.
220   unsigned isLoadFromStackSlot(const MachineInstr &MI,
221                                int &FrameIndex) const override;
222   unsigned isStoreToStackSlot(const MachineInstr &MI,
223                               int &FrameIndex) const override;
224   bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
225                        int &SrcFrameIndex) const override;
226   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
227                      MachineBasicBlock *&FBB,
228                      SmallVectorImpl<MachineOperand> &Cond,
229                      bool AllowModify) const override;
230   unsigned removeBranch(MachineBasicBlock &MBB,
231                         int *BytesRemoved = nullptr) const override;
232   unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
233                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
234                         const DebugLoc &DL,
235                         int *BytesAdded = nullptr) const override;
236   bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
237                       Register &SrcReg2, int64_t &Mask,
238                       int64_t &Value) const override;
239   bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
240                        Register, Register, Register, int &, int &,
241                        int &) const override;
242   void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
243                     const DebugLoc &DL, Register DstReg,
244                     ArrayRef<MachineOperand> Cond, Register TrueReg,
245                     Register FalseReg) const override;
246   bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
247                      MachineRegisterInfo *MRI) const override;
248   bool isPredicable(const MachineInstr &MI) const override;
249   bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
250                            unsigned ExtraPredCycles,
251                            BranchProbability Probability) const override;
252   bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
253                            unsigned NumCyclesT, unsigned ExtraPredCyclesT,
254                            MachineBasicBlock &FMBB,
255                            unsigned NumCyclesF, unsigned ExtraPredCyclesF,
256                            BranchProbability Probability) const override;
257   bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
258                             BranchProbability Probability) const override;
259   bool PredicateInstruction(MachineInstr &MI,
260                             ArrayRef<MachineOperand> Pred) const override;
261   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
262                    const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
263                    bool KillSrc) const override;
264   void storeRegToStackSlot(MachineBasicBlock &MBB,
265                            MachineBasicBlock::iterator MBBI, Register SrcReg,
266                            bool isKill, int FrameIndex,
267                            const TargetRegisterClass *RC,
268                            const TargetRegisterInfo *TRI,
269                            Register VReg) const override;
270   void loadRegFromStackSlot(MachineBasicBlock &MBB,
271                             MachineBasicBlock::iterator MBBI, Register DestReg,
272                             int FrameIdx, const TargetRegisterClass *RC,
273                             const TargetRegisterInfo *TRI,
274                             Register VReg) const override;
275   MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
276                                       LiveIntervals *LIS) const override;
277   MachineInstr *
278   foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
279                         ArrayRef<unsigned> Ops,
280                         MachineBasicBlock::iterator InsertPt, int FrameIndex,
281                         LiveIntervals *LIS = nullptr,
282                         VirtRegMap *VRM = nullptr) const override;
283   MachineInstr *foldMemoryOperandImpl(
284       MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
285       MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
286       LiveIntervals *LIS = nullptr) const override;
287   bool expandPostRAPseudo(MachineInstr &MBBI) const override;
288   bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
289     override;
290 
291   // Return the SystemZRegisterInfo, which this class owns.
getRegisterInfo()292   const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
293 
294   // Return the size in bytes of MI.
295   unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
296 
297   // Return true if MI is a conditional or unconditional branch.
298   // When returning true, set Cond to the mask of condition-code
299   // values on which the instruction will branch, and set Target
300   // to the operand that contains the branch target.  This target
301   // can be a register or a basic block.
302   SystemZII::Branch getBranchInfo(const MachineInstr &MI) const;
303 
304   // Get the load and store opcodes for a given register class.
305   void getLoadStoreOpcodes(const TargetRegisterClass *RC,
306                            unsigned &LoadOpcode, unsigned &StoreOpcode) const;
307 
308   // Opcode is the opcode of an instruction that has an address operand,
309   // and the caller wants to perform that instruction's operation on an
310   // address that has displacement Offset.  Return the opcode of a suitable
311   // instruction (which might be Opcode itself) or 0 if no such instruction
312   // exists.  MI may be passed in order to allow examination of physical
313   // register operands (i.e. if a VR32/64 reg ended up as an FP or Vector reg).
314   unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset,
315                               const MachineInstr *MI = nullptr) const;
316 
317   // Return true if Opcode has a mapping in 12 <-> 20 bit displacements.
318   bool hasDisplacementPairInsn(unsigned Opcode) const;
319 
320   // If Opcode is a load instruction that has a LOAD AND TEST form,
321   // return the opcode for the testing form, otherwise return 0.
322   unsigned getLoadAndTest(unsigned Opcode) const;
323 
324   // Return true if ROTATE AND ... SELECTED BITS can be used to select bits
325   // Mask of the R2 operand, given that only the low BitSize bits of Mask are
326   // significant.  Set Start and End to the I3 and I4 operands if so.
327   bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
328                    unsigned &Start, unsigned &End) const;
329 
330   // If Opcode is a COMPARE opcode for which an associated fused COMPARE AND *
331   // operation exists, return the opcode for the latter, otherwise return 0.
332   // MI, if nonnull, is the compare instruction.
333   unsigned getFusedCompare(unsigned Opcode,
334                            SystemZII::FusedCompareType Type,
335                            const MachineInstr *MI = nullptr) const;
336 
337   // Try to find all CC users of the compare instruction (MBBI) and update
338   // all of them to maintain equivalent behavior after swapping the compare
339   // operands. Return false if not all users can be conclusively found and
340   // handled. The compare instruction is *not* changed.
341   bool prepareCompareSwapOperands(MachineBasicBlock::iterator MBBI) const;
342 
343   // If Opcode is a LOAD opcode for with an associated LOAD AND TRAP
344   // operation exists, returh the opcode for the latter, otherwise return 0.
345   unsigned getLoadAndTrap(unsigned Opcode) const;
346 
347   // Emit code before MBBI in MI to move immediate value Value into
348   // physical register Reg.
349   void loadImmediate(MachineBasicBlock &MBB,
350                      MachineBasicBlock::iterator MBBI,
351                      unsigned Reg, uint64_t Value) const;
352 
353   // Perform target specific instruction verification.
354   bool verifyInstruction(const MachineInstr &MI,
355                          StringRef &ErrInfo) const override;
356 
357   // Sometimes, it is possible for the target to tell, even without
358   // aliasing information, that two MIs access different memory
359   // addresses. This function returns true if two MIs access different
360   // memory addresses and false otherwise.
361   bool
362   areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
363                                   const MachineInstr &MIb) const override;
364 };
365 
366 } // end namespace llvm
367 
368 #endif // LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H
369