xref: /freebsd/sys/dev/cxgb/cxgb_ioctl.h (revision 78d14616)
1 /**************************************************************************
2 SPDX-License-Identifier: BSD-2-Clause
3 
4 Copyright (c) 2007-2008, Chelsio Inc.
5 All rights reserved.
6 
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9 
10  1. Redistributions of source code must retain the above copyright notice,
11     this list of conditions and the following disclaimer.
12 
13  2. Neither the name of the Chelsio Corporation nor the names of its
14     contributors may be used to endorse or promote products derived from
15     this software without specific prior written permission.
16 
17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 POSSIBILITY OF SUCH DAMAGE.
28 
29 ***************************************************************************/
30 #ifndef __CHIOCTL_H__
31 #define __CHIOCTL_H__
32 
33 /*
34  * Ioctl commands specific to this driver.
35  */
36 enum {
37 	CH_SETREG = 0x40,
38 	CH_GETREG,
39 	CH_GETMTUTAB,
40 	CH_SETMTUTAB,
41 	CH_SET_PM,
42 	CH_GET_PM,
43 	CH_READ_TCAM_WORD,
44 	CH_GET_MEM,
45 	CH_GET_SGE_CONTEXT,
46 	CH_GET_SGE_DESC,
47 	CH_LOAD_FW,
48 	CH_SET_TRACE_FILTER,
49 	CH_GET_QSET_PARAMS,
50 	CH_GET_QSET_NUM,
51 	CH_SET_PKTSCHED,
52 	CH_IFCONF_GETREGS,
53 	CH_GET_MIIREG,
54 	CH_SET_MIIREG,
55 	CH_GET_EEPROM,
56 	CH_SET_HW_SCHED,
57 	CH_LOAD_BOOT,
58 	CH_CLEAR_STATS,
59 	CH_GET_UP_LA,
60 	CH_GET_UP_IOQS,
61 	CH_SET_FILTER,
62 	CH_DEL_FILTER,
63 	CH_GET_FILTER,
64 };
65 
66 /* statistics categories */
67 enum {
68 	STATS_PORT  = 1 << 1,
69 	STATS_QUEUE = 1 << 2,
70 };
71 
72 struct ch_reg {
73 	uint32_t addr;
74 	uint32_t val;
75 };
76 
77 struct ch_cntxt {
78 	uint32_t cntxt_type;
79 	uint32_t cntxt_id;
80 	uint32_t data[4];
81 };
82 
83 /* context types */
84 enum { CNTXT_TYPE_EGRESS, CNTXT_TYPE_FL, CNTXT_TYPE_RSP, CNTXT_TYPE_CQ };
85 
86 struct ch_desc {
87 	uint32_t queue_num;
88 	uint32_t idx;
89 	uint32_t size;
90 	uint8_t  data[128];
91 };
92 
93 struct ch_mem_range {
94 	uint32_t mem_id;
95 	uint32_t addr;
96 	uint32_t len;
97 	uint32_t version;
98 	uint8_t  *buf;
99 };
100 
101 enum { MEM_CM, MEM_PMRX, MEM_PMTX };   /* ch_mem_range.mem_id values */
102 
103 struct ch_qset_params {
104 	uint32_t qset_idx;
105 	int32_t  txq_size[3];
106 	int32_t  rspq_size;
107 	int32_t  fl_size[2];
108 	int32_t  intr_lat;
109 	int32_t  polling;
110 	int32_t  lro;
111 	int32_t  cong_thres;
112 	int32_t  vector;
113 	int32_t  qnum;
114 };
115 
116 struct ch_pktsched_params {
117 	uint8_t  sched;
118 	uint8_t  idx;
119 	uint8_t  min;
120 	uint8_t  max;
121 	uint8_t  binding;
122 };
123 
124 struct ch_hw_sched {
125 	uint8_t  sched;
126 	int8_t   mode;
127 	int8_t   channel;
128 	int32_t  kbps;        /* rate in Kbps */
129 	int32_t  class_ipg;   /* tenths of nanoseconds */
130 	int32_t  flow_ipg;    /* usec */
131 };
132 
133 struct ch_mtus {
134 	uint32_t nmtus;
135 	uint16_t mtus[NMTUS];
136 };
137 
138 struct ch_pm {
139 	uint32_t tx_pg_sz;
140 	uint32_t tx_num_pg;
141 	uint32_t rx_pg_sz;
142 	uint32_t rx_num_pg;
143 	uint32_t pm_total;
144 };
145 
146 struct ch_tcam_word {
147 	uint32_t addr;
148 	uint32_t buf[3];
149 };
150 
151 struct ch_trace {
152 	uint32_t sip;
153 	uint32_t sip_mask;
154 	uint32_t dip;
155 	uint32_t dip_mask;
156 	uint16_t sport;
157 	uint16_t sport_mask;
158 	uint16_t dport;
159 	uint16_t dport_mask;
160 	uint32_t vlan:12;
161 	uint32_t vlan_mask:12;
162 	uint32_t intf:4;
163 	uint32_t intf_mask:4;
164 	uint8_t  proto;
165 	uint8_t  proto_mask;
166 	uint8_t  invert_match:1;
167 	uint8_t  config_tx:1;
168 	uint8_t  config_rx:1;
169 	uint8_t  trace_tx:1;
170 	uint8_t  trace_rx:1;
171 };
172 
173 #define REGDUMP_SIZE  (4 * 1024)
174 
175 struct ch_ifconf_regs {
176 	uint32_t  version;
177 	uint32_t  len; /* bytes */
178 	uint8_t   *data;
179 };
180 
181 struct ch_mii_data {
182 	uint32_t phy_id;
183 	uint32_t reg_num;
184 	uint32_t val_in;
185 	uint32_t val_out;
186 };
187 
188 struct ch_eeprom {
189 	uint32_t magic;
190 	uint32_t offset;
191 	uint32_t len;
192 	uint8_t  *data;
193 };
194 
195 #define LA_BUFSIZE	(2 * 1024)
196 struct ch_up_la {
197 	uint32_t stopped;
198 	uint32_t idx;
199 	uint32_t bufsize;
200 	uint32_t *data;
201 };
202 
203 struct t3_ioq_entry {
204 	uint32_t ioq_cp;
205 	uint32_t ioq_pp;
206 	uint32_t ioq_alen;
207 	uint32_t ioq_stats;
208 };
209 
210 #define IOQS_BUFSIZE	(1024)
211 struct ch_up_ioqs {
212 	uint32_t ioq_rx_enable;
213 	uint32_t ioq_tx_enable;
214 	uint32_t ioq_rx_status;
215 	uint32_t ioq_tx_status;
216 	uint32_t bufsize;
217 	struct t3_ioq_entry *data;
218 };
219 
220 struct ch_filter_tuple {
221 	uint32_t sip;
222 	uint32_t dip;
223 	uint16_t sport;
224 	uint16_t dport;
225 	uint16_t vlan:12;
226 	uint16_t vlan_prio:3;
227 };
228 
229 struct ch_filter {
230 	uint32_t filter_id;
231 	struct ch_filter_tuple val;
232 	struct ch_filter_tuple mask;
233 	uint16_t mac_addr_idx;
234 	uint8_t mac_hit:1;
235 	uint8_t proto:2;
236 
237 	uint8_t want_filter_id:1;
238 	uint8_t pass:1;
239 	uint8_t rss:1;
240 	uint8_t qset;
241 };
242 
243 #define CHELSIO_SETREG		_IOW('f', CH_SETREG, struct ch_reg)
244 #define CHELSIO_GETREG		_IOWR('f', CH_GETREG, struct ch_reg)
245 #define CHELSIO_GETMTUTAB	_IOR('f', CH_GETMTUTAB, struct ch_mtus)
246 #define CHELSIO_SETMTUTAB	_IOW('f', CH_SETMTUTAB, struct ch_mtus)
247 #define CHELSIO_SET_PM		_IOW('f', CH_SET_PM, struct ch_pm)
248 #define CHELSIO_GET_PM		_IOR('f', CH_GET_PM, struct ch_pm)
249 #define CHELSIO_READ_TCAM_WORD	_IOWR('f', CH_READ_TCAM_WORD, struct ch_tcam_word)
250 #define CHELSIO_GET_MEM		_IOWR('f', CH_GET_MEM, struct ch_mem_range)
251 #define CHELSIO_GET_SGE_CONTEXT	_IOWR('f', CH_GET_SGE_CONTEXT, struct ch_cntxt)
252 #define CHELSIO_GET_SGE_DESC	_IOWR('f', CH_GET_SGE_DESC, struct ch_desc)
253 #define CHELSIO_LOAD_FW		_IOWR('f', CH_LOAD_FW, struct ch_mem_range)
254 #define CHELSIO_SET_TRACE_FILTER _IOW('f', CH_SET_TRACE_FILTER, struct ch_trace)
255 #define CHELSIO_GET_QSET_PARAMS	_IOWR('f', CH_GET_QSET_PARAMS, struct ch_qset_params)
256 #define CHELSIO_GET_QSET_NUM	_IOR('f', CH_GET_QSET_NUM, struct ch_reg)
257 #define CHELSIO_SET_PKTSCHED	_IOW('f', CH_SET_PKTSCHED, struct ch_pktsched_params)
258 #define CHELSIO_SET_HW_SCHED	_IOW('f', CH_SET_HW_SCHED, struct ch_hw_sched)
259 #define CHELSIO_LOAD_BOOT	_IOW('f', CH_LOAD_BOOT, struct ch_mem_range)
260 #define CHELSIO_CLEAR_STATS	_IO('f', CH_CLEAR_STATS)
261 #define CHELSIO_IFCONF_GETREGS	_IOWR('f', CH_IFCONF_GETREGS, struct ch_ifconf_regs)
262 #define CHELSIO_GET_MIIREG	_IOWR('f', CH_GET_MIIREG, struct ch_mii_data)
263 #define CHELSIO_SET_MIIREG	_IOW('f', CH_SET_MIIREG, struct ch_mii_data)
264 #define CHELSIO_GET_EEPROM	_IOWR('f', CH_GET_EEPROM, struct ch_eeprom)
265 #define CHELSIO_GET_UP_LA	_IOWR('f', CH_GET_UP_LA, struct ch_up_la)
266 #define CHELSIO_GET_UP_IOQS	_IOWR('f', CH_GET_UP_IOQS, struct ch_up_ioqs)
267 #define CHELSIO_SET_FILTER	_IOW('f', CH_SET_FILTER, struct ch_filter)
268 #define CHELSIO_DEL_FILTER	_IOW('f', CH_DEL_FILTER, struct ch_filter)
269 #define CHELSIO_GET_FILTER	_IOWR('f', CH_GET_FILTER, struct ch_filter)
270 #endif
271