1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dccg.h"
27 #include "clk_mgr_internal.h"
28 #include "dcn32/dcn32_clk_mgr_smu_msg.h"
29 #include "dcn20/dcn20_clk_mgr.h"
30 #include "dce100/dce_clk_mgr.h"
31 #include "dcn31/dcn31_clk_mgr.h"
32 #include "dcn32/dcn32_clk_mgr.h"
33 #include "reg_helper.h"
34 #include "core_types.h"
35 #include "dm_helpers.h"
36 #include "link.h"
37 #include "dc_state_priv.h"
38 #include "atomfirmware.h"
39 #include "dcn32_smu13_driver_if.h"
40
41 #include "dcn/dcn_3_2_0_offset.h"
42 #include "dcn/dcn_3_2_0_sh_mask.h"
43
44 #include "dml/dcn32/dcn32_fpu.h"
45
46 #define DCN_BASE__INST0_SEG1 0x000000C0
47
48 #define mmCLK1_CLK_PLL_REQ 0x16E37
49 #define mmCLK1_CLK0_DFS_CNTL 0x16E69
50 #define mmCLK1_CLK1_DFS_CNTL 0x16E6C
51 #define mmCLK1_CLK2_DFS_CNTL 0x16E6F
52 #define mmCLK1_CLK3_DFS_CNTL 0x16E72
53 #define mmCLK1_CLK4_DFS_CNTL 0x16E75
54
55 #define mmCLK1_CLK0_CURRENT_CNT 0x16EE7
56 #define mmCLK1_CLK1_CURRENT_CNT 0x16EE8
57 #define mmCLK1_CLK2_CURRENT_CNT 0x16EE9
58 #define mmCLK1_CLK3_CURRENT_CNT 0x16EEA
59 #define mmCLK1_CLK4_CURRENT_CNT 0x16EEB
60
61 #define mmCLK4_CLK0_CURRENT_CNT 0x1B0C9
62
63 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffUL
64 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000UL
65 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000UL
66 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x00000000
67 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0x0000000c
68 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x00000010
69
70 #define mmCLK01_CLK0_CLK_PLL_REQ 0x16E37
71 #define mmCLK01_CLK0_CLK0_DFS_CNTL 0x16E64
72 #define mmCLK01_CLK0_CLK1_DFS_CNTL 0x16E67
73 #define mmCLK01_CLK0_CLK2_DFS_CNTL 0x16E6A
74 #define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E6D
75 #define mmCLK01_CLK0_CLK4_DFS_CNTL 0x16E70
76
77 #define CLK0_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffL
78 #define CLK0_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000L
79 #define CLK0_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000L
80 #define CLK0_CLK_PLL_REQ__FbMult_int__SHIFT 0x00000000
81 #define CLK0_CLK_PLL_REQ__PllSpineDiv__SHIFT 0x0000000c
82 #define CLK0_CLK_PLL_REQ__FbMult_frac__SHIFT 0x00000010
83
84 #undef FN
85 #define FN(reg_name, field_name) \
86 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
87
88 #define REG(reg) \
89 (clk_mgr->regs->reg)
90
91 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
92
93 #define BASE(seg) BASE_INNER(seg)
94
95 #define SR(reg_name)\
96 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
97 reg ## reg_name
98
99 #define CLK_SR_DCN32(reg_name)\
100 .reg_name = mm ## reg_name
101
102 static const struct clk_mgr_registers clk_mgr_regs_dcn32 = {
103 CLK_REG_LIST_DCN32()
104 };
105
106 static const struct clk_mgr_shift clk_mgr_shift_dcn32 = {
107 CLK_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
108 };
109
110 static const struct clk_mgr_mask clk_mgr_mask_dcn32 = {
111 CLK_COMMON_MASK_SH_LIST_DCN32(_MASK)
112 };
113
114
115 #define CLK_SR_DCN321(reg_name, block, inst)\
116 .reg_name = mm ## block ## _ ## reg_name
117
118 static const struct clk_mgr_registers clk_mgr_regs_dcn321 = {
119 CLK_REG_LIST_DCN321()
120 };
121
122 static const struct clk_mgr_shift clk_mgr_shift_dcn321 = {
123 CLK_COMMON_MASK_SH_LIST_DCN321(__SHIFT)
124 };
125
126 static const struct clk_mgr_mask clk_mgr_mask_dcn321 = {
127 CLK_COMMON_MASK_SH_LIST_DCN321(_MASK)
128 };
129
130
131 /* Query SMU for all clock states for a particular clock */
dcn32_init_single_clock(struct clk_mgr_internal * clk_mgr,PPCLK_e clk,unsigned int * entry_0,unsigned int * num_levels)132 static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,
133 unsigned int *num_levels)
134 {
135 unsigned int i;
136 char *entry_i = (char *)entry_0;
137
138 uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
139
140 if (ret & (1 << 31))
141 /* fine-grained, only min and max */
142 *num_levels = 2;
143 else
144 /* discrete, a number of fixed states */
145 /* will set num_levels to 0 on failure */
146 *num_levels = ret & 0xFF;
147
148 /* if the initial message failed, num_levels will be 0 */
149 for (i = 0; i < *num_levels; i++) {
150 *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
151 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
152 }
153 }
154
dcn32_build_wm_range_table(struct clk_mgr_internal * clk_mgr)155 static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
156 {
157 DC_FP_START();
158 dcn32_build_wm_range_table_fpu(clk_mgr);
159 DC_FP_END();
160 }
161
dcn32_init_clocks(struct clk_mgr * clk_mgr_base)162 void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
163 {
164 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
165 unsigned int num_levels;
166 struct clk_limit_num_entries *num_entries_per_clk;
167 unsigned int i;
168
169 if (!clk_mgr_base->bw_params)
170 return;
171
172 num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
173
174 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
175 clk_mgr_base->clks.p_state_change_support = true;
176 clk_mgr_base->clks.prev_p_state_change_support = true;
177 clk_mgr_base->clks.fclk_prev_p_state_change_support = true;
178 clk_mgr->smu_present = false;
179 clk_mgr->dpm_present = false;
180
181 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
182 clk_mgr->smu_present = true;
183
184 if (!clk_mgr->smu_present)
185 return;
186
187 dcn30_smu_check_driver_if_version(clk_mgr);
188 dcn30_smu_check_msg_header_version(clk_mgr);
189
190 /* DCFCLK */
191 dcn32_init_single_clock(clk_mgr, PPCLK_DCFCLK,
192 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
193 &num_entries_per_clk->num_dcfclk_levels);
194 clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);
195
196 /* SOCCLK */
197 dcn32_init_single_clock(clk_mgr, PPCLK_SOCCLK,
198 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
199 &num_entries_per_clk->num_socclk_levels);
200 clk_mgr_base->bw_params->dc_mode_limit.socclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_SOCCLK);
201
202 /* DTBCLK */
203 if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch) {
204 dcn32_init_single_clock(clk_mgr, PPCLK_DTBCLK,
205 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
206 &num_entries_per_clk->num_dtbclk_levels);
207 clk_mgr_base->bw_params->dc_mode_limit.dtbclk_mhz =
208 dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DTBCLK);
209 }
210
211 /* DISPCLK */
212 dcn32_init_single_clock(clk_mgr, PPCLK_DISPCLK,
213 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
214 &num_entries_per_clk->num_dispclk_levels);
215 num_levels = num_entries_per_clk->num_dispclk_levels;
216 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK);
217 //HW recommends limit of 1950 MHz in display clock for all DCN3.2.x
218 if (clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz > 1950)
219 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 1950;
220
221 /* DPPCLK */
222 dcn32_init_single_clock(clk_mgr, PPCLK_DPPCLK,
223 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz,
224 &num_entries_per_clk->num_dppclk_levels);
225 num_levels = num_entries_per_clk->num_dppclk_levels;
226 clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DPPCLK);
227 //HW recommends limit of 1950 MHz in display clock for all DCN3.2.x
228 if (clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz > 1950)
229 clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz = 1950;
230
231 if (num_entries_per_clk->num_dcfclk_levels &&
232 num_entries_per_clk->num_dtbclk_levels &&
233 num_entries_per_clk->num_dispclk_levels)
234 clk_mgr->dpm_present = true;
235
236 if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {
237 for (i = 0; i < num_levels; i++)
238 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
239 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))
240 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
241 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);
242 }
243 for (i = 0; i < num_levels; i++)
244 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz > 1950)
245 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz = 1950;
246
247 if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {
248 for (i = 0; i < num_levels; i++)
249 if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
250 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))
251 clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
252 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);
253 }
254
255 for (i = 0; i < num_levels; i++)
256 if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz > 1950)
257 clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz = 1950;
258
259 /* Get UCLK, update bounding box */
260 clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
261
262 /* WM range table */
263 dcn32_build_wm_range_table(clk_mgr);
264 }
265
dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,int ref_dtbclk_khz)266 static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
267 struct dc_state *context,
268 int ref_dtbclk_khz)
269 {
270 struct dccg *dccg = clk_mgr->dccg;
271 uint32_t tg_mask = 0;
272 int i;
273
274 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
275 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
276 struct dtbclk_dto_params dto_params = {0};
277
278 /* use mask to program DTO once per tg */
279 if (pipe_ctx->stream_res.tg &&
280 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {
281 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);
282
283 dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
284 dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
285
286 dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
287 //dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params);
288 }
289 }
290 }
291
292 /* Since DPPCLK request to PMFW needs to be exact (due to DPP DTO programming),
293 * update DPPCLK to be the exact frequency that will be set after the DPPCLK
294 * divider is updated. This will prevent rounding issues that could cause DPP
295 * refclk and DPP DTO to not match up.
296 */
dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal * clk_mgr,struct dc_clocks * new_clocks)297 static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks)
298 {
299 int dpp_divider = 0;
300 int disp_divider = 0;
301
302 if (new_clocks->dppclk_khz) {
303 dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
304 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz;
305 new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
306 }
307 if (new_clocks->dispclk_khz > 0) {
308 disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
309 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dispclk_khz;
310 new_clocks->dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
311 }
312 }
313
dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,bool safe_to_lower)314 void dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
315 struct dc_state *context, bool safe_to_lower)
316 {
317 int i;
318
319 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
320 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
321 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;
322
323 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
324
325 if (context->res_ctx.pipe_ctx[i].plane_res.dpp)
326 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
327 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
328 /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
329 * In this case just continue in loop
330 */
331 continue;
332 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {
333 /* The software state is not valid if dpp resource is NULL and
334 * dppclk_khz > 0.
335 */
336 ASSERT(false);
337 continue;
338 }
339
340 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
341
342 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
343 clk_mgr->dccg->funcs->update_dpp_dto(
344 clk_mgr->dccg, dpp_inst, dppclk_khz);
345 }
346 }
347
dcn32_update_clocks_update_dentist(struct clk_mgr_internal * clk_mgr,struct dc_state * context)348 static void dcn32_update_clocks_update_dentist(
349 struct clk_mgr_internal *clk_mgr,
350 struct dc_state *context)
351 {
352 uint32_t new_disp_divider = 0;
353 uint32_t new_dispclk_wdivider = 0;
354 uint32_t old_dispclk_wdivider = 0;
355 uint32_t i;
356 uint32_t dentist_dispclk_wdivider_readback = 0;
357 struct dc *dc = clk_mgr->base.ctx->dc;
358
359 if (clk_mgr->base.clks.dispclk_khz == 0)
360 return;
361
362 new_disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
363 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
364
365 new_dispclk_wdivider = dentist_get_did_from_divider(new_disp_divider);
366 REG_GET(DENTIST_DISPCLK_CNTL,
367 DENTIST_DISPCLK_WDIVIDER, &old_dispclk_wdivider);
368
369 /* When changing divider to or from 127, some extra programming is required to prevent corruption */
370 if (old_dispclk_wdivider == 127 && new_dispclk_wdivider != 127) {
371 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
372 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
373 uint32_t fifo_level;
374 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
375 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
376 int32_t N;
377 int32_t j;
378
379 if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))
380 continue;
381 /* Virtual encoders don't have this function */
382 if (!stream_enc->funcs->get_fifo_cal_average_level)
383 continue;
384 fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
385 stream_enc);
386 N = fifo_level / 4;
387 dccg->funcs->set_fifo_errdet_ovr_en(
388 dccg,
389 true);
390 for (j = 0; j < N - 4; j++)
391 dccg->funcs->otg_drop_pixel(
392 dccg,
393 pipe_ctx->stream_res.tg->inst);
394 dccg->funcs->set_fifo_errdet_ovr_en(
395 dccg,
396 false);
397 }
398 } else if (new_dispclk_wdivider == 127 && old_dispclk_wdivider != 127) {
399 /* request clock with 126 divider first */
400 uint32_t temp_disp_divider = dentist_get_divider_from_did(126);
401 uint32_t temp_dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / temp_disp_divider;
402
403 if (clk_mgr->smu_present)
404 /*
405 * SMU uses discrete dispclk presets. We applied
406 * the same formula to increase our dppclk_khz
407 * to the next matching discrete value. By
408 * contract, we should use the preset dispclk
409 * floored in Mhz to describe the intended clock.
410 */
411 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK,
412 khz_to_mhz_floor(temp_dispclk_khz));
413
414 if (dc->debug.override_dispclk_programming) {
415 REG_GET(DENTIST_DISPCLK_CNTL,
416 DENTIST_DISPCLK_WDIVIDER, &dentist_dispclk_wdivider_readback);
417
418 if (dentist_dispclk_wdivider_readback != 126) {
419 REG_UPDATE(DENTIST_DISPCLK_CNTL,
420 DENTIST_DISPCLK_WDIVIDER, 126);
421 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);
422 }
423 }
424
425 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
426 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
427 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
428 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
429 uint32_t fifo_level;
430 int32_t N;
431 int32_t j;
432
433 if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER))
434 continue;
435 /* Virtual encoders don't have this function */
436 if (!stream_enc->funcs->get_fifo_cal_average_level)
437 continue;
438 fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
439 stream_enc);
440 N = fifo_level / 4;
441 dccg->funcs->set_fifo_errdet_ovr_en(dccg, true);
442 for (j = 0; j < 12 - N; j++)
443 dccg->funcs->otg_add_pixel(dccg,
444 pipe_ctx->stream_res.tg->inst);
445 dccg->funcs->set_fifo_errdet_ovr_en(dccg, false);
446 }
447 }
448
449 /* do requested DISPCLK updates*/
450 if (clk_mgr->smu_present)
451 /*
452 * SMU uses discrete dispclk presets. We applied
453 * the same formula to increase our dppclk_khz
454 * to the next matching discrete value. By
455 * contract, we should use the preset dispclk
456 * floored in Mhz to describe the intended clock.
457 */
458 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK,
459 khz_to_mhz_floor(clk_mgr->base.clks.dispclk_khz));
460
461 if (dc->debug.override_dispclk_programming) {
462 REG_GET(DENTIST_DISPCLK_CNTL,
463 DENTIST_DISPCLK_WDIVIDER, &dentist_dispclk_wdivider_readback);
464
465 if (dentist_dispclk_wdivider_readback > new_dispclk_wdivider) {
466 REG_UPDATE(DENTIST_DISPCLK_CNTL,
467 DENTIST_DISPCLK_WDIVIDER, new_dispclk_wdivider);
468 REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);
469 }
470 }
471
472 }
473
dcn32_get_dispclk_from_dentist(struct clk_mgr * clk_mgr_base)474 static int dcn32_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base)
475 {
476 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
477 uint32_t dispclk_wdivider;
478 int disp_divider;
479
480 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider);
481 disp_divider = dentist_get_divider_from_did(dispclk_wdivider);
482
483 /* Return DISPCLK freq in Khz */
484 if (disp_divider)
485 return (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
486
487 return 0;
488 }
489
dcn32_check_native_scaling(struct pipe_ctx * pipe)490 static bool dcn32_check_native_scaling(struct pipe_ctx *pipe)
491 {
492 bool is_native_scaling = false;
493 int width = pipe->plane_state->src_rect.width;
494 int height = pipe->plane_state->src_rect.height;
495
496 if (pipe->stream->timing.h_addressable == width &&
497 pipe->stream->timing.v_addressable == height &&
498 pipe->plane_state->dst_rect.width == width &&
499 pipe->plane_state->dst_rect.height == height)
500 is_native_scaling = true;
501
502 return is_native_scaling;
503 }
504
dcn32_auto_dpm_test_log(struct dc_clocks * new_clocks,struct clk_mgr_internal * clk_mgr,struct dc_state * context)505 static void dcn32_auto_dpm_test_log(
506 struct dc_clocks *new_clocks,
507 struct clk_mgr_internal *clk_mgr,
508 struct dc_state *context)
509 {
510 unsigned int dispclk_khz_reg, dppclk_khz_reg, dprefclk_khz_reg, dcfclk_khz_reg, dtbclk_khz_reg,
511 fclk_khz_reg, mall_ss_size_bytes;
512 int dramclk_khz_override, fclk_khz_override, num_fclk_levels;
513
514 struct pipe_ctx *pipe_ctx_list[MAX_PIPES];
515 int active_pipe_count = 0;
516
517 for (int i = 0; i < MAX_PIPES; i++) {
518 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
519
520 if (pipe_ctx->stream && dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {
521 pipe_ctx_list[active_pipe_count] = pipe_ctx;
522 active_pipe_count++;
523 }
524 }
525
526 msleep(5);
527
528 mall_ss_size_bytes = context->bw_ctx.bw.dcn.mall_ss_size_bytes;
529
530 dispclk_khz_reg = REG_READ(CLK1_CLK0_CURRENT_CNT); // DISPCLK
531 dppclk_khz_reg = REG_READ(CLK1_CLK1_CURRENT_CNT); // DPPCLK
532 dprefclk_khz_reg = REG_READ(CLK1_CLK2_CURRENT_CNT); // DPREFCLK
533 dcfclk_khz_reg = REG_READ(CLK1_CLK3_CURRENT_CNT); // DCFCLK
534 dtbclk_khz_reg = REG_READ(CLK1_CLK4_CURRENT_CNT); // DTBCLK
535 fclk_khz_reg = REG_READ(CLK4_CLK0_CURRENT_CNT); // FCLK
536
537 // Overrides for these clocks in case there is no p_state change support
538 dramclk_khz_override = new_clocks->dramclk_khz;
539 fclk_khz_override = new_clocks->fclk_khz;
540
541 num_fclk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_fclk_levels - 1;
542
543 if (!new_clocks->p_state_change_support) {
544 dramclk_khz_override = clk_mgr->base.bw_params->max_memclk_mhz * 1000;
545 }
546 if (!new_clocks->fclk_p_state_change_support) {
547 fclk_khz_override = clk_mgr->base.bw_params->clk_table.entries[num_fclk_levels].fclk_mhz * 1000;
548 }
549
550 ////////////////////////////////////////////////////////////////////////////
551 // IMPORTANT: When adding more clocks to these logs, do NOT put a newline
552 // anywhere other than at the very end of the string.
553 //
554 // Formatting example (make sure to have " - " between each entry):
555 //
556 // AutoDPMTest: clk1:%d - clk2:%d - clk3:%d - clk4:%d\n"
557 ////////////////////////////////////////////////////////////////////////////
558 if (active_pipe_count > 0 &&
559 new_clocks->dramclk_khz > 0 &&
560 new_clocks->fclk_khz > 0 &&
561 new_clocks->dcfclk_khz > 0 &&
562 new_clocks->dppclk_khz > 0) {
563
564 uint32_t pix_clk_list[MAX_PIPES] = {0};
565 int p_state_list[MAX_PIPES] = {0};
566 int disp_src_width_list[MAX_PIPES] = {0};
567 int disp_src_height_list[MAX_PIPES] = {0};
568 uint64_t disp_src_refresh_list[MAX_PIPES] = {0};
569 bool is_scaled_list[MAX_PIPES] = {0};
570
571 for (int i = 0; i < active_pipe_count; i++) {
572 struct pipe_ctx *curr_pipe_ctx = pipe_ctx_list[i];
573 uint64_t refresh_rate;
574
575 pix_clk_list[i] = curr_pipe_ctx->stream->timing.pix_clk_100hz;
576 p_state_list[i] = curr_pipe_ctx->p_state_type;
577
578 refresh_rate = (curr_pipe_ctx->stream->timing.pix_clk_100hz * (uint64_t)100 +
579 curr_pipe_ctx->stream->timing.v_total * (uint64_t)curr_pipe_ctx->stream->timing.h_total - (uint64_t)1);
580 refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.v_total);
581 refresh_rate = div_u64(refresh_rate, curr_pipe_ctx->stream->timing.h_total);
582 disp_src_refresh_list[i] = refresh_rate;
583
584 if (curr_pipe_ctx->plane_state) {
585 is_scaled_list[i] = !(dcn32_check_native_scaling(curr_pipe_ctx));
586 disp_src_width_list[i] = curr_pipe_ctx->plane_state->src_rect.width;
587 disp_src_height_list[i] = curr_pipe_ctx->plane_state->src_rect.height;
588 }
589 }
590
591 DC_LOG_AUTO_DPM_TEST("AutoDPMTest: dramclk:%d - fclk:%d - "
592 "dcfclk:%d - dppclk:%d - dispclk_hw:%d - "
593 "dppclk_hw:%d - dprefclk_hw:%d - dcfclk_hw:%d - "
594 "dtbclk_hw:%d - fclk_hw:%d - pix_clk_0:%d - pix_clk_1:%d - "
595 "pix_clk_2:%d - pix_clk_3:%d - mall_ss_size:%d - p_state_type_0:%d - "
596 "p_state_type_1:%d - p_state_type_2:%d - p_state_type_3:%d - "
597 "pix_width_0:%d - pix_height_0:%d - refresh_rate_0:%lld - is_scaled_0:%d - "
598 "pix_width_1:%d - pix_height_1:%d - refresh_rate_1:%lld - is_scaled_1:%d - "
599 "pix_width_2:%d - pix_height_2:%d - refresh_rate_2:%lld - is_scaled_2:%d - "
600 "pix_width_3:%d - pix_height_3:%d - refresh_rate_3:%lld - is_scaled_3:%d - LOG_END\n",
601 dramclk_khz_override,
602 fclk_khz_override,
603 new_clocks->dcfclk_khz,
604 new_clocks->dppclk_khz,
605 dispclk_khz_reg,
606 dppclk_khz_reg,
607 dprefclk_khz_reg,
608 dcfclk_khz_reg,
609 dtbclk_khz_reg,
610 fclk_khz_reg,
611 pix_clk_list[0], pix_clk_list[1], pix_clk_list[3], pix_clk_list[2],
612 mall_ss_size_bytes,
613 p_state_list[0], p_state_list[1], p_state_list[2], p_state_list[3],
614 disp_src_width_list[0], disp_src_height_list[0], disp_src_refresh_list[0], is_scaled_list[0],
615 disp_src_width_list[1], disp_src_height_list[1], disp_src_refresh_list[1], is_scaled_list[1],
616 disp_src_width_list[2], disp_src_height_list[2], disp_src_refresh_list[2], is_scaled_list[2],
617 disp_src_width_list[3], disp_src_height_list[3], disp_src_refresh_list[3], is_scaled_list[3]);
618 }
619 }
620
dcn32_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)621 static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
622 struct dc_state *context,
623 bool safe_to_lower)
624 {
625 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
626 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
627 struct dc *dc = clk_mgr_base->ctx->dc;
628 int display_count;
629 bool update_dppclk = false;
630 bool update_dispclk = false;
631 bool enter_display_off = false;
632 bool dpp_clock_lowered = false;
633 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
634 bool force_reset = false;
635 bool update_uclk = false, update_fclk = false;
636 bool p_state_change_support;
637 bool fclk_p_state_change_support;
638
639 if (clk_mgr_base->clks.dispclk_khz == 0 ||
640 (dc->debug.force_clock_mode & 0x1)) {
641 /* This is from resume or boot up, if forced_clock cfg option used,
642 * we bypass program dispclk and DPPCLK, but need set them for S3.
643 */
644 force_reset = true;
645
646 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
647
648 /* Force_clock_mode 0x1: force reset the clock even it is the same clock
649 * as long as it is in Passive level.
650 */
651 }
652 display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
653
654 if (display_count == 0)
655 enter_display_off = true;
656
657 if (clk_mgr->smu_present) {
658 if (enter_display_off == safe_to_lower)
659 dcn30_smu_set_num_of_displays(clk_mgr, display_count);
660
661 clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support;
662
663 fclk_p_state_change_support = new_clocks->fclk_p_state_change_support;
664
665 if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) &&
666 !dc->work_arounds.clock_update_disable_mask.fclk) {
667 clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
668
669 /* To enable FCLK P-state switching, send FCLK_PSTATE_SUPPORTED message to PMFW */
670 if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && clk_mgr_base->clks.fclk_p_state_change_support) {
671 /* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
672 dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED);
673 }
674 }
675
676 if (dc->debug.force_min_dcfclk_mhz > 0)
677 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
678 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
679
680 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) &&
681 !dc->work_arounds.clock_update_disable_mask.dcfclk) {
682 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
683 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
684 }
685
686 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) &&
687 !dc->work_arounds.clock_update_disable_mask.dcfclk_ds) {
688 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
689 dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
690 }
691
692 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
693 /* We don't actually care about socclk, don't notify SMU of hard min */
694 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
695
696 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
697 clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways;
698
699 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
700 clk_mgr_base->clks.num_ways < new_clocks->num_ways) {
701 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
702 dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
703 }
704
705 p_state_change_support = new_clocks->p_state_change_support;
706 if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support) &&
707 !dc->work_arounds.clock_update_disable_mask.uclk) {
708 clk_mgr_base->clks.p_state_change_support = p_state_change_support;
709
710 /* to disable P-State switching, set UCLK min = max */
711 if (!clk_mgr_base->clks.p_state_change_support) {
712 if (dc->clk_mgr->dc_mode_softmax_enabled) {
713 /* On DCN32x we will never have the functional UCLK min above the softmax
714 * since we calculate mode support based on softmax being the max UCLK
715 * frequency.
716 */
717 if (dc->debug.disable_dc_mode_overwrite) {
718 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
719 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
720 } else
721 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
722 dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
723 } else {
724 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
725 }
726 }
727 }
728
729 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching)
730 dcn32_smu_wait_for_dmub_ack_mclk(clk_mgr, true);
731 else
732 dcn32_smu_wait_for_dmub_ack_mclk(clk_mgr, false);
733
734 /* Always update saved value, even if new value not set due to P-State switching unsupported. Also check safe_to_lower for FCLK */
735 if (safe_to_lower && (clk_mgr_base->clks.fclk_p_state_change_support != clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
736 update_fclk = true;
737 }
738
739 if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && !clk_mgr_base->clks.fclk_p_state_change_support && update_fclk &&
740 !dc->work_arounds.clock_update_disable_mask.fclk) {
741 /* Handle code for sending a message to PMFW that FCLK P-state change is not supported */
742 dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED);
743 }
744
745 /* Always update saved value, even if new value not set due to P-State switching unsupported */
746 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz) &&
747 !dc->work_arounds.clock_update_disable_mask.uclk) {
748 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
749 update_uclk = true;
750 }
751
752 /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
753 if (clk_mgr_base->clks.p_state_change_support &&
754 (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support) &&
755 !dc->work_arounds.clock_update_disable_mask.uclk) {
756 if (dc->clk_mgr->dc_mode_softmax_enabled && dc->debug.disable_dc_mode_overwrite)
757 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
758 max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)));
759
760 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
761 }
762
763 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
764 clk_mgr_base->clks.num_ways > new_clocks->num_ways) {
765 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
766 dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
767 }
768 }
769
770 dcn32_update_dppclk_dispclk_freq(clk_mgr, new_clocks);
771 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
772 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
773 dpp_clock_lowered = true;
774
775 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
776
777 if (clk_mgr->smu_present && !dpp_clock_lowered)
778 /*
779 * SMU uses discrete dppclk presets. We applied
780 * the same formula to increase our dppclk_khz
781 * to the next matching discrete value. By
782 * contract, we should use the preset dppclk
783 * floored in Mhz to describe the intended clock.
784 */
785 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK,
786 khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz));
787
788 update_dppclk = true;
789 }
790
791 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
792 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
793
794 update_dispclk = true;
795 }
796
797 if (!new_clocks->dtbclk_en) {
798 new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
799 }
800
801 /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
802 if (!dc->debug.disable_dtb_ref_clk_switch &&
803 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
804 /* DCCG requires KHz precision for DTBCLK */
805 clk_mgr_base->clks.ref_dtbclk_khz =
806 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));
807
808 dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz);
809 }
810
811 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
812 if (dpp_clock_lowered) {
813 /* if clock is being lowered, increase DTO before lowering refclk */
814 dcn32_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
815 dcn32_update_clocks_update_dentist(clk_mgr, context);
816 if (clk_mgr->smu_present)
817 /*
818 * SMU uses discrete dppclk presets. We applied
819 * the same formula to increase our dppclk_khz
820 * to the next matching discrete value. By
821 * contract, we should use the preset dppclk
822 * floored in Mhz to describe the intended clock.
823 */
824 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK,
825 khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz));
826 } else {
827 /* if clock is being raised, increase refclk before lowering DTO */
828 if (update_dppclk || update_dispclk)
829 dcn32_update_clocks_update_dentist(clk_mgr, context);
830 /* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures
831 * that we do not lower dto when it is not safe to lower. We do not need to
832 * compare the current and new dppclk before calling this function.
833 */
834 dcn32_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
835 }
836 }
837
838 if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
839 /*update dmcu for wait_loop count*/
840 dmcu->funcs->set_psr_wait_loop(dmcu,
841 clk_mgr_base->clks.dispclk_khz / 1000 / 7);
842
843 if (dc->config.enable_auto_dpm_test_logs) {
844 dcn32_auto_dpm_test_log(new_clocks, clk_mgr, context);
845 }
846 }
847
dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)848 static uint32_t dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
849 {
850 struct fixed31_32 pll_req;
851 uint32_t pll_req_reg = 0;
852
853 /* get FbMult value */
854 if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev))
855 pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
856 else
857 pll_req_reg = REG_READ(CLK1_CLK_PLL_REQ);
858
859 /* set up a fixed-point number
860 * this works because the int part is on the right edge of the register
861 * and the frac part is on the left edge
862 */
863 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
864 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
865
866 /* multiply by REFCLK period */
867 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
868
869 return dc_fixpt_floor(pll_req);
870 }
871
dcn32_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)872 static void dcn32_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
873 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
874 {
875 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
876 uint32_t dprefclk_did = 0;
877 uint32_t dcfclk_did = 0;
878 uint32_t dtbclk_did = 0;
879 uint32_t dispclk_did = 0;
880 uint32_t dppclk_did = 0;
881 uint32_t target_div = 0;
882
883 if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
884 /* DFS Slice 0 is used for DISPCLK */
885 dispclk_did = REG_READ(CLK0_CLK0_DFS_CNTL);
886 /* DFS Slice 1 is used for DPPCLK */
887 dppclk_did = REG_READ(CLK0_CLK1_DFS_CNTL);
888 /* DFS Slice 2 is used for DPREFCLK */
889 dprefclk_did = REG_READ(CLK0_CLK2_DFS_CNTL);
890 /* DFS Slice 3 is used for DCFCLK */
891 dcfclk_did = REG_READ(CLK0_CLK3_DFS_CNTL);
892 /* DFS Slice 4 is used for DTBCLK */
893 dtbclk_did = REG_READ(CLK0_CLK4_DFS_CNTL);
894 } else {
895 /* DFS Slice 0 is used for DISPCLK */
896 dispclk_did = REG_READ(CLK1_CLK0_DFS_CNTL);
897 /* DFS Slice 1 is used for DPPCLK */
898 dppclk_did = REG_READ(CLK1_CLK1_DFS_CNTL);
899 /* DFS Slice 2 is used for DPREFCLK */
900 dprefclk_did = REG_READ(CLK1_CLK2_DFS_CNTL);
901 /* DFS Slice 3 is used for DCFCLK */
902 dcfclk_did = REG_READ(CLK1_CLK3_DFS_CNTL);
903 /* DFS Slice 4 is used for DTBCLK */
904 dtbclk_did = REG_READ(CLK1_CLK4_DFS_CNTL);
905 }
906
907 /* Convert DISPCLK DFS Slice DID to divider*/
908 target_div = dentist_get_divider_from_did(dispclk_did);
909 //Get dispclk in khz
910 regs_and_bypass->dispclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
911 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
912
913 /* Convert DISPCLK DFS Slice DID to divider*/
914 target_div = dentist_get_divider_from_did(dppclk_did);
915 //Get dppclk in khz
916 regs_and_bypass->dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
917 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
918
919 /* Convert DPREFCLK DFS Slice DID to divider*/
920 target_div = dentist_get_divider_from_did(dprefclk_did);
921 //Get dprefclk in khz
922 regs_and_bypass->dprefclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
923 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
924
925 /* Convert DCFCLK DFS Slice DID to divider*/
926 target_div = dentist_get_divider_from_did(dcfclk_did);
927 //Get dcfclk in khz
928 regs_and_bypass->dcfclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
929 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
930
931 /* Convert DTBCLK DFS Slice DID to divider*/
932 target_div = dentist_get_divider_from_did(dtbclk_did);
933 //Get dtbclk in khz
934 regs_and_bypass->dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
935 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
936 }
937
dcn32_clock_read_ss_info(struct clk_mgr_internal * clk_mgr)938 static void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)
939 {
940 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
941 int ss_info_num = bp->funcs->get_ss_entry_number(
942 bp, AS_SIGNAL_TYPE_GPU_PLL);
943
944 if (ss_info_num) {
945 struct spread_spectrum_info info = { { 0 } };
946 enum bp_result result = bp->funcs->get_spread_spectrum_info(
947 bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
948
949 /* SSInfo.spreadSpectrumPercentage !=0 would be sign
950 * that SS is enabled
951 */
952 if (result == BP_RESULT_OK &&
953 info.spread_spectrum_percentage != 0) {
954 clk_mgr->ss_on_dprefclk = true;
955 clk_mgr->dprefclk_ss_divider = info.spread_percentage_divider;
956
957 if (info.type.CENTER_MODE == 0) {
958 /* Currently for DP Reference clock we
959 * need only SS percentage for
960 * downspread
961 */
962 clk_mgr->dprefclk_ss_percentage =
963 info.spread_spectrum_percentage;
964 }
965 }
966 }
967 }
dcn32_notify_wm_ranges(struct clk_mgr * clk_mgr_base)968 static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
969 {
970 unsigned int i;
971 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
972 WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
973
974 if (!clk_mgr->smu_present)
975 return;
976
977 if (!table)
978 return;
979
980 memset(table, 0, sizeof(*table));
981
982 /* collect valid ranges, place in pmfw table */
983 for (i = 0; i < WM_SET_COUNT; i++)
984 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
985 table->Watermarks.WatermarkRow[i].WmSetting = i;
986 table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
987 }
988 dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
989 dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
990 dcn32_smu_transfer_wm_table_dram_2_smu(clk_mgr);
991 }
992
993 /* Set min memclk to minimum, either constrained by the current mode or DPM0 */
dcn32_set_hard_min_memclk(struct clk_mgr * clk_mgr_base,bool current_mode)994 static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
995 {
996 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
997
998 if (!clk_mgr->smu_present)
999 return;
1000
1001 if (current_mode) {
1002 if (clk_mgr_base->clks.p_state_change_support)
1003 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
1004 khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
1005 else
1006 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
1007 clk_mgr_base->bw_params->max_memclk_mhz);
1008 } else {
1009 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
1010 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
1011 }
1012 }
1013
1014 /* Set max memclk to highest DPM value */
dcn32_set_hard_max_memclk(struct clk_mgr * clk_mgr_base)1015 static void dcn32_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
1016 {
1017 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1018
1019 if (!clk_mgr->smu_present)
1020 return;
1021
1022 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->bw_params->max_memclk_mhz);
1023 }
1024
1025 /* Get current memclk states, update bounding box */
dcn32_get_memclk_states_from_smu(struct clk_mgr * clk_mgr_base)1026 static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
1027 {
1028 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1029 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
1030 unsigned int num_levels;
1031
1032 if (!clk_mgr->smu_present)
1033 return;
1034
1035 /* Refresh memclk and fclk states */
1036 dcn32_init_single_clock(clk_mgr, PPCLK_UCLK,
1037 &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
1038 &num_entries_per_clk->num_memclk_levels);
1039 clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_UCLK);
1040 clk_mgr_base->bw_params->dc_mode_softmax_memclk = clk_mgr_base->bw_params->dc_mode_limit.memclk_mhz;
1041
1042 /* memclk must have at least one level */
1043 num_entries_per_clk->num_memclk_levels = num_entries_per_clk->num_memclk_levels ? num_entries_per_clk->num_memclk_levels : 1;
1044
1045 dcn32_init_single_clock(clk_mgr, PPCLK_FCLK,
1046 &clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
1047 &num_entries_per_clk->num_fclk_levels);
1048 clk_mgr_base->bw_params->dc_mode_limit.fclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_FCLK);
1049
1050 if (num_entries_per_clk->num_memclk_levels >= num_entries_per_clk->num_fclk_levels) {
1051 num_levels = num_entries_per_clk->num_memclk_levels;
1052 } else {
1053 num_levels = num_entries_per_clk->num_fclk_levels;
1054 }
1055 clk_mgr_base->bw_params->max_memclk_mhz =
1056 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz;
1057 clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
1058
1059 if (clk_mgr->dpm_present && !num_levels)
1060 clk_mgr->dpm_present = false;
1061
1062 if (!clk_mgr->dpm_present)
1063 dcn32_patch_dpm_table(clk_mgr_base->bw_params);
1064
1065 DC_FP_START();
1066 /* Refresh bounding box */
1067 clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
1068 clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
1069 DC_FP_END();
1070 }
1071
dcn32_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)1072 static bool dcn32_are_clock_states_equal(struct dc_clocks *a,
1073 struct dc_clocks *b)
1074 {
1075 if (a->dispclk_khz != b->dispclk_khz)
1076 return false;
1077 else if (a->dppclk_khz != b->dppclk_khz)
1078 return false;
1079 else if (a->dcfclk_khz != b->dcfclk_khz)
1080 return false;
1081 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
1082 return false;
1083 else if (a->dramclk_khz != b->dramclk_khz)
1084 return false;
1085 else if (a->p_state_change_support != b->p_state_change_support)
1086 return false;
1087 else if (a->fclk_p_state_change_support != b->fclk_p_state_change_support)
1088 return false;
1089
1090 return true;
1091 }
1092
dcn32_enable_pme_wa(struct clk_mgr * clk_mgr_base)1093 static void dcn32_enable_pme_wa(struct clk_mgr *clk_mgr_base)
1094 {
1095 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1096
1097 if (!clk_mgr->smu_present)
1098 return;
1099
1100 dcn32_smu_set_pme_workaround(clk_mgr);
1101 }
1102
dcn32_is_smu_present(struct clk_mgr * clk_mgr_base)1103 static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base)
1104 {
1105 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1106 return clk_mgr->smu_present;
1107 }
1108
dcn32_set_max_memclk(struct clk_mgr * clk_mgr_base,unsigned int memclk_mhz)1109 static void dcn32_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
1110 {
1111 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1112
1113 if (!clk_mgr->smu_present)
1114 return;
1115
1116 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
1117 }
1118
dcn32_set_min_memclk(struct clk_mgr * clk_mgr_base,unsigned int memclk_mhz)1119 static void dcn32_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
1120 {
1121 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1122
1123 if (!clk_mgr->smu_present)
1124 return;
1125
1126 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
1127 }
1128
1129 static struct clk_mgr_funcs dcn32_funcs = {
1130 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
1131 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
1132 .update_clocks = dcn32_update_clocks,
1133 .dump_clk_registers = dcn32_dump_clk_registers,
1134 .init_clocks = dcn32_init_clocks,
1135 .notify_wm_ranges = dcn32_notify_wm_ranges,
1136 .set_hard_min_memclk = dcn32_set_hard_min_memclk,
1137 .set_hard_max_memclk = dcn32_set_hard_max_memclk,
1138 .set_max_memclk = dcn32_set_max_memclk,
1139 .set_min_memclk = dcn32_set_min_memclk,
1140 .get_memclk_states_from_smu = dcn32_get_memclk_states_from_smu,
1141 .are_clock_states_equal = dcn32_are_clock_states_equal,
1142 .enable_pme_wa = dcn32_enable_pme_wa,
1143 .is_smu_present = dcn32_is_smu_present,
1144 .get_dispclk_from_dentist = dcn32_get_dispclk_from_dentist,
1145 };
1146
dcn32_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_internal * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)1147 void dcn32_clk_mgr_construct(
1148 struct dc_context *ctx,
1149 struct clk_mgr_internal *clk_mgr,
1150 struct pp_smu_funcs *pp_smu,
1151 struct dccg *dccg)
1152 {
1153 struct clk_log_info log_info = {0};
1154
1155 clk_mgr->base.ctx = ctx;
1156 clk_mgr->base.funcs = &dcn32_funcs;
1157 if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
1158 clk_mgr->regs = &clk_mgr_regs_dcn321;
1159 clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn321;
1160 clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn321;
1161 } else {
1162 clk_mgr->regs = &clk_mgr_regs_dcn32;
1163 clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn32;
1164 clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn32;
1165 }
1166
1167 clk_mgr->dccg = dccg;
1168 clk_mgr->dfs_bypass_disp_clk = 0;
1169
1170 clk_mgr->dprefclk_ss_percentage = 0;
1171 clk_mgr->dprefclk_ss_divider = 1000;
1172 clk_mgr->ss_on_dprefclk = false;
1173 clk_mgr->dfs_ref_freq_khz = 100000;
1174
1175 /* Changed from DCN3.2_clock_frequency doc to match
1176 * dcn32_dump_clk_registers from 4 * dentist_vco_freq_khz /
1177 * dprefclk DID divider
1178 */
1179 clk_mgr->base.dprefclk_khz = 716666;
1180 if (ctx->dc->debug.disable_dtb_ref_clk_switch) {
1181 //initialize DTB ref clock value if DPM disabled
1182 if (ctx->dce_version == DCN_VERSION_3_21)
1183 clk_mgr->base.clks.ref_dtbclk_khz = 477800;
1184 else
1185 clk_mgr->base.clks.ref_dtbclk_khz = 268750;
1186 }
1187
1188
1189 /* integer part is now VCO frequency in kHz */
1190 clk_mgr->base.dentist_vco_freq_khz = dcn32_get_vco_frequency_from_reg(clk_mgr);
1191
1192 /* in case we don't get a value from the register, use default */
1193 if (clk_mgr->base.dentist_vco_freq_khz == 0)
1194 clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */
1195
1196 dcn32_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
1197
1198 if (ctx->dc->debug.disable_dtb_ref_clk_switch &&
1199 clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) {
1200 clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk;
1201 }
1202
1203 if (clk_mgr->base.boot_snapshot.dprefclk != 0) {
1204 clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;
1205 }
1206 dcn32_clock_read_ss_info(clk_mgr);
1207
1208 clk_mgr->dfs_bypass_enabled = false;
1209
1210 clk_mgr->smu_present = false;
1211
1212 clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
1213 if (!clk_mgr->base.bw_params) {
1214 BREAK_TO_DEBUGGER();
1215 return;
1216 }
1217
1218 /* need physical address of table to give to PMFW */
1219 clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
1220 DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
1221 &clk_mgr->wm_range_table_addr);
1222 if (!clk_mgr->wm_range_table) {
1223 BREAK_TO_DEBUGGER();
1224 return;
1225 }
1226 }
1227
dcn32_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr)1228 void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
1229 {
1230 kfree(clk_mgr->base.bw_params);
1231
1232 if (clk_mgr->wm_range_table)
1233 dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
1234 clk_mgr->wm_range_table);
1235 }
1236
1237