1 /* $OpenBSD: pciide_cmd_reg.h,v 1.12 2024/09/06 10:54:08 jsg Exp $ */ 2 /* $NetBSD: pciide_cmd_reg.h,v 1.9 2000/08/02 20:23:46 bouyer Exp $ */ 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef _DEV_PCI_PCIIDE_CMD_REG_H_ 30 #define _DEV_PCI_PCIIDE_CMD_REG_H_ 31 32 /* 33 * Registers definitions for CMD Technologies's PCI 064x IDE controllers. 34 */ 35 36 /* Interesting revision of the 0646 */ 37 #define CMD0646U2_REV 0x05 38 #define CMD0646U_REV 0x03 39 40 /* Configuration (RO) */ 41 #define CMD_CONF 0x50 42 #define CMD_CONF_REV_MASK 0x03 /* 0640/3/6 only */ 43 #define CMD_CONF_DRV0_INTR 0x04 44 #define CMD_CONF_DEVID 0x18 /* 0640/3/6 only */ 45 #define CMD_CONF_VESAPRT 0x20 /* 0640/3/6 only */ 46 #define CMD_CONF_DSA1 0x40 47 #define CMD_CONF_DSA0 0x80 /* 0640/3/6 only */ 48 49 /* Control register (RW) */ 50 #define CMD_CTRL 0x51 51 #define CMD_CTRL_HR_FIFO 0x01 /* 0640/3/6 only */ 52 #define CMD_CTRL_HW_FIFO 0x02 /* 0640/3/6 only */ 53 #define CMD_CTRL_DEVSEL 0x04 54 #define CMD_CTRL_2PORT 0x08 55 #define CMD_CTRL_PAR 0x10 /* 0640/3/6 only */ 56 #define CMD_CTRL_HW_HLD 0x20 /* 0640/3/6 only */ 57 #define CMD_CTRL_DRV0_RAHEAD 0x40 58 #define CMD_CTRL_DRV1_RAHEAD 0x80 59 60 /* 61 * data read/write timing registers . 0640 uses the same for drive 0 and 1 62 * on the secondary channel 63 */ 64 #define CMD_DATA_TIM(chan, drive) \ 65 (((chan) == 0) ? \ 66 ((drive) == 0) ? 0x54: 0x56 \ 67 : \ 68 ((drive) == 0) ? 0x58 : 0x5b) 69 70 /* secondary channel status and addr timings */ 71 #define CMD_ARTTIM23 0x57 72 #define CMD_ARTTIM23_IRQ 0x10 73 #define CMD_ARTTIM23_RHAEAD(d) ((0x4) << (d)) 74 75 /* DMA master read mode select */ 76 #define CMD_DMA_MODE 0x71 77 #define CMD_DMA_MASK 0x03 78 #define CMD_DMA 0x00 79 #define CMD_DMA_MULTIPLE 0x01 80 #define CMD_DMA_LINE 0x03 81 /* the following bits are only for 0646U/646U2/648/649 */ 82 #define CMD_DMA_IRQ(chan) (0x4 << (chan)) 83 #define CMD_DMA_IRQ_DIS(chan) (0x10 << (chan)) 84 #define CMD_DMA_RST 0x40 85 86 /* the following is only for 0646U/646U2/648/649 */ 87 /* busmaster control/status register */ 88 #define CMD_BICSR 0x79 89 #define CMD_BICSR_80(chan) (0x01 << (chan)) 90 /* Ultra/DMA timings reg */ 91 #define CMD_UDMATIM(channel) (0x73 + (8 * (channel))) 92 #define CMD_UDMATIM_UDMA(drive) (0x01 << (drive)) 93 #define CMD_UDMATIM_UDMA33(drive) (0x04 << (drive)) 94 #define CMD_UDMATIM_TIM_MASK 0x3 95 #define CMD_UDMATIM_TIM_OFF(drive) (4 + ((drive) * 2)) 96 static int8_t cmd0646_9_tim_udma[] = {0x03, 0x02, 0x01, 0x02, 0x01, 0x00}; 97 98 /* 99 * timings values for the 0643/6/8/9 100 * for all dma_mode we have to have 101 * DMA_timings(dma_mode) >= PIO_timings(dma_mode + 2) 102 */ 103 static int8_t cmd0643_9_data_tim_pio[] = {0xA9, 0x57, 0x44, 0x32, 0x3F}; 104 static int8_t cmd0643_9_data_tim_dma[] = {0x87, 0x32, 0x3F}; 105 106 #endif /* !_DEV_PCI_PCIIDE_CMD_REG_H_ */ 107