1 /* $OpenBSD: armreg.h,v 1.40 2025/01/25 12:29:35 kettenis Exp $ */ 2 /*- 3 * Copyright (c) 2013, 2014 Andrew Turner 4 * Copyright (c) 2015 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * This software was developed by Andrew Turner under 8 * sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: head/sys/arm64/include/armreg.h 309248 2016-11-28 14:24:07Z andrew $ 32 */ 33 34 #ifndef _MACHINE_ARMREG_H_ 35 #define _MACHINE_ARMREG_H_ 36 37 #define INSN_SIZE 4 38 39 #define READ_SPECIALREG(reg) \ 40 ({ uint64_t val; \ 41 __asm volatile("mrs %0, " __STRING(reg) : "=&r" (val)); \ 42 val; \ 43 }) 44 #define WRITE_SPECIALREG(reg, val) \ 45 __asm volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)val)) 46 47 /* CCSIDR_EL1 - Current Cache Size ID Register */ 48 #define CCSIDR_SETS_MASK 0x0fffe000 49 #define CCSIDR_SETS_SHIFT 13 50 #define CCSIDR_SETS(reg) \ 51 ((((reg) & CCSIDR_SETS_MASK) >> CCSIDR_SETS_SHIFT) + 1) 52 #define CCSIDR_WAYS_MASK 0x00001ff8 53 #define CCSIDR_WAYS_SHIFT 3 54 #define CCSIDR_WAYS(reg) \ 55 ((((reg) & CCSIDR_WAYS_MASK) >> CCSIDR_WAYS_SHIFT) + 1) 56 #define CCSIDR_LINE_MASK 0x00000007 57 #define CCSIDR_LINE_SIZE(reg) (1 << (((reg) & CCSIDR_LINE_MASK) + 4)) 58 59 #define CCSIDR_CCIDX_SETS_MASK 0x00ffffff00000000ULL 60 #define CCSIDR_CCIDX_SETS_SHIFT 32 61 #define CCSIDR_CCIDX_SETS(reg) \ 62 ((((reg) & CCSIDR_CCIDX_SETS_MASK) >> CCSIDR_CCIDX_SETS_SHIFT) + 1) 63 #define CCSIDR_CCIDX_WAYS_MASK 0x0000000000fffff8ULL 64 #define CCSIDR_CCIDX_WAYS_SHIFT 3 65 #define CCSIDR_CCIDX_WAYS(reg) \ 66 ((((reg) & CCSIDR_CCIDX_WAYS_MASK) >> CCSIDR_CCIDX_WAYS_SHIFT) + 1) 67 #define CCSIDR_CCIDX_LINE_MASK 0x0000000000000007ULL 68 #define CCSIDR_CCIDX_LINE_SIZE(reg) \ 69 (1 << (((reg) & CCSIDR_CCIDX_LINE_MASK) + 4)) 70 71 /* CLIDR_EL1 - Cache Level ID Register */ 72 #define CLIDR_CTYPE_MASK 0x7 73 #define CLIDR_CTYPE_INSN 0x1 74 #define CLIDR_CTYPE_DATA 0x2 75 #define CLIDR_CTYPE_UNIFIED 0x4 76 77 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control Register */ 78 #define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */ 79 #define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */ 80 #define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */ 81 #define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */ 82 #define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/ 83 84 /* CNTKCTL_EL1 - Counter-timer Kernel Control Register */ 85 #define CNTKCTL_EL0VCTEN (1 << 1) /* Allow EL0 virtual counter access */ 86 87 /* CNTV_CTL_EL0 */ 88 #define CNTV_CTL_ENABLE (1 << 0) 89 #define CNTV_CTL_IMASK (1 << 1) 90 #define CNTV_CTL_ISTATUS (1 << 2) 91 92 /* CPACR_EL1 */ 93 #define CPACR_FPEN_MASK (0x3 << 20) 94 #define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */ 95 #define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */ 96 #define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */ 97 #define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */ 98 #define CPACR_TTA (0x1 << 28) 99 100 /* CSSELR_EL1 - Cache Size Selection Register */ 101 #define CSSELR_IND (1 << 0) 102 #define CSSELR_LEVEL_SHIFT 1 103 104 /* CTR_EL0 - Cache Type Register */ 105 #define CTR_DLINE_SHIFT 16 106 #define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) 107 #define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT) 108 #define CTR_IL1P_SHIFT 14 109 #define CTR_IL1P_MASK (0x3 << CTR_IL1P_SHIFT) 110 #define CTR_IL1P_AIVIVT (0x1 << CTR_IL1P_SHIFT) 111 #define CTR_IL1P_VIPT (0x2 << CTR_IL1P_SHIFT) 112 #define CTR_IL1P_PIPT (0x3 << CTR_IL1P_SHIFT) 113 #define CTR_ILINE_SHIFT 0 114 #define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) 115 #define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT) 116 117 /* MPIDR_EL1 - Multiprocessor Affinity Register */ 118 #define MPIDR_AFF3 (0xFFULL << 32) 119 #define MPIDR_AFF2 (0xFFULL << 16) 120 #define MPIDR_AFF1 (0xFFULL << 8) 121 #define MPIDR_AFF0 (0xFFULL << 0) 122 #define MPIDR_AFF (MPIDR_AFF3|MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0) 123 124 /* DCZID_EL0 - Data Cache Zero ID register */ 125 #define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */ 126 #define DCZID_BS_SHIFT 0 127 #define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT) 128 #define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT) 129 130 /* ESR_ELx */ 131 #define ESR_ELx_ISS_MASK 0x00ffffff 132 #define ISS_INSN_FnV (0x01 << 10) 133 #define ISS_INSN_EA (0x01 << 9) 134 #define ISS_INSN_S1PTW (0x01 << 7) 135 #define ISS_INSN_IFSC_MASK (0x1f << 0) 136 #define ISS_DATA_ISV (0x01 << 24) 137 #define ISS_DATA_SAS_MASK (0x03 << 22) 138 #define ISS_DATA_SSE (0x01 << 21) 139 #define ISS_DATA_SRT_MASK (0x1f << 16) 140 #define ISS_DATA_SF (0x01 << 15) 141 #define ISS_DATA_AR (0x01 << 14) 142 #define ISS_DATA_FnV (0x01 << 10) 143 #define ISS_DATA_EA (0x01 << 9) 144 #define ISS_DATA_CM (0x01 << 8) 145 #define ISS_DATA_S1PTW (0x01 << 7) 146 #define ISS_DATA_WnR (0x01 << 6) 147 #define ISS_DATA_DFSC_MASK (0x3f << 0) 148 #define ISS_DATA_DFSC_ASF_L0 (0x00 << 0) 149 #define ISS_DATA_DFSC_ASF_L1 (0x01 << 0) 150 #define ISS_DATA_DFSC_ASF_L2 (0x02 << 0) 151 #define ISS_DATA_DFSC_ASF_L3 (0x03 << 0) 152 #define ISS_DATA_DFSC_TF_L0 (0x04 << 0) 153 #define ISS_DATA_DFSC_TF_L1 (0x05 << 0) 154 #define ISS_DATA_DFSC_TF_L2 (0x06 << 0) 155 #define ISS_DATA_DFSC_TF_L3 (0x07 << 0) 156 #define ISS_DATA_DFSC_AFF_L1 (0x09 << 0) 157 #define ISS_DATA_DFSC_AFF_L2 (0x0a << 0) 158 #define ISS_DATA_DFSC_AFF_L3 (0x0b << 0) 159 #define ISS_DATA_DFSC_PF_L1 (0x0d << 0) 160 #define ISS_DATA_DFSC_PF_L2 (0x0e << 0) 161 #define ISS_DATA_DFSC_PF_L3 (0x0f << 0) 162 #define ISS_DATA_DFSC_EXT (0x10 << 0) 163 #define ISS_DATA_DFSC_EXT_L0 (0x14 << 0) 164 #define ISS_DATA_DFSC_EXT_L1 (0x15 << 0) 165 #define ISS_DATA_DFSC_EXT_L2 (0x16 << 0) 166 #define ISS_DATA_DFSC_EXT_L3 (0x17 << 0) 167 #define ISS_DATA_DFSC_ECC (0x18 << 0) 168 #define ISS_DATA_DFSC_ECC_L0 (0x1c << 0) 169 #define ISS_DATA_DFSC_ECC_L1 (0x1d << 0) 170 #define ISS_DATA_DFSC_ECC_L2 (0x1e << 0) 171 #define ISS_DATA_DFSC_ECC_L3 (0x1f << 0) 172 #define ISS_DATA_DFSC_ALIGN (0x21 << 0) 173 #define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0) 174 #define ISS_MSR_DIR_SHIFT 0 175 #define ISS_MSR_DIR (0x01 << ISS_MSR_DIR_SHIFT) 176 #define ISS_MSR_Rt_SHIFT 5 177 #define ISS_MSR_Rt_MASK (0x1f << ISS_MSR_Rt_SHIFT) 178 #define ISS_MSR_Rt(x) (((x) & ISS_MSR_Rt_MASK) >> ISS_MSR_Rt_SHIFT) 179 #define ISS_MSR_CRm_SHIFT 1 180 #define ISS_MSR_CRm_MASK (0xf << ISS_MSR_CRm_SHIFT) 181 #define ISS_MSR_CRm(x) (((x) & ISS_MSR_CRm_MASK) >> ISS_MSR_CRm_SHIFT) 182 #define ISS_MSR_CRn_SHIFT 10 183 #define ISS_MSR_CRn_MASK (0xf << ISS_MSR_CRn_SHIFT) 184 #define ISS_MSR_CRn(x) (((x) & ISS_MSR_CRn_MASK) >> ISS_MSR_CRn_SHIFT) 185 #define ISS_MSR_OP1_SHIFT 14 186 #define ISS_MSR_OP1_MASK (0x7 << ISS_MSR_OP1_SHIFT) 187 #define ISS_MSR_OP1(x) (((x) & ISS_MSR_OP1_MASK) >> ISS_MSR_OP1_SHIFT) 188 #define ISS_MSR_OP2_SHIFT 17 189 #define ISS_MSR_OP2_MASK (0x7 << ISS_MSR_OP2_SHIFT) 190 #define ISS_MSR_OP2(x) (((x) & ISS_MSR_OP2_MASK) >> ISS_MSR_OP2_SHIFT) 191 #define ISS_MSR_OP0_SHIFT 20 192 #define ISS_MSR_OP0_MASK (0x3 << ISS_MSR_OP0_SHIFT) 193 #define ISS_MSR_OP0(x) (((x) & ISS_MSR_OP0_MASK) >> ISS_MSR_OP0_SHIFT) 194 #define ESR_ELx_IL (0x01 << 25) 195 #define ESR_ELx_EC_SHIFT 26 196 #define ESR_ELx_EC_MASK (0x3f << 26) 197 #define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 198 #define EXCP_UNKNOWN 0x00 /* Unkwn exception */ 199 #define EXCP_FP_SIMD 0x07 /* FP/SIMD trap */ 200 #define EXCP_BRANCH_TGT 0x0d /* Branch target exception */ 201 #define EXCP_ILL_STATE 0x0e /* Illegal execution state */ 202 #define EXCP_SVC 0x15 /* SVC trap */ 203 #define EXCP_MSR 0x18 /* MSR/MRS trap */ 204 #define EXCP_FPAC 0x1c /* Faulting PAC trap */ 205 #define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */ 206 #define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */ 207 #define EXCP_PC_ALIGN 0x22 /* PC alignment fault */ 208 #define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */ 209 #define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */ 210 #define EXCP_SP_ALIGN 0x26 /* SP alignment fault */ 211 #define EXCP_TRAP_FP 0x2c /* Trapped FP exception */ 212 #define EXCP_SERROR 0x2f /* SError interrupt */ 213 #define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */ 214 #define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */ 215 #define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */ 216 #define EXCP_BRK 0x3c /* Breakpoint */ 217 218 /* ICC_CTLR_EL1 */ 219 #define ICC_CTLR_EL1_EOIMODE (1U << 1) 220 #define ICC_CTLR_EL1_PRIBITS_SHIFT 8 221 #define ICC_CTLR_EL1_PRIBITS_MASK (0x7UL << 8) 222 #define ICC_CTLR_EL1_PRIBITS(reg) \ 223 (((reg) & ICC_CTLR_EL1_PRIBITS_MASK) >> ICC_CTLR_EL1_PRIBITS_SHIFT) 224 225 /* ICC_IAR1_EL1 */ 226 #define ICC_IAR1_EL1_SPUR (0x03ff) 227 228 /* ICC_IGRPEN0_EL1 */ 229 #define ICC_IGRPEN0_EL1_EN (1U << 0) 230 231 /* ICC_PMR_EL1 */ 232 #define ICC_PMR_EL1_PRIO_MASK (0xFFUL) 233 234 /* ICC_SGI1R_EL1 */ 235 #define ICC_SGI1R_EL1_TL_MASK 0xffffUL 236 #define ICC_SGI1R_EL1_AFF1_SHIFT 16 237 #define ICC_SGI1R_EL1_SGIID_SHIFT 24 238 #define ICC_SGI1R_EL1_AFF2_SHIFT 32 239 #define ICC_SGI1R_EL1_AFF3_SHIFT 48 240 #define ICC_SGI1R_EL1_SGIID_MASK 0xfUL 241 #define ICC_SGI1R_EL1_IRM (0x1UL << 40) 242 243 /* ICC_SRE_EL1 */ 244 #define ICC_SRE_EL1_SRE (1U << 0) 245 246 /* ICC_SRE_EL2 */ 247 #define ICC_SRE_EL2_SRE (1U << 0) 248 #define ICC_SRE_EL2_EN (1U << 3) 249 250 /* ID_AA64DFR0_EL1 */ 251 #define ID_AA64DFR0_MASK 0x00000000f0f0ffffUL 252 #define ID_AA64DFR0_DEBUG_VER_SHIFT 0 253 #define ID_AA64DFR0_DEBUG_VER_MASK (0xfULL << ID_AA64DFR0_DEBUG_VER_SHIFT) 254 #define ID_AA64DFR0_DEBUG_VER(x) ((x) & ID_AA64DFR0_DEBUG_VER_MASK) 255 #define ID_AA64DFR0_DEBUG_VER_8 (0x6ULL << ID_AA64DFR0_DEBUG_VER_SHIFT) 256 #define ID_AA64DFR0_DEBUG_VER_8_VHE (0x7ULL << ID_AA64DFR0_DEBUG_VER_SHIFT) 257 #define ID_AA64DFR0_TRACE_VER_SHIFT 4 258 #define ID_AA64DFR0_TRACE_VER_MASK (0xfULL << ID_AA64DFR0_TRACE_VER_SHIFT) 259 #define ID_AA64DFR0_TRACE_VER(x) ((x) & ID_AA64DFR0_TRACE_VER_MASK) 260 #define ID_AA64DFR0_TRACE_VER_NONE (0x0ULL << ID_AA64DFR0_TRACE_VER_SHIFT) 261 #define ID_AA64DFR0_TRACE_VER_IMPL (0x1ULL << ID_AA64DFR0_TRACE_VER_SHIFT) 262 #define ID_AA64DFR0_PMU_VER_SHIFT 8 263 #define ID_AA64DFR0_PMU_VER_MASK (0xfULL << ID_AA64DFR0_PMU_VER_SHIFT) 264 #define ID_AA64DFR0_PMU_VER(x) ((x) & ID_AA64DFR0_PMU_VER_MASK) 265 #define ID_AA64DFR0_PMU_VER_NONE (0x0ULL << ID_AA64DFR0_PMU_VER_SHIFT) 266 #define ID_AA64DFR0_PMU_VER_3 (0x1ULL << ID_AA64DFR0_PMU_VER_SHIFT) 267 #define ID_AA64DFR0_PMU_VER_3_1 (0x4ULL << ID_AA64DFR0_PMU_VER_SHIFT) 268 #define ID_AA64DFR0_PMU_VER_IMPL (0xfULL << ID_AA64DFR0_PMU_VER_SHIFT) 269 #define ID_AA64DFR0_BRPS_SHIFT 12 270 #define ID_AA64DFR0_BRPS_MASK (0xfULL << ID_AA64DFR0_BRPS_SHIFT) 271 #define ID_AA64DFR0_BRPS(x) \ 272 ((((x) >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) + 1) 273 #define ID_AA64DFR0_WRPS_SHIFT 20 274 #define ID_AA64DFR0_WRPS_MASK (0xfULL << ID_AA64DFR0_WRPS_SHIFT) 275 #define ID_AA64DFR0_WRPS(x) \ 276 ((((x) >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) + 1) 277 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 278 #define ID_AA64DFR0_CTX_CMPS_MASK (0xfULL << ID_AA64DFR0_CTX_CMPS_SHIFT) 279 #define ID_AA64DFR0_CTX_CMPS(x) \ 280 ((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1) 281 282 /* ID_AA64ISAR0_EL1 */ 283 #define ID_AA64ISAR0_MASK 0xfffffffff0fffff0ULL 284 #define ID_AA64ISAR0_AES_SHIFT 4 285 #define ID_AA64ISAR0_AES_MASK (0xfULL << ID_AA64ISAR0_AES_SHIFT) 286 #define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK) 287 #define ID_AA64ISAR0_AES_NONE (0x0ULL << ID_AA64ISAR0_AES_SHIFT) 288 #define ID_AA64ISAR0_AES_BASE (0x1ULL << ID_AA64ISAR0_AES_SHIFT) 289 #define ID_AA64ISAR0_AES_PMULL (0x2ULL << ID_AA64ISAR0_AES_SHIFT) 290 #define ID_AA64ISAR0_SHA1_SHIFT 8 291 #define ID_AA64ISAR0_SHA1_MASK (0xfULL << ID_AA64ISAR0_SHA1_SHIFT) 292 #define ID_AA64ISAR0_SHA1(x) ((x) & ID_AA64ISAR0_SHA1_MASK) 293 #define ID_AA64ISAR0_SHA1_NONE (0x0ULL << ID_AA64ISAR0_SHA1_SHIFT) 294 #define ID_AA64ISAR0_SHA1_BASE (0x1ULL << ID_AA64ISAR0_SHA1_SHIFT) 295 #define ID_AA64ISAR0_SHA2_SHIFT 12 296 #define ID_AA64ISAR0_SHA2_MASK (0xfULL << ID_AA64ISAR0_SHA2_SHIFT) 297 #define ID_AA64ISAR0_SHA2(x) ((x) & ID_AA64ISAR0_SHA2_MASK) 298 #define ID_AA64ISAR0_SHA2_NONE (0x0ULL << ID_AA64ISAR0_SHA2_SHIFT) 299 #define ID_AA64ISAR0_SHA2_BASE (0x1ULL << ID_AA64ISAR0_SHA2_SHIFT) 300 #define ID_AA64ISAR0_SHA2_512 (0x2ULL << ID_AA64ISAR0_SHA2_SHIFT) 301 #define ID_AA64ISAR0_CRC32_SHIFT 16 302 #define ID_AA64ISAR0_CRC32_MASK (0xfULL << ID_AA64ISAR0_CRC32_SHIFT) 303 #define ID_AA64ISAR0_CRC32(x) ((x) & ID_AA64ISAR0_CRC32_MASK) 304 #define ID_AA64ISAR0_CRC32_NONE (0x0ULL << ID_AA64ISAR0_CRC32_SHIFT) 305 #define ID_AA64ISAR0_CRC32_BASE (0x1ULL << ID_AA64ISAR0_CRC32_SHIFT) 306 #define ID_AA64ISAR0_ATOMIC_SHIFT 20 307 #define ID_AA64ISAR0_ATOMIC_MASK (0xfULL << ID_AA64ISAR0_ATOMIC_SHIFT) 308 #define ID_AA64ISAR0_ATOMIC(x) ((x) & ID_AA64ISAR0_ATOMIC_MASK) 309 #define ID_AA64ISAR0_ATOMIC_NONE (0x0ULL << ID_AA64ISAR0_ATOMIC_SHIFT) 310 #define ID_AA64ISAR0_ATOMIC_IMPL (0x2ULL << ID_AA64ISAR0_ATOMIC_SHIFT) 311 #define ID_AA64ISAR0_RDM_SHIFT 28 312 #define ID_AA64ISAR0_RDM_MASK (0xfULL << ID_AA64ISAR0_RDM_SHIFT) 313 #define ID_AA64ISAR0_RDM(x) ((x) & ID_AA64ISAR0_RDM_MASK) 314 #define ID_AA64ISAR0_RDM_NONE (0x0ULL << ID_AA64ISAR0_RDM_SHIFT) 315 #define ID_AA64ISAR0_RDM_IMPL (0x1ULL << ID_AA64ISAR0_RDM_SHIFT) 316 #define ID_AA64ISAR0_SHA3_SHIFT 32 317 #define ID_AA64ISAR0_SHA3_MASK (0xfULL << ID_AA64ISAR0_SHA3_SHIFT) 318 #define ID_AA64ISAR0_SHA3(x) ((x) & ID_AA64ISAR0_SHA3_MASK) 319 #define ID_AA64ISAR0_SHA3_NONE (0x0ULL << ID_AA64ISAR0_SHA3_SHIFT) 320 #define ID_AA64ISAR0_SHA3_IMPL (0x1ULL << ID_AA64ISAR0_SHA3_SHIFT) 321 #define ID_AA64ISAR0_SM3_SHIFT 36 322 #define ID_AA64ISAR0_SM3_MASK (0xfULL << ID_AA64ISAR0_SM3_SHIFT) 323 #define ID_AA64ISAR0_SM3(x) ((x) & ID_AA64ISAR0_SM3_MASK) 324 #define ID_AA64ISAR0_SM3_NONE (0x0ULL << ID_AA64ISAR0_SM3_SHIFT) 325 #define ID_AA64ISAR0_SM3_IMPL (0x1ULL << ID_AA64ISAR0_SM3_SHIFT) 326 #define ID_AA64ISAR0_SM4_SHIFT 40 327 #define ID_AA64ISAR0_SM4_MASK (0xfULL << ID_AA64ISAR0_SM4_SHIFT) 328 #define ID_AA64ISAR0_SM4(x) ((x) & ID_AA64ISAR0_SM4_MASK) 329 #define ID_AA64ISAR0_SM4_NONE (0x0ULL << ID_AA64ISAR0_SM4_SHIFT) 330 #define ID_AA64ISAR0_SM4_IMPL (0x1ULL << ID_AA64ISAR0_SM4_SHIFT) 331 #define ID_AA64ISAR0_DP_SHIFT 44 332 #define ID_AA64ISAR0_DP_MASK (0xfULL << ID_AA64ISAR0_DP_SHIFT) 333 #define ID_AA64ISAR0_DP(x) ((x) & ID_AA64ISAR0_DP_MASK) 334 #define ID_AA64ISAR0_DP_NONE (0x0ULL << ID_AA64ISAR0_DP_SHIFT) 335 #define ID_AA64ISAR0_DP_IMPL (0x1ULL << ID_AA64ISAR0_DP_SHIFT) 336 #define ID_AA64ISAR0_FHM_SHIFT 48 337 #define ID_AA64ISAR0_FHM_MASK (0xfULL << ID_AA64ISAR0_FHM_SHIFT) 338 #define ID_AA64ISAR0_FHM(x) ((x) & ID_AA64ISAR0_FHM_MASK) 339 #define ID_AA64ISAR0_FHM_NONE (0x0ULL << ID_AA64ISAR0_FHM_SHIFT) 340 #define ID_AA64ISAR0_FHM_IMPL (0x1ULL << ID_AA64ISAR0_FHM_SHIFT) 341 #define ID_AA64ISAR0_TS_SHIFT 52 342 #define ID_AA64ISAR0_TS_MASK (0xfULL << ID_AA64ISAR0_TS_SHIFT) 343 #define ID_AA64ISAR0_TS(x) ((x) & ID_AA64ISAR0_TS_MASK) 344 #define ID_AA64ISAR0_TS_NONE (0x0ULL << ID_AA64ISAR0_TS_SHIFT) 345 #define ID_AA64ISAR0_TS_BASE (0x1ULL << ID_AA64ISAR0_TS_SHIFT) 346 #define ID_AA64ISAR0_TS_AXFLAG (0x2ULL << ID_AA64ISAR0_TS_SHIFT) 347 #define ID_AA64ISAR0_TLB_SHIFT 56 348 #define ID_AA64ISAR0_TLB_MASK (0xfULL << ID_AA64ISAR0_TLB_SHIFT) 349 #define ID_AA64ISAR0_TLB(x) ((x) & ID_AA64ISAR0_TLB_MASK) 350 #define ID_AA64ISAR0_TLB_NONE (0x0ULL << ID_AA64ISAR0_TLB_SHIFT) 351 #define ID_AA64ISAR0_TLB_IOS (0x1ULL << ID_AA64ISAR0_TLB_SHIFT) 352 #define ID_AA64ISAR0_TLB_IRANGE (0x2ULL << ID_AA64ISAR0_TLB_SHIFT) 353 #define ID_AA64ISAR0_RNDR_SHIFT 60 354 #define ID_AA64ISAR0_RNDR_MASK (0xfULL << ID_AA64ISAR0_RNDR_SHIFT) 355 #define ID_AA64ISAR0_RNDR(x) ((x) & ID_AA64ISAR0_RNDR_MASK) 356 #define ID_AA64ISAR0_RNDR_NONE (0x0ULL << ID_AA64ISAR0_RNDR_SHIFT) 357 #define ID_AA64ISAR0_RNDR_IMPL (0x1ULL << ID_AA64ISAR0_RNDR_SHIFT) 358 359 /* ID_AA64ISAR1_EL1 */ 360 #define ID_AA64ISAR1_MASK 0xffffffffffffffffULL 361 #define ID_AA64ISAR1_DPB_SHIFT 0 362 #define ID_AA64ISAR1_DPB_MASK (0xfULL << ID_AA64ISAR1_DPB_SHIFT) 363 #define ID_AA64ISAR1_DPB(x) ((x) & ID_AA64ISAR1_DPB_MASK) 364 #define ID_AA64ISAR1_DPB_NONE (0x0ULL << ID_AA64ISAR1_DPB_SHIFT) 365 #define ID_AA64ISAR1_DPB_IMPL (0x1ULL << ID_AA64ISAR1_DPB_SHIFT) 366 #define ID_AA64ISAR1_DPB_DCCVADP (0x2ULL << ID_AA64ISAR1_DPB_SHIFT) 367 #define ID_AA64ISAR1_APA_SHIFT 4 368 #define ID_AA64ISAR1_APA_MASK (0xfULL << ID_AA64ISAR1_APA_SHIFT) 369 #define ID_AA64ISAR1_APA(x) ((x) & ID_AA64ISAR1_APA_MASK) 370 #define ID_AA64ISAR1_APA_NONE (0x0ULL << ID_AA64ISAR1_APA_SHIFT) 371 #define ID_AA64ISAR1_APA_PAC (0x1ULL << ID_AA64ISAR1_APA_SHIFT) 372 #define ID_AA64ISAR1_APA_EPAC (0x2ULL << ID_AA64ISAR1_APA_SHIFT) 373 #define ID_AA64ISAR1_APA_EPAC2 (0x3ULL << ID_AA64ISAR1_APA_SHIFT) 374 #define ID_AA64ISAR1_APA_FPAC (0x4ULL << ID_AA64ISAR1_APA_SHIFT) 375 #define ID_AA64ISAR1_APA_FPAC_COMBINED (0x5ULL << ID_AA64ISAR1_APA_SHIFT) 376 #define ID_AA64ISAR1_API_SHIFT 8 377 #define ID_AA64ISAR1_API_MASK (0xfULL << ID_AA64ISAR1_API_SHIFT) 378 #define ID_AA64ISAR1_API(x) ((x) & ID_AA64ISAR1_API_MASK) 379 #define ID_AA64ISAR1_API_NONE (0x0ULL << ID_AA64ISAR1_API_SHIFT) 380 #define ID_AA64ISAR1_API_PAC (0x1ULL << ID_AA64ISAR1_API_SHIFT) 381 #define ID_AA64ISAR1_API_EPAC (0x2ULL << ID_AA64ISAR1_API_SHIFT) 382 #define ID_AA64ISAR1_API_EPAC2 (0x3ULL << ID_AA64ISAR1_API_SHIFT) 383 #define ID_AA64ISAR1_API_FPAC (0x4ULL << ID_AA64ISAR1_API_SHIFT) 384 #define ID_AA64ISAR1_API_FPAC_COMBINED (0x5ULL << ID_AA64ISAR1_API_SHIFT) 385 #define ID_AA64ISAR1_JSCVT_SHIFT 12 386 #define ID_AA64ISAR1_JSCVT_MASK (0xfULL << ID_AA64ISAR1_JSCVT_SHIFT) 387 #define ID_AA64ISAR1_JSCVT(x) ((x) & ID_AA64ISAR1_JSCVT_MASK) 388 #define ID_AA64ISAR1_JSCVT_NONE (0x0ULL << ID_AA64ISAR1_JSCVT_SHIFT) 389 #define ID_AA64ISAR1_JSCVT_IMPL (0x1ULL << ID_AA64ISAR1_JSCVT_SHIFT) 390 #define ID_AA64ISAR1_FCMA_SHIFT 16 391 #define ID_AA64ISAR1_FCMA_MASK (0xfULL << ID_AA64ISAR1_FCMA_SHIFT) 392 #define ID_AA64ISAR1_FCMA(x) ((x) & ID_AA64ISAR1_FCMA_MASK) 393 #define ID_AA64ISAR1_FCMA_NONE (0x0ULL << ID_AA64ISAR1_FCMA_SHIFT) 394 #define ID_AA64ISAR1_FCMA_IMPL (0x1ULL << ID_AA64ISAR1_FCMA_SHIFT) 395 #define ID_AA64ISAR1_LRCPC_SHIFT 20 396 #define ID_AA64ISAR1_LRCPC_MASK (0xfULL << ID_AA64ISAR1_LRCPC_SHIFT) 397 #define ID_AA64ISAR1_LRCPC(x) ((x) & ID_AA64ISAR1_LRCPC_MASK) 398 #define ID_AA64ISAR1_LRCPC_NONE (0x0ULL << ID_AA64ISAR1_LRCPC_SHIFT) 399 #define ID_AA64ISAR1_LRCPC_BASE (0x1ULL << ID_AA64ISAR1_LRCPC_SHIFT) 400 #define ID_AA64ISAR1_LRCPC_LDAPUR (0x2ULL << ID_AA64ISAR1_LRCPC_SHIFT) 401 #define ID_AA64ISAR1_GPA_SHIFT 24 402 #define ID_AA64ISAR1_GPA_MASK (0xfULL << ID_AA64ISAR1_GPA_SHIFT) 403 #define ID_AA64ISAR1_GPA(x) ((x) & ID_AA64ISAR1_GPA_MASK) 404 #define ID_AA64ISAR1_GPA_NONE (0x0ULL << ID_AA64ISAR1_GPA_SHIFT) 405 #define ID_AA64ISAR1_GPA_IMPL (0x1ULL << ID_AA64ISAR1_GPA_SHIFT) 406 #define ID_AA64ISAR1_GPI_SHIFT 28 407 #define ID_AA64ISAR1_GPI_MASK (0xfULL << ID_AA64ISAR1_GPI_SHIFT) 408 #define ID_AA64ISAR1_GPI(x) ((x) & ID_AA64ISAR1_GPI_MASK) 409 #define ID_AA64ISAR1_GPI_NONE (0x0ULL << ID_AA64ISAR1_GPI_SHIFT) 410 #define ID_AA64ISAR1_GPI_IMPL (0x1ULL << ID_AA64ISAR1_GPI_SHIFT) 411 #define ID_AA64ISAR1_FRINTTS_SHIFT 32 412 #define ID_AA64ISAR1_FRINTTS_MASK (0xfULL << ID_AA64ISAR1_FRINTTS_SHIFT) 413 #define ID_AA64ISAR1_FRINTTS(x) ((x) & ID_AA64ISAR1_FRINTTS_MASK) 414 #define ID_AA64ISAR1_FRINTTS_NONE (0x0ULL << ID_AA64ISAR1_FRINTTS_SHIFT) 415 #define ID_AA64ISAR1_FRINTTS_IMPL (0x1ULL << ID_AA64ISAR1_FRINTTS_SHIFT) 416 #define ID_AA64ISAR1_SB_SHIFT 36 417 #define ID_AA64ISAR1_SB_MASK (0xfULL << ID_AA64ISAR1_SB_SHIFT) 418 #define ID_AA64ISAR1_SB(x) ((x) & ID_AA64ISAR1_SB_MASK) 419 #define ID_AA64ISAR1_SB_NONE (0x0ULL << ID_AA64ISAR1_SB_SHIFT) 420 #define ID_AA64ISAR1_SB_IMPL (0x1ULL << ID_AA64ISAR1_SB_SHIFT) 421 #define ID_AA64ISAR1_SPECRES_SHIFT 40 422 #define ID_AA64ISAR1_SPECRES_MASK (0xfULL << ID_AA64ISAR1_SPECRES_SHIFT) 423 #define ID_AA64ISAR1_SPECRES(x) ((x) & ID_AA64ISAR1_SPECRES_MASK) 424 #define ID_AA64ISAR1_SPECRES_NONE (0x0ULL << ID_AA64ISAR1_SPECRES_SHIFT) 425 #define ID_AA64ISAR1_SPECRES_IMPL (0x1ULL << ID_AA64ISAR1_SPECRES_SHIFT) 426 #define ID_AA64ISAR1_BF16_SHIFT 44 427 #define ID_AA64ISAR1_BF16_MASK (0xfULL << ID_AA64ISAR1_BF16_SHIFT) 428 #define ID_AA64ISAR1_BF16(x) ((x) & ID_AA64ISAR1_BF16_MASK) 429 #define ID_AA64ISAR1_BF16_NONE (0x0ULL << ID_AA64ISAR1_BF16_SHIFT) 430 #define ID_AA64ISAR1_BF16_BASE (0x1ULL << ID_AA64ISAR1_BF16_SHIFT) 431 #define ID_AA64ISAR1_BF16_EBF (0x2ULL << ID_AA64ISAR1_BF16_SHIFT) 432 #define ID_AA64ISAR1_DGH_SHIFT 48 433 #define ID_AA64ISAR1_DGH_MASK (0xfULL << ID_AA64ISAR1_DGH_SHIFT) 434 #define ID_AA64ISAR1_DGH(x) ((x) & ID_AA64ISAR1_DGH_MASK) 435 #define ID_AA64ISAR1_DGH_NONE (0x0ULL << ID_AA64ISAR1_DGH_SHIFT) 436 #define ID_AA64ISAR1_DGH_IMPL (0x1ULL << ID_AA64ISAR1_DGH_SHIFT) 437 #define ID_AA64ISAR1_I8MM_SHIFT 52 438 #define ID_AA64ISAR1_I8MM_MASK (0xfULL << ID_AA64ISAR1_I8MM_SHIFT) 439 #define ID_AA64ISAR1_I8MM(x) ((x) & ID_AA64ISAR1_I8MM_MASK) 440 #define ID_AA64ISAR1_I8MM_NONE (0x0ULL << ID_AA64ISAR1_I8MM_SHIFT) 441 #define ID_AA64ISAR1_I8MM_IMPL (0x1ULL << ID_AA64ISAR1_I8MM_SHIFT) 442 #define ID_AA64ISAR1_XS_SHIFT 56 443 #define ID_AA64ISAR1_XS_MASK (0xfULL << ID_AA64ISAR1_XS_SHIFT) 444 #define ID_AA64ISAR1_XS(x) ((x) & ID_AA64ISAR1_XS_MASK) 445 #define ID_AA64ISAR1_XS_NONE (0x0ULL << ID_AA64ISAR1_XS_SHIFT) 446 #define ID_AA64ISAR1_XS_IMPL (0x1ULL << ID_AA64ISAR1_XS_SHIFT) 447 #define ID_AA64ISAR1_LS64_SHIFT 60 448 #define ID_AA64ISAR1_LS64_MASK (0xfULL << ID_AA64ISAR1_LS64_SHIFT) 449 #define ID_AA64ISAR1_LS64(x) ((x) & ID_AA64ISAR1_LS64_MASK) 450 #define ID_AA64ISAR1_LS64_NONE (0x0ULL << ID_AA64ISAR1_LS64_SHIFT) 451 #define ID_AA64ISAR1_LS64_BASE (0x1ULL << ID_AA64ISAR1_LS64_SHIFT) 452 #define ID_AA64ISAR1_LS64_V (0x2ULL << ID_AA64ISAR1_LS64_SHIFT) 453 #define ID_AA64ISAR1_LS64_ACCDATA (0x3ULL << ID_AA64ISAR1_LS64_SHIFT) 454 455 /* ID_AA64ISAR2_EL1 */ 456 #define ID_AA64ISAR2_MASK 0x00ff0000f0ff00ffULL 457 #define ID_AA64ISAR2_WFXT_SHIFT 0 458 #define ID_AA64ISAR2_WFXT_MASK (0xfULL << ID_AA64ISAR2_WFXT_SHIFT) 459 #define ID_AA64ISAR2_WFXT(x) ((x) & ID_AA64ISAR2_WFXT_MASK) 460 #define ID_AA64ISAR2_WFXT_NONE (0x0ULL << ID_AA64ISAR2_WFXT_SHIFT) 461 #define ID_AA64ISAR2_WFXT_IMPL (0x2ULL << ID_AA64ISAR2_WFXT_SHIFT) 462 #define ID_AA64ISAR2_RPRES_SHIFT 4 463 #define ID_AA64ISAR2_RPRES_MASK (0xfULL << ID_AA64ISAR2_RPRES_SHIFT) 464 #define ID_AA64ISAR2_RPRES(x) ((x) & ID_AA64ISAR2_RPRES_MASK) 465 #define ID_AA64ISAR2_RPRES_NONE (0x0ULL << ID_AA64ISAR2_RPRES_SHIFT) 466 #define ID_AA64ISAR2_RPRES_IMPL (0x1ULL << ID_AA64ISAR2_RPRES_SHIFT) 467 #define ID_AA64ISAR2_GPA3_SHIFT 8 468 #define ID_AA64ISAR2_GPA3_WIDTH 4 469 #define ID_AA64ISAR2_GPA3_MASK (0xfULL << ID_AA64ISAR2_GPA3_SHIFT) 470 #define ID_AA64ISAR2_GPA3(x) ((x) & ID_AA64ISAR2_GPA3_MASK) 471 #define ID_AA64ISAR2_GPA3_NONE (0x0ULL << ID_AA64ISAR2_GPA3_SHIFT) 472 #define ID_AA64ISAR2_GPA3_IMPL (0x1ULL << ID_AA64ISAR2_GPA3_SHIFT) 473 #define ID_AA64ISAR2_APA3_SHIFT 12 474 #define ID_AA64ISAR2_APA3_WIDTH 4 475 #define ID_AA64ISAR2_APA3_MASK (0xfULL << ID_AA64ISAR2_APA3_SHIFT) 476 #define ID_AA64ISAR2_APA3(x) ((x) & ID_AA64ISAR2_APA3_MASK) 477 #define ID_AA64ISAR2_APA3_NONE (0x0ULL << ID_AA64ISAR2_APA3_SHIFT) 478 #define ID_AA64ISAR2_APA3_PAC (0x1ULL << ID_AA64ISAR2_APA3_SHIFT) 479 #define ID_AA64ISAR2_APA3_EPAC (0x2ULL << ID_AA64ISAR2_APA3_SHIFT) 480 #define ID_AA64ISAR2_APA3_EPAC2 (0x3ULL << ID_AA64ISAR2_APA3_SHIFT) 481 #define ID_AA64ISAR2_APA3_FPAC (0x4ULL << ID_AA64ISAR2_APA3_SHIFT) 482 #define ID_AA64ISAR2_APA3_FPAC_COMBINED (0x5ULL << ID_AA64ISAR2_APA3_SHIFT) 483 #define ID_AA64ISAR2_MOPS_SHIFT 16 484 #define ID_AA64ISAR2_MOPS_MASK (0xfULL << ID_AA64ISAR2_MOPS_SHIFT) 485 #define ID_AA64ISAR2_MOPS(x) ((x) & ID_AA64ISAR2_MOPS_MASK) 486 #define ID_AA64ISAR2_MOPS_NONE (0x0ULL << ID_AA64ISAR2_MOPS_SHIFT) 487 #define ID_AA64ISAR2_MOPS_IMPL (0x1ULL << ID_AA64ISAR2_MOPS_SHIFT) 488 #define ID_AA64ISAR2_BC_SHIFT 20 489 #define ID_AA64ISAR2_BC_MASK (0xfULL << ID_AA64ISAR2_BC_SHIFT) 490 #define ID_AA64ISAR2_BC(x) ((x) & ID_AA64ISAR2_BC_MASK) 491 #define ID_AA64ISAR2_BC_NONE (0x0ULL << ID_AA64ISAR2_BC_SHIFT) 492 #define ID_AA64ISAR2_BC_IMPL (0x1ULL << ID_AA64ISAR2_BC_SHIFT) 493 #define ID_AA64ISAR2_CLRBHB_SHIFT 28 494 #define ID_AA64ISAR2_CLRBHB_MASK (0xfULL << ID_AA64ISAR2_CLRBHB_SHIFT) 495 #define ID_AA64ISAR2_CLRBHB(x) ((x) & ID_AA64ISAR2_CLRBHB_MASK) 496 #define ID_AA64ISAR2_CLRBHB_NONE (0x0ULL << ID_AA64ISAR2_CLRBHB_SHIFT) 497 #define ID_AA64ISAR2_CLRBHB_IMPL (0x1ULL << ID_AA64ISAR2_CLRBHB_SHIFT) 498 #define ID_AA64ISAR2_RPRFM_SHIFT 48 499 #define ID_AA64ISAR2_RPRFM_MASK (0xfULL << ID_AA64ISAR2_RPRFM_SHIFT) 500 #define ID_AA64ISAR2_RPRFM(x) ((x) & ID_AA64ISAR2_RPRFM_MASK) 501 #define ID_AA64ISAR2_RPRFM_NONE (0x0ULL << ID_AA64ISAR2_RPRFM_SHIFT) 502 #define ID_AA64ISAR2_RPRFM_IMPL (0x1ULL << ID_AA64ISAR2_RPRFM_SHIFT) 503 #define ID_AA64ISAR2_CSSC_SHIFT 52 504 #define ID_AA64ISAR2_CSSC_MASK (0xfULL << ID_AA64ISAR2_CSSC_SHIFT) 505 #define ID_AA64ISAR2_CSSC(x) ((x) & ID_AA64ISAR2_CSSC_MASK) 506 #define ID_AA64ISAR2_CSSC_NONE (0x0ULL << ID_AA64ISAR2_CSSC_SHIFT) 507 #define ID_AA64ISAR2_CSSC_IMPL (0x1ULL << ID_AA64ISAR2_CSSC_SHIFT) 508 509 /* ID_AA64MMFR0_EL1 */ 510 #define ID_AA64MMFR0_MASK 0xf0000000ffffffffULL 511 #define ID_AA64MMFR0_PA_RANGE_SHIFT 0 512 #define ID_AA64MMFR0_PA_RANGE_MASK (0xfULL << ID_AA64MMFR0_PA_RANGE_SHIFT) 513 #define ID_AA64MMFR0_PA_RANGE(x) ((x) & ID_AA64MMFR0_PA_RANGE_MASK) 514 #define ID_AA64MMFR0_PA_RANGE_4G (0x0ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) 515 #define ID_AA64MMFR0_PA_RANGE_64G (0x1ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) 516 #define ID_AA64MMFR0_PA_RANGE_1T (0x2ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) 517 #define ID_AA64MMFR0_PA_RANGE_4T (0x3ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) 518 #define ID_AA64MMFR0_PA_RANGE_16T (0x4ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) 519 #define ID_AA64MMFR0_PA_RANGE_256T (0x5ULL << ID_AA64MMFR0_PA_RANGE_SHIFT) 520 #define ID_AA64MMFR0_ASID_BITS_SHIFT 4 521 #define ID_AA64MMFR0_ASID_BITS_MASK (0xfULL << ID_AA64MMFR0_ASID_BITS_SHIFT) 522 #define ID_AA64MMFR0_ASID_BITS(x) ((x) & ID_AA64MMFR0_ASID_BITS_MASK) 523 #define ID_AA64MMFR0_ASID_BITS_8 (0x0ULL << ID_AA64MMFR0_ASID_BITS_SHIFT) 524 #define ID_AA64MMFR0_ASID_BITS_16 (0x2ULL << ID_AA64MMFR0_ASID_BITS_SHIFT) 525 #define ID_AA64MMFR0_BIGEND_SHIFT 8 526 #define ID_AA64MMFR0_BIGEND_MASK (0xfULL << ID_AA64MMFR0_BIGEND_SHIFT) 527 #define ID_AA64MMFR0_BIGEND(x) ((x) & ID_AA64MMFR0_BIGEND_MASK) 528 #define ID_AA64MMFR0_BIGEND_FIXED (0x0ULL << ID_AA64MMFR0_BIGEND_SHIFT) 529 #define ID_AA64MMFR0_BIGEND_MIXED (0x1ULL << ID_AA64MMFR0_BIGEND_SHIFT) 530 #define ID_AA64MMFR0_S_NS_MEM_SHIFT 12 531 #define ID_AA64MMFR0_S_NS_MEM_MASK (0xfULL << ID_AA64MMFR0_S_NS_MEM_SHIFT) 532 #define ID_AA64MMFR0_S_NS_MEM(x) ((x) & ID_AA64MMFR0_S_NS_MEM_MASK) 533 #define ID_AA64MMFR0_S_NS_MEM_NONE (0x0ULL << ID_AA64MMFR0_S_NS_MEM_SHIFT) 534 #define ID_AA64MMFR0_S_NS_MEM_DISTINCT (0x1ULL << ID_AA64MMFR0_S_NS_MEM_SHIFT) 535 #define ID_AA64MMFR0_BIGEND_EL0_SHIFT 16 536 #define ID_AA64MMFR0_BIGEND_EL0_MASK (0xfULL << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 537 #define ID_AA64MMFR0_BIGEND_EL0(x) ((x) & ID_AA64MMFR0_BIGEND_EL0_MASK) 538 #define ID_AA64MMFR0_BIGEND_EL0_FIXED (0x0ULL << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 539 #define ID_AA64MMFR0_BIGEND_EL0_MIXED (0x1ULL << ID_AA64MMFR0_BIGEND_EL0_SHIFT) 540 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 541 #define ID_AA64MMFR0_TGRAN16_MASK (0xfULL << ID_AA64MMFR0_TGRAN16_SHIFT) 542 #define ID_AA64MMFR0_TGRAN16(x) ((x) & ID_AA64MMFR0_TGRAN16_MASK) 543 #define ID_AA64MMFR0_TGRAN16_NONE (0x0ULL << ID_AA64MMFR0_TGRAN16_SHIFT) 544 #define ID_AA64MMFR0_TGRAN16_IMPL (0x1ULL << ID_AA64MMFR0_TGRAN16_SHIFT) 545 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 546 #define ID_AA64MMFR0_TGRAN64_MASK (0xfULL << ID_AA64MMFR0_TGRAN64_SHIFT) 547 #define ID_AA64MMFR0_TGRAN64(x) ((x) & ID_AA64MMFR0_TGRAN64_MASK) 548 #define ID_AA64MMFR0_TGRAN64_IMPL (0x0ULL << ID_AA64MMFR0_TGRAN64_SHIFT) 549 #define ID_AA64MMFR0_TGRAN64_NONE (0xfULL << ID_AA64MMFR0_TGRAN64_SHIFT) 550 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 551 #define ID_AA64MMFR0_TGRAN4_MASK (0xfULL << ID_AA64MMFR0_TGRAN4_SHIFT) 552 #define ID_AA64MMFR0_TGRAN4(x) ((x) & ID_AA64MMFR0_TGRAN4_MASK) 553 #define ID_AA64MMFR0_TGRAN4_IMPL (0x0ULL << ID_AA64MMFR0_TGRAN4_SHIFT) 554 #define ID_AA64MMFR0_TGRAN4_NONE (0xfULL << ID_AA64MMFR0_TGRAN4_SHIFT) 555 #define ID_AA64MMFR0_ECV_SHIFT 60 556 #define ID_AA64MMFR0_ECV_MASK (0xfULL << ID_AA64MMFR0_ECV_SHIFT) 557 #define ID_AA64MMFR0_ECV(x) ((x) & ID_AA64MMFR0_ECV_MASK) 558 #define ID_AA64MMFR0_ECV_NONE (0x0ULL << ID_AA64MMFR0_ECV_SHIFT) 559 #define ID_AA64MMFR0_ECV_IMPL (0x1ULL << ID_AA64MMFR0_ECV_SHIFT) 560 #define ID_AA64MMFR0_ECV_CNTHCTL (0x2ULL << ID_AA64MMFR0_ECV_SHIFT) 561 562 /* ID_AA64MMFR1_EL1 */ 563 #define ID_AA64MMFR1_MASK 0xf000f000ffffffffULL 564 #define ID_AA64MMFR1_HAFDBS_SHIFT 0 565 #define ID_AA64MMFR1_HAFDBS_MASK (0xfULL << ID_AA64MMFR1_HAFDBS_SHIFT) 566 #define ID_AA64MMFR1_HAFDBS(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) 567 #define ID_AA64MMFR1_HAFDBS_NONE (0x0ULL << ID_AA64MMFR1_HAFDBS_SHIFT) 568 #define ID_AA64MMFR1_HAFDBS_AF (0x1ULL << ID_AA64MMFR1_HAFDBS_SHIFT) 569 #define ID_AA64MMFR1_HAFDBS_AF_DBS (0x2ULL << ID_AA64MMFR1_HAFDBS_SHIFT) 570 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 571 #define ID_AA64MMFR1_VMIDBITS_MASK (0xfULL << ID_AA64MMFR1_VMIDBITS_SHIFT) 572 #define ID_AA64MMFR1_VMIDBITS(x) ((x) & ID_AA64MMFR1_VMIDBITS_MASK) 573 #define ID_AA64MMFR1_VMIDBITS_8 (0x0ULL << ID_AA64MMFR1_VMIDBITS_SHIFT) 574 #define ID_AA64MMFR1_VMIDBITS_16 (0x2ULL << ID_AA64MMFR1_VMIDBITS_SHIFT) 575 #define ID_AA64MMFR1_VH_SHIFT 8 576 #define ID_AA64MMFR1_VH_MASK (0xfULL << ID_AA64MMFR1_VH_SHIFT) 577 #define ID_AA64MMFR1_VH(x) ((x) & ID_AA64MMFR1_VH_MASK) 578 #define ID_AA64MMFR1_VH_NONE (0x0ULL << ID_AA64MMFR1_VH_SHIFT) 579 #define ID_AA64MMFR1_VH_IMPL (0x1ULL << ID_AA64MMFR1_VH_SHIFT) 580 #define ID_AA64MMFR1_HPDS_SHIFT 12 581 #define ID_AA64MMFR1_HPDS_MASK (0xfULL << ID_AA64MMFR1_HPDS_SHIFT) 582 #define ID_AA64MMFR1_HPDS(x) ((x) & ID_AA64MMFR1_HPDS_MASK) 583 #define ID_AA64MMFR1_HPDS_NONE (0x0ULL << ID_AA64MMFR1_HPDS_SHIFT) 584 #define ID_AA64MMFR1_HPDS_IMPL (0x1ULL << ID_AA64MMFR1_HPDS_SHIFT) 585 #define ID_AA64MMFR1_LO_SHIFT 16 586 #define ID_AA64MMFR1_LO_MASK (0xfULL << ID_AA64MMFR1_LO_SHIFT) 587 #define ID_AA64MMFR1_LO(x) ((x) & ID_AA64MMFR1_LO_MASK) 588 #define ID_AA64MMFR1_LO_NONE (0x0ULL << ID_AA64MMFR1_LO_SHIFT) 589 #define ID_AA64MMFR1_LO_IMPL (0x1ULL << ID_AA64MMFR1_LO_SHIFT) 590 #define ID_AA64MMFR1_PAN_SHIFT 20 591 #define ID_AA64MMFR1_PAN_MASK (0xfULL << ID_AA64MMFR1_PAN_SHIFT) 592 #define ID_AA64MMFR1_PAN(x) ((x) & ID_AA64MMFR1_PAN_MASK) 593 #define ID_AA64MMFR1_PAN_NONE (0x0ULL << ID_AA64MMFR1_PAN_SHIFT) 594 #define ID_AA64MMFR1_PAN_IMPL (0x1ULL << ID_AA64MMFR1_PAN_SHIFT) 595 #define ID_AA64MMFR1_PAN_ATS1E1 (0x2ULL << ID_AA64MMFR1_PAN_SHIFT) 596 #define ID_AA64MMFR1_PAN_EPAN (0x3ULL << ID_AA64MMFR1_PAN_SHIFT) 597 #define ID_AA64MMFR1_SPECSEI_SHIFT 24 598 #define ID_AA64MMFR1_SPECSEI_MASK (0xfULL << ID_AA64MMFR1_SPECSEI_SHIFT) 599 #define ID_AA64MMFR1_SPECSEI(x) ((x) & ID_AA64MMFR1_SPECSEI_MASK) 600 #define ID_AA64MMFR1_SPECSEI_NONE (0x0ULL << ID_AA64MMFR1_SPECSEI_SHIFT) 601 #define ID_AA64MMFR1_SPECSEI_IMPL (0x1ULL << ID_AA64MMFR1_SPECSEI_SHIFT) 602 #define ID_AA64MMFR1_XNX_SHIFT 28 603 #define ID_AA64MMFR1_XNX_MASK (0xfULL << ID_AA64MMFR1_XNX_SHIFT) 604 #define ID_AA64MMFR1_XNX(x) ((x) & ID_AA64MMFR1_XNX_MASK) 605 #define ID_AA64MMFR1_XNX_NONE (0x0ULL << ID_AA64MMFR1_XNX_SHIFT) 606 #define ID_AA64MMFR1_XNX_IMPL (0x1ULL << ID_AA64MMFR1_XNX_SHIFT) 607 #define ID_AA64MMFR1_AFP_SHIFT 44 608 #define ID_AA64MMFR1_AFP_MASK (0xfULL << ID_AA64MMFR1_AFP_SHIFT) 609 #define ID_AA64MMFR1_AFP(x) ((x) & ID_AA64MMFR1_AFP_MASK) 610 #define ID_AA64MMFR1_AFP_NONE (0x0ULL << ID_AA64MMFR1_AFP_SHIFT) 611 #define ID_AA64MMFR1_AFP_IMPL (0x1ULL << ID_AA64MMFR1_AFP_SHIFT) 612 #define ID_AA64MMFR1_ECBHB_SHIFT 60 613 #define ID_AA64MMFR1_ECBHB_MASK (0xfULL << ID_AA64MMFR1_ECBHB_SHIFT) 614 #define ID_AA64MMFR1_ECBHB(x) ((x) & ID_AA64MMFR1_ECBHB_MASK) 615 #define ID_AA64MMFR1_ECBHB_NONE (0x0ULL << ID_AA64MMFR1_ECBHB_SHIFT) 616 #define ID_AA64MMFR1_ECBHB_IMPL (0x1ULL << ID_AA64MMFR1_ECBHB_SHIFT) 617 618 /* ID_AA64MMFR2_EL1 */ 619 #define ID_AA64MMFR2_MASK 0xffff0fffffffffffULL 620 #define ID_AA64MMFR2_CCIDX_SHIFT 20 621 #define ID_AA64MMFR2_CCIDX_MASK (0xfULL << ID_AA64MMFR2_CCIDX_SHIFT) 622 #define ID_AA64MMFR2_CCIDX(x) ((x) & ID_AA64MMFR2_CCIDX_MASK) 623 #define ID_AA64MMFR2_CCIDX_IMPL (0x1ULL << ID_AA64MMFR2_CCIDX_SHIFT) 624 #define ID_AA64MMFR2_AT_SHIFT 32 625 #define ID_AA64MMFR2_AT_MASK (0xfULL << ID_AA64MMFR2_AT_SHIFT) 626 #define ID_AA64MMFR2_AT(x) ((x) & ID_AA64MMFR2_AT_MASK) 627 #define ID_AA64MMFR2_AT_NONE (0x0ULL << ID_AA64MMFR2_AT_SHIFT) 628 #define ID_AA64MMFR2_AT_IMPL (0x1ULL << ID_AA64MMFR2_AT_SHIFT) 629 #define ID_AA64MMFR2_IDS_SHIFT 36 630 #define ID_AA64MMFR2_IDS_MASK (0xfULL << ID_AA64MMFR2_IDS_SHIFT) 631 #define ID_AA64MMFR2_IDS(x) ((x) & ID_AA64MMFR2_IDS_MASK) 632 #define ID_AA64MMFR2_IDS_NONE (0x0ULL << ID_AA64MMFR2_IDS_SHIFT) 633 #define ID_AA64MMFR2_IDS_IMPL (0x1ULL << ID_AA64MMFR2_IDS_SHIFT) 634 635 /* ID_AA64PFR0_EL1 */ 636 #define ID_AA64PFR0_MASK 0xff0fffffffffffffULL 637 #define ID_AA64PFR0_EL0_SHIFT 0 638 #define ID_AA64PFR0_EL0_MASK (0xfULL << ID_AA64PFR0_EL0_SHIFT) 639 #define ID_AA64PFR0_EL0(x) ((x) & ID_AA64PFR0_EL0_MASK) 640 #define ID_AA64PFR0_EL0_64 (0x1ULL << ID_AA64PFR0_EL0_SHIFT) 641 #define ID_AA64PFR0_EL0_64_32 (0x2ULL << ID_AA64PFR0_EL0_SHIFT) 642 #define ID_AA64PFR0_EL1_SHIFT 4 643 #define ID_AA64PFR0_EL1_MASK (0xfULL << ID_AA64PFR0_EL1_SHIFT) 644 #define ID_AA64PFR0_EL1(x) ((x) & ID_AA64PFR0_EL1_MASK) 645 #define ID_AA64PFR0_EL1_64 (0x1ULL << ID_AA64PFR0_EL1_SHIFT) 646 #define ID_AA64PFR0_EL1_64_32 (0x2ULL << ID_AA64PFR0_EL1_SHIFT) 647 #define ID_AA64PFR0_EL2_SHIFT 8 648 #define ID_AA64PFR0_EL2_MASK (0xfULL << ID_AA64PFR0_EL2_SHIFT) 649 #define ID_AA64PFR0_EL2(x) ((x) & ID_AA64PFR0_EL2_MASK) 650 #define ID_AA64PFR0_EL2_NONE (0x0ULL << ID_AA64PFR0_EL2_SHIFT) 651 #define ID_AA64PFR0_EL2_64 (0x1ULL << ID_AA64PFR0_EL2_SHIFT) 652 #define ID_AA64PFR0_EL2_64_32 (0x2ULL << ID_AA64PFR0_EL2_SHIFT) 653 #define ID_AA64PFR0_EL3_SHIFT 12 654 #define ID_AA64PFR0_EL3_MASK (0xfULL << ID_AA64PFR0_EL3_SHIFT) 655 #define ID_AA64PFR0_EL3(x) ((x) & ID_AA64PFR0_EL3_MASK) 656 #define ID_AA64PFR0_EL3_NONE (0x0ULL << ID_AA64PFR0_EL3_SHIFT) 657 #define ID_AA64PFR0_EL3_64 (0x1ULL << ID_AA64PFR0_EL3_SHIFT) 658 #define ID_AA64PFR0_EL3_64_32 (0x2ULL << ID_AA64PFR0_EL3_SHIFT) 659 #define ID_AA64PFR0_FP_SHIFT 16 660 #define ID_AA64PFR0_FP_MASK (0xfULL << ID_AA64PFR0_FP_SHIFT) 661 #define ID_AA64PFR0_FP(x) ((x) & ID_AA64PFR0_FP_MASK) 662 #define ID_AA64PFR0_FP_IMPL (0x0ULL << ID_AA64PFR0_FP_SHIFT) 663 #define ID_AA64PFR0_FP_HP (0x1ULL << ID_AA64PFR0_FP_SHIFT) 664 #define ID_AA64PFR0_FP_NONE (0xfULL << ID_AA64PFR0_FP_SHIFT) 665 #define ID_AA64PFR0_ADV_SIMD_SHIFT 20 666 #define ID_AA64PFR0_ADV_SIMD_MASK (0xfULL << ID_AA64PFR0_ADV_SIMD_SHIFT) 667 #define ID_AA64PFR0_ADV_SIMD(x) ((x) & ID_AA64PFR0_ADV_SIMD_MASK) 668 #define ID_AA64PFR0_ADV_SIMD_IMPL (0x0ULL << ID_AA64PFR0_ADV_SIMD_SHIFT) 669 #define ID_AA64PFR0_ADV_SIMD_HP (0x1ULL << ID_AA64PFR0_ADV_SIMD_SHIFT) 670 #define ID_AA64PFR0_ADV_SIMD_NONE (0xfULL << ID_AA64PFR0_ADV_SIMD_SHIFT) 671 #define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ 672 #define ID_AA64PFR0_GIC_SHIFT 24 673 #define ID_AA64PFR0_GIC_MASK (0xfULL << ID_AA64PFR0_GIC_SHIFT) 674 #define ID_AA64PFR0_GIC(x) ((x) & ID_AA64PFR0_GIC_MASK) 675 #define ID_AA64PFR0_GIC_CPUIF_NONE (0x0ULL << ID_AA64PFR0_GIC_SHIFT) 676 #define ID_AA64PFR0_GIC_CPUIF_EN (0x1ULL << ID_AA64PFR0_GIC_SHIFT) 677 #define ID_AA64PFR0_RAS_SHIFT 28 678 #define ID_AA64PFR0_RAS_MASK (0xfULL << ID_AA64PFR0_RAS_SHIFT) 679 #define ID_AA64PFR0_RAS(x) ((x) & ID_AA64PFR0_RAS_MASK) 680 #define ID_AA64PFR0_RAS_NONE (0x0ULL << ID_AA64PFR0_RAS_SHIFT) 681 #define ID_AA64PFR0_RAS_IMPL (0x1ULL << ID_AA64PFR0_RAS_SHIFT) 682 #define ID_AA64PFR0_RAS_IMPL_V1P1 (0x2ULL << ID_AA64PFR0_RAS_SHIFT) 683 #define ID_AA64PFR0_SVE_SHIFT 32 684 #define ID_AA64PFR0_SVE_MASK (0xfULL << ID_AA64PFR0_SVE_SHIFT) 685 #define ID_AA64PFR0_SVE(x) ((x) & ID_AA64PFR0_SVE_MASK) 686 #define ID_AA64PFR0_SVE_NONE (0x0ULL << ID_AA64PFR0_SVE_SHIFT) 687 #define ID_AA64PFR0_SVE_IMPL (0x1ULL << ID_AA64PFR0_SVE_SHIFT) 688 #define ID_AA64PFR0_SEL2_SHIFT 36 689 #define ID_AA64PFR0_SEL2_MASK (0xfULL << ID_AA64PFR0_SEL2_SHIFT) 690 #define ID_AA64PFR0_SEL2(x) ((x) & ID_AA64PFR0_SEL2_MASK) 691 #define ID_AA64PFR0_SEL2_NONE (0x0ULL << ID_AA64PFR0_SEL2_SHIFT) 692 #define ID_AA64PFR0_SEL2_IMPL (0x1ULL << ID_AA64PFR0_SEL2_SHIFT) 693 #define ID_AA64PFR0_MPAM_SHIFT 40 694 #define ID_AA64PFR0_MPAM_MASK (0xfULL << ID_AA64PFR0_MPAM_SHIFT) 695 #define ID_AA64PFR0_MPAM(x) ((x) & ID_AA64PFR0_MPAM_MASK) 696 #define ID_AA64PFR0_MPAM_NONE (0x0ULL << ID_AA64PFR0_MPAM_SHIFT) 697 #define ID_AA64PFR0_MPAM_IMPL (0x1ULL << ID_AA64PFR0_MPAM_SHIFT) 698 #define ID_AA64PFR0_AMU_SHIFT 44 699 #define ID_AA64PFR0_AMU_MASK (0xfULL << ID_AA64PFR0_AMU_SHIFT) 700 #define ID_AA64PFR0_AMU(x) ((x) & ID_AA64PFR0_AMU_MASK) 701 #define ID_AA64PFR0_AMU_NONE (0x0ULL << ID_AA64PFR0_AMU_SHIFT) 702 #define ID_AA64PFR0_AMU_IMPL (0x1ULL << ID_AA64PFR0_AMU_SHIFT) 703 #define ID_AA64PFR0_DIT_SHIFT 48 704 #define ID_AA64PFR0_DIT_MASK (0xfULL << ID_AA64PFR0_DIT_SHIFT) 705 #define ID_AA64PFR0_DIT(x) ((x) & ID_AA64PFR0_DIT_MASK) 706 #define ID_AA64PFR0_DIT_UNKNOWN (0x0ULL << ID_AA64PFR0_DIT_SHIFT) 707 #define ID_AA64PFR0_DIT_IMPL (0x1ULL << ID_AA64PFR0_DIT_SHIFT) 708 #define ID_AA64PFR0_CSV2_SHIFT 56 709 #define ID_AA64PFR0_CSV2_MASK (0xfULL << ID_AA64PFR0_CSV2_SHIFT) 710 #define ID_AA64PFR0_CSV2(x) ((x) & ID_AA64PFR0_CSV2_MASK) 711 #define ID_AA64PFR0_CSV2_UNKNOWN (0x0ULL << ID_AA64PFR0_CSV2_SHIFT) 712 #define ID_AA64PFR0_CSV2_IMPL (0x1ULL << ID_AA64PFR0_CSV2_SHIFT) 713 #define ID_AA64PFR0_CSV2_SCXT (0x2ULL << ID_AA64PFR0_CSV2_SHIFT) 714 #define ID_AA64PFR0_CSV2_HCXT (0x3ULL << ID_AA64PFR0_CSV2_SHIFT) 715 #define ID_AA64PFR0_CSV3_SHIFT 60 716 #define ID_AA64PFR0_CSV3_MASK (0xfULL << ID_AA64PFR0_CSV3_SHIFT) 717 #define ID_AA64PFR0_CSV3(x) ((x) & ID_AA64PFR0_CSV3_MASK) 718 #define ID_AA64PFR0_CSV3_UNKNOWN (0x0ULL << ID_AA64PFR0_CSV3_SHIFT) 719 #define ID_AA64PFR0_CSV3_IMPL (0x1ULL << ID_AA64PFR0_CSV3_SHIFT) 720 721 /* ID_AA64PFR1_EL1 */ 722 #define ID_AA64PFR1_MASK 0x000000000000ffffULL 723 #define ID_AA64PFR1_BT_SHIFT 0 724 #define ID_AA64PFR1_BT_MASK (0xfULL << ID_AA64PFR1_BT_SHIFT) 725 #define ID_AA64PFR1_BT(x) ((x) & ID_AA64PFR1_BT_MASK) 726 #define ID_AA64PFR1_BT_NONE (0x0ULL << ID_AA64PFR1_BT_SHIFT) 727 #define ID_AA64PFR1_BT_IMPL (0x1ULL << ID_AA64PFR1_BT_SHIFT) 728 #define ID_AA64PFR1_SSBS_SHIFT 4 729 #define ID_AA64PFR1_SSBS_MASK (0xfULL << ID_AA64PFR1_SSBS_SHIFT) 730 #define ID_AA64PFR1_SSBS(x) ((x) & ID_AA64PFR1_SSBS_MASK) 731 #define ID_AA64PFR1_SSBS_NONE (0x0ULL << ID_AA64PFR1_SSBS_SHIFT) 732 #define ID_AA64PFR1_SSBS_PSTATE (0x1ULL << ID_AA64PFR1_SSBS_SHIFT) 733 #define ID_AA64PFR1_SSBS_PSTATE_MSR (0x2ULL << ID_AA64PFR1_SSBS_SHIFT) 734 #define ID_AA64PFR1_MTE_SHIFT 8 735 #define ID_AA64PFR1_MTE_MASK (0xfULL << ID_AA64PFR1_MTE_SHIFT) 736 #define ID_AA64PFR1_MTE(x) ((x) & ID_AA64PFR1_MTE_MASK) 737 #define ID_AA64PFR1_MTE_NONE (0x0ULL << ID_AA64PFR1_MTE_SHIFT) 738 #define ID_AA64PFR1_MTE_IMPL (0x1ULL << ID_AA64PFR1_MTE_SHIFT) 739 #define ID_AA64PFR1_RAS_FRAC_SHIFT 12 740 #define ID_AA64PFR1_RAS_FRAC_MASK (0xfULL << ID_AA64PFR1_RAS_FRAC_SHIFT) 741 #define ID_AA64PFR1_RAS_FRAC(x) ((x) & ID_AA64PFR1_RAS_FRAC_MASK) 742 #define ID_AA64PFR1_RAS_FRAC_NONE (0x0ULL << ID_AA64PFR1_RAS_FRAC_SHIFT) 743 #define ID_AA64PFR1_RAS_FRAC_IMPL (0x1ULL << ID_AA64PFR1_RAS_FRAC_SHIFT) 744 745 /* MAIR_EL1 - Memory Attribute Indirection Register */ 746 #define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8)) 747 #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) 748 #define MAIR_DEVICE_nGnRnE 0x00 749 #define MAIR_NORMAL_NC 0x44 750 #define MAIR_NORMAL_WT 0x88 751 #define MAIR_NORMAL_WB 0xff 752 753 /* PAR_EL1 - Physical Address Register */ 754 #define PAR_F_SHIFT 0 755 #define PAR_F (0x1 << PAR_F_SHIFT) 756 #define PAR_SUCCESS(x) (((x) & PAR_F) == 0) 757 /* When PAR_F == 0 (success) */ 758 #define PAR_SH_SHIFT 7 759 #define PAR_SH_MASK (0x3 << PAR_SH_SHIFT) 760 #define PAR_NS_SHIFT 9 761 #define PAR_NS_MASK (0x3 << PAR_NS_SHIFT) 762 #define PAR_PA_SHIFT 12 763 #define PAR_PA_MASK 0x0000fffffffff000 764 #define PAR_ATTR_SHIFT 56 765 #define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT) 766 /* When PAR_F == 1 (aborted) */ 767 #define PAR_FST_SHIFT 1 768 #define PAR_FST_MASK (0x3f << PAR_FST_SHIFT) 769 #define PAR_PTW_SHIFT 8 770 #define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT) 771 #define PAR_S_SHIFT 9 772 #define PAR_S_MASK (0x1 << PAR_S_SHIFT) 773 774 /* SCTLR_EL1 - System Control Register */ 775 #define SCTLR_RES0 0xffffffffc8222400 /* Reserved, write 0 */ 776 #define SCTLR_RES1 0x0000000030d00800 /* Reserved, write 1 */ 777 778 #define SCTLR_M 0x0000000000000001 779 #define SCTLR_A 0x0000000000000002 780 #define SCTLR_C 0x0000000000000004 781 #define SCTLR_SA 0x0000000000000008 782 #define SCTLR_SA0 0x0000000000000010 783 #define SCTLR_CP15BEN 0x0000000000000020 784 #define SCTLR_THEE 0x0000000000000040 785 #define SCTLR_ITD 0x0000000000000080 786 #define SCTLR_SED 0x0000000000000100 787 #define SCTLR_UMA 0x0000000000000200 788 #define SCTLR_I 0x0000000000001000 789 #define SCTLR_EnDB 0x0000000000002000 790 #define SCTLR_DZE 0x0000000000004000 791 #define SCTLR_UCT 0x0000000000008000 792 #define SCTLR_nTWI 0x0000000000010000 793 #define SCTLR_nTWE 0x0000000000040000 794 #define SCTLR_WXN 0x0000000000080000 795 #define SCTLR_SPAN 0x0000000000800000 796 #define SCTLR_EOE 0x0000000001000000 797 #define SCTLR_EE 0x0000000002000000 798 #define SCTLR_UCI 0x0000000004000000 799 #define SCTLR_EnDA 0x0000000008000000 800 #define SCTLR_EnIB 0x0000000040000000 801 #define SCTLR_EnIA 0x0000000080000000 802 #define SCTLR_BT0 0x0000000800000000 803 #define SCTLR_BT1 0x0000001000000000 804 #define SCTLR_EPAN 0x0200000000000000 805 806 /* SPSR_EL1 */ 807 /* 808 * When the exception is taken in AArch64: 809 * M[4] is 0 for AArch64 mode 810 * M[3:2] is the exception level 811 * M[1] is unused 812 * M[0] is the SP select: 813 * 0: always SP0 814 * 1: current ELs SP 815 */ 816 #define PSR_M_EL0t 0x00000000 817 #define PSR_M_EL1t 0x00000004 818 #define PSR_M_EL1h 0x00000005 819 #define PSR_M_EL2t 0x00000008 820 #define PSR_M_EL2h 0x00000009 821 #define PSR_M_MASK 0x0000001f 822 823 #define PSR_F 0x00000040 824 #define PSR_I 0x00000080 825 #define PSR_A 0x00000100 826 #define PSR_D 0x00000200 827 #define PSR_BTYPE 0x00000c00 828 #define PSR_SSBS 0x00001000 829 #define PSR_IL 0x00100000 830 #define PSR_SS 0x00200000 831 #define PSR_PAN 0x00400000 832 #define PSR_UAO 0x00800000 833 #define PSR_DIT 0x01000000 834 #define PSR_TCO 0x02000000 835 #define PSR_V 0x10000000 836 #define PSR_C 0x20000000 837 #define PSR_Z 0x40000000 838 #define PSR_N 0x80000000 839 840 /* TCR_EL1 - Translation Control Register */ 841 #define TCR_AS (1UL << 36) 842 843 #define TCR_IPS_SHIFT 32 844 #define TCR_IPS_32BIT (0UL << TCR_IPS_SHIFT) 845 #define TCR_IPS_36BIT (1UL << TCR_IPS_SHIFT) 846 #define TCR_IPS_40BIT (2UL << TCR_IPS_SHIFT) 847 #define TCR_IPS_42BIT (3UL << TCR_IPS_SHIFT) 848 #define TCR_IPS_44BIT (4UL << TCR_IPS_SHIFT) 849 #define TCR_IPS_48BIT (5UL << TCR_IPS_SHIFT) 850 851 #define TCR_TG1_SHIFT 30 852 #define TCR_TG1_16K (1UL << TCR_TG1_SHIFT) 853 #define TCR_TG1_4K (2UL << TCR_TG1_SHIFT) 854 #define TCR_TG1_64K (3UL << TCR_TG1_SHIFT) 855 856 #define TCR_SH1_SHIFT 28 857 #define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT) 858 #define TCR_ORGN1_SHIFT 26 859 #define TCR_ORGN1_WBWA (0x1UL << TCR_ORGN1_SHIFT) 860 #define TCR_IRGN1_SHIFT 24 861 #define TCR_IRGN1_WBWA (0x1UL << TCR_IRGN1_SHIFT) 862 863 #define TCR_A1 (1UL << 22) 864 865 #define TCR_TG0_SHIFT 14 866 #define TCR_TG0_4K (0UL << TCR_TG0_SHIFT) 867 #define TCR_TG0_64K (1UL << TCR_TG0_SHIFT) 868 #define TCR_TG0_16K (2UL << TCR_TG0_SHIFT) 869 870 #define TCR_SH0_SHIFT 12 871 #define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT) 872 #define TCR_ORGN0_SHIFT 10 873 #define TCR_ORGN0_WBWA (0x1UL << TCR_ORGN0_SHIFT) 874 #define TCR_IRGN0_SHIFT 8 875 #define TCR_IRGN0_WBWA (0x1UL << TCR_IRGN0_SHIFT) 876 877 #define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\ 878 (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)) 879 #define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS) 880 881 #define TCR_T1SZ_SHIFT 16 882 #define TCR_T0SZ_SHIFT 0 883 #define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) 884 #define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) 885 #define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) 886 887 /* Monitor Debug System Control Register */ 888 #define DBG_MDSCR_SS (0x1 << 0) 889 #define DBG_MDSCR_TDCC (0x1 << 12) 890 #define DBG_MDSCR_KDE (0x1 << 13) 891 #define DBG_MDSCR_MDE (0x1 << 15) 892 893 /* Performance Monitoring Counters */ 894 #define PMCR_E (1 << 0) /* Enable all counters */ 895 #define PMCR_P (1 << 1) /* Reset all counters */ 896 #define PMCR_C (1 << 2) /* Clock counter reset */ 897 #define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ 898 #define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ 899 #define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ 900 #define PMCR_LC (1 << 6) /* Long cycle count enable */ 901 #define PMCR_IMP_SHIFT 24 /* Implementer code */ 902 #define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) 903 #define PMCR_IDCODE_SHIFT 16 /* Identification code */ 904 #define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) 905 #define PMCR_IDCODE_CORTEX_A57 0x01 906 #define PMCR_IDCODE_CORTEX_A72 0x02 907 #define PMCR_IDCODE_CORTEX_A53 0x03 908 #define PMCR_N_SHIFT 11 /* Number of counters implemented */ 909 #define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) 910 911 #define I_bit (1 << 7) /* IRQ disable */ 912 #define F_bit 0 /* FIQ disable - not actually used */ 913 914 #endif /* !_MACHINE_ARMREG_H_ */ 915