1 /* 2 * (C) Copyright 2009-2012 3 * Jens Scharsig <esw@bus-elekronik.de> 4 * BuS Elektronik GmbH & Co. KG 5 * 6 * Configuation settings for the VL_MA2SC board. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 /*--------------------------------------------------------------------------*/ 15 16 #define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/ 17 #define CONFIG_VL_MA2SC /* on an VL_MA2SC Board */ 18 #define CONFIG_ARCH_CPU_INIT 19 #define CONFIG_MISC_INIT_R 20 21 #include <asm/hardware.h> 22 23 #define MACH_TYPE_VL_MA2SC 2412 24 #define CONFIG_MACH_TYPE MACH_TYPE_VL_MA2SC 25 26 #define CONFIG_SYS_DCACHE_OFF 27 28 #ifdef CONFIG_RAMLOAD 29 #define CONFIG_SYS_TEXT_BASE 0x21000000 30 #else 31 #define CONFIG_SYS_TEXT_BASE 0x00000000 32 #endif 33 #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ 34 35 #define CONFIG_IDENT_STRING " on MiS Activ 2" 36 #define CONFIG_VERSION_VARIABLE 37 #define CONFIG_AT91_GPIO 38 39 #if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD) 40 #define CONFIG_SYS_USE_NORFLASH 41 #define CONFIG_SYS_USE_BOOT_NORFLASH 42 #endif 43 44 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 45 #define CONFIG_SETUP_MEMORY_TAGS 46 #define CONFIG_INITRD_TAG 47 48 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH 49 #define CONFIG_SKIP_LOWLEVEL_INIT 50 #endif 51 52 /* 53 * Hardware drivers 54 */ 55 56 #define CONFIG_BOARD_EARLY_INIT_F 57 58 #define CONFIG_WATCHDOG 59 60 #define CONFIG_ATMEL_USART 61 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 62 #define CONFIG_USART_ID ATMEL_ID_SYS 63 64 /* LCD */ 65 #define CONFIG_LCD 66 #define CONFIG_ATMEL_LCD 67 #define CONFIG_SPLASH_SCREEN 68 #define CONFIG_SYS_BLACK_ON_WHITE 69 #define LCD_BPP LCD_COLOR8 70 #define CONFIG_ATMEL_LCD_BGR555 71 72 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 73 #define CONFIG_BOOTDELAY 3 74 75 /* 76 * BOOTP options 77 */ 78 #define CONFIG_BOOTP_BOOTFILESIZE 79 #define CONFIG_BOOTP_BOOTPATH 80 #define CONFIG_BOOTP_GATEWAY 81 #define CONFIG_BOOTP_HOSTNAME 82 83 /* 84 * Command line configuration. 85 */ 86 #define CONFIG_CMD_BMP 87 #define CONFIG_CMD_DATE 88 #define CONFIG_CMD_DHCP 89 #define CONFIG_CMD_I2C 90 #define CONFIG_CMD_NAND 91 #define CONFIG_CMD_MII 92 #define CONFIG_CMD_PING 93 #define CONFIG_CMD_MD5SUM 94 #define CONFIG_CMD_SHA1SUM 95 /* 96 #define CONFIG_CMD_SPI 97 */ 98 #define CONFIG_CMD_FAT 99 #define CONFIG_CMD_USB 100 101 #define CONFIG_SYS_LONGHELP 102 #define CONFIG_MD5 103 #define CONFIG_SHA1 104 105 /*---------------------------------------------------------------------------- 106 * Hardware confuguration 107 *---------------------------------------------------------------------------*/ 108 109 /* USB */ 110 #define CONFIG_USB_ATMEL 111 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 112 #define CONFIG_USB_OHCI_NEW 113 #define CONFIG_DOS_PARTITION 114 #define CONFIG_SYS_USB_OHCI_CPU_INIT 115 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* UHP_BASE */ 116 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" 117 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 118 #define CONFIG_USB_STORAGE 119 #define CONFIG_AT91C_PQFP_UHPBUG 120 121 /* I2C-Bus */ 122 123 #define CONFIG_SYS_I2C_SPEED 50000 124 #define CONFIG_SYS_I2C_SLAVE 0 /* not used */ 125 126 #ifndef CONFIG_HARD_I2C 127 #define CONFIG_SYS_I2C 128 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 129 #define CONFIG_SYS_I2C_SOFT_SPEED CONFIG_SYS_I2C_SPEED 130 #define CONFIG_SYS_I2C_SOFT_SLAVE CONFIG_SYS_I2C_SLAVE 131 132 /* Software I2C driver configuration */ 133 #define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED) 134 135 #define AT91_PIN_SDA (1<<4) /* AT91C_PIO_PB4 */ 136 #define AT91_PIN_SCL (1<<5) /* AT91C_PIO_PB5 */ 137 138 #define I2C_INIT i2c_init_board(); 139 #define I2C_ACTIVE writel(AT91_PIN_SDA, &pio->piob.mddr); 140 #define I2C_TRISTATE writel(AT91_PIN_SDA, &pio->piob.mder); 141 #define I2C_READ ((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0) 142 #define I2C_SDA(bit) \ 143 do { \ 144 if (bit) \ 145 writel(AT91_PIN_SDA, &pio->piob.sodr); \ 146 else \ 147 writel(AT91_PIN_SDA, &pio->piob.codr); \ 148 } while (0); 149 #define I2C_SCL(bit) \ 150 do { \ 151 if (bit) \ 152 writel(AT91_PIN_SCL, &pio->piob.sodr); \ 153 else \ 154 writel(AT91_PIN_SCL, &pio->piob.codr); \ 155 } while (0); 156 #endif 157 158 /* I2C-RTC */ 159 160 #ifdef CONFIG_CMD_DATE 161 #define CONFIG_RTC_DS1338 162 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 163 #endif 164 165 /* EEPROM */ 166 167 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 168 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 169 170 /* define PDC[31:16] as DATA[31:16] */ 171 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 172 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 173 174 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ 175 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ 176 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ 177 AT91_MATRIX_CSA_EBI_CS1A) 178 179 /* user reset enable */ 180 #define CONFIG_SYS_RSTC_RMR_VAL \ 181 (AT91_RSTC_KEY | \ 182 AT91_RSTC_MR_URSTEN | \ 183 AT91_RSTC_MR_ERSTL(15)) 184 185 /* Disable Watchdog */ 186 #define CONFIG_SYS_WDTC_WDMR_VAL \ 187 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ 188 AT91_WDT_MR_WDV(0xFFF) | \ 189 AT91_WDT_MR_WDDIS | \ 190 AT91_WDT_MR_WDD(0xFFF)) 191 192 /* clocks */ 193 194 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */ 195 196 #define MHZ180 197 #if defined(MHZ199) 198 /* 199,8994 MHZ */ 199 #define MASTER_PLL_MUL 911 200 #define MASTER_PLL_DIV 56 201 #define MASTER_PLL_OUT 2 202 #elif defined(MHZ180) 203 /* 180 MHZ */ 204 #define MASTER_PLL_MUL 1875 205 #define MASTER_PLL_DIV 128 206 #define MASTER_PLL_OUT 2 207 #elif defined(MHZTEST) 208 /* Test MHZ */ 209 #define CONFIG_DISPLAY_CPUINFO 210 #define MASTER_PLL_MUL 8 211 #define MASTER_PLL_DIV 1 212 #define MASTER_PLL_OUT 2 213 #else 214 /* 176.9472 MHZ */ 215 #define MASTER_PLL_MUL 72 216 #define MASTER_PLL_DIV 5 217 #define MASTER_PLL_OUT 2 218 #endif 219 220 #define CONFIG_SYS_MOR_VAL \ 221 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) 222 223 #define CONFIG_SYS_PLLAR_VAL \ 224 (AT91_PMC_PLLAR_29 | \ 225 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ 226 AT91_PMC_PLLXR_PLLCOUNT(63) | \ 227 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ 228 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) 229 230 /* PCK/2 = MCK Master Clock from PLLA */ 231 #define CONFIG_SYS_MCKR1_VAL \ 232 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ 233 AT91_PMC_MCKR_MDIV_2) 234 235 /* PCK/2 = MCK Master Clock from PLLA */ 236 #define CONFIG_SYS_MCKR2_VAL \ 237 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ 238 AT91_PMC_MCKR_MDIV_2) 239 240 /* SDRAM */ 241 #define CONFIG_NR_DRAM_BANKS 1 242 #define CONFIG_SYS_SDRAM_BASE 0x20000000 243 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 244 #define CONFIG_SYS_INIT_SP_ADDR 0x00504000 /* use internal SRAM0 */ 245 246 #define CONFIG_SYS_SDRC_MR_VAL1 0 247 #define CONFIG_SYS_SDRC_TR_VAL1 700 248 #define CONFIG_SYS_SDRC_CR_VAL \ 249 (AT91_SDRAMC_NC_9 | \ 250 AT91_SDRAMC_NR_13 | \ 251 AT91_SDRAMC_NB_4 | \ 252 AT91_SDRAMC_CAS_3 | \ 253 AT91_SDRAMC_DBW_32 | \ 254 (2 << 8) | /* Write Recovery Delay */ \ 255 (7 << 12) | /* Row Cycle Delay */ \ 256 (2 << 16) | /* Row Precharge Delay */ \ 257 (2 << 20) | /* Row to Column Delay */ \ 258 (5 << 24) | /* Active to Precharge Delay */ \ 259 (8 << 28)) /* Exit Self Refresh to Active Delay */ 260 261 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM 262 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE 263 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ 264 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH 265 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ 266 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ 267 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ 268 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ 269 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ 270 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ 271 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ 272 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ 273 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR 274 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ 275 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL 276 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ 277 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ 278 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ 279 280 /* NOR flash */ 281 282 #define CONFIG_FLASH_SHOW_PROGRESS 45 283 #define CONFIG_SYS_FLASH_CFI 284 #define CONFIG_FLASH_CFI_DRIVER 285 #define PHYS_FLASH_1 0x10000000 286 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 287 #define CONFIG_SYS_MAX_FLASH_SECT 256 288 #define CONFIG_SYS_MAX_FLASH_BANKS 1 289 290 #define CONFIG_ENV_IS_IN_FLASH 291 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) 292 293 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ 294 #define CONFIG_SYS_SMC0_SETUP0_VAL \ 295 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ 296 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) 297 #define CONFIG_SYS_SMC0_PULSE0_VAL \ 298 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ 299 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) 300 #define CONFIG_SYS_SMC0_CYCLE0_VAL \ 301 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) 302 #define CONFIG_SYS_SMC0_MODE0_VAL \ 303 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ 304 AT91_SMC_MODE_DBW_16 | \ 305 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) 306 307 /* NAND flash */ 308 #ifdef CONFIG_CMD_NAND 309 #define CONFIG_NAND_ATMEL 310 #define CONFIG_SYS_MAX_NAND_DEVICE 1 311 #define CONFIG_SYS_NAND_BASE 0x40000000 312 #define CONFIG_SYS_NAND_DBW_8 1 313 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */ 314 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */ 315 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) 316 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(0) 317 #endif 318 319 /* Ethernet */ 320 #define CONFIG_MACB 321 #define CONFIG_RMII 322 #define CONFIG_NET_RETRY_COUNT 5 323 #define CONFIG_AT91_WANTS_COMMON_PHY 324 325 #define CONFIG_OVERWRITE_ETHADDR_ONCE 326 327 #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ 328 329 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 330 #define CONFIG_SYS_MEMTEST_END 0x21e00000 331 332 /* Address and size of Primary Environment Sector */ 333 #ifdef CONFIG_ENV_IS_IN_FLASH 334 #define CONFIG_ENV_SIZE 0x20000 335 #else 336 #define CONFIG_ENV_SIZE 0x2000 337 #endif 338 339 #define CONFIG_BAUDRATE 115200 340 #define CONFIG_SYS_BAUDRATE_TABLE {312500, 230400, 115200, 19200, \ 341 38400, 57600, 9600 } 342 343 #define CONFIG_SYS_PROMPT "U-Boot> " 344 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 345 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 346 #define CONFIG_SYS_PBSIZE \ 347 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 348 #define CONFIG_CMDLINE_EDITING 349 #define CONFIG_AUTO_COMPLETE 350 351 /* 352 * Size of malloc() pool 353 */ 354 #define CONFIG_SYS_MALLOC_LEN \ 355 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) 356 357 #ifndef CONFIG_RAMLOAD 358 #define CONFIG_BOOTCOMMAND "run nfsboot" 359 #endif 360 #define CONFIG_BOOT_RETRY_TIME -1 361 #define CONFIG_BOOT_RETRY_MIN 15 362 363 #define CONFIG_NFSBOOTCOMMAND \ 364 "dhcp $(copy_addr) $(kernelname);" \ 365 "run bootargsdefaults;" \ 366 "set bootargs $(bootargs) boot=nfs " \ 367 ";echo $(bootargs)" \ 368 ";bootm" 369 370 #define CONFIG_EXTRA_ENV_SETTINGS \ 371 "ubootaddr=10000000\0" \ 372 "splashimage=10080000\0" \ 373 "kerneladdr=100A0000\0" \ 374 "kernelsize=00800000\0" \ 375 "minifsaddr=108A0000\0" \ 376 "minifssize=00060000\0" \ 377 "rootfsaddr=10900000\0" \ 378 "copy_addr=20200000\0" \ 379 "rootfssize=01700000\0" \ 380 "kernelname=uImage_vl_ma2sc\0" \ 381 "bootargsdefaults=set bootargs " \ 382 "console=ttyS0,115200 " \ 383 "video=atmel_lcdfb " \ 384 "mem=62M " \ 385 "panic=10 " \ 386 "boardrevison=\\\"${revision}\\\" " \ 387 "uboot=\\\"${ver}\\\" " \ 388 "\0" \ 389 "update_all=run update_kernel;run update_root;" \ 390 "run update_splash; run update_uboot\0" \ 391 "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \ 392 "dhcp $(copy_addr) $(kernelname);" \ 393 "erase $(kerneladdr) +$(kernelsize);" \ 394 "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \ 395 "protect on $(kerneladdr) +$(kernelsize)" \ 396 "\0" \ 397 "update_root=protect off $(rootfsaddr) +$(rootfssize);" \ 398 "dhcp $(copy_addr) vl_ma2sc.root;" \ 399 "erase $(rootfsaddr) +$(rootfssize);" \ 400 "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \ 401 "\0" \ 402 "update_splash=protect off $(splashimage) +20000;" \ 403 "dhcp $(copy_addr) splash_vl_ma2sc.bmp;" \ 404 "erase $(splashimage) +20000;" \ 405 "cp.b $(fileaddr) 10080000 $(filesize);" \ 406 "protect on $(splashimage) +20000\0" \ 407 "update_uboot=protect off 10000000 1005FFFF;" \ 408 "dhcp $(copy_addr) u-boot_vl_ma2sc;" \ 409 "erase 10000000 1005FFFF;" \ 410 "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \ 411 "protect on 10000000 1005FFFF;reset\0" \ 412 "emergency=run bootargsdefaults;" \ 413 "set bootargs $(bootargs) root=initramfs boot=emergency " \ 414 ";bootm $(kerneladdr)\0" \ 415 "netemergency=run bootargsdefaults;" \ 416 "dhcp $(copy_addr) $(kernelname);" \ 417 "set bootargs $(bootargs) root=initramfs boot=emergency " \ 418 ";bootm $(copy_addr)\0" \ 419 "norboot=run bootargsdefaults;" \ 420 "set bootargs $(bootargs) root=initramfs boot=local quiet " \ 421 ";bootm $(kerneladdr)\0" \ 422 "nandboot=run bootargsdefaults;" \ 423 "set bootargs $(bootargs) root=initramfs boot=nand " \ 424 ";bootm $(kerneladdr)\0" \ 425 "setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0" \ 426 "clearenv=protect off 10060000 1007FFFF;" \ 427 "erase 10060000 1007FFFF;reset\0" \ 428 " " 429 430 #endif 431