1 /* $OpenBSD: cn30xxcorereg.h,v 1.2 2017/11/01 14:43:01 visa Exp $ */ 2 3 /* 4 * Copyright (c) 2014 YASUOKA Masahiko <yasuoka@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _CN30XXCOREREG_H_ 20 #define _CN30XXCOREREG_H_ 21 22 /* 23 * Cavium Networks OCTEON CN30XX Hardware Reference Manual CN30XX-HM-1.0 24 * 4. cnMIPS Cores 25 */ 26 27 /* 4.11 Core Coprocessor 0 Privileged Registers */ 28 29 /* CvmCtl Registers */ 30 #define COP_0_CVMCTL_FUSE_START_BIT 0x80000000 31 #define COP_0_CVMCTL_NOFDA_CP2 0x10000000 32 #define COP_0_CVMCTL_NOMUL 0x08000000 33 #define COP_0_CVMCTL_NOCRYPTO 0x04000000 34 #define COP_0_CVMCTL_RST_SHT 0x02000000 35 #define COP_0_CVMCTL_BIST_DIS 0x01000000 36 #define COP_0_CVMCTL_DISSETPRED 0x00800000 37 #define COP_0_CVMCTL_DISJRPRED 0x00400000 38 #define COP_0_CVMCTL_DISICACHE 0x00200000 39 #define COP_0_CVMCTL_DISWAIT 0x00100000 40 #define COP_0_CVMCTL_DEFET 0x00080000 41 #define COP_0_CVMCTL_DISCO 0x00040000 42 #define COP_0_CVMCTL_DISCE 0x00020000 43 #define COP_0_CVMCTL_DDCLK 0x00010000 44 #define COP_0_CVMCTL_DCICLK 0x00008000 45 #define COP_0_CVMCTL_REPUN 0x00004000 46 #define COP_0_CVMCTL_IPREF 0x00002000 47 #define COP_0_CVMCTL_USEUN 0x00001000 48 #define COP_0_CVMCTL_DISIOCACHE 0x00000800 49 #define COP_0_CVMCTL_IRAND 0x00000400 50 #define COP_0_CVMCTL_IPPCI 0x00000380 51 #define COP_0_CVMCTL_IPTI 0x00000070 52 #define COP_0_CVMCTL_LE 0x00000002 53 #define COP_0_CVMCTL_USELY 0x00000001 54 55 /* CvmMemCtl register */ 56 #define COP_0_CVMMEMCTL_LMTENA 0x0008000000000000ull 57 #define COP_0_CVMMEMCTL_LMTLINE_M 0x0007e00000000000ull 58 #define COP_0_CVMMEMCTL_LMTLINE_S 45 59 60 #endif /* _CN30XXCOREREG_H_ */ 61