1// DO NOT EDIT 2// generated by: ppc64map -fmt=decoder ../pp64.csv 3 4package ppc64asm 5 6const ( 7 _ Op = iota 8 BRD 9 BRH 10 BRW 11 CFUGED 12 CNTLZDM 13 CNTTZDM 14 DCFFIXQQ 15 DCTFIXQQ 16 LXVKQ 17 LXVP 18 LXVPX 19 LXVRBX 20 LXVRDX 21 LXVRHX 22 LXVRWX 23 MTVSRBM 24 MTVSRBMI 25 MTVSRDM 26 MTVSRHM 27 MTVSRQM 28 MTVSRWM 29 PADDI 30 PDEPD 31 PEXTD 32 PLBZ 33 PLD 34 PLFD 35 PLFS 36 PLHA 37 PLHZ 38 PLQ 39 PLWA 40 PLWZ 41 PLXSD 42 PLXSSP 43 PLXV 44 PLXVP 45 PMXVBF16GER2 46 PMXVBF16GER2NN 47 PMXVBF16GER2NP 48 PMXVBF16GER2PN 49 PMXVBF16GER2PP 50 PMXVF16GER2 51 PMXVF16GER2NN 52 PMXVF16GER2NP 53 PMXVF16GER2PN 54 PMXVF16GER2PP 55 PMXVF32GER 56 PMXVF32GERNN 57 PMXVF32GERNP 58 PMXVF32GERPN 59 PMXVF32GERPP 60 PMXVF64GER 61 PMXVF64GERNN 62 PMXVF64GERNP 63 PMXVF64GERPN 64 PMXVF64GERPP 65 PMXVI16GER2 66 PMXVI16GER2PP 67 PMXVI16GER2S 68 PMXVI16GER2SPP 69 PMXVI4GER8 70 PMXVI4GER8PP 71 PMXVI8GER4 72 PMXVI8GER4PP 73 PMXVI8GER4SPP 74 PNOP 75 PSTB 76 PSTD 77 PSTFD 78 PSTFS 79 PSTH 80 PSTQ 81 PSTW 82 PSTXSD 83 PSTXSSP 84 PSTXV 85 PSTXVP 86 SETBC 87 SETBCR 88 SETNBC 89 SETNBCR 90 STXVP 91 STXVPX 92 STXVRBX 93 STXVRDX 94 STXVRHX 95 STXVRWX 96 VCFUGED 97 VCLRLB 98 VCLRRB 99 VCLZDM 100 VCMPEQUQ 101 VCMPEQUQCC 102 VCMPGTSQ 103 VCMPGTSQCC 104 VCMPGTUQ 105 VCMPGTUQCC 106 VCMPSQ 107 VCMPUQ 108 VCNTMBB 109 VCNTMBD 110 VCNTMBH 111 VCNTMBW 112 VCTZDM 113 VDIVESD 114 VDIVESQ 115 VDIVESW 116 VDIVEUD 117 VDIVEUQ 118 VDIVEUW 119 VDIVSD 120 VDIVSQ 121 VDIVSW 122 VDIVUD 123 VDIVUQ 124 VDIVUW 125 VEXPANDBM 126 VEXPANDDM 127 VEXPANDHM 128 VEXPANDQM 129 VEXPANDWM 130 VEXTDDVLX 131 VEXTDDVRX 132 VEXTDUBVLX 133 VEXTDUBVRX 134 VEXTDUHVLX 135 VEXTDUHVRX 136 VEXTDUWVLX 137 VEXTDUWVRX 138 VEXTRACTBM 139 VEXTRACTDM 140 VEXTRACTHM 141 VEXTRACTQM 142 VEXTRACTWM 143 VEXTSD2Q 144 VGNB 145 VINSBLX 146 VINSBRX 147 VINSBVLX 148 VINSBVRX 149 VINSD 150 VINSDLX 151 VINSDRX 152 VINSHLX 153 VINSHRX 154 VINSHVLX 155 VINSHVRX 156 VINSW 157 VINSWLX 158 VINSWRX 159 VINSWVLX 160 VINSWVRX 161 VMODSD 162 VMODSQ 163 VMODSW 164 VMODUD 165 VMODUQ 166 VMODUW 167 VMSUMCUD 168 VMULESD 169 VMULEUD 170 VMULHSD 171 VMULHSW 172 VMULHUD 173 VMULHUW 174 VMULLD 175 VMULOSD 176 VMULOUD 177 VPDEPD 178 VPEXTD 179 VRLQ 180 VRLQMI 181 VRLQNM 182 VSLDBI 183 VSLQ 184 VSRAQ 185 VSRDBI 186 VSRQ 187 VSTRIBL 188 VSTRIBLCC 189 VSTRIBR 190 VSTRIBRCC 191 VSTRIHL 192 VSTRIHLCC 193 VSTRIHR 194 VSTRIHRCC 195 XSCMPEQQP 196 XSCMPGEQP 197 XSCMPGTQP 198 XSCVQPSQZ 199 XSCVQPUQZ 200 XSCVSQQP 201 XSCVUQQP 202 XSMAXCQP 203 XSMINCQP 204 XVBF16GER2 205 XVBF16GER2NN 206 XVBF16GER2NP 207 XVBF16GER2PN 208 XVBF16GER2PP 209 XVCVBF16SPN 210 XVCVSPBF16 211 XVF16GER2 212 XVF16GER2NN 213 XVF16GER2NP 214 XVF16GER2PN 215 XVF16GER2PP 216 XVF32GER 217 XVF32GERNN 218 XVF32GERNP 219 XVF32GERPN 220 XVF32GERPP 221 XVF64GER 222 XVF64GERNN 223 XVF64GERNP 224 XVF64GERPN 225 XVF64GERPP 226 XVI16GER2 227 XVI16GER2PP 228 XVI16GER2S 229 XVI16GER2SPP 230 XVI4GER8 231 XVI4GER8PP 232 XVI8GER4 233 XVI8GER4PP 234 XVI8GER4SPP 235 XVTLSBB 236 XXBLENDVB 237 XXBLENDVD 238 XXBLENDVH 239 XXBLENDVW 240 XXEVAL 241 XXGENPCVBM 242 XXGENPCVDM 243 XXGENPCVHM 244 XXGENPCVWM 245 XXMFACC 246 XXMTACC 247 XXPERMX 248 XXSETACCZ 249 XXSPLTI32DX 250 XXSPLTIDP 251 XXSPLTIW 252 MSGCLRU 253 MSGSNDU 254 URFID 255 ADDEX 256 MFFSCDRN 257 MFFSCDRNI 258 MFFSCE 259 MFFSCRN 260 MFFSCRNI 261 MFFSL 262 SLBIAG 263 VMSUMUDM 264 ADDPCIS 265 BCDCFNCC 266 BCDCFSQCC 267 BCDCFZCC 268 BCDCPSGNCC 269 BCDCTNCC 270 BCDCTSQCC 271 BCDCTZCC 272 BCDSCC 273 BCDSETSGNCC 274 BCDSRCC 275 BCDTRUNCCC 276 BCDUSCC 277 BCDUTRUNCCC 278 CMPEQB 279 CMPRB 280 CNTTZD 281 CNTTZDCC 282 CNTTZW 283 CNTTZWCC 284 COPY 285 CPABORT 286 DARN 287 DTSTSFI 288 DTSTSFIQ 289 EXTSWSLI 290 EXTSWSLICC 291 LDAT 292 LWAT 293 LXSD 294 LXSIBZX 295 LXSIHZX 296 LXSSP 297 LXV 298 LXVB16X 299 LXVH8X 300 LXVL 301 LXVLL 302 LXVWSX 303 LXVX 304 MADDHD 305 MADDHDU 306 MADDLD 307 MCRXRX 308 MFVSRLD 309 MODSD 310 MODSW 311 MODUD 312 MODUW 313 MSGSYNC 314 MTVSRDD 315 MTVSRWS 316 PASTECC 317 SETB 318 SLBIEG 319 SLBSYNC 320 STDAT 321 STOP 322 STWAT 323 STXSD 324 STXSIBX 325 STXSIHX 326 STXSSP 327 STXV 328 STXVB16X 329 STXVH8X 330 STXVL 331 STXVLL 332 STXVX 333 VABSDUB 334 VABSDUH 335 VABSDUW 336 VBPERMD 337 VCLZLSBB 338 VCMPNEB 339 VCMPNEBCC 340 VCMPNEH 341 VCMPNEHCC 342 VCMPNEW 343 VCMPNEWCC 344 VCMPNEZB 345 VCMPNEZBCC 346 VCMPNEZH 347 VCMPNEZHCC 348 VCMPNEZW 349 VCMPNEZWCC 350 VCTZB 351 VCTZD 352 VCTZH 353 VCTZLSBB 354 VCTZW 355 VEXTRACTD 356 VEXTRACTUB 357 VEXTRACTUH 358 VEXTRACTUW 359 VEXTSB2D 360 VEXTSB2W 361 VEXTSH2D 362 VEXTSH2W 363 VEXTSW2D 364 VEXTUBLX 365 VEXTUBRX 366 VEXTUHLX 367 VEXTUHRX 368 VEXTUWLX 369 VEXTUWRX 370 VINSERTB 371 VINSERTD 372 VINSERTH 373 VINSERTW 374 VMUL10CUQ 375 VMUL10ECUQ 376 VMUL10EUQ 377 VMUL10UQ 378 VNEGD 379 VNEGW 380 VPERMR 381 VPRTYBD 382 VPRTYBQ 383 VPRTYBW 384 VRLDMI 385 VRLDNM 386 VRLWMI 387 VRLWNM 388 VSLV 389 VSRV 390 WAIT 391 XSABSQP 392 XSADDQP 393 XSADDQPO 394 XSCMPEQDP 395 XSCMPEXPDP 396 XSCMPEXPQP 397 XSCMPGEDP 398 XSCMPGTDP 399 XSCMPOQP 400 XSCMPUQP 401 XSCPSGNQP 402 XSCVDPHP 403 XSCVDPQP 404 XSCVHPDP 405 XSCVQPDP 406 XSCVQPDPO 407 XSCVQPSDZ 408 XSCVQPSWZ 409 XSCVQPUDZ 410 XSCVQPUWZ 411 XSCVSDQP 412 XSCVUDQP 413 XSDIVQP 414 XSDIVQPO 415 XSIEXPDP 416 XSIEXPQP 417 XSMADDQP 418 XSMADDQPO 419 XSMAXCDP 420 XSMAXJDP 421 XSMINCDP 422 XSMINJDP 423 XSMSUBQP 424 XSMSUBQPO 425 XSMULQP 426 XSMULQPO 427 XSNABSQP 428 XSNEGQP 429 XSNMADDQP 430 XSNMADDQPO 431 XSNMSUBQP 432 XSNMSUBQPO 433 XSRQPI 434 XSRQPIX 435 XSRQPXP 436 XSSQRTQP 437 XSSQRTQPO 438 XSSUBQP 439 XSSUBQPO 440 XSTSTDCDP 441 XSTSTDCQP 442 XSTSTDCSP 443 XSXEXPDP 444 XSXEXPQP 445 XSXSIGDP 446 XSXSIGQP 447 XVCVHPSP 448 XVCVSPHP 449 XVIEXPDP 450 XVIEXPSP 451 XVTSTDCDP 452 XVTSTDCSP 453 XVXEXPDP 454 XVXEXPSP 455 XVXSIGDP 456 XVXSIGSP 457 XXBRD 458 XXBRH 459 XXBRQ 460 XXBRW 461 XXEXTRACTUW 462 XXINSERTW 463 XXPERM 464 XXPERMR 465 XXSPLTIB 466 BCDADDCC 467 BCDSUBCC 468 BCTAR 469 BCTARL 470 CLRBHRB 471 FMRGEW 472 FMRGOW 473 ICBT 474 LQARX 475 LXSIWAX 476 LXSIWZX 477 LXSSPX 478 MFBHRBE 479 MFVSRD 480 MFVSRWZ 481 MSGCLR 482 MSGCLRP 483 MSGSND 484 MSGSNDP 485 MTVSRD 486 MTVSRWA 487 MTVSRWZ 488 RFEBB 489 STQCXCC 490 STXSIWX 491 STXSSPX 492 VADDCUQ 493 VADDECUQ 494 VADDEUQM 495 VADDUDM 496 VADDUQM 497 VBPERMQ 498 VCIPHER 499 VCIPHERLAST 500 VCLZB 501 VCLZD 502 VCLZH 503 VCLZW 504 VCMPEQUD 505 VCMPEQUDCC 506 VCMPGTSD 507 VCMPGTSDCC 508 VCMPGTUD 509 VCMPGTUDCC 510 VEQV 511 VGBBD 512 VMAXSD 513 VMAXUD 514 VMINSD 515 VMINUD 516 VMRGEW 517 VMRGOW 518 VMULESW 519 VMULEUW 520 VMULOSW 521 VMULOUW 522 VMULUWM 523 VNAND 524 VNCIPHER 525 VNCIPHERLAST 526 VORC 527 VPERMXOR 528 VPKSDSS 529 VPKSDUS 530 VPKUDUM 531 VPKUDUS 532 VPMSUMB 533 VPMSUMD 534 VPMSUMH 535 VPMSUMW 536 VPOPCNTB 537 VPOPCNTD 538 VPOPCNTH 539 VPOPCNTW 540 VRLD 541 VSBOX 542 VSHASIGMAD 543 VSHASIGMAW 544 VSLD 545 VSRAD 546 VSRD 547 VSUBCUQ 548 VSUBECUQ 549 VSUBEUQM 550 VSUBUDM 551 VSUBUQM 552 VUPKHSW 553 VUPKLSW 554 XSADDSP 555 XSCVDPSPN 556 XSCVSPDPN 557 XSCVSXDSP 558 XSCVUXDSP 559 XSDIVSP 560 XSMADDASP 561 XSMADDMSP 562 XSMSUBASP 563 XSMSUBMSP 564 XSMULSP 565 XSNMADDASP 566 XSNMADDMSP 567 XSNMSUBASP 568 XSNMSUBMSP 569 XSRESP 570 XSRSP 571 XSRSQRTESP 572 XSSQRTSP 573 XSSUBSP 574 XXLEQV 575 XXLNAND 576 XXLORC 577 ADDG6S 578 BPERMD 579 CBCDTD 580 CDTBCD 581 DCFFIX 582 DCFFIXCC 583 DIVDE 584 DIVDECC 585 DIVDEO 586 DIVDEOCC 587 DIVDEU 588 DIVDEUCC 589 DIVDEUO 590 DIVDEUOCC 591 DIVWE 592 DIVWECC 593 DIVWEO 594 DIVWEOCC 595 DIVWEU 596 DIVWEUCC 597 DIVWEUO 598 DIVWEUOCC 599 FCFIDS 600 FCFIDSCC 601 FCFIDU 602 FCFIDUCC 603 FCFIDUS 604 FCFIDUSCC 605 FCTIDU 606 FCTIDUCC 607 FCTIDUZ 608 FCTIDUZCC 609 FCTIWU 610 FCTIWUCC 611 FCTIWUZ 612 FCTIWUZCC 613 FTDIV 614 FTSQRT 615 LBARX 616 LDBRX 617 LFIWZX 618 LHARX 619 LXSDX 620 LXVD2X 621 LXVDSX 622 LXVW4X 623 POPCNTD 624 POPCNTW 625 STBCXCC 626 STDBRX 627 STHCXCC 628 STXSDX 629 STXVD2X 630 STXVW4X 631 XSABSDP 632 XSADDDP 633 XSCMPODP 634 XSCMPUDP 635 XSCPSGNDP 636 XSCVDPSP 637 XSCVDPSXDS 638 XSCVDPSXWS 639 XSCVDPUXDS 640 XSCVDPUXWS 641 XSCVSPDP 642 XSCVSXDDP 643 XSCVUXDDP 644 XSDIVDP 645 XSMADDADP 646 XSMADDMDP 647 XSMAXDP 648 XSMINDP 649 XSMSUBADP 650 XSMSUBMDP 651 XSMULDP 652 XSNABSDP 653 XSNEGDP 654 XSNMADDADP 655 XSNMADDMDP 656 XSNMSUBADP 657 XSNMSUBMDP 658 XSRDPI 659 XSRDPIC 660 XSRDPIM 661 XSRDPIP 662 XSRDPIZ 663 XSREDP 664 XSRSQRTEDP 665 XSSQRTDP 666 XSSUBDP 667 XSTDIVDP 668 XSTSQRTDP 669 XVABSDP 670 XVABSSP 671 XVADDDP 672 XVADDSP 673 XVCMPEQDP 674 XVCMPEQDPCC 675 XVCMPEQSP 676 XVCMPEQSPCC 677 XVCMPGEDP 678 XVCMPGEDPCC 679 XVCMPGESP 680 XVCMPGESPCC 681 XVCMPGTDP 682 XVCMPGTDPCC 683 XVCMPGTSP 684 XVCMPGTSPCC 685 XVCPSGNDP 686 XVCPSGNSP 687 XVCVDPSP 688 XVCVDPSXDS 689 XVCVDPSXWS 690 XVCVDPUXDS 691 XVCVDPUXWS 692 XVCVSPDP 693 XVCVSPSXDS 694 XVCVSPSXWS 695 XVCVSPUXDS 696 XVCVSPUXWS 697 XVCVSXDDP 698 XVCVSXDSP 699 XVCVSXWDP 700 XVCVSXWSP 701 XVCVUXDDP 702 XVCVUXDSP 703 XVCVUXWDP 704 XVCVUXWSP 705 XVDIVDP 706 XVDIVSP 707 XVMADDADP 708 XVMADDASP 709 XVMADDMDP 710 XVMADDMSP 711 XVMAXDP 712 XVMAXSP 713 XVMINDP 714 XVMINSP 715 XVMSUBADP 716 XVMSUBASP 717 XVMSUBMDP 718 XVMSUBMSP 719 XVMULDP 720 XVMULSP 721 XVNABSDP 722 XVNABSSP 723 XVNEGDP 724 XVNEGSP 725 XVNMADDADP 726 XVNMADDASP 727 XVNMADDMDP 728 XVNMADDMSP 729 XVNMSUBADP 730 XVNMSUBASP 731 XVNMSUBMDP 732 XVNMSUBMSP 733 XVRDPI 734 XVRDPIC 735 XVRDPIM 736 XVRDPIP 737 XVRDPIZ 738 XVREDP 739 XVRESP 740 XVRSPI 741 XVRSPIC 742 XVRSPIM 743 XVRSPIP 744 XVRSPIZ 745 XVRSQRTEDP 746 XVRSQRTESP 747 XVSQRTDP 748 XVSQRTSP 749 XVSUBDP 750 XVSUBSP 751 XVTDIVDP 752 XVTDIVSP 753 XVTSQRTDP 754 XVTSQRTSP 755 XXLAND 756 XXLANDC 757 XXLNOR 758 XXLOR 759 XXLXOR 760 XXMRGHW 761 XXMRGLW 762 XXPERMDI 763 XXSEL 764 XXSLDWI 765 XXSPLTW 766 CMPB 767 DADD 768 DADDCC 769 DADDQ 770 DADDQCC 771 DCFFIXQ 772 DCFFIXQCC 773 DCMPO 774 DCMPOQ 775 DCMPU 776 DCMPUQ 777 DCTDP 778 DCTDPCC 779 DCTFIX 780 DCTFIXCC 781 DCTFIXQ 782 DCTFIXQCC 783 DCTQPQ 784 DCTQPQCC 785 DDEDPD 786 DDEDPDCC 787 DDEDPDQ 788 DDEDPDQCC 789 DDIV 790 DDIVCC 791 DDIVQ 792 DDIVQCC 793 DENBCD 794 DENBCDCC 795 DENBCDQ 796 DENBCDQCC 797 DIEX 798 DIEXCC 799 DIEXQCC 800 DIEXQ 801 DMUL 802 DMULCC 803 DMULQ 804 DMULQCC 805 DQUA 806 DQUACC 807 DQUAI 808 DQUAICC 809 DQUAIQ 810 DQUAIQCC 811 DQUAQ 812 DQUAQCC 813 DRDPQ 814 DRDPQCC 815 DRINTN 816 DRINTNCC 817 DRINTNQ 818 DRINTNQCC 819 DRINTX 820 DRINTXCC 821 DRINTXQ 822 DRINTXQCC 823 DRRND 824 DRRNDCC 825 DRRNDQ 826 DRRNDQCC 827 DRSP 828 DRSPCC 829 DSCLI 830 DSCLICC 831 DSCLIQ 832 DSCLIQCC 833 DSCRI 834 DSCRICC 835 DSCRIQ 836 DSCRIQCC 837 DSUB 838 DSUBCC 839 DSUBQ 840 DSUBQCC 841 DTSTDC 842 DTSTDCQ 843 DTSTDG 844 DTSTDGQ 845 DTSTEX 846 DTSTEXQ 847 DTSTSF 848 DTSTSFQ 849 DXEX 850 DXEXCC 851 DXEXQ 852 DXEXQCC 853 FCPSGN 854 FCPSGNCC 855 LBZCIX 856 LDCIX 857 LFDP 858 LFDPX 859 LFIWAX 860 LHZCIX 861 LWZCIX 862 PRTYD 863 PRTYW 864 SLBFEECC 865 STBCIX 866 STDCIX 867 STFDP 868 STFDPX 869 STHCIX 870 STWCIX 871 ISEL 872 LVEBX 873 LVEHX 874 LVEWX 875 LVSL 876 LVSR 877 LVX 878 LVXL 879 MFVSCR 880 MTVSCR 881 STVEBX 882 STVEHX 883 STVEWX 884 STVX 885 STVXL 886 TLBIEL 887 VADDCUW 888 VADDFP 889 VADDSBS 890 VADDSHS 891 VADDSWS 892 VADDUBM 893 VADDUBS 894 VADDUHM 895 VADDUHS 896 VADDUWM 897 VADDUWS 898 VAND 899 VANDC 900 VAVGSB 901 VAVGSH 902 VAVGSW 903 VAVGUB 904 VAVGUH 905 VAVGUW 906 VCFSX 907 VCFUX 908 VCMPBFP 909 VCMPBFPCC 910 VCMPEQFP 911 VCMPEQFPCC 912 VCMPEQUB 913 VCMPEQUBCC 914 VCMPEQUH 915 VCMPEQUHCC 916 VCMPEQUW 917 VCMPEQUWCC 918 VCMPGEFP 919 VCMPGEFPCC 920 VCMPGTFP 921 VCMPGTFPCC 922 VCMPGTSB 923 VCMPGTSBCC 924 VCMPGTSH 925 VCMPGTSHCC 926 VCMPGTSW 927 VCMPGTSWCC 928 VCMPGTUB 929 VCMPGTUBCC 930 VCMPGTUH 931 VCMPGTUHCC 932 VCMPGTUW 933 VCMPGTUWCC 934 VCTSXS 935 VCTUXS 936 VEXPTEFP 937 VLOGEFP 938 VMADDFP 939 VMAXFP 940 VMAXSB 941 VMAXSH 942 VMAXSW 943 VMAXUB 944 VMAXUH 945 VMAXUW 946 VMHADDSHS 947 VMHRADDSHS 948 VMINFP 949 VMINSB 950 VMINSH 951 VMINSW 952 VMINUB 953 VMINUH 954 VMINUW 955 VMLADDUHM 956 VMRGHB 957 VMRGHH 958 VMRGHW 959 VMRGLB 960 VMRGLH 961 VMRGLW 962 VMSUMMBM 963 VMSUMSHM 964 VMSUMSHS 965 VMSUMUBM 966 VMSUMUHM 967 VMSUMUHS 968 VMULESB 969 VMULESH 970 VMULEUB 971 VMULEUH 972 VMULOSB 973 VMULOSH 974 VMULOUB 975 VMULOUH 976 VNMSUBFP 977 VNOR 978 VOR 979 VPERM 980 VPKPX 981 VPKSHSS 982 VPKSHUS 983 VPKSWSS 984 VPKSWUS 985 VPKUHUM 986 VPKUHUS 987 VPKUWUM 988 VPKUWUS 989 VREFP 990 VRFIM 991 VRFIN 992 VRFIP 993 VRFIZ 994 VRLB 995 VRLH 996 VRLW 997 VRSQRTEFP 998 VSEL 999 VSL 1000 VSLB 1001 VSLDOI 1002 VSLH 1003 VSLO 1004 VSLW 1005 VSPLTB 1006 VSPLTH 1007 VSPLTISB 1008 VSPLTISH 1009 VSPLTISW 1010 VSPLTW 1011 VSR 1012 VSRAB 1013 VSRAH 1014 VSRAW 1015 VSRB 1016 VSRH 1017 VSRO 1018 VSRW 1019 VSUBCUW 1020 VSUBFP 1021 VSUBSBS 1022 VSUBSHS 1023 VSUBSWS 1024 VSUBUBM 1025 VSUBUBS 1026 VSUBUHM 1027 VSUBUHS 1028 VSUBUWM 1029 VSUBUWS 1030 VSUM2SWS 1031 VSUM4SBS 1032 VSUM4SHS 1033 VSUM4UBS 1034 VSUMSWS 1035 VUPKHPX 1036 VUPKHSB 1037 VUPKHSH 1038 VUPKLPX 1039 VUPKLSB 1040 VUPKLSH 1041 VXOR 1042 FRE 1043 FRECC 1044 FRIM 1045 FRIMCC 1046 FRIN 1047 FRINCC 1048 FRIP 1049 FRIPCC 1050 FRIZ 1051 FRIZCC 1052 FRSQRTES 1053 FRSQRTESCC 1054 HRFID 1055 POPCNTB 1056 MFOCRF 1057 MTOCRF 1058 SLBMFEE 1059 SLBMFEV 1060 SLBMTE 1061 RFSCV 1062 SCV 1063 LQ 1064 STQ 1065 CNTLZD 1066 CNTLZDCC 1067 DCBF 1068 DCBST 1069 DCBT 1070 DCBTST 1071 DIVD 1072 DIVDCC 1073 DIVDO 1074 DIVDOCC 1075 DIVDU 1076 DIVDUCC 1077 DIVDUO 1078 DIVDUOCC 1079 DIVW 1080 DIVWCC 1081 DIVWO 1082 DIVWOCC 1083 DIVWU 1084 DIVWUCC 1085 DIVWUO 1086 DIVWUOCC 1087 EIEIO 1088 EXTSB 1089 EXTSBCC 1090 EXTSW 1091 EXTSWCC 1092 FADDS 1093 FADDSCC 1094 FCFID 1095 FCFIDCC 1096 FCTID 1097 FCTIDCC 1098 FCTIDZ 1099 FCTIDZCC 1100 FDIVS 1101 FDIVSCC 1102 FMADDS 1103 FMADDSCC 1104 FMSUBS 1105 FMSUBSCC 1106 FMULS 1107 FMULSCC 1108 FNMADDS 1109 FNMADDSCC 1110 FNMSUBS 1111 FNMSUBSCC 1112 FRES 1113 FRESCC 1114 FRSQRTE 1115 FRSQRTECC 1116 FSEL 1117 FSELCC 1118 FSQRTS 1119 FSQRTSCC 1120 FSUBS 1121 FSUBSCC 1122 ICBI 1123 LD 1124 LDARX 1125 LDU 1126 LDUX 1127 LDX 1128 LWA 1129 LWARX 1130 LWAUX 1131 LWAX 1132 MFTB 1133 MTMSRD 1134 MULHD 1135 MULHDCC 1136 MULHDU 1137 MULHDUCC 1138 MULHW 1139 MULHWCC 1140 MULHWU 1141 MULHWUCC 1142 MULLD 1143 MULLDCC 1144 MULLDO 1145 MULLDOCC 1146 RFID 1147 RLDCL 1148 RLDCLCC 1149 RLDCR 1150 RLDCRCC 1151 RLDIC 1152 RLDICCC 1153 RLDICL 1154 RLDICLCC 1155 RLDICR 1156 RLDICRCC 1157 RLDIMI 1158 RLDIMICC 1159 SC 1160 SLBIA 1161 SLBIE 1162 SLD 1163 SLDCC 1164 SRAD 1165 SRADCC 1166 SRADI 1167 SRADICC 1168 SRD 1169 SRDCC 1170 STD 1171 STDCXCC 1172 STDU 1173 STDUX 1174 STDX 1175 STFIWX 1176 STWCXCC 1177 SUBF 1178 SUBFCC 1179 SUBFO 1180 SUBFOCC 1181 TD 1182 TDI 1183 TLBSYNC 1184 FCTIW 1185 FCTIWCC 1186 FCTIWZ 1187 FCTIWZCC 1188 FSQRT 1189 FSQRTCC 1190 ADD 1191 ADDCC 1192 ADDO 1193 ADDOCC 1194 ADDC 1195 ADDCCC 1196 ADDCO 1197 ADDCOCC 1198 ADDE 1199 ADDECC 1200 ADDEO 1201 ADDEOCC 1202 LI 1203 ADDI 1204 ADDIC 1205 ADDICCC 1206 LIS 1207 ADDIS 1208 ADDME 1209 ADDMECC 1210 ADDMEO 1211 ADDMEOCC 1212 ADDZE 1213 ADDZECC 1214 ADDZEO 1215 ADDZEOCC 1216 AND 1217 ANDCC 1218 ANDC 1219 ANDCCC 1220 ANDICC 1221 ANDISCC 1222 B 1223 BA 1224 BL 1225 BLA 1226 BC 1227 BCA 1228 BCL 1229 BCLA 1230 BCCTR 1231 BCCTRL 1232 BCLR 1233 BCLRL 1234 CMPW 1235 CMPD 1236 CMP 1237 CMPWI 1238 CMPDI 1239 CMPI 1240 CMPLW 1241 CMPLD 1242 CMPL 1243 CMPLWI 1244 CMPLDI 1245 CMPLI 1246 CNTLZW 1247 CNTLZWCC 1248 CRAND 1249 CRANDC 1250 CREQV 1251 CRNAND 1252 CRNOR 1253 CROR 1254 CRORC 1255 CRXOR 1256 DCBZ 1257 EQV 1258 EQVCC 1259 EXTSH 1260 EXTSHCC 1261 FABS 1262 FABSCC 1263 FADD 1264 FADDCC 1265 FCMPO 1266 FCMPU 1267 FDIV 1268 FDIVCC 1269 FMADD 1270 FMADDCC 1271 FMR 1272 FMRCC 1273 FMSUB 1274 FMSUBCC 1275 FMUL 1276 FMULCC 1277 FNABS 1278 FNABSCC 1279 FNEG 1280 FNEGCC 1281 FNMADD 1282 FNMADDCC 1283 FNMSUB 1284 FNMSUBCC 1285 FRSP 1286 FRSPCC 1287 FSUB 1288 FSUBCC 1289 ISYNC 1290 LBZ 1291 LBZU 1292 LBZUX 1293 LBZX 1294 LFD 1295 LFDU 1296 LFDUX 1297 LFDX 1298 LFS 1299 LFSU 1300 LFSUX 1301 LFSX 1302 LHA 1303 LHAU 1304 LHAUX 1305 LHAX 1306 LHBRX 1307 LHZ 1308 LHZU 1309 LHZUX 1310 LHZX 1311 LMW 1312 LSWI 1313 LSWX 1314 LWBRX 1315 LWZ 1316 LWZU 1317 LWZUX 1318 LWZX 1319 MCRF 1320 MCRFS 1321 MFCR 1322 MFFS 1323 MFFSCC 1324 MFMSR 1325 MFSPR 1326 MTCRF 1327 MTFSB0 1328 MTFSB0CC 1329 MTFSB1 1330 MTFSB1CC 1331 MTFSF 1332 MTFSFCC 1333 MTFSFI 1334 MTFSFICC 1335 MTMSR 1336 MTSPR 1337 MULLI 1338 MULLW 1339 MULLWCC 1340 MULLWO 1341 MULLWOCC 1342 NAND 1343 NANDCC 1344 NEG 1345 NEGCC 1346 NEGO 1347 NEGOCC 1348 NOR 1349 NORCC 1350 OR 1351 ORCC 1352 ORC 1353 ORCCC 1354 NOP 1355 ORI 1356 ORIS 1357 RLWIMI 1358 RLWIMICC 1359 RLWINM 1360 RLWINMCC 1361 RLWNM 1362 RLWNMCC 1363 SLW 1364 SLWCC 1365 SRAW 1366 SRAWCC 1367 SRAWI 1368 SRAWICC 1369 SRW 1370 SRWCC 1371 STB 1372 STBU 1373 STBUX 1374 STBX 1375 STFD 1376 STFDU 1377 STFDUX 1378 STFDX 1379 STFS 1380 STFSU 1381 STFSUX 1382 STFSX 1383 STH 1384 STHBRX 1385 STHU 1386 STHUX 1387 STHX 1388 STMW 1389 STSWI 1390 STSWX 1391 STW 1392 STWBRX 1393 STWU 1394 STWUX 1395 STWX 1396 SUBFC 1397 SUBFCCC 1398 SUBFCO 1399 SUBFCOCC 1400 SUBFE 1401 SUBFECC 1402 SUBFEO 1403 SUBFEOCC 1404 SUBFIC 1405 SUBFME 1406 SUBFMECC 1407 SUBFMEO 1408 SUBFMEOCC 1409 SUBFZE 1410 SUBFZECC 1411 SUBFZEO 1412 SUBFZEOCC 1413 SYNC 1414 TLBIE 1415 TW 1416 TWI 1417 XOR 1418 XORCC 1419 XORI 1420 XORIS 1421) 1422 1423var opstr = [...]string{ 1424 BRD: "brd", 1425 BRH: "brh", 1426 BRW: "brw", 1427 CFUGED: "cfuged", 1428 CNTLZDM: "cntlzdm", 1429 CNTTZDM: "cnttzdm", 1430 DCFFIXQQ: "dcffixqq", 1431 DCTFIXQQ: "dctfixqq", 1432 LXVKQ: "lxvkq", 1433 LXVP: "lxvp", 1434 LXVPX: "lxvpx", 1435 LXVRBX: "lxvrbx", 1436 LXVRDX: "lxvrdx", 1437 LXVRHX: "lxvrhx", 1438 LXVRWX: "lxvrwx", 1439 MTVSRBM: "mtvsrbm", 1440 MTVSRBMI: "mtvsrbmi", 1441 MTVSRDM: "mtvsrdm", 1442 MTVSRHM: "mtvsrhm", 1443 MTVSRQM: "mtvsrqm", 1444 MTVSRWM: "mtvsrwm", 1445 PADDI: "paddi", 1446 PDEPD: "pdepd", 1447 PEXTD: "pextd", 1448 PLBZ: "plbz", 1449 PLD: "pld", 1450 PLFD: "plfd", 1451 PLFS: "plfs", 1452 PLHA: "plha", 1453 PLHZ: "plhz", 1454 PLQ: "plq", 1455 PLWA: "plwa", 1456 PLWZ: "plwz", 1457 PLXSD: "plxsd", 1458 PLXSSP: "plxssp", 1459 PLXV: "plxv", 1460 PLXVP: "plxvp", 1461 PMXVBF16GER2: "pmxvbf16ger2", 1462 PMXVBF16GER2NN: "pmxvbf16ger2nn", 1463 PMXVBF16GER2NP: "pmxvbf16ger2np", 1464 PMXVBF16GER2PN: "pmxvbf16ger2pn", 1465 PMXVBF16GER2PP: "pmxvbf16ger2pp", 1466 PMXVF16GER2: "pmxvf16ger2", 1467 PMXVF16GER2NN: "pmxvf16ger2nn", 1468 PMXVF16GER2NP: "pmxvf16ger2np", 1469 PMXVF16GER2PN: "pmxvf16ger2pn", 1470 PMXVF16GER2PP: "pmxvf16ger2pp", 1471 PMXVF32GER: "pmxvf32ger", 1472 PMXVF32GERNN: "pmxvf32gernn", 1473 PMXVF32GERNP: "pmxvf32gernp", 1474 PMXVF32GERPN: "pmxvf32gerpn", 1475 PMXVF32GERPP: "pmxvf32gerpp", 1476 PMXVF64GER: "pmxvf64ger", 1477 PMXVF64GERNN: "pmxvf64gernn", 1478 PMXVF64GERNP: "pmxvf64gernp", 1479 PMXVF64GERPN: "pmxvf64gerpn", 1480 PMXVF64GERPP: "pmxvf64gerpp", 1481 PMXVI16GER2: "pmxvi16ger2", 1482 PMXVI16GER2PP: "pmxvi16ger2pp", 1483 PMXVI16GER2S: "pmxvi16ger2s", 1484 PMXVI16GER2SPP: "pmxvi16ger2spp", 1485 PMXVI4GER8: "pmxvi4ger8", 1486 PMXVI4GER8PP: "pmxvi4ger8pp", 1487 PMXVI8GER4: "pmxvi8ger4", 1488 PMXVI8GER4PP: "pmxvi8ger4pp", 1489 PMXVI8GER4SPP: "pmxvi8ger4spp", 1490 PNOP: "pnop", 1491 PSTB: "pstb", 1492 PSTD: "pstd", 1493 PSTFD: "pstfd", 1494 PSTFS: "pstfs", 1495 PSTH: "psth", 1496 PSTQ: "pstq", 1497 PSTW: "pstw", 1498 PSTXSD: "pstxsd", 1499 PSTXSSP: "pstxssp", 1500 PSTXV: "pstxv", 1501 PSTXVP: "pstxvp", 1502 SETBC: "setbc", 1503 SETBCR: "setbcr", 1504 SETNBC: "setnbc", 1505 SETNBCR: "setnbcr", 1506 STXVP: "stxvp", 1507 STXVPX: "stxvpx", 1508 STXVRBX: "stxvrbx", 1509 STXVRDX: "stxvrdx", 1510 STXVRHX: "stxvrhx", 1511 STXVRWX: "stxvrwx", 1512 VCFUGED: "vcfuged", 1513 VCLRLB: "vclrlb", 1514 VCLRRB: "vclrrb", 1515 VCLZDM: "vclzdm", 1516 VCMPEQUQ: "vcmpequq", 1517 VCMPEQUQCC: "vcmpequq.", 1518 VCMPGTSQ: "vcmpgtsq", 1519 VCMPGTSQCC: "vcmpgtsq.", 1520 VCMPGTUQ: "vcmpgtuq", 1521 VCMPGTUQCC: "vcmpgtuq.", 1522 VCMPSQ: "vcmpsq", 1523 VCMPUQ: "vcmpuq", 1524 VCNTMBB: "vcntmbb", 1525 VCNTMBD: "vcntmbd", 1526 VCNTMBH: "vcntmbh", 1527 VCNTMBW: "vcntmbw", 1528 VCTZDM: "vctzdm", 1529 VDIVESD: "vdivesd", 1530 VDIVESQ: "vdivesq", 1531 VDIVESW: "vdivesw", 1532 VDIVEUD: "vdiveud", 1533 VDIVEUQ: "vdiveuq", 1534 VDIVEUW: "vdiveuw", 1535 VDIVSD: "vdivsd", 1536 VDIVSQ: "vdivsq", 1537 VDIVSW: "vdivsw", 1538 VDIVUD: "vdivud", 1539 VDIVUQ: "vdivuq", 1540 VDIVUW: "vdivuw", 1541 VEXPANDBM: "vexpandbm", 1542 VEXPANDDM: "vexpanddm", 1543 VEXPANDHM: "vexpandhm", 1544 VEXPANDQM: "vexpandqm", 1545 VEXPANDWM: "vexpandwm", 1546 VEXTDDVLX: "vextddvlx", 1547 VEXTDDVRX: "vextddvrx", 1548 VEXTDUBVLX: "vextdubvlx", 1549 VEXTDUBVRX: "vextdubvrx", 1550 VEXTDUHVLX: "vextduhvlx", 1551 VEXTDUHVRX: "vextduhvrx", 1552 VEXTDUWVLX: "vextduwvlx", 1553 VEXTDUWVRX: "vextduwvrx", 1554 VEXTRACTBM: "vextractbm", 1555 VEXTRACTDM: "vextractdm", 1556 VEXTRACTHM: "vextracthm", 1557 VEXTRACTQM: "vextractqm", 1558 VEXTRACTWM: "vextractwm", 1559 VEXTSD2Q: "vextsd2q", 1560 VGNB: "vgnb", 1561 VINSBLX: "vinsblx", 1562 VINSBRX: "vinsbrx", 1563 VINSBVLX: "vinsbvlx", 1564 VINSBVRX: "vinsbvrx", 1565 VINSD: "vinsd", 1566 VINSDLX: "vinsdlx", 1567 VINSDRX: "vinsdrx", 1568 VINSHLX: "vinshlx", 1569 VINSHRX: "vinshrx", 1570 VINSHVLX: "vinshvlx", 1571 VINSHVRX: "vinshvrx", 1572 VINSW: "vinsw", 1573 VINSWLX: "vinswlx", 1574 VINSWRX: "vinswrx", 1575 VINSWVLX: "vinswvlx", 1576 VINSWVRX: "vinswvrx", 1577 VMODSD: "vmodsd", 1578 VMODSQ: "vmodsq", 1579 VMODSW: "vmodsw", 1580 VMODUD: "vmodud", 1581 VMODUQ: "vmoduq", 1582 VMODUW: "vmoduw", 1583 VMSUMCUD: "vmsumcud", 1584 VMULESD: "vmulesd", 1585 VMULEUD: "vmuleud", 1586 VMULHSD: "vmulhsd", 1587 VMULHSW: "vmulhsw", 1588 VMULHUD: "vmulhud", 1589 VMULHUW: "vmulhuw", 1590 VMULLD: "vmulld", 1591 VMULOSD: "vmulosd", 1592 VMULOUD: "vmuloud", 1593 VPDEPD: "vpdepd", 1594 VPEXTD: "vpextd", 1595 VRLQ: "vrlq", 1596 VRLQMI: "vrlqmi", 1597 VRLQNM: "vrlqnm", 1598 VSLDBI: "vsldbi", 1599 VSLQ: "vslq", 1600 VSRAQ: "vsraq", 1601 VSRDBI: "vsrdbi", 1602 VSRQ: "vsrq", 1603 VSTRIBL: "vstribl", 1604 VSTRIBLCC: "vstribl.", 1605 VSTRIBR: "vstribr", 1606 VSTRIBRCC: "vstribr.", 1607 VSTRIHL: "vstrihl", 1608 VSTRIHLCC: "vstrihl.", 1609 VSTRIHR: "vstrihr", 1610 VSTRIHRCC: "vstrihr.", 1611 XSCMPEQQP: "xscmpeqqp", 1612 XSCMPGEQP: "xscmpgeqp", 1613 XSCMPGTQP: "xscmpgtqp", 1614 XSCVQPSQZ: "xscvqpsqz", 1615 XSCVQPUQZ: "xscvqpuqz", 1616 XSCVSQQP: "xscvsqqp", 1617 XSCVUQQP: "xscvuqqp", 1618 XSMAXCQP: "xsmaxcqp", 1619 XSMINCQP: "xsmincqp", 1620 XVBF16GER2: "xvbf16ger2", 1621 XVBF16GER2NN: "xvbf16ger2nn", 1622 XVBF16GER2NP: "xvbf16ger2np", 1623 XVBF16GER2PN: "xvbf16ger2pn", 1624 XVBF16GER2PP: "xvbf16ger2pp", 1625 XVCVBF16SPN: "xvcvbf16spn", 1626 XVCVSPBF16: "xvcvspbf16", 1627 XVF16GER2: "xvf16ger2", 1628 XVF16GER2NN: "xvf16ger2nn", 1629 XVF16GER2NP: "xvf16ger2np", 1630 XVF16GER2PN: "xvf16ger2pn", 1631 XVF16GER2PP: "xvf16ger2pp", 1632 XVF32GER: "xvf32ger", 1633 XVF32GERNN: "xvf32gernn", 1634 XVF32GERNP: "xvf32gernp", 1635 XVF32GERPN: "xvf32gerpn", 1636 XVF32GERPP: "xvf32gerpp", 1637 XVF64GER: "xvf64ger", 1638 XVF64GERNN: "xvf64gernn", 1639 XVF64GERNP: "xvf64gernp", 1640 XVF64GERPN: "xvf64gerpn", 1641 XVF64GERPP: "xvf64gerpp", 1642 XVI16GER2: "xvi16ger2", 1643 XVI16GER2PP: "xvi16ger2pp", 1644 XVI16GER2S: "xvi16ger2s", 1645 XVI16GER2SPP: "xvi16ger2spp", 1646 XVI4GER8: "xvi4ger8", 1647 XVI4GER8PP: "xvi4ger8pp", 1648 XVI8GER4: "xvi8ger4", 1649 XVI8GER4PP: "xvi8ger4pp", 1650 XVI8GER4SPP: "xvi8ger4spp", 1651 XVTLSBB: "xvtlsbb", 1652 XXBLENDVB: "xxblendvb", 1653 XXBLENDVD: "xxblendvd", 1654 XXBLENDVH: "xxblendvh", 1655 XXBLENDVW: "xxblendvw", 1656 XXEVAL: "xxeval", 1657 XXGENPCVBM: "xxgenpcvbm", 1658 XXGENPCVDM: "xxgenpcvdm", 1659 XXGENPCVHM: "xxgenpcvhm", 1660 XXGENPCVWM: "xxgenpcvwm", 1661 XXMFACC: "xxmfacc", 1662 XXMTACC: "xxmtacc", 1663 XXPERMX: "xxpermx", 1664 XXSETACCZ: "xxsetaccz", 1665 XXSPLTI32DX: "xxsplti32dx", 1666 XXSPLTIDP: "xxspltidp", 1667 XXSPLTIW: "xxspltiw", 1668 MSGCLRU: "msgclru", 1669 MSGSNDU: "msgsndu", 1670 URFID: "urfid", 1671 ADDEX: "addex", 1672 MFFSCDRN: "mffscdrn", 1673 MFFSCDRNI: "mffscdrni", 1674 MFFSCE: "mffsce", 1675 MFFSCRN: "mffscrn", 1676 MFFSCRNI: "mffscrni", 1677 MFFSL: "mffsl", 1678 SLBIAG: "slbiag", 1679 VMSUMUDM: "vmsumudm", 1680 ADDPCIS: "addpcis", 1681 BCDCFNCC: "bcdcfn.", 1682 BCDCFSQCC: "bcdcfsq.", 1683 BCDCFZCC: "bcdcfz.", 1684 BCDCPSGNCC: "bcdcpsgn.", 1685 BCDCTNCC: "bcdctn.", 1686 BCDCTSQCC: "bcdctsq.", 1687 BCDCTZCC: "bcdctz.", 1688 BCDSCC: "bcds.", 1689 BCDSETSGNCC: "bcdsetsgn.", 1690 BCDSRCC: "bcdsr.", 1691 BCDTRUNCCC: "bcdtrunc.", 1692 BCDUSCC: "bcdus.", 1693 BCDUTRUNCCC: "bcdutrunc.", 1694 CMPEQB: "cmpeqb", 1695 CMPRB: "cmprb", 1696 CNTTZD: "cnttzd", 1697 CNTTZDCC: "cnttzd.", 1698 CNTTZW: "cnttzw", 1699 CNTTZWCC: "cnttzw.", 1700 COPY: "copy", 1701 CPABORT: "cpabort", 1702 DARN: "darn", 1703 DTSTSFI: "dtstsfi", 1704 DTSTSFIQ: "dtstsfiq", 1705 EXTSWSLI: "extswsli", 1706 EXTSWSLICC: "extswsli.", 1707 LDAT: "ldat", 1708 LWAT: "lwat", 1709 LXSD: "lxsd", 1710 LXSIBZX: "lxsibzx", 1711 LXSIHZX: "lxsihzx", 1712 LXSSP: "lxssp", 1713 LXV: "lxv", 1714 LXVB16X: "lxvb16x", 1715 LXVH8X: "lxvh8x", 1716 LXVL: "lxvl", 1717 LXVLL: "lxvll", 1718 LXVWSX: "lxvwsx", 1719 LXVX: "lxvx", 1720 MADDHD: "maddhd", 1721 MADDHDU: "maddhdu", 1722 MADDLD: "maddld", 1723 MCRXRX: "mcrxrx", 1724 MFVSRLD: "mfvsrld", 1725 MODSD: "modsd", 1726 MODSW: "modsw", 1727 MODUD: "modud", 1728 MODUW: "moduw", 1729 MSGSYNC: "msgsync", 1730 MTVSRDD: "mtvsrdd", 1731 MTVSRWS: "mtvsrws", 1732 PASTECC: "paste.", 1733 SETB: "setb", 1734 SLBIEG: "slbieg", 1735 SLBSYNC: "slbsync", 1736 STDAT: "stdat", 1737 STOP: "stop", 1738 STWAT: "stwat", 1739 STXSD: "stxsd", 1740 STXSIBX: "stxsibx", 1741 STXSIHX: "stxsihx", 1742 STXSSP: "stxssp", 1743 STXV: "stxv", 1744 STXVB16X: "stxvb16x", 1745 STXVH8X: "stxvh8x", 1746 STXVL: "stxvl", 1747 STXVLL: "stxvll", 1748 STXVX: "stxvx", 1749 VABSDUB: "vabsdub", 1750 VABSDUH: "vabsduh", 1751 VABSDUW: "vabsduw", 1752 VBPERMD: "vbpermd", 1753 VCLZLSBB: "vclzlsbb", 1754 VCMPNEB: "vcmpneb", 1755 VCMPNEBCC: "vcmpneb.", 1756 VCMPNEH: "vcmpneh", 1757 VCMPNEHCC: "vcmpneh.", 1758 VCMPNEW: "vcmpnew", 1759 VCMPNEWCC: "vcmpnew.", 1760 VCMPNEZB: "vcmpnezb", 1761 VCMPNEZBCC: "vcmpnezb.", 1762 VCMPNEZH: "vcmpnezh", 1763 VCMPNEZHCC: "vcmpnezh.", 1764 VCMPNEZW: "vcmpnezw", 1765 VCMPNEZWCC: "vcmpnezw.", 1766 VCTZB: "vctzb", 1767 VCTZD: "vctzd", 1768 VCTZH: "vctzh", 1769 VCTZLSBB: "vctzlsbb", 1770 VCTZW: "vctzw", 1771 VEXTRACTD: "vextractd", 1772 VEXTRACTUB: "vextractub", 1773 VEXTRACTUH: "vextractuh", 1774 VEXTRACTUW: "vextractuw", 1775 VEXTSB2D: "vextsb2d", 1776 VEXTSB2W: "vextsb2w", 1777 VEXTSH2D: "vextsh2d", 1778 VEXTSH2W: "vextsh2w", 1779 VEXTSW2D: "vextsw2d", 1780 VEXTUBLX: "vextublx", 1781 VEXTUBRX: "vextubrx", 1782 VEXTUHLX: "vextuhlx", 1783 VEXTUHRX: "vextuhrx", 1784 VEXTUWLX: "vextuwlx", 1785 VEXTUWRX: "vextuwrx", 1786 VINSERTB: "vinsertb", 1787 VINSERTD: "vinsertd", 1788 VINSERTH: "vinserth", 1789 VINSERTW: "vinsertw", 1790 VMUL10CUQ: "vmul10cuq", 1791 VMUL10ECUQ: "vmul10ecuq", 1792 VMUL10EUQ: "vmul10euq", 1793 VMUL10UQ: "vmul10uq", 1794 VNEGD: "vnegd", 1795 VNEGW: "vnegw", 1796 VPERMR: "vpermr", 1797 VPRTYBD: "vprtybd", 1798 VPRTYBQ: "vprtybq", 1799 VPRTYBW: "vprtybw", 1800 VRLDMI: "vrldmi", 1801 VRLDNM: "vrldnm", 1802 VRLWMI: "vrlwmi", 1803 VRLWNM: "vrlwnm", 1804 VSLV: "vslv", 1805 VSRV: "vsrv", 1806 WAIT: "wait", 1807 XSABSQP: "xsabsqp", 1808 XSADDQP: "xsaddqp", 1809 XSADDQPO: "xsaddqpo", 1810 XSCMPEQDP: "xscmpeqdp", 1811 XSCMPEXPDP: "xscmpexpdp", 1812 XSCMPEXPQP: "xscmpexpqp", 1813 XSCMPGEDP: "xscmpgedp", 1814 XSCMPGTDP: "xscmpgtdp", 1815 XSCMPOQP: "xscmpoqp", 1816 XSCMPUQP: "xscmpuqp", 1817 XSCPSGNQP: "xscpsgnqp", 1818 XSCVDPHP: "xscvdphp", 1819 XSCVDPQP: "xscvdpqp", 1820 XSCVHPDP: "xscvhpdp", 1821 XSCVQPDP: "xscvqpdp", 1822 XSCVQPDPO: "xscvqpdpo", 1823 XSCVQPSDZ: "xscvqpsdz", 1824 XSCVQPSWZ: "xscvqpswz", 1825 XSCVQPUDZ: "xscvqpudz", 1826 XSCVQPUWZ: "xscvqpuwz", 1827 XSCVSDQP: "xscvsdqp", 1828 XSCVUDQP: "xscvudqp", 1829 XSDIVQP: "xsdivqp", 1830 XSDIVQPO: "xsdivqpo", 1831 XSIEXPDP: "xsiexpdp", 1832 XSIEXPQP: "xsiexpqp", 1833 XSMADDQP: "xsmaddqp", 1834 XSMADDQPO: "xsmaddqpo", 1835 XSMAXCDP: "xsmaxcdp", 1836 XSMAXJDP: "xsmaxjdp", 1837 XSMINCDP: "xsmincdp", 1838 XSMINJDP: "xsminjdp", 1839 XSMSUBQP: "xsmsubqp", 1840 XSMSUBQPO: "xsmsubqpo", 1841 XSMULQP: "xsmulqp", 1842 XSMULQPO: "xsmulqpo", 1843 XSNABSQP: "xsnabsqp", 1844 XSNEGQP: "xsnegqp", 1845 XSNMADDQP: "xsnmaddqp", 1846 XSNMADDQPO: "xsnmaddqpo", 1847 XSNMSUBQP: "xsnmsubqp", 1848 XSNMSUBQPO: "xsnmsubqpo", 1849 XSRQPI: "xsrqpi", 1850 XSRQPIX: "xsrqpix", 1851 XSRQPXP: "xsrqpxp", 1852 XSSQRTQP: "xssqrtqp", 1853 XSSQRTQPO: "xssqrtqpo", 1854 XSSUBQP: "xssubqp", 1855 XSSUBQPO: "xssubqpo", 1856 XSTSTDCDP: "xststdcdp", 1857 XSTSTDCQP: "xststdcqp", 1858 XSTSTDCSP: "xststdcsp", 1859 XSXEXPDP: "xsxexpdp", 1860 XSXEXPQP: "xsxexpqp", 1861 XSXSIGDP: "xsxsigdp", 1862 XSXSIGQP: "xsxsigqp", 1863 XVCVHPSP: "xvcvhpsp", 1864 XVCVSPHP: "xvcvsphp", 1865 XVIEXPDP: "xviexpdp", 1866 XVIEXPSP: "xviexpsp", 1867 XVTSTDCDP: "xvtstdcdp", 1868 XVTSTDCSP: "xvtstdcsp", 1869 XVXEXPDP: "xvxexpdp", 1870 XVXEXPSP: "xvxexpsp", 1871 XVXSIGDP: "xvxsigdp", 1872 XVXSIGSP: "xvxsigsp", 1873 XXBRD: "xxbrd", 1874 XXBRH: "xxbrh", 1875 XXBRQ: "xxbrq", 1876 XXBRW: "xxbrw", 1877 XXEXTRACTUW: "xxextractuw", 1878 XXINSERTW: "xxinsertw", 1879 XXPERM: "xxperm", 1880 XXPERMR: "xxpermr", 1881 XXSPLTIB: "xxspltib", 1882 BCDADDCC: "bcdadd.", 1883 BCDSUBCC: "bcdsub.", 1884 BCTAR: "bctar", 1885 BCTARL: "bctarl", 1886 CLRBHRB: "clrbhrb", 1887 FMRGEW: "fmrgew", 1888 FMRGOW: "fmrgow", 1889 ICBT: "icbt", 1890 LQARX: "lqarx", 1891 LXSIWAX: "lxsiwax", 1892 LXSIWZX: "lxsiwzx", 1893 LXSSPX: "lxsspx", 1894 MFBHRBE: "mfbhrbe", 1895 MFVSRD: "mfvsrd", 1896 MFVSRWZ: "mfvsrwz", 1897 MSGCLR: "msgclr", 1898 MSGCLRP: "msgclrp", 1899 MSGSND: "msgsnd", 1900 MSGSNDP: "msgsndp", 1901 MTVSRD: "mtvsrd", 1902 MTVSRWA: "mtvsrwa", 1903 MTVSRWZ: "mtvsrwz", 1904 RFEBB: "rfebb", 1905 STQCXCC: "stqcx.", 1906 STXSIWX: "stxsiwx", 1907 STXSSPX: "stxsspx", 1908 VADDCUQ: "vaddcuq", 1909 VADDECUQ: "vaddecuq", 1910 VADDEUQM: "vaddeuqm", 1911 VADDUDM: "vaddudm", 1912 VADDUQM: "vadduqm", 1913 VBPERMQ: "vbpermq", 1914 VCIPHER: "vcipher", 1915 VCIPHERLAST: "vcipherlast", 1916 VCLZB: "vclzb", 1917 VCLZD: "vclzd", 1918 VCLZH: "vclzh", 1919 VCLZW: "vclzw", 1920 VCMPEQUD: "vcmpequd", 1921 VCMPEQUDCC: "vcmpequd.", 1922 VCMPGTSD: "vcmpgtsd", 1923 VCMPGTSDCC: "vcmpgtsd.", 1924 VCMPGTUD: "vcmpgtud", 1925 VCMPGTUDCC: "vcmpgtud.", 1926 VEQV: "veqv", 1927 VGBBD: "vgbbd", 1928 VMAXSD: "vmaxsd", 1929 VMAXUD: "vmaxud", 1930 VMINSD: "vminsd", 1931 VMINUD: "vminud", 1932 VMRGEW: "vmrgew", 1933 VMRGOW: "vmrgow", 1934 VMULESW: "vmulesw", 1935 VMULEUW: "vmuleuw", 1936 VMULOSW: "vmulosw", 1937 VMULOUW: "vmulouw", 1938 VMULUWM: "vmuluwm", 1939 VNAND: "vnand", 1940 VNCIPHER: "vncipher", 1941 VNCIPHERLAST: "vncipherlast", 1942 VORC: "vorc", 1943 VPERMXOR: "vpermxor", 1944 VPKSDSS: "vpksdss", 1945 VPKSDUS: "vpksdus", 1946 VPKUDUM: "vpkudum", 1947 VPKUDUS: "vpkudus", 1948 VPMSUMB: "vpmsumb", 1949 VPMSUMD: "vpmsumd", 1950 VPMSUMH: "vpmsumh", 1951 VPMSUMW: "vpmsumw", 1952 VPOPCNTB: "vpopcntb", 1953 VPOPCNTD: "vpopcntd", 1954 VPOPCNTH: "vpopcnth", 1955 VPOPCNTW: "vpopcntw", 1956 VRLD: "vrld", 1957 VSBOX: "vsbox", 1958 VSHASIGMAD: "vshasigmad", 1959 VSHASIGMAW: "vshasigmaw", 1960 VSLD: "vsld", 1961 VSRAD: "vsrad", 1962 VSRD: "vsrd", 1963 VSUBCUQ: "vsubcuq", 1964 VSUBECUQ: "vsubecuq", 1965 VSUBEUQM: "vsubeuqm", 1966 VSUBUDM: "vsubudm", 1967 VSUBUQM: "vsubuqm", 1968 VUPKHSW: "vupkhsw", 1969 VUPKLSW: "vupklsw", 1970 XSADDSP: "xsaddsp", 1971 XSCVDPSPN: "xscvdpspn", 1972 XSCVSPDPN: "xscvspdpn", 1973 XSCVSXDSP: "xscvsxdsp", 1974 XSCVUXDSP: "xscvuxdsp", 1975 XSDIVSP: "xsdivsp", 1976 XSMADDASP: "xsmaddasp", 1977 XSMADDMSP: "xsmaddmsp", 1978 XSMSUBASP: "xsmsubasp", 1979 XSMSUBMSP: "xsmsubmsp", 1980 XSMULSP: "xsmulsp", 1981 XSNMADDASP: "xsnmaddasp", 1982 XSNMADDMSP: "xsnmaddmsp", 1983 XSNMSUBASP: "xsnmsubasp", 1984 XSNMSUBMSP: "xsnmsubmsp", 1985 XSRESP: "xsresp", 1986 XSRSP: "xsrsp", 1987 XSRSQRTESP: "xsrsqrtesp", 1988 XSSQRTSP: "xssqrtsp", 1989 XSSUBSP: "xssubsp", 1990 XXLEQV: "xxleqv", 1991 XXLNAND: "xxlnand", 1992 XXLORC: "xxlorc", 1993 ADDG6S: "addg6s", 1994 BPERMD: "bpermd", 1995 CBCDTD: "cbcdtd", 1996 CDTBCD: "cdtbcd", 1997 DCFFIX: "dcffix", 1998 DCFFIXCC: "dcffix.", 1999 DIVDE: "divde", 2000 DIVDECC: "divde.", 2001 DIVDEO: "divdeo", 2002 DIVDEOCC: "divdeo.", 2003 DIVDEU: "divdeu", 2004 DIVDEUCC: "divdeu.", 2005 DIVDEUO: "divdeuo", 2006 DIVDEUOCC: "divdeuo.", 2007 DIVWE: "divwe", 2008 DIVWECC: "divwe.", 2009 DIVWEO: "divweo", 2010 DIVWEOCC: "divweo.", 2011 DIVWEU: "divweu", 2012 DIVWEUCC: "divweu.", 2013 DIVWEUO: "divweuo", 2014 DIVWEUOCC: "divweuo.", 2015 FCFIDS: "fcfids", 2016 FCFIDSCC: "fcfids.", 2017 FCFIDU: "fcfidu", 2018 FCFIDUCC: "fcfidu.", 2019 FCFIDUS: "fcfidus", 2020 FCFIDUSCC: "fcfidus.", 2021 FCTIDU: "fctidu", 2022 FCTIDUCC: "fctidu.", 2023 FCTIDUZ: "fctiduz", 2024 FCTIDUZCC: "fctiduz.", 2025 FCTIWU: "fctiwu", 2026 FCTIWUCC: "fctiwu.", 2027 FCTIWUZ: "fctiwuz", 2028 FCTIWUZCC: "fctiwuz.", 2029 FTDIV: "ftdiv", 2030 FTSQRT: "ftsqrt", 2031 LBARX: "lbarx", 2032 LDBRX: "ldbrx", 2033 LFIWZX: "lfiwzx", 2034 LHARX: "lharx", 2035 LXSDX: "lxsdx", 2036 LXVD2X: "lxvd2x", 2037 LXVDSX: "lxvdsx", 2038 LXVW4X: "lxvw4x", 2039 POPCNTD: "popcntd", 2040 POPCNTW: "popcntw", 2041 STBCXCC: "stbcx.", 2042 STDBRX: "stdbrx", 2043 STHCXCC: "sthcx.", 2044 STXSDX: "stxsdx", 2045 STXVD2X: "stxvd2x", 2046 STXVW4X: "stxvw4x", 2047 XSABSDP: "xsabsdp", 2048 XSADDDP: "xsadddp", 2049 XSCMPODP: "xscmpodp", 2050 XSCMPUDP: "xscmpudp", 2051 XSCPSGNDP: "xscpsgndp", 2052 XSCVDPSP: "xscvdpsp", 2053 XSCVDPSXDS: "xscvdpsxds", 2054 XSCVDPSXWS: "xscvdpsxws", 2055 XSCVDPUXDS: "xscvdpuxds", 2056 XSCVDPUXWS: "xscvdpuxws", 2057 XSCVSPDP: "xscvspdp", 2058 XSCVSXDDP: "xscvsxddp", 2059 XSCVUXDDP: "xscvuxddp", 2060 XSDIVDP: "xsdivdp", 2061 XSMADDADP: "xsmaddadp", 2062 XSMADDMDP: "xsmaddmdp", 2063 XSMAXDP: "xsmaxdp", 2064 XSMINDP: "xsmindp", 2065 XSMSUBADP: "xsmsubadp", 2066 XSMSUBMDP: "xsmsubmdp", 2067 XSMULDP: "xsmuldp", 2068 XSNABSDP: "xsnabsdp", 2069 XSNEGDP: "xsnegdp", 2070 XSNMADDADP: "xsnmaddadp", 2071 XSNMADDMDP: "xsnmaddmdp", 2072 XSNMSUBADP: "xsnmsubadp", 2073 XSNMSUBMDP: "xsnmsubmdp", 2074 XSRDPI: "xsrdpi", 2075 XSRDPIC: "xsrdpic", 2076 XSRDPIM: "xsrdpim", 2077 XSRDPIP: "xsrdpip", 2078 XSRDPIZ: "xsrdpiz", 2079 XSREDP: "xsredp", 2080 XSRSQRTEDP: "xsrsqrtedp", 2081 XSSQRTDP: "xssqrtdp", 2082 XSSUBDP: "xssubdp", 2083 XSTDIVDP: "xstdivdp", 2084 XSTSQRTDP: "xstsqrtdp", 2085 XVABSDP: "xvabsdp", 2086 XVABSSP: "xvabssp", 2087 XVADDDP: "xvadddp", 2088 XVADDSP: "xvaddsp", 2089 XVCMPEQDP: "xvcmpeqdp", 2090 XVCMPEQDPCC: "xvcmpeqdp.", 2091 XVCMPEQSP: "xvcmpeqsp", 2092 XVCMPEQSPCC: "xvcmpeqsp.", 2093 XVCMPGEDP: "xvcmpgedp", 2094 XVCMPGEDPCC: "xvcmpgedp.", 2095 XVCMPGESP: "xvcmpgesp", 2096 XVCMPGESPCC: "xvcmpgesp.", 2097 XVCMPGTDP: "xvcmpgtdp", 2098 XVCMPGTDPCC: "xvcmpgtdp.", 2099 XVCMPGTSP: "xvcmpgtsp", 2100 XVCMPGTSPCC: "xvcmpgtsp.", 2101 XVCPSGNDP: "xvcpsgndp", 2102 XVCPSGNSP: "xvcpsgnsp", 2103 XVCVDPSP: "xvcvdpsp", 2104 XVCVDPSXDS: "xvcvdpsxds", 2105 XVCVDPSXWS: "xvcvdpsxws", 2106 XVCVDPUXDS: "xvcvdpuxds", 2107 XVCVDPUXWS: "xvcvdpuxws", 2108 XVCVSPDP: "xvcvspdp", 2109 XVCVSPSXDS: "xvcvspsxds", 2110 XVCVSPSXWS: "xvcvspsxws", 2111 XVCVSPUXDS: "xvcvspuxds", 2112 XVCVSPUXWS: "xvcvspuxws", 2113 XVCVSXDDP: "xvcvsxddp", 2114 XVCVSXDSP: "xvcvsxdsp", 2115 XVCVSXWDP: "xvcvsxwdp", 2116 XVCVSXWSP: "xvcvsxwsp", 2117 XVCVUXDDP: "xvcvuxddp", 2118 XVCVUXDSP: "xvcvuxdsp", 2119 XVCVUXWDP: "xvcvuxwdp", 2120 XVCVUXWSP: "xvcvuxwsp", 2121 XVDIVDP: "xvdivdp", 2122 XVDIVSP: "xvdivsp", 2123 XVMADDADP: "xvmaddadp", 2124 XVMADDASP: "xvmaddasp", 2125 XVMADDMDP: "xvmaddmdp", 2126 XVMADDMSP: "xvmaddmsp", 2127 XVMAXDP: "xvmaxdp", 2128 XVMAXSP: "xvmaxsp", 2129 XVMINDP: "xvmindp", 2130 XVMINSP: "xvminsp", 2131 XVMSUBADP: "xvmsubadp", 2132 XVMSUBASP: "xvmsubasp", 2133 XVMSUBMDP: "xvmsubmdp", 2134 XVMSUBMSP: "xvmsubmsp", 2135 XVMULDP: "xvmuldp", 2136 XVMULSP: "xvmulsp", 2137 XVNABSDP: "xvnabsdp", 2138 XVNABSSP: "xvnabssp", 2139 XVNEGDP: "xvnegdp", 2140 XVNEGSP: "xvnegsp", 2141 XVNMADDADP: "xvnmaddadp", 2142 XVNMADDASP: "xvnmaddasp", 2143 XVNMADDMDP: "xvnmaddmdp", 2144 XVNMADDMSP: "xvnmaddmsp", 2145 XVNMSUBADP: "xvnmsubadp", 2146 XVNMSUBASP: "xvnmsubasp", 2147 XVNMSUBMDP: "xvnmsubmdp", 2148 XVNMSUBMSP: "xvnmsubmsp", 2149 XVRDPI: "xvrdpi", 2150 XVRDPIC: "xvrdpic", 2151 XVRDPIM: "xvrdpim", 2152 XVRDPIP: "xvrdpip", 2153 XVRDPIZ: "xvrdpiz", 2154 XVREDP: "xvredp", 2155 XVRESP: "xvresp", 2156 XVRSPI: "xvrspi", 2157 XVRSPIC: "xvrspic", 2158 XVRSPIM: "xvrspim", 2159 XVRSPIP: "xvrspip", 2160 XVRSPIZ: "xvrspiz", 2161 XVRSQRTEDP: "xvrsqrtedp", 2162 XVRSQRTESP: "xvrsqrtesp", 2163 XVSQRTDP: "xvsqrtdp", 2164 XVSQRTSP: "xvsqrtsp", 2165 XVSUBDP: "xvsubdp", 2166 XVSUBSP: "xvsubsp", 2167 XVTDIVDP: "xvtdivdp", 2168 XVTDIVSP: "xvtdivsp", 2169 XVTSQRTDP: "xvtsqrtdp", 2170 XVTSQRTSP: "xvtsqrtsp", 2171 XXLAND: "xxland", 2172 XXLANDC: "xxlandc", 2173 XXLNOR: "xxlnor", 2174 XXLOR: "xxlor", 2175 XXLXOR: "xxlxor", 2176 XXMRGHW: "xxmrghw", 2177 XXMRGLW: "xxmrglw", 2178 XXPERMDI: "xxpermdi", 2179 XXSEL: "xxsel", 2180 XXSLDWI: "xxsldwi", 2181 XXSPLTW: "xxspltw", 2182 CMPB: "cmpb", 2183 DADD: "dadd", 2184 DADDCC: "dadd.", 2185 DADDQ: "daddq", 2186 DADDQCC: "daddq.", 2187 DCFFIXQ: "dcffixq", 2188 DCFFIXQCC: "dcffixq.", 2189 DCMPO: "dcmpo", 2190 DCMPOQ: "dcmpoq", 2191 DCMPU: "dcmpu", 2192 DCMPUQ: "dcmpuq", 2193 DCTDP: "dctdp", 2194 DCTDPCC: "dctdp.", 2195 DCTFIX: "dctfix", 2196 DCTFIXCC: "dctfix.", 2197 DCTFIXQ: "dctfixq", 2198 DCTFIXQCC: "dctfixq.", 2199 DCTQPQ: "dctqpq", 2200 DCTQPQCC: "dctqpq.", 2201 DDEDPD: "ddedpd", 2202 DDEDPDCC: "ddedpd.", 2203 DDEDPDQ: "ddedpdq", 2204 DDEDPDQCC: "ddedpdq.", 2205 DDIV: "ddiv", 2206 DDIVCC: "ddiv.", 2207 DDIVQ: "ddivq", 2208 DDIVQCC: "ddivq.", 2209 DENBCD: "denbcd", 2210 DENBCDCC: "denbcd.", 2211 DENBCDQ: "denbcdq", 2212 DENBCDQCC: "denbcdq.", 2213 DIEX: "diex", 2214 DIEXCC: "diex.", 2215 DIEXQCC: "diexq.", 2216 DIEXQ: "diexq", 2217 DMUL: "dmul", 2218 DMULCC: "dmul.", 2219 DMULQ: "dmulq", 2220 DMULQCC: "dmulq.", 2221 DQUA: "dqua", 2222 DQUACC: "dqua.", 2223 DQUAI: "dquai", 2224 DQUAICC: "dquai.", 2225 DQUAIQ: "dquaiq", 2226 DQUAIQCC: "dquaiq.", 2227 DQUAQ: "dquaq", 2228 DQUAQCC: "dquaq.", 2229 DRDPQ: "drdpq", 2230 DRDPQCC: "drdpq.", 2231 DRINTN: "drintn", 2232 DRINTNCC: "drintn.", 2233 DRINTNQ: "drintnq", 2234 DRINTNQCC: "drintnq.", 2235 DRINTX: "drintx", 2236 DRINTXCC: "drintx.", 2237 DRINTXQ: "drintxq", 2238 DRINTXQCC: "drintxq.", 2239 DRRND: "drrnd", 2240 DRRNDCC: "drrnd.", 2241 DRRNDQ: "drrndq", 2242 DRRNDQCC: "drrndq.", 2243 DRSP: "drsp", 2244 DRSPCC: "drsp.", 2245 DSCLI: "dscli", 2246 DSCLICC: "dscli.", 2247 DSCLIQ: "dscliq", 2248 DSCLIQCC: "dscliq.", 2249 DSCRI: "dscri", 2250 DSCRICC: "dscri.", 2251 DSCRIQ: "dscriq", 2252 DSCRIQCC: "dscriq.", 2253 DSUB: "dsub", 2254 DSUBCC: "dsub.", 2255 DSUBQ: "dsubq", 2256 DSUBQCC: "dsubq.", 2257 DTSTDC: "dtstdc", 2258 DTSTDCQ: "dtstdcq", 2259 DTSTDG: "dtstdg", 2260 DTSTDGQ: "dtstdgq", 2261 DTSTEX: "dtstex", 2262 DTSTEXQ: "dtstexq", 2263 DTSTSF: "dtstsf", 2264 DTSTSFQ: "dtstsfq", 2265 DXEX: "dxex", 2266 DXEXCC: "dxex.", 2267 DXEXQ: "dxexq", 2268 DXEXQCC: "dxexq.", 2269 FCPSGN: "fcpsgn", 2270 FCPSGNCC: "fcpsgn.", 2271 LBZCIX: "lbzcix", 2272 LDCIX: "ldcix", 2273 LFDP: "lfdp", 2274 LFDPX: "lfdpx", 2275 LFIWAX: "lfiwax", 2276 LHZCIX: "lhzcix", 2277 LWZCIX: "lwzcix", 2278 PRTYD: "prtyd", 2279 PRTYW: "prtyw", 2280 SLBFEECC: "slbfee.", 2281 STBCIX: "stbcix", 2282 STDCIX: "stdcix", 2283 STFDP: "stfdp", 2284 STFDPX: "stfdpx", 2285 STHCIX: "sthcix", 2286 STWCIX: "stwcix", 2287 ISEL: "isel", 2288 LVEBX: "lvebx", 2289 LVEHX: "lvehx", 2290 LVEWX: "lvewx", 2291 LVSL: "lvsl", 2292 LVSR: "lvsr", 2293 LVX: "lvx", 2294 LVXL: "lvxl", 2295 MFVSCR: "mfvscr", 2296 MTVSCR: "mtvscr", 2297 STVEBX: "stvebx", 2298 STVEHX: "stvehx", 2299 STVEWX: "stvewx", 2300 STVX: "stvx", 2301 STVXL: "stvxl", 2302 TLBIEL: "tlbiel", 2303 VADDCUW: "vaddcuw", 2304 VADDFP: "vaddfp", 2305 VADDSBS: "vaddsbs", 2306 VADDSHS: "vaddshs", 2307 VADDSWS: "vaddsws", 2308 VADDUBM: "vaddubm", 2309 VADDUBS: "vaddubs", 2310 VADDUHM: "vadduhm", 2311 VADDUHS: "vadduhs", 2312 VADDUWM: "vadduwm", 2313 VADDUWS: "vadduws", 2314 VAND: "vand", 2315 VANDC: "vandc", 2316 VAVGSB: "vavgsb", 2317 VAVGSH: "vavgsh", 2318 VAVGSW: "vavgsw", 2319 VAVGUB: "vavgub", 2320 VAVGUH: "vavguh", 2321 VAVGUW: "vavguw", 2322 VCFSX: "vcfsx", 2323 VCFUX: "vcfux", 2324 VCMPBFP: "vcmpbfp", 2325 VCMPBFPCC: "vcmpbfp.", 2326 VCMPEQFP: "vcmpeqfp", 2327 VCMPEQFPCC: "vcmpeqfp.", 2328 VCMPEQUB: "vcmpequb", 2329 VCMPEQUBCC: "vcmpequb.", 2330 VCMPEQUH: "vcmpequh", 2331 VCMPEQUHCC: "vcmpequh.", 2332 VCMPEQUW: "vcmpequw", 2333 VCMPEQUWCC: "vcmpequw.", 2334 VCMPGEFP: "vcmpgefp", 2335 VCMPGEFPCC: "vcmpgefp.", 2336 VCMPGTFP: "vcmpgtfp", 2337 VCMPGTFPCC: "vcmpgtfp.", 2338 VCMPGTSB: "vcmpgtsb", 2339 VCMPGTSBCC: "vcmpgtsb.", 2340 VCMPGTSH: "vcmpgtsh", 2341 VCMPGTSHCC: "vcmpgtsh.", 2342 VCMPGTSW: "vcmpgtsw", 2343 VCMPGTSWCC: "vcmpgtsw.", 2344 VCMPGTUB: "vcmpgtub", 2345 VCMPGTUBCC: "vcmpgtub.", 2346 VCMPGTUH: "vcmpgtuh", 2347 VCMPGTUHCC: "vcmpgtuh.", 2348 VCMPGTUW: "vcmpgtuw", 2349 VCMPGTUWCC: "vcmpgtuw.", 2350 VCTSXS: "vctsxs", 2351 VCTUXS: "vctuxs", 2352 VEXPTEFP: "vexptefp", 2353 VLOGEFP: "vlogefp", 2354 VMADDFP: "vmaddfp", 2355 VMAXFP: "vmaxfp", 2356 VMAXSB: "vmaxsb", 2357 VMAXSH: "vmaxsh", 2358 VMAXSW: "vmaxsw", 2359 VMAXUB: "vmaxub", 2360 VMAXUH: "vmaxuh", 2361 VMAXUW: "vmaxuw", 2362 VMHADDSHS: "vmhaddshs", 2363 VMHRADDSHS: "vmhraddshs", 2364 VMINFP: "vminfp", 2365 VMINSB: "vminsb", 2366 VMINSH: "vminsh", 2367 VMINSW: "vminsw", 2368 VMINUB: "vminub", 2369 VMINUH: "vminuh", 2370 VMINUW: "vminuw", 2371 VMLADDUHM: "vmladduhm", 2372 VMRGHB: "vmrghb", 2373 VMRGHH: "vmrghh", 2374 VMRGHW: "vmrghw", 2375 VMRGLB: "vmrglb", 2376 VMRGLH: "vmrglh", 2377 VMRGLW: "vmrglw", 2378 VMSUMMBM: "vmsummbm", 2379 VMSUMSHM: "vmsumshm", 2380 VMSUMSHS: "vmsumshs", 2381 VMSUMUBM: "vmsumubm", 2382 VMSUMUHM: "vmsumuhm", 2383 VMSUMUHS: "vmsumuhs", 2384 VMULESB: "vmulesb", 2385 VMULESH: "vmulesh", 2386 VMULEUB: "vmuleub", 2387 VMULEUH: "vmuleuh", 2388 VMULOSB: "vmulosb", 2389 VMULOSH: "vmulosh", 2390 VMULOUB: "vmuloub", 2391 VMULOUH: "vmulouh", 2392 VNMSUBFP: "vnmsubfp", 2393 VNOR: "vnor", 2394 VOR: "vor", 2395 VPERM: "vperm", 2396 VPKPX: "vpkpx", 2397 VPKSHSS: "vpkshss", 2398 VPKSHUS: "vpkshus", 2399 VPKSWSS: "vpkswss", 2400 VPKSWUS: "vpkswus", 2401 VPKUHUM: "vpkuhum", 2402 VPKUHUS: "vpkuhus", 2403 VPKUWUM: "vpkuwum", 2404 VPKUWUS: "vpkuwus", 2405 VREFP: "vrefp", 2406 VRFIM: "vrfim", 2407 VRFIN: "vrfin", 2408 VRFIP: "vrfip", 2409 VRFIZ: "vrfiz", 2410 VRLB: "vrlb", 2411 VRLH: "vrlh", 2412 VRLW: "vrlw", 2413 VRSQRTEFP: "vrsqrtefp", 2414 VSEL: "vsel", 2415 VSL: "vsl", 2416 VSLB: "vslb", 2417 VSLDOI: "vsldoi", 2418 VSLH: "vslh", 2419 VSLO: "vslo", 2420 VSLW: "vslw", 2421 VSPLTB: "vspltb", 2422 VSPLTH: "vsplth", 2423 VSPLTISB: "vspltisb", 2424 VSPLTISH: "vspltish", 2425 VSPLTISW: "vspltisw", 2426 VSPLTW: "vspltw", 2427 VSR: "vsr", 2428 VSRAB: "vsrab", 2429 VSRAH: "vsrah", 2430 VSRAW: "vsraw", 2431 VSRB: "vsrb", 2432 VSRH: "vsrh", 2433 VSRO: "vsro", 2434 VSRW: "vsrw", 2435 VSUBCUW: "vsubcuw", 2436 VSUBFP: "vsubfp", 2437 VSUBSBS: "vsubsbs", 2438 VSUBSHS: "vsubshs", 2439 VSUBSWS: "vsubsws", 2440 VSUBUBM: "vsububm", 2441 VSUBUBS: "vsububs", 2442 VSUBUHM: "vsubuhm", 2443 VSUBUHS: "vsubuhs", 2444 VSUBUWM: "vsubuwm", 2445 VSUBUWS: "vsubuws", 2446 VSUM2SWS: "vsum2sws", 2447 VSUM4SBS: "vsum4sbs", 2448 VSUM4SHS: "vsum4shs", 2449 VSUM4UBS: "vsum4ubs", 2450 VSUMSWS: "vsumsws", 2451 VUPKHPX: "vupkhpx", 2452 VUPKHSB: "vupkhsb", 2453 VUPKHSH: "vupkhsh", 2454 VUPKLPX: "vupklpx", 2455 VUPKLSB: "vupklsb", 2456 VUPKLSH: "vupklsh", 2457 VXOR: "vxor", 2458 FRE: "fre", 2459 FRECC: "fre.", 2460 FRIM: "frim", 2461 FRIMCC: "frim.", 2462 FRIN: "frin", 2463 FRINCC: "frin.", 2464 FRIP: "frip", 2465 FRIPCC: "frip.", 2466 FRIZ: "friz", 2467 FRIZCC: "friz.", 2468 FRSQRTES: "frsqrtes", 2469 FRSQRTESCC: "frsqrtes.", 2470 HRFID: "hrfid", 2471 POPCNTB: "popcntb", 2472 MFOCRF: "mfocrf", 2473 MTOCRF: "mtocrf", 2474 SLBMFEE: "slbmfee", 2475 SLBMFEV: "slbmfev", 2476 SLBMTE: "slbmte", 2477 RFSCV: "rfscv", 2478 SCV: "scv", 2479 LQ: "lq", 2480 STQ: "stq", 2481 CNTLZD: "cntlzd", 2482 CNTLZDCC: "cntlzd.", 2483 DCBF: "dcbf", 2484 DCBST: "dcbst", 2485 DCBT: "dcbt", 2486 DCBTST: "dcbtst", 2487 DIVD: "divd", 2488 DIVDCC: "divd.", 2489 DIVDO: "divdo", 2490 DIVDOCC: "divdo.", 2491 DIVDU: "divdu", 2492 DIVDUCC: "divdu.", 2493 DIVDUO: "divduo", 2494 DIVDUOCC: "divduo.", 2495 DIVW: "divw", 2496 DIVWCC: "divw.", 2497 DIVWO: "divwo", 2498 DIVWOCC: "divwo.", 2499 DIVWU: "divwu", 2500 DIVWUCC: "divwu.", 2501 DIVWUO: "divwuo", 2502 DIVWUOCC: "divwuo.", 2503 EIEIO: "eieio", 2504 EXTSB: "extsb", 2505 EXTSBCC: "extsb.", 2506 EXTSW: "extsw", 2507 EXTSWCC: "extsw.", 2508 FADDS: "fadds", 2509 FADDSCC: "fadds.", 2510 FCFID: "fcfid", 2511 FCFIDCC: "fcfid.", 2512 FCTID: "fctid", 2513 FCTIDCC: "fctid.", 2514 FCTIDZ: "fctidz", 2515 FCTIDZCC: "fctidz.", 2516 FDIVS: "fdivs", 2517 FDIVSCC: "fdivs.", 2518 FMADDS: "fmadds", 2519 FMADDSCC: "fmadds.", 2520 FMSUBS: "fmsubs", 2521 FMSUBSCC: "fmsubs.", 2522 FMULS: "fmuls", 2523 FMULSCC: "fmuls.", 2524 FNMADDS: "fnmadds", 2525 FNMADDSCC: "fnmadds.", 2526 FNMSUBS: "fnmsubs", 2527 FNMSUBSCC: "fnmsubs.", 2528 FRES: "fres", 2529 FRESCC: "fres.", 2530 FRSQRTE: "frsqrte", 2531 FRSQRTECC: "frsqrte.", 2532 FSEL: "fsel", 2533 FSELCC: "fsel.", 2534 FSQRTS: "fsqrts", 2535 FSQRTSCC: "fsqrts.", 2536 FSUBS: "fsubs", 2537 FSUBSCC: "fsubs.", 2538 ICBI: "icbi", 2539 LD: "ld", 2540 LDARX: "ldarx", 2541 LDU: "ldu", 2542 LDUX: "ldux", 2543 LDX: "ldx", 2544 LWA: "lwa", 2545 LWARX: "lwarx", 2546 LWAUX: "lwaux", 2547 LWAX: "lwax", 2548 MFTB: "mftb", 2549 MTMSRD: "mtmsrd", 2550 MULHD: "mulhd", 2551 MULHDCC: "mulhd.", 2552 MULHDU: "mulhdu", 2553 MULHDUCC: "mulhdu.", 2554 MULHW: "mulhw", 2555 MULHWCC: "mulhw.", 2556 MULHWU: "mulhwu", 2557 MULHWUCC: "mulhwu.", 2558 MULLD: "mulld", 2559 MULLDCC: "mulld.", 2560 MULLDO: "mulldo", 2561 MULLDOCC: "mulldo.", 2562 RFID: "rfid", 2563 RLDCL: "rldcl", 2564 RLDCLCC: "rldcl.", 2565 RLDCR: "rldcr", 2566 RLDCRCC: "rldcr.", 2567 RLDIC: "rldic", 2568 RLDICCC: "rldic.", 2569 RLDICL: "rldicl", 2570 RLDICLCC: "rldicl.", 2571 RLDICR: "rldicr", 2572 RLDICRCC: "rldicr.", 2573 RLDIMI: "rldimi", 2574 RLDIMICC: "rldimi.", 2575 SC: "sc", 2576 SLBIA: "slbia", 2577 SLBIE: "slbie", 2578 SLD: "sld", 2579 SLDCC: "sld.", 2580 SRAD: "srad", 2581 SRADCC: "srad.", 2582 SRADI: "sradi", 2583 SRADICC: "sradi.", 2584 SRD: "srd", 2585 SRDCC: "srd.", 2586 STD: "std", 2587 STDCXCC: "stdcx.", 2588 STDU: "stdu", 2589 STDUX: "stdux", 2590 STDX: "stdx", 2591 STFIWX: "stfiwx", 2592 STWCXCC: "stwcx.", 2593 SUBF: "subf", 2594 SUBFCC: "subf.", 2595 SUBFO: "subfo", 2596 SUBFOCC: "subfo.", 2597 TD: "td", 2598 TDI: "tdi", 2599 TLBSYNC: "tlbsync", 2600 FCTIW: "fctiw", 2601 FCTIWCC: "fctiw.", 2602 FCTIWZ: "fctiwz", 2603 FCTIWZCC: "fctiwz.", 2604 FSQRT: "fsqrt", 2605 FSQRTCC: "fsqrt.", 2606 ADD: "add", 2607 ADDCC: "add.", 2608 ADDO: "addo", 2609 ADDOCC: "addo.", 2610 ADDC: "addc", 2611 ADDCCC: "addc.", 2612 ADDCO: "addco", 2613 ADDCOCC: "addco.", 2614 ADDE: "adde", 2615 ADDECC: "adde.", 2616 ADDEO: "addeo", 2617 ADDEOCC: "addeo.", 2618 LI: "li", 2619 ADDI: "addi", 2620 ADDIC: "addic", 2621 ADDICCC: "addic.", 2622 LIS: "lis", 2623 ADDIS: "addis", 2624 ADDME: "addme", 2625 ADDMECC: "addme.", 2626 ADDMEO: "addmeo", 2627 ADDMEOCC: "addmeo.", 2628 ADDZE: "addze", 2629 ADDZECC: "addze.", 2630 ADDZEO: "addzeo", 2631 ADDZEOCC: "addzeo.", 2632 AND: "and", 2633 ANDCC: "and.", 2634 ANDC: "andc", 2635 ANDCCC: "andc.", 2636 ANDICC: "andi.", 2637 ANDISCC: "andis.", 2638 B: "b", 2639 BA: "ba", 2640 BL: "bl", 2641 BLA: "bla", 2642 BC: "bc", 2643 BCA: "bca", 2644 BCL: "bcl", 2645 BCLA: "bcla", 2646 BCCTR: "bcctr", 2647 BCCTRL: "bcctrl", 2648 BCLR: "bclr", 2649 BCLRL: "bclrl", 2650 CMPW: "cmpw", 2651 CMPD: "cmpd", 2652 CMP: "cmp", 2653 CMPWI: "cmpwi", 2654 CMPDI: "cmpdi", 2655 CMPI: "cmpi", 2656 CMPLW: "cmplw", 2657 CMPLD: "cmpld", 2658 CMPL: "cmpl", 2659 CMPLWI: "cmplwi", 2660 CMPLDI: "cmpldi", 2661 CMPLI: "cmpli", 2662 CNTLZW: "cntlzw", 2663 CNTLZWCC: "cntlzw.", 2664 CRAND: "crand", 2665 CRANDC: "crandc", 2666 CREQV: "creqv", 2667 CRNAND: "crnand", 2668 CRNOR: "crnor", 2669 CROR: "cror", 2670 CRORC: "crorc", 2671 CRXOR: "crxor", 2672 DCBZ: "dcbz", 2673 EQV: "eqv", 2674 EQVCC: "eqv.", 2675 EXTSH: "extsh", 2676 EXTSHCC: "extsh.", 2677 FABS: "fabs", 2678 FABSCC: "fabs.", 2679 FADD: "fadd", 2680 FADDCC: "fadd.", 2681 FCMPO: "fcmpo", 2682 FCMPU: "fcmpu", 2683 FDIV: "fdiv", 2684 FDIVCC: "fdiv.", 2685 FMADD: "fmadd", 2686 FMADDCC: "fmadd.", 2687 FMR: "fmr", 2688 FMRCC: "fmr.", 2689 FMSUB: "fmsub", 2690 FMSUBCC: "fmsub.", 2691 FMUL: "fmul", 2692 FMULCC: "fmul.", 2693 FNABS: "fnabs", 2694 FNABSCC: "fnabs.", 2695 FNEG: "fneg", 2696 FNEGCC: "fneg.", 2697 FNMADD: "fnmadd", 2698 FNMADDCC: "fnmadd.", 2699 FNMSUB: "fnmsub", 2700 FNMSUBCC: "fnmsub.", 2701 FRSP: "frsp", 2702 FRSPCC: "frsp.", 2703 FSUB: "fsub", 2704 FSUBCC: "fsub.", 2705 ISYNC: "isync", 2706 LBZ: "lbz", 2707 LBZU: "lbzu", 2708 LBZUX: "lbzux", 2709 LBZX: "lbzx", 2710 LFD: "lfd", 2711 LFDU: "lfdu", 2712 LFDUX: "lfdux", 2713 LFDX: "lfdx", 2714 LFS: "lfs", 2715 LFSU: "lfsu", 2716 LFSUX: "lfsux", 2717 LFSX: "lfsx", 2718 LHA: "lha", 2719 LHAU: "lhau", 2720 LHAUX: "lhaux", 2721 LHAX: "lhax", 2722 LHBRX: "lhbrx", 2723 LHZ: "lhz", 2724 LHZU: "lhzu", 2725 LHZUX: "lhzux", 2726 LHZX: "lhzx", 2727 LMW: "lmw", 2728 LSWI: "lswi", 2729 LSWX: "lswx", 2730 LWBRX: "lwbrx", 2731 LWZ: "lwz", 2732 LWZU: "lwzu", 2733 LWZUX: "lwzux", 2734 LWZX: "lwzx", 2735 MCRF: "mcrf", 2736 MCRFS: "mcrfs", 2737 MFCR: "mfcr", 2738 MFFS: "mffs", 2739 MFFSCC: "mffs.", 2740 MFMSR: "mfmsr", 2741 MFSPR: "mfspr", 2742 MTCRF: "mtcrf", 2743 MTFSB0: "mtfsb0", 2744 MTFSB0CC: "mtfsb0.", 2745 MTFSB1: "mtfsb1", 2746 MTFSB1CC: "mtfsb1.", 2747 MTFSF: "mtfsf", 2748 MTFSFCC: "mtfsf.", 2749 MTFSFI: "mtfsfi", 2750 MTFSFICC: "mtfsfi.", 2751 MTMSR: "mtmsr", 2752 MTSPR: "mtspr", 2753 MULLI: "mulli", 2754 MULLW: "mullw", 2755 MULLWCC: "mullw.", 2756 MULLWO: "mullwo", 2757 MULLWOCC: "mullwo.", 2758 NAND: "nand", 2759 NANDCC: "nand.", 2760 NEG: "neg", 2761 NEGCC: "neg.", 2762 NEGO: "nego", 2763 NEGOCC: "nego.", 2764 NOR: "nor", 2765 NORCC: "nor.", 2766 OR: "or", 2767 ORCC: "or.", 2768 ORC: "orc", 2769 ORCCC: "orc.", 2770 NOP: "nop", 2771 ORI: "ori", 2772 ORIS: "oris", 2773 RLWIMI: "rlwimi", 2774 RLWIMICC: "rlwimi.", 2775 RLWINM: "rlwinm", 2776 RLWINMCC: "rlwinm.", 2777 RLWNM: "rlwnm", 2778 RLWNMCC: "rlwnm.", 2779 SLW: "slw", 2780 SLWCC: "slw.", 2781 SRAW: "sraw", 2782 SRAWCC: "sraw.", 2783 SRAWI: "srawi", 2784 SRAWICC: "srawi.", 2785 SRW: "srw", 2786 SRWCC: "srw.", 2787 STB: "stb", 2788 STBU: "stbu", 2789 STBUX: "stbux", 2790 STBX: "stbx", 2791 STFD: "stfd", 2792 STFDU: "stfdu", 2793 STFDUX: "stfdux", 2794 STFDX: "stfdx", 2795 STFS: "stfs", 2796 STFSU: "stfsu", 2797 STFSUX: "stfsux", 2798 STFSX: "stfsx", 2799 STH: "sth", 2800 STHBRX: "sthbrx", 2801 STHU: "sthu", 2802 STHUX: "sthux", 2803 STHX: "sthx", 2804 STMW: "stmw", 2805 STSWI: "stswi", 2806 STSWX: "stswx", 2807 STW: "stw", 2808 STWBRX: "stwbrx", 2809 STWU: "stwu", 2810 STWUX: "stwux", 2811 STWX: "stwx", 2812 SUBFC: "subfc", 2813 SUBFCCC: "subfc.", 2814 SUBFCO: "subfco", 2815 SUBFCOCC: "subfco.", 2816 SUBFE: "subfe", 2817 SUBFECC: "subfe.", 2818 SUBFEO: "subfeo", 2819 SUBFEOCC: "subfeo.", 2820 SUBFIC: "subfic", 2821 SUBFME: "subfme", 2822 SUBFMECC: "subfme.", 2823 SUBFMEO: "subfmeo", 2824 SUBFMEOCC: "subfmeo.", 2825 SUBFZE: "subfze", 2826 SUBFZECC: "subfze.", 2827 SUBFZEO: "subfzeo", 2828 SUBFZEOCC: "subfzeo.", 2829 SYNC: "sync", 2830 TLBIE: "tlbie", 2831 TW: "tw", 2832 TWI: "twi", 2833 XOR: "xor", 2834 XORCC: "xor.", 2835 XORI: "xori", 2836 XORIS: "xoris", 2837} 2838 2839var ( 2840 ap_Reg_11_15 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{11, 5, 0}}} 2841 ap_Reg_6_10 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{6, 5, 0}}} 2842 ap_Reg_16_20 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{16, 5, 0}}} 2843 ap_FPReg_6_10 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{6, 5, 0}}} 2844 ap_VecReg_16_20 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{16, 5, 0}}} 2845 ap_VecReg_6_10 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{6, 5, 0}}} 2846 ap_FPReg_16_20 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{16, 5, 0}}} 2847 ap_VecSReg_31_31_6_10 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{31, 1, 0}, {6, 5, 0}}} 2848 ap_ImmUnsigned_16_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 5, 0}}} 2849 ap_VecSpReg_10_10_6_9 = &argField{Type: TypeVecSpReg, Shift: 0, BitFields: BitFields{{10, 1, 0}, {6, 4, 0}}} 2850 ap_Offset_16_27_shift4 = &argField{Type: TypeOffset, Shift: 4, BitFields: BitFields{{16, 12, 0}}} 2851 ap_ImmUnsigned_16_25_11_15_31_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 10, 0}, {11, 5, 0}, {31, 1, 0}}} 2852 ap_Reg_38_42 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{6, 5, 1}}} 2853 ap_Reg_43_47 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{11, 5, 1}}} 2854 ap_ImmSigned_14_31_48_63 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{14, 18, 0}, {16, 16, 1}}} 2855 ap_ImmUnsigned_11_11 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 1, 0}}} 2856 ap_Offset_14_31_48_63 = &argField{Type: TypeOffset, Shift: 0, BitFields: BitFields{{14, 18, 0}, {16, 16, 1}}} 2857 ap_FPReg_38_42 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{6, 5, 1}}} 2858 ap_VecReg_38_42 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{6, 5, 1}}} 2859 ap_VecSReg_37_37_38_42 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{5, 1, 1}, {6, 5, 1}}} 2860 ap_VecSpReg_42_42_38_41 = &argField{Type: TypeVecSpReg, Shift: 0, BitFields: BitFields{{10, 1, 1}, {6, 4, 1}}} 2861 ap_MMAReg_38_40 = &argField{Type: TypeMMAReg, Shift: 0, BitFields: BitFields{{6, 3, 1}}} 2862 ap_VecSReg_61_61_43_47 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{29, 1, 1}, {11, 5, 1}}} 2863 ap_VecSReg_62_62_48_52 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{30, 1, 1}, {16, 5, 1}}} 2864 ap_ImmUnsigned_24_27 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{24, 4, 0}}} 2865 ap_ImmUnsigned_28_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{28, 4, 0}}} 2866 ap_ImmUnsigned_16_17 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 2, 0}}} 2867 ap_ImmUnsigned_28_29 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{28, 2, 0}}} 2868 ap_ImmUnsigned_16_23 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 8, 0}}} 2869 ap_ImmUnsigned_16_19 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 4, 0}}} 2870 ap_CondRegBit_11_15 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{11, 5, 0}}} 2871 ap_VecReg_11_15 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{11, 5, 0}}} 2872 ap_CondRegField_6_8 = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{6, 3, 0}}} 2873 ap_ImmUnsigned_15_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{15, 1, 0}}} 2874 ap_Reg_21_25 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{21, 5, 0}}} 2875 ap_ImmUnsigned_13_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{13, 3, 0}}} 2876 ap_ImmUnsigned_12_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 4, 0}}} 2877 ap_VecReg_21_25 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{21, 5, 0}}} 2878 ap_ImmUnsigned_23_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{23, 3, 0}}} 2879 ap_MMAReg_6_8 = &argField{Type: TypeMMAReg, Shift: 0, BitFields: BitFields{{6, 3, 0}}} 2880 ap_VecSReg_29_29_11_15 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{29, 1, 0}, {11, 5, 0}}} 2881 ap_VecSReg_30_30_16_20 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{30, 1, 0}, {16, 5, 0}}} 2882 ap_VecSReg_63_63_38_42 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{31, 1, 1}, {6, 5, 1}}} 2883 ap_VecSReg_60_60_53_57 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{28, 1, 1}, {21, 5, 1}}} 2884 ap_ImmUnsigned_24_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{24, 8, 0}}} 2885 ap_ImmUnsigned_11_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 5, 0}}} 2886 ap_ImmUnsigned_29_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{29, 3, 0}}} 2887 ap_VecSReg_47_47_38_42 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{15, 1, 1}, {6, 5, 1}}} 2888 ap_ImmUnsigned_46_46 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{14, 1, 1}}} 2889 ap_ImmUnsigned_16_31_48_63 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 16, 0}, {16, 16, 1}}} 2890 ap_ImmUnsigned_21_22 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 2, 0}}} 2891 ap_ImmUnsigned_18_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{18, 3, 0}}} 2892 ap_ImmUnsigned_19_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{19, 2, 0}}} 2893 ap_ImmSigned_16_25_11_15_31_31 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 10, 0}, {11, 5, 0}, {31, 1, 0}}} 2894 ap_ImmUnsigned_22_22 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 1, 0}}} 2895 ap_ImmUnsigned_10_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{10, 1, 0}}} 2896 ap_ImmUnsigned_14_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{14, 2, 0}}} 2897 ap_ImmUnsigned_10_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{10, 6, 0}}} 2898 ap_ImmUnsigned_30_30_16_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{30, 1, 0}, {16, 5, 0}}} 2899 ap_Offset_16_29_shift2 = &argField{Type: TypeOffset, Shift: 2, BitFields: BitFields{{16, 14, 0}}} 2900 ap_VecSReg_28_28_6_10 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{28, 1, 0}, {6, 5, 0}}} 2901 ap_CondRegField_11_13 = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{11, 3, 0}}} 2902 ap_ImmUnsigned_9_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{9, 2, 0}}} 2903 ap_ImmUnsigned_9_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{9, 7, 0}}} 2904 ap_ImmUnsigned_25_25_29_29_11_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{25, 1, 0}, {29, 1, 0}, {11, 5, 0}}} 2905 ap_ImmUnsigned_13_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{13, 8, 0}}} 2906 ap_ImmUnsigned_6_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 5, 0}}} 2907 ap_FPReg_11_15 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{11, 5, 0}}} 2908 ap_ImmUnsigned_7_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 4, 0}}} 2909 ap_ImmUnsigned_31_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{31, 1, 0}}} 2910 ap_SpReg_11_20 = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{11, 10, 0}}} 2911 ap_ImmUnsigned_20_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 1, 0}}} 2912 ap_ImmUnsigned_16_16 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 1, 0}}} 2913 ap_ImmUnsigned_17_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{17, 4, 0}}} 2914 ap_ImmUnsigned_22_23 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 2, 0}}} 2915 ap_VecSReg_28_28_21_25 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{28, 1, 0}, {21, 5, 0}}} 2916 ap_ImmUnsigned_11_12 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 2, 0}}} 2917 ap_ImmSigned_11_15 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{11, 5, 0}}} 2918 ap_ImmUnsigned_16_21 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 6, 0}}} 2919 ap_CondRegBit_21_25 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{21, 5, 0}}} 2920 ap_ImmUnsigned_12_13 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 2, 0}}} 2921 ap_ImmUnsigned_14_14 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{14, 1, 0}}} 2922 ap_ImmUnsigned_22_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 4, 0}}} 2923 ap_ImmUnsigned_12_19 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 8, 0}}} 2924 ap_ImmUnsigned_20_26 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 7, 0}}} 2925 ap_ImmUnsigned_8_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{8, 3, 0}}} 2926 ap_FPReg_21_25 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{21, 5, 0}}} 2927 ap_SpReg_16_20_11_15 = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{16, 5, 0}, {11, 5, 0}}} 2928 ap_ImmUnsigned_26_26_21_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 1, 0}, {21, 5, 0}}} 2929 ap_ImmSigned_16_31 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 16, 0}}} 2930 ap_ImmUnsigned_16_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 16, 0}}} 2931 ap_PCRel_6_29_shift2 = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{6, 24, 0}}} 2932 ap_Label_6_29_shift2 = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{6, 24, 0}}} 2933 ap_PCRel_16_29_shift2 = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{16, 14, 0}}} 2934 ap_Label_16_29_shift2 = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{16, 14, 0}}} 2935 ap_CondRegBit_6_10 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{6, 5, 0}}} 2936 ap_CondRegBit_16_20 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{16, 5, 0}}} 2937 ap_Offset_16_31 = &argField{Type: TypeOffset, Shift: 0, BitFields: BitFields{{16, 16, 0}}} 2938 ap_ImmUnsigned_7_14 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 8, 0}}} 2939 ap_ImmUnsigned_6_6 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 1, 0}}} 2940 ap_ImmUnsigned_6_8 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 3, 0}}} 2941 ap_ImmUnsigned_21_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 5, 0}}} 2942 ap_ImmUnsigned_26_30 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 5, 0}}} 2943) 2944 2945var instFormats = [...]instFormat{ 2946 {BRD, 0xfc0007fe00000000, 0x7c00017600000000, 0xf80100000000, // Byte-Reverse Doubleword X-form (brd RA,RS) 2947 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 2948 {BRH, 0xfc0007fe00000000, 0x7c0001b600000000, 0xf80100000000, // Byte-Reverse Halfword X-form (brh RA,RS) 2949 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 2950 {BRW, 0xfc0007fe00000000, 0x7c00013600000000, 0xf80100000000, // Byte-Reverse Word X-form (brw RA,RS) 2951 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 2952 {CFUGED, 0xfc0007fe00000000, 0x7c0001b800000000, 0x100000000, // Centrifuge Doubleword X-form (cfuged RA,RS,RB) 2953 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 2954 {CNTLZDM, 0xfc0007fe00000000, 0x7c00007600000000, 0x100000000, // Count Leading Zeros Doubleword under bit Mask X-form (cntlzdm RA,RS,RB) 2955 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 2956 {CNTTZDM, 0xfc0007fe00000000, 0x7c00047600000000, 0x100000000, // Count Trailing Zeros Doubleword under bit Mask X-form (cnttzdm RA,RS,RB) 2957 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 2958 {DCFFIXQQ, 0xfc1f07fe00000000, 0xfc0007c400000000, 0x100000000, // DFP Convert From Fixed Quadword Quad X-form (dcffixqq FRTp,VRB) 2959 [6]*argField{ap_FPReg_6_10, ap_VecReg_16_20}}, 2960 {DCTFIXQQ, 0xfc1f07fe00000000, 0xfc0107c400000000, 0x100000000, // DFP Convert To Fixed Quadword Quad X-form (dctfixqq VRT,FRBp) 2961 [6]*argField{ap_VecReg_6_10, ap_FPReg_16_20}}, 2962 {LXVKQ, 0xfc1f07fe00000000, 0xf01f02d000000000, 0x0, // Load VSX Vector Special Value Quadword X-form (lxvkq XT,UIM) 2963 [6]*argField{ap_VecSReg_31_31_6_10, ap_ImmUnsigned_16_20}}, 2964 {LXVP, 0xfc00000f00000000, 0x1800000000000000, 0x0, // Load VSX Vector Paired DQ-form (lxvp XTp,DQ(RA)) 2965 [6]*argField{ap_VecSpReg_10_10_6_9, ap_Offset_16_27_shift4, ap_Reg_11_15}}, 2966 {LXVPX, 0xfc0007fe00000000, 0x7c00029a00000000, 0x100000000, // Load VSX Vector Paired Indexed X-form (lxvpx XTp,RA,RB) 2967 [6]*argField{ap_VecSpReg_10_10_6_9, ap_Reg_11_15, ap_Reg_16_20}}, 2968 {LXVRBX, 0xfc0007fe00000000, 0x7c00001a00000000, 0x0, // Load VSX Vector Rightmost Byte Indexed X-form (lxvrbx XT,RA,RB) 2969 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2970 {LXVRDX, 0xfc0007fe00000000, 0x7c0000da00000000, 0x0, // Load VSX Vector Rightmost Doubleword Indexed X-form (lxvrdx XT,RA,RB) 2971 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2972 {LXVRHX, 0xfc0007fe00000000, 0x7c00005a00000000, 0x0, // Load VSX Vector Rightmost Halfword Indexed X-form (lxvrhx XT,RA,RB) 2973 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2974 {LXVRWX, 0xfc0007fe00000000, 0x7c00009a00000000, 0x0, // Load VSX Vector Rightmost Word Indexed X-form (lxvrwx XT,RA,RB) 2975 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2976 {MTVSRBM, 0xfc1f07ff00000000, 0x1010064200000000, 0x0, // Move to VSR Byte Mask VX-form (mtvsrbm VRT,RB) 2977 [6]*argField{ap_VecReg_6_10, ap_Reg_16_20}}, 2978 {MTVSRBMI, 0xfc00003e00000000, 0x1000001400000000, 0x0, // Move To VSR Byte Mask Immediate DX-form (mtvsrbmi VRT,bm) 2979 [6]*argField{ap_VecReg_6_10, ap_ImmUnsigned_16_25_11_15_31_31}}, 2980 {MTVSRDM, 0xfc1f07ff00000000, 0x1013064200000000, 0x0, // Move to VSR Doubleword Mask VX-form (mtvsrdm VRT,RB) 2981 [6]*argField{ap_VecReg_6_10, ap_Reg_16_20}}, 2982 {MTVSRHM, 0xfc1f07ff00000000, 0x1011064200000000, 0x0, // Move to VSR Halfword Mask VX-form (mtvsrhm VRT,RB) 2983 [6]*argField{ap_VecReg_6_10, ap_Reg_16_20}}, 2984 {MTVSRQM, 0xfc1f07ff00000000, 0x1014064200000000, 0x0, // Move to VSR Quadword Mask VX-form (mtvsrqm VRT,RB) 2985 [6]*argField{ap_VecReg_6_10, ap_Reg_16_20}}, 2986 {MTVSRWM, 0xfc1f07ff00000000, 0x1012064200000000, 0x0, // Move to VSR Word Mask VX-form (mtvsrwm VRT,RB) 2987 [6]*argField{ap_VecReg_6_10, ap_Reg_16_20}}, 2988 {PADDI, 0xff800000fc000000, 0x600000038000000, 0x6c000000000000, // Prefixed Add Immediate MLS:D-form (paddi RT,RA,SI,R) 2989 [6]*argField{ap_Reg_38_42, ap_Reg_43_47, ap_ImmSigned_14_31_48_63, ap_ImmUnsigned_11_11}}, 2990 {PDEPD, 0xfc0007fe00000000, 0x7c00013800000000, 0x100000000, // Parallel Bits Deposit Doubleword X-form (pdepd RA,RS,RB) 2991 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 2992 {PEXTD, 0xfc0007fe00000000, 0x7c00017800000000, 0x100000000, // Parallel Bits Extract Doubleword X-form (pextd RA,RS,RB) 2993 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 2994 {PLBZ, 0xff800000fc000000, 0x600000088000000, 0x6c000000000000, // Prefixed Load Byte and Zero MLS:D-form (plbz RT,D(RA),R) 2995 [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 2996 {PLD, 0xff800000fc000000, 0x4000000e4000000, 0x6c000000000000, // Prefixed Load Doubleword 8LS:D-form (pld RT,D(RA),R) 2997 [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 2998 {PLFD, 0xff800000fc000000, 0x6000000c8000000, 0x6c000000000000, // Prefixed Load Floating-Point Double MLS:D-form (plfd FRT,D(RA),R) 2999 [6]*argField{ap_FPReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3000 {PLFS, 0xff800000fc000000, 0x6000000c0000000, 0x6c000000000000, // Prefixed Load Floating-Point Single MLS:D-form (plfs FRT,D(RA),R) 3001 [6]*argField{ap_FPReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3002 {PLHA, 0xff800000fc000000, 0x6000000a8000000, 0x6c000000000000, // Prefixed Load Halfword Algebraic MLS:D-form (plha RT,D(RA),R) 3003 [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3004 {PLHZ, 0xff800000fc000000, 0x6000000a0000000, 0x6c000000000000, // Prefixed Load Halfword and Zero MLS:D-form (plhz RT,D(RA),R) 3005 [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3006 {PLQ, 0xff800000fc000000, 0x4000000e0000000, 0x6c000000000000, // Prefixed Load Quadword 8LS:D-form (plq RTp,D(RA),R) 3007 [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3008 {PLWA, 0xff800000fc000000, 0x4000000a4000000, 0x6c000000000000, // Prefixed Load Word Algebraic 8LS:D-form (plwa RT,D(RA),R) 3009 [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3010 {PLWZ, 0xff800000fc000000, 0x600000080000000, 0x6c000000000000, // Prefixed Load Word and Zero MLS:D-form (plwz RT,D(RA),R) 3011 [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3012 {PLXSD, 0xff800000fc000000, 0x4000000a8000000, 0x6c000000000000, // Prefixed Load VSX Scalar Doubleword 8LS:D-form (plxsd VRT,D(RA),R) 3013 [6]*argField{ap_VecReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3014 {PLXSSP, 0xff800000fc000000, 0x4000000ac000000, 0x6c000000000000, // Prefixed Load VSX Scalar Single-Precision 8LS:D-form (plxssp VRT,D(RA),R) 3015 [6]*argField{ap_VecReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3016 {PLXV, 0xff800000f8000000, 0x4000000c8000000, 0x6c000000000000, // Prefixed Load VSX Vector 8LS:D-form (plxv XT,D(RA),R) 3017 [6]*argField{ap_VecSReg_37_37_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3018 {PLXVP, 0xff800000fc000000, 0x4000000e8000000, 0x6c000000000000, // Prefixed Load VSX Vector Paired 8LS:D-form (plxvp XTp,D(RA),R) 3019 [6]*argField{ap_VecSpReg_42_42_38_41, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3020 {PMXVBF16GER2, 0xfff00000fc0007f8, 0x7900000ec000198, 0xf3f0000000000, // Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) MMIRR:XX3-form (pmxvbf16ger2 AT,XA,XB,XMSK,YMSK,PMSK) 3021 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}}, 3022 {PMXVBF16GER2NN, 0xfff00000fc0007f8, 0x7900000ec000790, 0xf3f0000000000, // Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Negative accumulate MMIRR:XX3-form (pmxvbf16ger2nn AT,XA,XB,XMSK,YMSK,PMSK) 3023 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}}, 3024 {PMXVBF16GER2NP, 0xfff00000fc0007f8, 0x7900000ec000390, 0xf3f0000000000, // Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Positive accumulate MMIRR:XX3-form (pmxvbf16ger2np AT,XA,XB,XMSK,YMSK,PMSK) 3025 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}}, 3026 {PMXVBF16GER2PN, 0xfff00000fc0007f8, 0x7900000ec000590, 0xf3f0000000000, // Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Negative accumulate MMIRR:XX3-form (pmxvbf16ger2pn AT,XA,XB,XMSK,YMSK,PMSK) 3027 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}}, 3028 {PMXVBF16GER2PP, 0xfff00000fc0007f8, 0x7900000ec000190, 0xf3f0000000000, // Prefixed Masked VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvbf16ger2pp AT,XA,XB,XMSK,YMSK,PMSK) 3029 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}}, 3030 {PMXVF16GER2, 0xfff00000fc0007f8, 0x7900000ec000098, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) MMIRR:XX3-form (pmxvf16ger2 AT,XA,XB,XMSK,YMSK,PMSK) 3031 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}}, 3032 {PMXVF16GER2NN, 0xfff00000fc0007f8, 0x7900000ec000690, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Negative accumulate MMIRR:XX3-form (pmxvf16ger2nn AT,XA,XB,XMSK,YMSK,PMSK) 3033 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}}, 3034 {PMXVF16GER2NP, 0xfff00000fc0007f8, 0x7900000ec000290, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Positive accumulate MMIRR:XX3-form (pmxvf16ger2np AT,XA,XB,XMSK,YMSK,PMSK) 3035 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}}, 3036 {PMXVF16GER2PN, 0xfff00000fc0007f8, 0x7900000ec000490, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Negative accumulate MMIRR:XX3-form (pmxvf16ger2pn AT,XA,XB,XMSK,YMSK,PMSK) 3037 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}}, 3038 {PMXVF16GER2PP, 0xfff00000fc0007f8, 0x7900000ec000090, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvf16ger2pp AT,XA,XB,XMSK,YMSK,PMSK) 3039 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}}, 3040 {PMXVF32GER, 0xfff00000fc0007f8, 0x7900000ec0000d8, 0xfff0000000000, // Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) MMIRR:XX3-form (pmxvf32ger AT,XA,XB,XMSK,YMSK) 3041 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31}}, 3042 {PMXVF32GERNN, 0xfff00000fc0007f8, 0x7900000ec0006d0, 0xfff0000000000, // Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate MMIRR:XX3-form (pmxvf32gernn AT,XA,XB,XMSK,YMSK) 3043 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31}}, 3044 {PMXVF32GERNP, 0xfff00000fc0007f8, 0x7900000ec0002d0, 0xfff0000000000, // Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate MMIRR:XX3-form (pmxvf32gernp AT,XA,XB,XMSK,YMSK) 3045 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31}}, 3046 {PMXVF32GERPN, 0xfff00000fc0007f8, 0x7900000ec0004d0, 0xfff0000000000, // Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate MMIRR:XX3-form (pmxvf32gerpn AT,XA,XB,XMSK,YMSK) 3047 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31}}, 3048 {PMXVF32GERPP, 0xfff00000fc0007f8, 0x7900000ec0000d0, 0xfff0000000000, // Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvf32gerpp AT,XA,XB,XMSK,YMSK) 3049 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31}}, 3050 {PMXVF64GER, 0xfff00000fc0007f8, 0x7900000ec0001d8, 0xfff0300000000, // Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) MMIRR:XX3-form (pmxvf64ger AT,XAp,XB,XMSK,YMSK) 3051 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_29}}, 3052 {PMXVF64GERNN, 0xfff00000fc0007f8, 0x7900000ec0007d0, 0xfff0300000000, // Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate MMIRR:XX3-form (pmxvf64gernn AT,XAp,XB,XMSK,YMSK) 3053 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_29}}, 3054 {PMXVF64GERNP, 0xfff00000fc0007f8, 0x7900000ec0003d0, 0xfff0300000000, // Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate MMIRR:XX3-form (pmxvf64gernp AT,XAp,XB,XMSK,YMSK) 3055 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_29}}, 3056 {PMXVF64GERPN, 0xfff00000fc0007f8, 0x7900000ec0005d0, 0xfff0300000000, // Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate MMIRR:XX3-form (pmxvf64gerpn AT,XAp,XB,XMSK,YMSK) 3057 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_29}}, 3058 {PMXVF64GERPP, 0xfff00000fc0007f8, 0x7900000ec0001d0, 0xfff0300000000, // Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvf64gerpp AT,XAp,XB,XMSK,YMSK) 3059 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_29}}, 3060 {PMXVI16GER2, 0xfff00000fc0007f8, 0x7900000ec000258, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) MMIRR:XX3-form (pmxvi16ger2 AT,XA,XB,XMSK,YMSK,PMSK) 3061 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}}, 3062 {PMXVI16GER2PP, 0xfff00000fc0007f8, 0x7900000ec000358, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvi16ger2pp AT,XA,XB,XMSK,YMSK,PMSK) 3063 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}}, 3064 {PMXVI16GER2S, 0xfff00000fc0007f8, 0x7900000ec000158, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation MMIRR:XX3-form (pmxvi16ger2s AT,XA,XB,XMSK,YMSK,PMSK) 3065 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}}, 3066 {PMXVI16GER2SPP, 0xfff00000fc0007f8, 0x7900000ec000150, 0xf3f0000000000, // Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvi16ger2spp AT,XA,XB,XMSK,YMSK,PMSK) 3067 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_17}}, 3068 {PMXVI4GER8, 0xfff00000fc0007f8, 0x7900000ec000118, 0xf000000000000, // Prefixed Masked VSX Vector 4-bit Signed Integer GER (rank-8 update) MMIRR:XX3-form (pmxvi4ger8 AT,XA,XB,XMSK,YMSK,PMSK) 3069 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_23}}, 3070 {PMXVI4GER8PP, 0xfff00000fc0007f8, 0x7900000ec000110, 0xf000000000000, // Prefixed Masked VSX Vector 4-bit Signed Integer GER (rank-8 update) Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvi4ger8pp AT,XA,XB,XMSK,YMSK,PMSK) 3071 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_23}}, 3072 {PMXVI8GER4, 0xfff00000fc0007f8, 0x7900000ec000018, 0xf0f0000000000, // Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) MMIRR:XX3-form (pmxvi8ger4 AT,XA,XB,XMSK,YMSK,PMSK) 3073 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_19}}, 3074 {PMXVI8GER4PP, 0xfff00000fc0007f8, 0x7900000ec000010, 0xf0f0000000000, // Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvi8ger4pp AT,XA,XB,XMSK,YMSK,PMSK) 3075 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_19}}, 3076 {PMXVI8GER4SPP, 0xfff00000fc0007f8, 0x7900000ec000318, 0xf0f0000000000, // Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) with Saturate Positive multiply, Positive accumulate MMIRR:XX3-form (pmxvi8ger4spp AT,XA,XB,XMSK,YMSK,PMSK) 3077 [6]*argField{ap_MMAReg_38_40, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31, ap_ImmUnsigned_16_19}}, 3078 {PNOP, 0xfff3fffe00000000, 0x700000000000000, 0xc000100000000, // Prefixed Nop MRR:*-form (pnop) 3079 [6]*argField{}}, 3080 {PSTB, 0xff800000fc000000, 0x600000098000000, 0x6c000000000000, // Prefixed Store Byte MLS:D-form (pstb RS,D(RA),R) 3081 [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3082 {PSTD, 0xff800000fc000000, 0x4000000f4000000, 0x6c000000000000, // Prefixed Store Doubleword 8LS:D-form (pstd RS,D(RA),R) 3083 [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3084 {PSTFD, 0xff800000fc000000, 0x6000000d8000000, 0x6c000000000000, // Prefixed Store Floating-Point Double MLS:D-form (pstfd FRS,D(RA),R) 3085 [6]*argField{ap_FPReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3086 {PSTFS, 0xff800000fc000000, 0x6000000d0000000, 0x6c000000000000, // Prefixed Store Floating-Point Single MLS:D-form (pstfs FRS,D(RA),R) 3087 [6]*argField{ap_FPReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3088 {PSTH, 0xff800000fc000000, 0x6000000b0000000, 0x6c000000000000, // Prefixed Store Halfword MLS:D-form (psth RS,D(RA),R) 3089 [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3090 {PSTQ, 0xff800000fc000000, 0x4000000f0000000, 0x6c000000000000, // Prefixed Store Quadword 8LS:D-form (pstq RSp,D(RA),R) 3091 [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3092 {PSTW, 0xff800000fc000000, 0x600000090000000, 0x6c000000000000, // Prefixed Store Word MLS:D-form (pstw RS,D(RA),R) 3093 [6]*argField{ap_Reg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3094 {PSTXSD, 0xff800000fc000000, 0x4000000b8000000, 0x6c000000000000, // Prefixed Store VSX Scalar Doubleword 8LS:D-form (pstxsd VRS,D(RA),R) 3095 [6]*argField{ap_VecReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3096 {PSTXSSP, 0xff800000fc000000, 0x4000000bc000000, 0x6c000000000000, // Prefixed Store VSX Scalar Single-Precision 8LS:D-form (pstxssp VRS,D(RA),R) 3097 [6]*argField{ap_VecReg_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3098 {PSTXV, 0xff800000f8000000, 0x4000000d8000000, 0x6c000000000000, // Prefixed Store VSX Vector 8LS:D-form (pstxv XS,D(RA),R) 3099 [6]*argField{ap_VecSReg_37_37_38_42, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3100 {PSTXVP, 0xff800000fc000000, 0x4000000f8000000, 0x6c000000000000, // Prefixed Store VSX Vector Paired 8LS:D-form (pstxvp XSp,D(RA),R) 3101 [6]*argField{ap_VecSpReg_42_42_38_41, ap_Offset_14_31_48_63, ap_Reg_43_47, ap_ImmUnsigned_11_11}}, 3102 {SETBC, 0xfc0007fe00000000, 0x7c00030000000000, 0xf80100000000, // Set Boolean Condition X-form (setbc RT,BI) 3103 [6]*argField{ap_Reg_6_10, ap_CondRegBit_11_15}}, 3104 {SETBCR, 0xfc0007fe00000000, 0x7c00034000000000, 0xf80100000000, // Set Boolean Condition Reverse X-form (setbcr RT,BI) 3105 [6]*argField{ap_Reg_6_10, ap_CondRegBit_11_15}}, 3106 {SETNBC, 0xfc0007fe00000000, 0x7c00038000000000, 0xf80100000000, // Set Negative Boolean Condition X-form (setnbc RT,BI) 3107 [6]*argField{ap_Reg_6_10, ap_CondRegBit_11_15}}, 3108 {SETNBCR, 0xfc0007fe00000000, 0x7c0003c000000000, 0xf80100000000, // Set Negative Boolean Condition Reverse X-form (setnbcr RT,BI) 3109 [6]*argField{ap_Reg_6_10, ap_CondRegBit_11_15}}, 3110 {STXVP, 0xfc00000f00000000, 0x1800000100000000, 0x0, // Store VSX Vector Paired DQ-form (stxvp XSp,DQ(RA)) 3111 [6]*argField{ap_VecSpReg_10_10_6_9, ap_Offset_16_27_shift4, ap_Reg_11_15}}, 3112 {STXVPX, 0xfc0007fe00000000, 0x7c00039a00000000, 0x100000000, // Store VSX Vector Paired Indexed X-form (stxvpx XSp,RA,RB) 3113 [6]*argField{ap_VecSpReg_10_10_6_9, ap_Reg_11_15, ap_Reg_16_20}}, 3114 {STXVRBX, 0xfc0007fe00000000, 0x7c00011a00000000, 0x0, // Store VSX Vector Rightmost Byte Indexed X-form (stxvrbx XS,RA,RB) 3115 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3116 {STXVRDX, 0xfc0007fe00000000, 0x7c0001da00000000, 0x0, // Store VSX Vector Rightmost Doubleword Indexed X-form (stxvrdx XS,RA,RB) 3117 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3118 {STXVRHX, 0xfc0007fe00000000, 0x7c00015a00000000, 0x0, // Store VSX Vector Rightmost Halfword Indexed X-form (stxvrhx XS,RA,RB) 3119 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3120 {STXVRWX, 0xfc0007fe00000000, 0x7c00019a00000000, 0x0, // Store VSX Vector Rightmost Word Indexed X-form (stxvrwx XS,RA,RB) 3121 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3122 {VCFUGED, 0xfc0007ff00000000, 0x1000054d00000000, 0x0, // Vector Centrifuge Doubleword VX-form (vcfuged VRT,VRA,VRB) 3123 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3124 {VCLRLB, 0xfc0007ff00000000, 0x1000018d00000000, 0x0, // Vector Clear Leftmost Bytes VX-form (vclrlb VRT,VRA,RB) 3125 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_Reg_16_20}}, 3126 {VCLRRB, 0xfc0007ff00000000, 0x100001cd00000000, 0x0, // Vector Clear Rightmost Bytes VX-form (vclrrb VRT,VRA,RB) 3127 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_Reg_16_20}}, 3128 {VCLZDM, 0xfc0007ff00000000, 0x1000078400000000, 0x0, // Vector Count Leading Zeros Doubleword under bit Mask VX-form (vclzdm VRT,VRA,VRB) 3129 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3130 {VCMPEQUQ, 0xfc0007ff00000000, 0x100001c700000000, 0x0, // Vector Compare Equal Quadword VC-form (vcmpequq VRT,VRA,VRB) 3131 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3132 {VCMPEQUQCC, 0xfc0007ff00000000, 0x100005c700000000, 0x0, // Vector Compare Equal Quadword VC-form (vcmpequq. VRT,VRA,VRB) 3133 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3134 {VCMPGTSQ, 0xfc0007ff00000000, 0x1000038700000000, 0x0, // Vector Compare Greater Than Signed Quadword VC-form (vcmpgtsq VRT,VRA,VRB) 3135 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3136 {VCMPGTSQCC, 0xfc0007ff00000000, 0x1000078700000000, 0x0, // Vector Compare Greater Than Signed Quadword VC-form (vcmpgtsq. VRT,VRA,VRB) 3137 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3138 {VCMPGTUQ, 0xfc0007ff00000000, 0x1000028700000000, 0x0, // Vector Compare Greater Than Unsigned Quadword VC-form (vcmpgtuq VRT,VRA,VRB) 3139 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3140 {VCMPGTUQCC, 0xfc0007ff00000000, 0x1000068700000000, 0x0, // Vector Compare Greater Than Unsigned Quadword VC-form (vcmpgtuq. VRT,VRA,VRB) 3141 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3142 {VCMPSQ, 0xfc0007ff00000000, 0x1000014100000000, 0x60000000000000, // Vector Compare Signed Quadword VX-form (vcmpsq BF,VRA,VRB) 3143 [6]*argField{ap_CondRegField_6_8, ap_VecReg_11_15, ap_VecReg_16_20}}, 3144 {VCMPUQ, 0xfc0007ff00000000, 0x1000010100000000, 0x60000000000000, // Vector Compare Unsigned Quadword VX-form (vcmpuq BF,VRA,VRB) 3145 [6]*argField{ap_CondRegField_6_8, ap_VecReg_11_15, ap_VecReg_16_20}}, 3146 {VCNTMBB, 0xfc1e07ff00000000, 0x1018064200000000, 0x0, // Vector Count Mask Bits Byte VX-form (vcntmbb RT,VRB,MP) 3147 [6]*argField{ap_Reg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_15_15}}, 3148 {VCNTMBD, 0xfc1e07ff00000000, 0x101e064200000000, 0x0, // Vector Count Mask Bits Doubleword VX-form (vcntmbd RT,VRB,MP) 3149 [6]*argField{ap_Reg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_15_15}}, 3150 {VCNTMBH, 0xfc1e07ff00000000, 0x101a064200000000, 0x0, // Vector Count Mask Bits Halfword VX-form (vcntmbh RT,VRB,MP) 3151 [6]*argField{ap_Reg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_15_15}}, 3152 {VCNTMBW, 0xfc1e07ff00000000, 0x101c064200000000, 0x0, // Vector Count Mask Bits Word VX-form (vcntmbw RT,VRB,MP) 3153 [6]*argField{ap_Reg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_15_15}}, 3154 {VCTZDM, 0xfc0007ff00000000, 0x100007c400000000, 0x0, // Vector Count Trailing Zeros Doubleword under bit Mask VX-form (vctzdm VRT,VRA,VRB) 3155 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3156 {VDIVESD, 0xfc0007ff00000000, 0x100003cb00000000, 0x0, // Vector Divide Extended Signed Doubleword VX-form (vdivesd VRT,VRA,VRB) 3157 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3158 {VDIVESQ, 0xfc0007ff00000000, 0x1000030b00000000, 0x0, // Vector Divide Extended Signed Quadword VX-form (vdivesq VRT,VRA,VRB) 3159 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3160 {VDIVESW, 0xfc0007ff00000000, 0x1000038b00000000, 0x0, // Vector Divide Extended Signed Word VX-form (vdivesw VRT,VRA,VRB) 3161 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3162 {VDIVEUD, 0xfc0007ff00000000, 0x100002cb00000000, 0x0, // Vector Divide Extended Unsigned Doubleword VX-form (vdiveud VRT,VRA,VRB) 3163 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3164 {VDIVEUQ, 0xfc0007ff00000000, 0x1000020b00000000, 0x0, // Vector Divide Extended Unsigned Quadword VX-form (vdiveuq VRT,VRA,VRB) 3165 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3166 {VDIVEUW, 0xfc0007ff00000000, 0x1000028b00000000, 0x0, // Vector Divide Extended Unsigned Word VX-form (vdiveuw VRT,VRA,VRB) 3167 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3168 {VDIVSD, 0xfc0007ff00000000, 0x100001cb00000000, 0x0, // Vector Divide Signed Doubleword VX-form (vdivsd VRT,VRA,VRB) 3169 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3170 {VDIVSQ, 0xfc0007ff00000000, 0x1000010b00000000, 0x0, // Vector Divide Signed Quadword VX-form (vdivsq VRT,VRA,VRB) 3171 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3172 {VDIVSW, 0xfc0007ff00000000, 0x1000018b00000000, 0x0, // Vector Divide Signed Word VX-form (vdivsw VRT,VRA,VRB) 3173 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3174 {VDIVUD, 0xfc0007ff00000000, 0x100000cb00000000, 0x0, // Vector Divide Unsigned Doubleword VX-form (vdivud VRT,VRA,VRB) 3175 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3176 {VDIVUQ, 0xfc0007ff00000000, 0x1000000b00000000, 0x0, // Vector Divide Unsigned Quadword VX-form (vdivuq VRT,VRA,VRB) 3177 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3178 {VDIVUW, 0xfc0007ff00000000, 0x1000008b00000000, 0x0, // Vector Divide Unsigned Word VX-form (vdivuw VRT,VRA,VRB) 3179 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3180 {VEXPANDBM, 0xfc1f07ff00000000, 0x1000064200000000, 0x0, // Vector Expand Byte Mask VX-form (vexpandbm VRT,VRB) 3181 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3182 {VEXPANDDM, 0xfc1f07ff00000000, 0x1003064200000000, 0x0, // Vector Expand Doubleword Mask VX-form (vexpanddm VRT,VRB) 3183 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3184 {VEXPANDHM, 0xfc1f07ff00000000, 0x1001064200000000, 0x0, // Vector Expand Halfword Mask VX-form (vexpandhm VRT,VRB) 3185 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3186 {VEXPANDQM, 0xfc1f07ff00000000, 0x1004064200000000, 0x0, // Vector Expand Quadword Mask VX-form (vexpandqm VRT,VRB) 3187 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3188 {VEXPANDWM, 0xfc1f07ff00000000, 0x1002064200000000, 0x0, // Vector Expand Word Mask VX-form (vexpandwm VRT,VRB) 3189 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3190 {VEXTDDVLX, 0xfc00003f00000000, 0x1000001e00000000, 0x0, // Vector Extract Double Doubleword to VSR using GPR-specified Left-Index VA-form (vextddvlx VRT,VRA,VRB,RC) 3191 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}}, 3192 {VEXTDDVRX, 0xfc00003f00000000, 0x1000001f00000000, 0x0, // Vector Extract Double Doubleword to VSR using GPR-specified Right-Index VA-form (vextddvrx VRT,VRA,VRB,RC) 3193 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}}, 3194 {VEXTDUBVLX, 0xfc00003f00000000, 0x1000001800000000, 0x0, // Vector Extract Double Unsigned Byte to VSR using GPR-specified Left-Index VA-form (vextdubvlx VRT,VRA,VRB,RC) 3195 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}}, 3196 {VEXTDUBVRX, 0xfc00003f00000000, 0x1000001900000000, 0x0, // Vector Extract Double Unsigned Byte to VSR using GPR-specified Right-Index VA-form (vextdubvrx VRT,VRA,VRB,RC) 3197 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}}, 3198 {VEXTDUHVLX, 0xfc00003f00000000, 0x1000001a00000000, 0x0, // Vector Extract Double Unsigned Halfword to VSR using GPR-specified Left-Index VA-form (vextduhvlx VRT,VRA,VRB,RC) 3199 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}}, 3200 {VEXTDUHVRX, 0xfc00003f00000000, 0x1000001b00000000, 0x0, // Vector Extract Double Unsigned Halfword to VSR using GPR-specified Right-Index VA-form (vextduhvrx VRT,VRA,VRB,RC) 3201 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}}, 3202 {VEXTDUWVLX, 0xfc00003f00000000, 0x1000001c00000000, 0x0, // Vector Extract Double Unsigned Word to VSR using GPR-specified Left-Index VA-form (vextduwvlx VRT,VRA,VRB,RC) 3203 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}}, 3204 {VEXTDUWVRX, 0xfc00003f00000000, 0x1000001d00000000, 0x0, // Vector Extract Double Unsigned Word to VSR using GPR-specified Right-Index VA-form (vextduwvrx VRT,VRA,VRB,RC) 3205 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_Reg_21_25}}, 3206 {VEXTRACTBM, 0xfc1f07ff00000000, 0x1008064200000000, 0x0, // Vector Extract Byte Mask VX-form (vextractbm RT,VRB) 3207 [6]*argField{ap_Reg_6_10, ap_VecReg_16_20}}, 3208 {VEXTRACTDM, 0xfc1f07ff00000000, 0x100b064200000000, 0x0, // Vector Extract Doubleword Mask VX-form (vextractdm RT,VRB) 3209 [6]*argField{ap_Reg_6_10, ap_VecReg_16_20}}, 3210 {VEXTRACTHM, 0xfc1f07ff00000000, 0x1009064200000000, 0x0, // Vector Extract Halfword Mask VX-form (vextracthm RT,VRB) 3211 [6]*argField{ap_Reg_6_10, ap_VecReg_16_20}}, 3212 {VEXTRACTQM, 0xfc1f07ff00000000, 0x100c064200000000, 0x0, // Vector Extract Quadword Mask VX-form (vextractqm RT,VRB) 3213 [6]*argField{ap_Reg_6_10, ap_VecReg_16_20}}, 3214 {VEXTRACTWM, 0xfc1f07ff00000000, 0x100a064200000000, 0x0, // Vector Extract Word Mask VX-form (vextractwm RT,VRB) 3215 [6]*argField{ap_Reg_6_10, ap_VecReg_16_20}}, 3216 {VEXTSD2Q, 0xfc1f07ff00000000, 0x101b060200000000, 0x0, // Vector Extend Sign Doubleword to Quadword VX-form (vextsd2q VRT,VRB) 3217 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3218 {VGNB, 0xfc0007ff00000000, 0x100004cc00000000, 0x18000000000000, // Vector Gather every Nth Bit VX-form (vgnb RT,VRB,N) 3219 [6]*argField{ap_Reg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_13_15}}, 3220 {VINSBLX, 0xfc0007ff00000000, 0x1000020f00000000, 0x0, // Vector Insert Byte from GPR using GPR-specified Left-Index VX-form (vinsblx VRT,RA,RB) 3221 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3222 {VINSBRX, 0xfc0007ff00000000, 0x1000030f00000000, 0x0, // Vector Insert Byte from GPR using GPR-specified Right-Index VX-form (vinsbrx VRT,RA,RB) 3223 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3224 {VINSBVLX, 0xfc0007ff00000000, 0x1000000f00000000, 0x0, // Vector Insert Byte from VSR using GPR-specified Left-Index VX-form (vinsbvlx VRT,RA,VRB) 3225 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_VecReg_16_20}}, 3226 {VINSBVRX, 0xfc0007ff00000000, 0x1000010f00000000, 0x0, // Vector Insert Byte from VSR using GPR-specified Right-Index VX-form (vinsbvrx VRT,RA,VRB) 3227 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_VecReg_16_20}}, 3228 {VINSD, 0xfc0007ff00000000, 0x100001cf00000000, 0x10000000000000, // Vector Insert Doubleword from GPR using immediate-specified index VX-form (vinsd VRT,RB,UIM) 3229 [6]*argField{ap_VecReg_6_10, ap_Reg_16_20, ap_ImmUnsigned_12_15}}, 3230 {VINSDLX, 0xfc0007ff00000000, 0x100002cf00000000, 0x0, // Vector Insert Doubleword from GPR using GPR-specified Left-Index VX-form (vinsdlx VRT,RA,RB) 3231 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3232 {VINSDRX, 0xfc0007ff00000000, 0x100003cf00000000, 0x0, // Vector Insert Doubleword from GPR using GPR-specified Right-Index VX-form (vinsdrx VRT,RA,RB) 3233 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3234 {VINSHLX, 0xfc0007ff00000000, 0x1000024f00000000, 0x0, // Vector Insert Halfword from GPR using GPR-specified Left-Index VX-form (vinshlx VRT,RA,RB) 3235 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3236 {VINSHRX, 0xfc0007ff00000000, 0x1000034f00000000, 0x0, // Vector Insert Halfword from GPR using GPR-specified Right-Index VX-form (vinshrx VRT,RA,RB) 3237 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3238 {VINSHVLX, 0xfc0007ff00000000, 0x1000004f00000000, 0x0, // Vector Insert Halfword from VSR using GPR-specified Left-Index VX-form (vinshvlx VRT,RA,VRB) 3239 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_VecReg_16_20}}, 3240 {VINSHVRX, 0xfc0007ff00000000, 0x1000014f00000000, 0x0, // Vector Insert Halfword from VSR using GPR-specified Right-Index VX-form (vinshvrx VRT,RA,VRB) 3241 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_VecReg_16_20}}, 3242 {VINSW, 0xfc0007ff00000000, 0x100000cf00000000, 0x10000000000000, // Vector Insert Word from GPR using immediate-specified index VX-form (vinsw VRT,RB,UIM) 3243 [6]*argField{ap_VecReg_6_10, ap_Reg_16_20, ap_ImmUnsigned_12_15}}, 3244 {VINSWLX, 0xfc0007ff00000000, 0x1000028f00000000, 0x0, // Vector Insert Word from GPR using GPR-specified Left-Index VX-form (vinswlx VRT,RA,RB) 3245 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3246 {VINSWRX, 0xfc0007ff00000000, 0x1000038f00000000, 0x0, // Vector Insert Word from GPR using GPR-specified Right-Index VX-form (vinswrx VRT,RA,RB) 3247 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3248 {VINSWVLX, 0xfc0007ff00000000, 0x1000008f00000000, 0x0, // Vector Insert Word from VSR using GPR-specified Left-Index VX-form (vinswvlx VRT,RA,VRB) 3249 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_VecReg_16_20}}, 3250 {VINSWVRX, 0xfc0007ff00000000, 0x1000018f00000000, 0x0, // Vector Insert Word from VSR using GPR-specified Left-Index VX-form (vinswvrx VRT,RA,VRB) 3251 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_VecReg_16_20}}, 3252 {VMODSD, 0xfc0007ff00000000, 0x100007cb00000000, 0x0, // Vector Modulo Signed Doubleword VX-form (vmodsd VRT,VRA,VRB) 3253 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3254 {VMODSQ, 0xfc0007ff00000000, 0x1000070b00000000, 0x0, // Vector Modulo Signed Quadword VX-form (vmodsq VRT,VRA,VRB) 3255 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3256 {VMODSW, 0xfc0007ff00000000, 0x1000078b00000000, 0x0, // Vector Modulo Signed Word VX-form (vmodsw VRT,VRA,VRB) 3257 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3258 {VMODUD, 0xfc0007ff00000000, 0x100006cb00000000, 0x0, // Vector Modulo Unsigned Doubleword VX-form (vmodud VRT,VRA,VRB) 3259 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3260 {VMODUQ, 0xfc0007ff00000000, 0x1000060b00000000, 0x0, // Vector Modulo Unsigned Quadword VX-form (vmoduq VRT,VRA,VRB) 3261 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3262 {VMODUW, 0xfc0007ff00000000, 0x1000068b00000000, 0x0, // Vector Modulo Unsigned Word VX-form (vmoduw VRT,VRA,VRB) 3263 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3264 {VMSUMCUD, 0xfc00003f00000000, 0x1000001700000000, 0x0, // Vector Multiply-Sum & write Carry-out Unsigned Doubleword VA-form (vmsumcud VRT,VRA,VRB,VRC) 3265 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3266 {VMULESD, 0xfc0007ff00000000, 0x100003c800000000, 0x0, // Vector Multiply Even Signed Doubleword VX-form (vmulesd VRT,VRA,VRB) 3267 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3268 {VMULEUD, 0xfc0007ff00000000, 0x100002c800000000, 0x0, // Vector Multiply Even Unsigned Doubleword VX-form (vmuleud VRT,VRA,VRB) 3269 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3270 {VMULHSD, 0xfc0007ff00000000, 0x100003c900000000, 0x0, // Vector Multiply High Signed Doubleword VX-form (vmulhsd VRT,VRA,VRB) 3271 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3272 {VMULHSW, 0xfc0007ff00000000, 0x1000038900000000, 0x0, // Vector Multiply High Signed Word VX-form (vmulhsw VRT,VRA,VRB) 3273 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3274 {VMULHUD, 0xfc0007ff00000000, 0x100002c900000000, 0x0, // Vector Multiply High Unsigned Doubleword VX-form (vmulhud VRT,VRA,VRB) 3275 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3276 {VMULHUW, 0xfc0007ff00000000, 0x1000028900000000, 0x0, // Vector Multiply High Unsigned Word VX-form (vmulhuw VRT,VRA,VRB) 3277 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3278 {VMULLD, 0xfc0007ff00000000, 0x100001c900000000, 0x0, // Vector Multiply Low Doubleword VX-form (vmulld VRT,VRA,VRB) 3279 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3280 {VMULOSD, 0xfc0007ff00000000, 0x100001c800000000, 0x0, // Vector Multiply Odd Signed Doubleword VX-form (vmulosd VRT,VRA,VRB) 3281 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3282 {VMULOUD, 0xfc0007ff00000000, 0x100000c800000000, 0x0, // Vector Multiply Odd Unsigned Doubleword VX-form (vmuloud VRT,VRA,VRB) 3283 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3284 {VPDEPD, 0xfc0007ff00000000, 0x100005cd00000000, 0x0, // Vector Parallel Bits Deposit Doubleword VX-form (vpdepd VRT,VRA,VRB) 3285 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3286 {VPEXTD, 0xfc0007ff00000000, 0x1000058d00000000, 0x0, // Vector Parallel Bits Extract Doubleword VX-form (vpextd VRT,VRA,VRB) 3287 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3288 {VRLQ, 0xfc0007ff00000000, 0x1000000500000000, 0x0, // Vector Rotate Left Quadword VX-form (vrlq VRT,VRA,VRB) 3289 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3290 {VRLQMI, 0xfc0007ff00000000, 0x1000004500000000, 0x0, // Vector Rotate Left Quadword then Mask Insert VX-form (vrlqmi VRT,VRA,VRB) 3291 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3292 {VRLQNM, 0xfc0007ff00000000, 0x1000014500000000, 0x0, // Vector Rotate Left Quadword then AND with Mask VX-form (vrlqnm VRT,VRA,VRB) 3293 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3294 {VSLDBI, 0xfc00063f00000000, 0x1000001600000000, 0x0, // Vector Shift Left Double by Bit Immediate VN-form (vsldbi VRT,VRA,VRB,SH) 3295 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_23_25}}, 3296 {VSLQ, 0xfc0007ff00000000, 0x1000010500000000, 0x0, // Vector Shift Left Quadword VX-form (vslq VRT,VRA,VRB) 3297 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3298 {VSRAQ, 0xfc0007ff00000000, 0x1000030500000000, 0x0, // Vector Shift Right Algebraic Quadword VX-form (vsraq VRT,VRA,VRB) 3299 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3300 {VSRDBI, 0xfc00063f00000000, 0x1000021600000000, 0x0, // Vector Shift Right Double by Bit Immediate VN-form (vsrdbi VRT,VRA,VRB,SH) 3301 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_23_25}}, 3302 {VSRQ, 0xfc0007ff00000000, 0x1000020500000000, 0x0, // Vector Shift Right Quadword VX-form (vsrq VRT,VRA,VRB) 3303 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3304 {VSTRIBL, 0xfc1f07ff00000000, 0x1000000d00000000, 0x0, // Vector String Isolate Byte Left-justified VX-form (vstribl VRT,VRB) 3305 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3306 {VSTRIBLCC, 0xfc1f07ff00000000, 0x1000040d00000000, 0x0, // Vector String Isolate Byte Left-justified VX-form (vstribl. VRT,VRB) 3307 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3308 {VSTRIBR, 0xfc1f07ff00000000, 0x1001000d00000000, 0x0, // Vector String Isolate Byte Right-justified VX-form (vstribr VRT,VRB) 3309 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3310 {VSTRIBRCC, 0xfc1f07ff00000000, 0x1001040d00000000, 0x0, // Vector String Isolate Byte Right-justified VX-form (vstribr. VRT,VRB) 3311 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3312 {VSTRIHL, 0xfc1f07ff00000000, 0x1002000d00000000, 0x0, // Vector String Isolate Halfword Left-justified VX-form (vstrihl VRT,VRB) 3313 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3314 {VSTRIHLCC, 0xfc1f07ff00000000, 0x1002040d00000000, 0x0, // Vector String Isolate Halfword Left-justified VX-form (vstrihl. VRT,VRB) 3315 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3316 {VSTRIHR, 0xfc1f07ff00000000, 0x1003000d00000000, 0x0, // Vector String Isolate Halfword Right-justified VX-form (vstrihr VRT,VRB) 3317 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3318 {VSTRIHRCC, 0xfc1f07ff00000000, 0x1003040d00000000, 0x0, // Vector String Isolate Halfword Right-justified VX-form (vstrihr. VRT,VRB) 3319 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3320 {XSCMPEQQP, 0xfc0007fe00000000, 0xfc00008800000000, 0x100000000, // VSX Scalar Compare Equal Quad-Precision X-form (xscmpeqqp VRT,VRA,VRB) 3321 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3322 {XSCMPGEQP, 0xfc0007fe00000000, 0xfc00018800000000, 0x100000000, // VSX Scalar Compare Greater Than or Equal Quad-Precision X-form (xscmpgeqp VRT,VRA,VRB) 3323 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3324 {XSCMPGTQP, 0xfc0007fe00000000, 0xfc0001c800000000, 0x100000000, // VSX Scalar Compare Greater Than Quad-Precision X-form (xscmpgtqp VRT,VRA,VRB) 3325 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3326 {XSCVQPSQZ, 0xfc1f07fe00000000, 0xfc08068800000000, 0x100000000, // VSX Scalar Convert with round to zero Quad-Precision to Signed Quadword X-form (xscvqpsqz VRT,VRB) 3327 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3328 {XSCVQPUQZ, 0xfc1f07fe00000000, 0xfc00068800000000, 0x100000000, // VSX Scalar Convert with round to zero Quad-Precision to Unsigned Quadword X-form (xscvqpuqz VRT,VRB) 3329 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3330 {XSCVSQQP, 0xfc1f07fe00000000, 0xfc0b068800000000, 0x100000000, // VSX Scalar Convert with round Signed Quadword to Quad-Precision X-form (xscvsqqp VRT,VRB) 3331 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3332 {XSCVUQQP, 0xfc1f07fe00000000, 0xfc03068800000000, 0x100000000, // VSX Scalar Convert with round Unsigned Quadword to Quad-Precision X-form (xscvuqqp VRT,VRB) 3333 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3334 {XSMAXCQP, 0xfc0007fe00000000, 0xfc00054800000000, 0x100000000, // VSX Scalar Maximum Type-C Quad-Precision X-form (xsmaxcqp VRT,VRA,VRB) 3335 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3336 {XSMINCQP, 0xfc0007fe00000000, 0xfc0005c800000000, 0x100000000, // VSX Scalar Minimum Type-C Quad-Precision X-form (xsmincqp VRT,VRA,VRB) 3337 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3338 {XVBF16GER2, 0xfc0007f800000000, 0xec00019800000000, 0x60000100000000, // VSX Vector bfloat16 GER (Rank-2 Update) XX3-form (xvbf16ger2 AT,XA,XB) 3339 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3340 {XVBF16GER2NN, 0xfc0007f800000000, 0xec00079000000000, 0x60000100000000, // VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Negative accumulate XX3-form (xvbf16ger2nn AT,XA,XB) 3341 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3342 {XVBF16GER2NP, 0xfc0007f800000000, 0xec00039000000000, 0x60000100000000, // VSX Vector bfloat16 GER (Rank-2 Update) Negative multiply, Positive accumulate XX3-form (xvbf16ger2np AT,XA,XB) 3343 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3344 {XVBF16GER2PN, 0xfc0007f800000000, 0xec00059000000000, 0x60000100000000, // VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Negative accumulate XX3-form (xvbf16ger2pn AT,XA,XB) 3345 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3346 {XVBF16GER2PP, 0xfc0007f800000000, 0xec00019000000000, 0x60000100000000, // VSX Vector bfloat16 GER (Rank-2 Update) Positive multiply, Positive accumulate XX3-form (xvbf16ger2pp AT,XA,XB) 3347 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3348 {XVCVBF16SPN, 0xfc1f07fc00000000, 0xf010076c00000000, 0x0, // VSX Vector Convert bfloat16 to Single-Precision format XX2-form (xvcvbf16spn XT,XB) 3349 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 3350 {XVCVSPBF16, 0xfc1f07fc00000000, 0xf011076c00000000, 0x0, // VSX Vector Convert with round Single-Precision to bfloat16 format XX2-form (xvcvspbf16 XT,XB) 3351 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 3352 {XVF16GER2, 0xfc0007f800000000, 0xec00009800000000, 0x60000100000000, // VSX Vector 16-bit Floating-Point GER (rank-2 update) XX3-form (xvf16ger2 AT,XA,XB) 3353 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3354 {XVF16GER2NN, 0xfc0007f800000000, 0xec00069000000000, 0x60000100000000, // VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Negative accumulate XX3-form (xvf16ger2nn AT,XA,XB) 3355 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3356 {XVF16GER2NP, 0xfc0007f800000000, 0xec00029000000000, 0x60000100000000, // VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Positive accumulate XX3-form (xvf16ger2np AT,XA,XB) 3357 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3358 {XVF16GER2PN, 0xfc0007f800000000, 0xec00049000000000, 0x60000100000000, // VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Negative accumulate XX3-form (xvf16ger2pn AT,XA,XB) 3359 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3360 {XVF16GER2PP, 0xfc0007f800000000, 0xec00009000000000, 0x60000100000000, // VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Positive accumulate XX3-form (xvf16ger2pp AT,XA,XB) 3361 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3362 {XVF32GER, 0xfc0007f800000000, 0xec0000d800000000, 0x60000100000000, // VSX Vector 32-bit Floating-Point GER (rank-1 update) XX3-form (xvf32ger AT,XA,XB) 3363 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3364 {XVF32GERNN, 0xfc0007f800000000, 0xec0006d000000000, 0x60000100000000, // VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate XX3-form (xvf32gernn AT,XA,XB) 3365 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3366 {XVF32GERNP, 0xfc0007f800000000, 0xec0002d000000000, 0x60000100000000, // VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate XX3-form (xvf32gernp AT,XA,XB) 3367 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3368 {XVF32GERPN, 0xfc0007f800000000, 0xec0004d000000000, 0x60000100000000, // VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate XX3-form (xvf32gerpn AT,XA,XB) 3369 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3370 {XVF32GERPP, 0xfc0007f800000000, 0xec0000d000000000, 0x60000100000000, // VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate XX3-form (xvf32gerpp AT,XA,XB) 3371 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3372 {XVF64GER, 0xfc0007f800000000, 0xec0001d800000000, 0x60000100000000, // VSX Vector 64-bit Floating-Point GER (rank-1 update) XX3-form (xvf64ger AT,XAp,XB) 3373 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3374 {XVF64GERNN, 0xfc0007f800000000, 0xec0007d000000000, 0x60000100000000, // VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate XX3-form (xvf64gernn AT,XAp,XB) 3375 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3376 {XVF64GERNP, 0xfc0007f800000000, 0xec0003d000000000, 0x60000100000000, // VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate XX3-form (xvf64gernp AT,XAp,XB) 3377 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3378 {XVF64GERPN, 0xfc0007f800000000, 0xec0005d000000000, 0x60000100000000, // VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate XX3-form (xvf64gerpn AT,XAp,XB) 3379 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3380 {XVF64GERPP, 0xfc0007f800000000, 0xec0001d000000000, 0x60000100000000, // VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate XX3-form (xvf64gerpp AT,XAp,XB) 3381 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3382 {XVI16GER2, 0xfc0007f800000000, 0xec00025800000000, 0x60000100000000, // VSX Vector 16-bit Signed Integer GER (rank-2 update) XX3-form (xvi16ger2 AT,XA,XB) 3383 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3384 {XVI16GER2PP, 0xfc0007f800000000, 0xec00035800000000, 0x60000100000000, // VSX Vector 16-bit Signed Integer GER (rank-2 update) Positive multiply, Positive accumulate XX3-form (xvi16ger2pp AT,XA,XB) 3385 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3386 {XVI16GER2S, 0xfc0007f800000000, 0xec00015800000000, 0x60000100000000, // VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation XX3-form (xvi16ger2s AT,XA,XB) 3387 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3388 {XVI16GER2SPP, 0xfc0007f800000000, 0xec00015000000000, 0x60000100000000, // VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation Positive multiply, Positive accumulate XX3-form (xvi16ger2spp AT,XA,XB) 3389 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3390 {XVI4GER8, 0xfc0007f800000000, 0xec00011800000000, 0x60000100000000, // VSX Vector 4-bit Signed Integer GER (rank-8 update) XX3-form (xvi4ger8 AT,XA,XB) 3391 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3392 {XVI4GER8PP, 0xfc0007f800000000, 0xec00011000000000, 0x60000100000000, // VSX Vector 4-bit Signed Integer GER (rank-8 update) Positive multiply, Positive accumulate XX3-form (xvi4ger8pp AT,XA,XB) 3393 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3394 {XVI8GER4, 0xfc0007f800000000, 0xec00001800000000, 0x60000100000000, // VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) XX3-form (xvi8ger4 AT,XA,XB) 3395 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3396 {XVI8GER4PP, 0xfc0007f800000000, 0xec00001000000000, 0x60000100000000, // VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Positive accumulate XX3-form (xvi8ger4pp AT,XA,XB) 3397 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3398 {XVI8GER4SPP, 0xfc0007f800000000, 0xec00031800000000, 0x60000100000000, // VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) with Saturate Positive multiply, Positive accumulate XX3-form (xvi8ger4spp AT,XA,XB) 3399 [6]*argField{ap_MMAReg_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3400 {XVTLSBB, 0xfc1f07fc00000000, 0xf002076c00000000, 0x60000100000000, // VSX Vector Test Least-Significant Bit by Byte XX2-form (xvtlsbb BF,XB) 3401 [6]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}}, 3402 {XXBLENDVB, 0xfff00000fc000030, 0x500000084000000, 0xfffff00000000, // VSX Vector Blend Variable Byte 8RR:XX4-form (xxblendvb XT,XA,XB,XC) 3403 [6]*argField{ap_VecSReg_63_63_38_42, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_VecSReg_60_60_53_57}}, 3404 {XXBLENDVD, 0xfff00000fc000030, 0x500000084000030, 0xfffff00000000, // VSX Vector Blend Variable Doubleword 8RR:XX4-form (xxblendvd XT,XA,XB,XC) 3405 [6]*argField{ap_VecSReg_63_63_38_42, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_VecSReg_60_60_53_57}}, 3406 {XXBLENDVH, 0xfff00000fc000030, 0x500000084000010, 0xfffff00000000, // VSX Vector Blend Variable Halfword 8RR:XX4-form (xxblendvh XT,XA,XB,XC) 3407 [6]*argField{ap_VecSReg_63_63_38_42, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_VecSReg_60_60_53_57}}, 3408 {XXBLENDVW, 0xfff00000fc000030, 0x500000084000020, 0xfffff00000000, // VSX Vector Blend Variable Word 8RR:XX4-form (xxblendvw XT,XA,XB,XC) 3409 [6]*argField{ap_VecSReg_63_63_38_42, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_VecSReg_60_60_53_57}}, 3410 {XXEVAL, 0xfff00000fc000030, 0x500000088000010, 0xfff0000000000, // VSX Vector Evaluate 8RR-XX4-form (xxeval XT,XA,XB,XC,IMM) 3411 [6]*argField{ap_VecSReg_63_63_38_42, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_VecSReg_60_60_53_57, ap_ImmUnsigned_24_31}}, 3412 {XXGENPCVBM, 0xfc0007fe00000000, 0xf000072800000000, 0x0, // VSX Vector Generate PCV from Byte Mask X-form (xxgenpcvbm XT,VRB,IMM) 3413 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}}, 3414 {XXGENPCVDM, 0xfc0007fe00000000, 0xf000076a00000000, 0x0, // VSX Vector Generate PCV from Doubleword Mask X-form (xxgenpcvdm XT,VRB,IMM) 3415 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}}, 3416 {XXGENPCVHM, 0xfc0007fe00000000, 0xf000072a00000000, 0x0, // VSX Vector Generate PCV from Halfword Mask X-form (xxgenpcvhm XT,VRB,IMM) 3417 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}}, 3418 {XXGENPCVWM, 0xfc0007fe00000000, 0xf000076800000000, 0x0, // VSX Vector Generate PCV from Word Mask X-form (xxgenpcvwm XT,VRB,IMM) 3419 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}}, 3420 {XXMFACC, 0xfc1f07fe00000000, 0x7c00016200000000, 0x60f80100000000, // VSX Move From Accumulator X-form (xxmfacc AS) 3421 [6]*argField{ap_MMAReg_6_8}}, 3422 {XXMTACC, 0xfc1f07fe00000000, 0x7c01016200000000, 0x60f80100000000, // VSX Move To Accumulator X-form (xxmtacc AT) 3423 [6]*argField{ap_MMAReg_6_8}}, 3424 {XXPERMX, 0xfff00000fc000030, 0x500000088000000, 0xffff800000000, // VSX Vector Permute Extended 8RR:XX4-form (xxpermx XT,XA,XB,XC,UIM) 3425 [6]*argField{ap_VecSReg_63_63_38_42, ap_VecSReg_61_61_43_47, ap_VecSReg_62_62_48_52, ap_VecSReg_60_60_53_57, ap_ImmUnsigned_29_31}}, 3426 {XXSETACCZ, 0xfc1f07fe00000000, 0x7c03016200000000, 0x60f80100000000, // VSX Set Accumulator to Zero X-form (xxsetaccz AT) 3427 [6]*argField{ap_MMAReg_6_8}}, 3428 {XXSPLTI32DX, 0xfff00000fc1c0000, 0x500000080000000, 0xf000000000000, // VSX Vector Splat Immediate32 Doubleword Indexed 8RR:D-form (xxsplti32dx XT,IX,IMM32) 3429 [6]*argField{ap_VecSReg_47_47_38_42, ap_ImmUnsigned_46_46, ap_ImmUnsigned_16_31_48_63}}, 3430 {XXSPLTIDP, 0xfff00000fc1e0000, 0x500000080040000, 0xf000000000000, // VSX Vector Splat Immediate Double-Precision 8RR:D-form (xxspltidp XT,IMM32) 3431 [6]*argField{ap_VecSReg_47_47_38_42, ap_ImmUnsigned_16_31_48_63}}, 3432 {XXSPLTIW, 0xfff00000fc1e0000, 0x500000080060000, 0xf000000000000, // VSX Vector Splat Immediate Word 8RR:D-form (xxspltiw XT,IMM32) 3433 [6]*argField{ap_VecSReg_47_47_38_42, ap_ImmUnsigned_16_31_48_63}}, 3434 {MSGCLRU, 0xfc0007fe00000000, 0x7c0000dc00000000, 0x3ff000100000000, // Ultravisor Message Clear X-form (msgclru RB) 3435 [6]*argField{ap_Reg_16_20}}, 3436 {MSGSNDU, 0xfc0007fe00000000, 0x7c00009c00000000, 0x3ff000100000000, // Ultravisor Message SendX-form (msgsndu RB) 3437 [6]*argField{ap_Reg_16_20}}, 3438 {URFID, 0xfc0007fe00000000, 0x4c00026400000000, 0x3fff80100000000, // Ultravisor Return From Interrupt Doubleword XL-form (urfid) 3439 [6]*argField{}}, 3440 {ADDEX, 0xfc0001fe00000000, 0x7c00015400000000, 0x100000000, // Add Extended using alternate carry bit Z23-form (addex RT,RA,RB,CY) 3441 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_21_22}}, 3442 {MFFSCDRN, 0xfc1f07fe00000000, 0xfc14048e00000000, 0x100000000, // Move From FPSCR Control & Set DRN X-form (mffscdrn FRT,FRB) 3443 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3444 {MFFSCDRNI, 0xfc1f07fe00000000, 0xfc15048e00000000, 0xc00100000000, // Move From FPSCR Control & Set DRN Immediate X-form (mffscdrni FRT,DRM) 3445 [6]*argField{ap_FPReg_6_10, ap_ImmUnsigned_18_20}}, 3446 {MFFSCE, 0xfc1f07fe00000000, 0xfc01048e00000000, 0xf80100000000, // Move From FPSCR & Clear Enables X-form (mffsce FRT) 3447 [6]*argField{ap_FPReg_6_10}}, 3448 {MFFSCRN, 0xfc1f07fe00000000, 0xfc16048e00000000, 0x100000000, // Move From FPSCR Control & Set RN X-form (mffscrn FRT,FRB) 3449 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3450 {MFFSCRNI, 0xfc1f07fe00000000, 0xfc17048e00000000, 0xe00100000000, // Move From FPSCR Control & Set RN Immediate X-form (mffscrni FRT,RM) 3451 [6]*argField{ap_FPReg_6_10, ap_ImmUnsigned_19_20}}, 3452 {MFFSL, 0xfc1f07fe00000000, 0xfc18048e00000000, 0xf80100000000, // Move From FPSCR Lightweight X-form (mffsl FRT) 3453 [6]*argField{ap_FPReg_6_10}}, 3454 {SLBIAG, 0xfc0007fe00000000, 0x7c0006a400000000, 0x1ef80100000000, // SLB Invalidate All Global X-form (slbiag RS, L) 3455 [6]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}}, 3456 {VMSUMUDM, 0xfc00003f00000000, 0x1000002300000000, 0x0, // Vector Multiply-Sum Unsigned Doubleword Modulo VA-form (vmsumudm VRT,VRA,VRB,VRC) 3457 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3458 {ADDPCIS, 0xfc00003e00000000, 0x4c00000400000000, 0x0, // Add PC Immediate Shifted DX-form (addpcis RT,D) 3459 [6]*argField{ap_Reg_6_10, ap_ImmSigned_16_25_11_15_31_31}}, 3460 {BCDCFNCC, 0xfc1f05ff00000000, 0x1007058100000000, 0x0, // Decimal Convert From National VX-form (bcdcfn. VRT,VRB,PS) 3461 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_22_22}}, 3462 {BCDCFSQCC, 0xfc1f05ff00000000, 0x1002058100000000, 0x0, // Decimal Convert From Signed Quadword VX-form (bcdcfsq. VRT,VRB,PS) 3463 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_22_22}}, 3464 {BCDCFZCC, 0xfc1f05ff00000000, 0x1006058100000000, 0x0, // Decimal Convert From Zoned VX-form (bcdcfz. VRT,VRB,PS) 3465 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_22_22}}, 3466 {BCDCPSGNCC, 0xfc0007ff00000000, 0x1000034100000000, 0x0, // Decimal Copy Sign VX-form (bcdcpsgn. VRT,VRA,VRB) 3467 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3468 {BCDCTNCC, 0xfc1f05ff00000000, 0x1005058100000000, 0x20000000000, // Decimal Convert To National VX-form (bcdctn. VRT,VRB) 3469 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3470 {BCDCTSQCC, 0xfc1f05ff00000000, 0x1000058100000000, 0x20000000000, // Decimal Convert To Signed Quadword VX-form (bcdctsq. VRT,VRB) 3471 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3472 {BCDCTZCC, 0xfc1f05ff00000000, 0x1004058100000000, 0x0, // Decimal Convert To Zoned VX-form (bcdctz. VRT,VRB,PS) 3473 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_22_22}}, 3474 {BCDSCC, 0xfc0005ff00000000, 0x100004c100000000, 0x0, // Decimal Shift VX-form (bcds. VRT,VRA,VRB,PS) 3475 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}}, 3476 {BCDSETSGNCC, 0xfc1f05ff00000000, 0x101f058100000000, 0x0, // Decimal Set Sign VX-form (bcdsetsgn. VRT,VRB,PS) 3477 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_22_22}}, 3478 {BCDSRCC, 0xfc0005ff00000000, 0x100005c100000000, 0x0, // Decimal Shift and Round VX-form (bcdsr. VRT,VRA,VRB,PS) 3479 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}}, 3480 {BCDTRUNCCC, 0xfc0005ff00000000, 0x1000050100000000, 0x0, // Decimal Truncate VX-form (bcdtrunc. VRT,VRA,VRB,PS) 3481 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}}, 3482 {BCDUSCC, 0xfc0005ff00000000, 0x1000048100000000, 0x20000000000, // Decimal Unsigned Shift VX-form (bcdus. VRT,VRA,VRB) 3483 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3484 {BCDUTRUNCCC, 0xfc0005ff00000000, 0x1000054100000000, 0x20000000000, // Decimal Unsigned Truncate VX-form (bcdutrunc. VRT,VRA,VRB) 3485 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3486 {CMPEQB, 0xfc0007fe00000000, 0x7c0001c000000000, 0x60000100000000, // Compare Equal Byte X-form (cmpeqb BF,RA,RB) 3487 [6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 3488 {CMPRB, 0xfc0007fe00000000, 0x7c00018000000000, 0x40000100000000, // Compare Ranged Byte X-form (cmprb BF,L,RA,RB) 3489 [6]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_Reg_16_20}}, 3490 {CNTTZD, 0xfc0007ff00000000, 0x7c00047400000000, 0xf80000000000, // Count Trailing Zeros Doubleword X-form (cnttzd RA,RS) 3491 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 3492 {CNTTZDCC, 0xfc0007ff00000000, 0x7c00047500000000, 0xf80000000000, // Count Trailing Zeros Doubleword X-form (cnttzd. RA,RS) 3493 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 3494 {CNTTZW, 0xfc0007ff00000000, 0x7c00043400000000, 0xf80000000000, // Count Trailing Zeros Word X-form (cnttzw RA,RS) 3495 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 3496 {CNTTZWCC, 0xfc0007ff00000000, 0x7c00043500000000, 0xf80000000000, // Count Trailing Zeros Word X-form (cnttzw. RA,RS) 3497 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 3498 {COPY, 0xfc2007fe00000000, 0x7c20060c00000000, 0x3c0000100000000, // Copy X-form (copy RA,RB) 3499 [6]*argField{ap_Reg_11_15, ap_Reg_16_20}}, 3500 {CPABORT, 0xfc0007fe00000000, 0x7c00068c00000000, 0x3fff80100000000, // Copy-Paste Abort X-form (cpabort) 3501 [6]*argField{}}, 3502 {DARN, 0xfc0007fe00000000, 0x7c0005e600000000, 0x1cf80100000000, // Deliver A Random Number X-form (darn RT,L) 3503 [6]*argField{ap_Reg_6_10, ap_ImmUnsigned_14_15}}, 3504 {DTSTSFI, 0xfc0007fe00000000, 0xec00054600000000, 0x40000100000000, // DFP Test Significance Immediate X-form (dtstsfi BF,UIM,FRB) 3505 [6]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_15, ap_FPReg_16_20}}, 3506 {DTSTSFIQ, 0xfc0007fe00000000, 0xfc00054600000000, 0x40000100000000, // DFP Test Significance Immediate Quad X-form (dtstsfiq BF,UIM,FRBp) 3507 [6]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_15, ap_FPReg_16_20}}, 3508 {EXTSWSLI, 0xfc0007fd00000000, 0x7c0006f400000000, 0x0, // Extend Sign Word and Shift Left Immediate XS-form (extswsli RA,RS,SH) 3509 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}}, 3510 {EXTSWSLICC, 0xfc0007fd00000000, 0x7c0006f500000000, 0x0, // Extend Sign Word and Shift Left Immediate XS-form (extswsli. RA,RS,SH) 3511 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}}, 3512 {LDAT, 0xfc0007fe00000000, 0x7c0004cc00000000, 0x100000000, // Load Doubleword ATomic X-form (ldat RT,RA,FC) 3513 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, 3514 {LWAT, 0xfc0007fe00000000, 0x7c00048c00000000, 0x100000000, // Load Word ATomic X-form (lwat RT,RA,FC) 3515 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, 3516 {LXSD, 0xfc00000300000000, 0xe400000200000000, 0x0, // Load VSX Scalar Doubleword DS-form (lxsd VRT,DS(RA)) 3517 [6]*argField{ap_VecReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, 3518 {LXSIBZX, 0xfc0007fe00000000, 0x7c00061a00000000, 0x0, // Load VSX Scalar as Integer Byte & Zero Indexed X-form (lxsibzx XT,RA,RB) 3519 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3520 {LXSIHZX, 0xfc0007fe00000000, 0x7c00065a00000000, 0x0, // Load VSX Scalar as Integer Halfword & Zero Indexed X-form (lxsihzx XT,RA,RB) 3521 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3522 {LXSSP, 0xfc00000300000000, 0xe400000300000000, 0x0, // Load VSX Scalar Single-Precision DS-form (lxssp VRT,DS(RA)) 3523 [6]*argField{ap_VecReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, 3524 {LXV, 0xfc00000700000000, 0xf400000100000000, 0x0, // Load VSX Vector DQ-form (lxv XT,DQ(RA)) 3525 [6]*argField{ap_VecSReg_28_28_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}}, 3526 {LXVB16X, 0xfc0007fe00000000, 0x7c0006d800000000, 0x0, // Load VSX Vector Byte*16 Indexed X-form (lxvb16x XT,RA,RB) 3527 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3528 {LXVH8X, 0xfc0007fe00000000, 0x7c00065800000000, 0x0, // Load VSX Vector Halfword*8 Indexed X-form (lxvh8x XT,RA,RB) 3529 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3530 {LXVL, 0xfc0007fe00000000, 0x7c00021a00000000, 0x0, // Load VSX Vector with Length X-form (lxvl XT,RA,RB) 3531 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3532 {LXVLL, 0xfc0007fe00000000, 0x7c00025a00000000, 0x0, // Load VSX Vector with Length Left-justified X-form (lxvll XT,RA,RB) 3533 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3534 {LXVWSX, 0xfc0007fe00000000, 0x7c0002d800000000, 0x0, // Load VSX Vector Word & Splat Indexed X-form (lxvwsx XT,RA,RB) 3535 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3536 {LXVX, 0xfc0007be00000000, 0x7c00021800000000, 0x4000000000, // Load VSX Vector Indexed X-form (lxvx XT,RA,RB) 3537 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3538 {MADDHD, 0xfc00003f00000000, 0x1000003000000000, 0x0, // Multiply-Add High Doubleword VA-form (maddhd RT,RA,RB,RC) 3539 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_Reg_21_25}}, 3540 {MADDHDU, 0xfc00003f00000000, 0x1000003100000000, 0x0, // Multiply-Add High Doubleword Unsigned VA-form (maddhdu RT,RA,RB,RC) 3541 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_Reg_21_25}}, 3542 {MADDLD, 0xfc00003f00000000, 0x1000003300000000, 0x0, // Multiply-Add Low Doubleword VA-form (maddld RT,RA,RB,RC) 3543 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_Reg_21_25}}, 3544 {MCRXRX, 0xfc0007fe00000000, 0x7c00048000000000, 0x7ff80100000000, // Move to CR from XER Extended X-form (mcrxrx BF) 3545 [6]*argField{ap_CondRegField_6_8}}, 3546 {MFVSRLD, 0xfc0007fe00000000, 0x7c00026600000000, 0xf80000000000, // Move From VSR Lower Doubleword X-form (mfvsrld RA,XS) 3547 [6]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}}, 3548 {MODSD, 0xfc0007fe00000000, 0x7c00061200000000, 0x100000000, // Modulo Signed Doubleword X-form (modsd RT,RA,RB) 3549 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3550 {MODSW, 0xfc0007fe00000000, 0x7c00061600000000, 0x100000000, // Modulo Signed Word X-form (modsw RT,RA,RB) 3551 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3552 {MODUD, 0xfc0007fe00000000, 0x7c00021200000000, 0x100000000, // Modulo Unsigned Doubleword X-form (modud RT,RA,RB) 3553 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3554 {MODUW, 0xfc0007fe00000000, 0x7c00021600000000, 0x100000000, // Modulo Unsigned Word X-form (moduw RT,RA,RB) 3555 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3556 {MSGSYNC, 0xfc0007fe00000000, 0x7c0006ec00000000, 0x3fff80100000000, // Message Synchronize X-form (msgsync) 3557 [6]*argField{}}, 3558 {MTVSRDD, 0xfc0007fe00000000, 0x7c00036600000000, 0x0, // Move To VSR Double Doubleword X-form (mtvsrdd XT,RA,RB) 3559 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3560 {MTVSRWS, 0xfc0007fe00000000, 0x7c00032600000000, 0xf80000000000, // Move To VSR Word & Splat X-form (mtvsrws XT,RA) 3561 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}}, 3562 {PASTECC, 0xfc0007ff00000000, 0x7c00070d00000000, 0x3c0000000000000, // Paste X-form (paste. RA,RB,L) 3563 [6]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_10_10}}, 3564 {SETB, 0xfc0007fe00000000, 0x7c00010000000000, 0x3f80100000000, // Set Boolean X-form (setb RT,BFA) 3565 [6]*argField{ap_Reg_6_10, ap_CondRegField_11_13}}, 3566 {SLBIEG, 0xfc0007fe00000000, 0x7c0003a400000000, 0x1f000100000000, // SLB Invalidate Entry Global X-form (slbieg RS,RB) 3567 [6]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 3568 {SLBSYNC, 0xfc0007fe00000000, 0x7c0002a400000000, 0x3fff80100000000, // SLB Synchronize X-form (slbsync) 3569 [6]*argField{}}, 3570 {STDAT, 0xfc0007fe00000000, 0x7c0005cc00000000, 0x100000000, // Store Doubleword ATomic X-form (stdat RS,RA,FC) 3571 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, 3572 {STOP, 0xfc0007fe00000000, 0x4c0002e400000000, 0x3fff80100000000, // Stop XL-form (stop) 3573 [6]*argField{}}, 3574 {STWAT, 0xfc0007fe00000000, 0x7c00058c00000000, 0x100000000, // Store Word ATomic X-form (stwat RS,RA,FC) 3575 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, 3576 {STXSD, 0xfc00000300000000, 0xf400000200000000, 0x0, // Store VSX Scalar Doubleword DS-form (stxsd VRS,DS(RA)) 3577 [6]*argField{ap_VecReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, 3578 {STXSIBX, 0xfc0007fe00000000, 0x7c00071a00000000, 0x0, // Store VSX Scalar as Integer Byte Indexed X-form (stxsibx XS,RA,RB) 3579 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3580 {STXSIHX, 0xfc0007fe00000000, 0x7c00075a00000000, 0x0, // Store VSX Scalar as Integer Halfword Indexed X-form (stxsihx XS,RA,RB) 3581 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3582 {STXSSP, 0xfc00000300000000, 0xf400000300000000, 0x0, // Store VSX Scalar Single DS-form (stxssp VRS,DS(RA)) 3583 [6]*argField{ap_VecReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, 3584 {STXV, 0xfc00000700000000, 0xf400000500000000, 0x0, // Store VSX Vector DQ-form (stxv XS,DQ(RA)) 3585 [6]*argField{ap_VecSReg_28_28_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}}, 3586 {STXVB16X, 0xfc0007fe00000000, 0x7c0007d800000000, 0x0, // Store VSX Vector Byte*16 Indexed X-form (stxvb16x XS,RA,RB) 3587 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3588 {STXVH8X, 0xfc0007fe00000000, 0x7c00075800000000, 0x0, // Store VSX Vector Halfword*8 Indexed X-form (stxvh8x XS,RA,RB) 3589 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3590 {STXVL, 0xfc0007fe00000000, 0x7c00031a00000000, 0x0, // Store VSX Vector with Length X-form (stxvl XS,RA,RB) 3591 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3592 {STXVLL, 0xfc0007fe00000000, 0x7c00035a00000000, 0x0, // Store VSX Vector with Length Left-justified X-form (stxvll XS,RA,RB) 3593 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3594 {STXVX, 0xfc0007fe00000000, 0x7c00031800000000, 0x0, // Store VSX Vector Indexed X-form (stxvx XS,RA,RB) 3595 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3596 {VABSDUB, 0xfc0007ff00000000, 0x1000040300000000, 0x0, // Vector Absolute Difference Unsigned Byte VX-form (vabsdub VRT,VRA,VRB) 3597 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3598 {VABSDUH, 0xfc0007ff00000000, 0x1000044300000000, 0x0, // Vector Absolute Difference Unsigned Halfword VX-form (vabsduh VRT,VRA,VRB) 3599 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3600 {VABSDUW, 0xfc0007ff00000000, 0x1000048300000000, 0x0, // Vector Absolute Difference Unsigned Word VX-form (vabsduw VRT,VRA,VRB) 3601 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3602 {VBPERMD, 0xfc0007ff00000000, 0x100005cc00000000, 0x0, // Vector Bit Permute Doubleword VX-form (vbpermd VRT,VRA,VRB) 3603 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3604 {VCLZLSBB, 0xfc1f07ff00000000, 0x1000060200000000, 0x0, // Vector Count Leading Zero Least-Significant Bits Byte VX-form (vclzlsbb RT,VRB) 3605 [6]*argField{ap_Reg_6_10, ap_VecReg_16_20}}, 3606 {VCMPNEB, 0xfc0007ff00000000, 0x1000000700000000, 0x0, // Vector Compare Not Equal Byte VC-form (vcmpneb VRT,VRA,VRB) 3607 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3608 {VCMPNEBCC, 0xfc0007ff00000000, 0x1000040700000000, 0x0, // Vector Compare Not Equal Byte VC-form (vcmpneb. VRT,VRA,VRB) 3609 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3610 {VCMPNEH, 0xfc0007ff00000000, 0x1000004700000000, 0x0, // Vector Compare Not Equal Halfword VC-form (vcmpneh VRT,VRA,VRB) 3611 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3612 {VCMPNEHCC, 0xfc0007ff00000000, 0x1000044700000000, 0x0, // Vector Compare Not Equal Halfword VC-form (vcmpneh. VRT,VRA,VRB) 3613 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3614 {VCMPNEW, 0xfc0007ff00000000, 0x1000008700000000, 0x0, // Vector Compare Not Equal Word VC-form (vcmpnew VRT,VRA,VRB) 3615 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3616 {VCMPNEWCC, 0xfc0007ff00000000, 0x1000048700000000, 0x0, // Vector Compare Not Equal Word VC-form (vcmpnew. VRT,VRA,VRB) 3617 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3618 {VCMPNEZB, 0xfc0007ff00000000, 0x1000010700000000, 0x0, // Vector Compare Not Equal or Zero Byte VC-form (vcmpnezb VRT,VRA,VRB) 3619 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3620 {VCMPNEZBCC, 0xfc0007ff00000000, 0x1000050700000000, 0x0, // Vector Compare Not Equal or Zero Byte VC-form (vcmpnezb. VRT,VRA,VRB) 3621 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3622 {VCMPNEZH, 0xfc0007ff00000000, 0x1000014700000000, 0x0, // Vector Compare Not Equal or Zero Halfword VC-form (vcmpnezh VRT,VRA,VRB) 3623 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3624 {VCMPNEZHCC, 0xfc0007ff00000000, 0x1000054700000000, 0x0, // Vector Compare Not Equal or Zero Halfword VC-form (vcmpnezh. VRT,VRA,VRB) 3625 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3626 {VCMPNEZW, 0xfc0007ff00000000, 0x1000018700000000, 0x0, // Vector Compare Not Equal or Zero Word VC-form (vcmpnezw VRT,VRA,VRB) 3627 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3628 {VCMPNEZWCC, 0xfc0007ff00000000, 0x1000058700000000, 0x0, // Vector Compare Not Equal or Zero Word VC-form (vcmpnezw. VRT,VRA,VRB) 3629 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3630 {VCTZB, 0xfc1f07ff00000000, 0x101c060200000000, 0x0, // Vector Count Trailing Zeros Byte VX-form (vctzb VRT,VRB) 3631 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3632 {VCTZD, 0xfc1f07ff00000000, 0x101f060200000000, 0x0, // Vector Count Trailing Zeros Doubleword VX-form (vctzd VRT,VRB) 3633 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3634 {VCTZH, 0xfc1f07ff00000000, 0x101d060200000000, 0x0, // Vector Count Trailing Zeros Halfword VX-form (vctzh VRT,VRB) 3635 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3636 {VCTZLSBB, 0xfc1f07ff00000000, 0x1001060200000000, 0x0, // Vector Count Trailing Zero Least-Significant Bits Byte VX-form (vctzlsbb RT,VRB) 3637 [6]*argField{ap_Reg_6_10, ap_VecReg_16_20}}, 3638 {VCTZW, 0xfc1f07ff00000000, 0x101e060200000000, 0x0, // Vector Count Trailing Zeros Word VX-form (vctzw VRT,VRB) 3639 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3640 {VEXTRACTD, 0xfc0007ff00000000, 0x100002cd00000000, 0x10000000000000, // Vector Extract Doubleword to VSR using immediate-specified index VX-form (vextractd VRT,VRB,UIM) 3641 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}}, 3642 {VEXTRACTUB, 0xfc0007ff00000000, 0x1000020d00000000, 0x10000000000000, // Vector Extract Unsigned Byte to VSR using immediate-specified index VX-form (vextractub VRT,VRB,UIM) 3643 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}}, 3644 {VEXTRACTUH, 0xfc0007ff00000000, 0x1000024d00000000, 0x10000000000000, // Vector Extract Unsigned Halfword to VSR using immediate-specified index VX-form (vextractuh VRT,VRB,UIM) 3645 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}}, 3646 {VEXTRACTUW, 0xfc0007ff00000000, 0x1000028d00000000, 0x10000000000000, // Vector Extract Unsigned Word to VSR using immediate-specified index VX-form (vextractuw VRT,VRB,UIM) 3647 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}}, 3648 {VEXTSB2D, 0xfc1f07ff00000000, 0x1018060200000000, 0x0, // Vector Extend Sign Byte To Doubleword VX-form (vextsb2d VRT,VRB) 3649 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3650 {VEXTSB2W, 0xfc1f07ff00000000, 0x1010060200000000, 0x0, // Vector Extend Sign Byte To Word VX-form (vextsb2w VRT,VRB) 3651 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3652 {VEXTSH2D, 0xfc1f07ff00000000, 0x1019060200000000, 0x0, // Vector Extend Sign Halfword To Doubleword VX-form (vextsh2d VRT,VRB) 3653 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3654 {VEXTSH2W, 0xfc1f07ff00000000, 0x1011060200000000, 0x0, // Vector Extend Sign Halfword To Word VX-form (vextsh2w VRT,VRB) 3655 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3656 {VEXTSW2D, 0xfc1f07ff00000000, 0x101a060200000000, 0x0, // Vector Extend Sign Word To Doubleword VX-form (vextsw2d VRT,VRB) 3657 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3658 {VEXTUBLX, 0xfc0007ff00000000, 0x1000060d00000000, 0x0, // Vector Extract Unsigned Byte to GPR using GPR-specified Left-Index VX-form (vextublx RT,RA,VRB) 3659 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_VecReg_16_20}}, 3660 {VEXTUBRX, 0xfc0007ff00000000, 0x1000070d00000000, 0x0, // Vector Extract Unsigned Byte to GPR using GPR-specified Right-Index VX-form (vextubrx RT,RA,VRB) 3661 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_VecReg_16_20}}, 3662 {VEXTUHLX, 0xfc0007ff00000000, 0x1000064d00000000, 0x0, // Vector Extract Unsigned Halfword to GPR using GPR-specified Left-Index VX-form (vextuhlx RT,RA,VRB) 3663 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_VecReg_16_20}}, 3664 {VEXTUHRX, 0xfc0007ff00000000, 0x1000074d00000000, 0x0, // Vector Extract Unsigned Halfword to GPR using GPR-specified Right-Index VX-form (vextuhrx RT,RA,VRB) 3665 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_VecReg_16_20}}, 3666 {VEXTUWLX, 0xfc0007ff00000000, 0x1000068d00000000, 0x0, // Vector Extract Unsigned Word to GPR using GPR-specified Left-Index VX-form (vextuwlx RT,RA,VRB) 3667 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_VecReg_16_20}}, 3668 {VEXTUWRX, 0xfc0007ff00000000, 0x1000078d00000000, 0x0, // Vector Extract Unsigned Word to GPR using GPR-specified Right-Index VX-form (vextuwrx RT,RA,VRB) 3669 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_VecReg_16_20}}, 3670 {VINSERTB, 0xfc0007ff00000000, 0x1000030d00000000, 0x10000000000000, // Vector Insert Byte from VSR using immediate-specified index VX-form (vinsertb VRT,VRB,UIM) 3671 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}}, 3672 {VINSERTD, 0xfc0007ff00000000, 0x100003cd00000000, 0x10000000000000, // Vector Insert Doubleword from VSR using immediate-specified index VX-form (vinsertd VRT,VRB,UIM) 3673 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}}, 3674 {VINSERTH, 0xfc0007ff00000000, 0x1000034d00000000, 0x10000000000000, // Vector Insert Halfword from VSR using immediate-specified index VX-form (vinserth VRT,VRB,UIM) 3675 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}}, 3676 {VINSERTW, 0xfc0007ff00000000, 0x1000038d00000000, 0x10000000000000, // Vector Insert Word from VSR using immediate-specified index VX-form (vinsertw VRT,VRB,UIM) 3677 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}}, 3678 {VMUL10CUQ, 0xfc0007ff00000000, 0x1000000100000000, 0xf80000000000, // Vector Multiply-by-10 & write Carry-out Unsigned Quadword VX-form (vmul10cuq VRT,VRA) 3679 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15}}, 3680 {VMUL10ECUQ, 0xfc0007ff00000000, 0x1000004100000000, 0x0, // Vector Multiply-by-10 Extended & write Carry-out Unsigned Quadword VX-form (vmul10ecuq VRT,VRA,VRB) 3681 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3682 {VMUL10EUQ, 0xfc0007ff00000000, 0x1000024100000000, 0x0, // Vector Multiply-by-10 Extended Unsigned Quadword VX-form (vmul10euq VRT,VRA,VRB) 3683 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3684 {VMUL10UQ, 0xfc0007ff00000000, 0x1000020100000000, 0xf80000000000, // Vector Multiply-by-10 Unsigned Quadword VX-form (vmul10uq VRT,VRA) 3685 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15}}, 3686 {VNEGD, 0xfc1f07ff00000000, 0x1007060200000000, 0x0, // Vector Negate Doubleword VX-form (vnegd VRT,VRB) 3687 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3688 {VNEGW, 0xfc1f07ff00000000, 0x1006060200000000, 0x0, // Vector Negate Word VX-form (vnegw VRT,VRB) 3689 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3690 {VPERMR, 0xfc00003f00000000, 0x1000003b00000000, 0x0, // Vector Permute Right-indexed VA-form (vpermr VRT,VRA,VRB,VRC) 3691 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3692 {VPRTYBD, 0xfc1f07ff00000000, 0x1009060200000000, 0x0, // Vector Parity Byte Doubleword VX-form (vprtybd VRT,VRB) 3693 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3694 {VPRTYBQ, 0xfc1f07ff00000000, 0x100a060200000000, 0x0, // Vector Parity Byte Quadword VX-form (vprtybq VRT,VRB) 3695 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3696 {VPRTYBW, 0xfc1f07ff00000000, 0x1008060200000000, 0x0, // Vector Parity Byte Word VX-form (vprtybw VRT,VRB) 3697 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3698 {VRLDMI, 0xfc0007ff00000000, 0x100000c500000000, 0x0, // Vector Rotate Left Doubleword then Mask Insert VX-form (vrldmi VRT,VRA,VRB) 3699 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3700 {VRLDNM, 0xfc0007ff00000000, 0x100001c500000000, 0x0, // Vector Rotate Left Doubleword then AND with Mask VX-form (vrldnm VRT,VRA,VRB) 3701 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3702 {VRLWMI, 0xfc0007ff00000000, 0x1000008500000000, 0x0, // Vector Rotate Left Word then Mask Insert VX-form (vrlwmi VRT,VRA,VRB) 3703 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3704 {VRLWNM, 0xfc0007ff00000000, 0x1000018500000000, 0x0, // Vector Rotate Left Word then AND with Mask VX-form (vrlwnm VRT,VRA,VRB) 3705 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3706 {VSLV, 0xfc0007ff00000000, 0x1000074400000000, 0x0, // Vector Shift Left Variable VX-form (vslv VRT,VRA,VRB) 3707 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3708 {VSRV, 0xfc0007ff00000000, 0x1000070400000000, 0x0, // Vector Shift Right Variable VX-form (vsrv VRT,VRA,VRB) 3709 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3710 {WAIT, 0xfc0007fe00000000, 0x7c00003c00000000, 0x9cf80100000000, // Wait X-form (wait WC,PL) 3711 [6]*argField{ap_ImmUnsigned_9_10, ap_ImmUnsigned_14_15}}, 3712 {XSABSQP, 0xfc1f07fe00000000, 0xfc00064800000000, 0x100000000, // VSX Scalar Absolute Quad-Precision X-form (xsabsqp VRT,VRB) 3713 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3714 {XSADDQP, 0xfc0007ff00000000, 0xfc00000800000000, 0x0, // VSX Scalar Add Quad-Precision [using round to Odd] X-form (xsaddqp VRT,VRA,VRB) 3715 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3716 {XSADDQPO, 0xfc0007ff00000000, 0xfc00000900000000, 0x0, // VSX Scalar Add Quad-Precision [using round to Odd] X-form (xsaddqpo VRT,VRA,VRB) 3717 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3718 {XSCMPEQDP, 0xfc0007f800000000, 0xf000001800000000, 0x0, // VSX Scalar Compare Equal Double-Precision XX3-form (xscmpeqdp XT,XA,XB) 3719 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3720 {XSCMPEXPDP, 0xfc0007f800000000, 0xf00001d800000000, 0x60000100000000, // VSX Scalar Compare Exponents Double-Precision XX3-form (xscmpexpdp BF,XA,XB) 3721 [6]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3722 {XSCMPEXPQP, 0xfc0007fe00000000, 0xfc00014800000000, 0x60000100000000, // VSX Scalar Compare Exponents Quad-Precision X-form (xscmpexpqp BF,VRA,VRB) 3723 [6]*argField{ap_CondRegField_6_8, ap_VecReg_11_15, ap_VecReg_16_20}}, 3724 {XSCMPGEDP, 0xfc0007f800000000, 0xf000009800000000, 0x0, // VSX Scalar Compare Greater Than or Equal Double-Precision XX3-form (xscmpgedp XT,XA,XB) 3725 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3726 {XSCMPGTDP, 0xfc0007f800000000, 0xf000005800000000, 0x0, // VSX Scalar Compare Greater Than Double-Precision XX3-form (xscmpgtdp XT,XA,XB) 3727 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3728 {XSCMPOQP, 0xfc0007fe00000000, 0xfc00010800000000, 0x60000100000000, // VSX Scalar Compare Ordered Quad-Precision X-form (xscmpoqp BF,VRA,VRB) 3729 [6]*argField{ap_CondRegField_6_8, ap_VecReg_11_15, ap_VecReg_16_20}}, 3730 {XSCMPUQP, 0xfc0007fe00000000, 0xfc00050800000000, 0x60000100000000, // VSX Scalar Compare Unordered Quad-Precision X-form (xscmpuqp BF,VRA,VRB) 3731 [6]*argField{ap_CondRegField_6_8, ap_VecReg_11_15, ap_VecReg_16_20}}, 3732 {XSCPSGNQP, 0xfc0007fe00000000, 0xfc0000c800000000, 0x100000000, // VSX Scalar Copy Sign Quad-Precision X-form (xscpsgnqp VRT,VRA,VRB) 3733 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3734 {XSCVDPHP, 0xfc1f07fc00000000, 0xf011056c00000000, 0x0, // VSX Scalar Convert with round Double-Precision to Half-Precision format XX2-form (xscvdphp XT,XB) 3735 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 3736 {XSCVDPQP, 0xfc1f07fe00000000, 0xfc16068800000000, 0x100000000, // VSX Scalar Convert Double-Precision to Quad-Precision format X-form (xscvdpqp VRT,VRB) 3737 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3738 {XSCVHPDP, 0xfc1f07fc00000000, 0xf010056c00000000, 0x0, // VSX Scalar Convert Half-Precision to Double-Precision format XX2-form (xscvhpdp XT,XB) 3739 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 3740 {XSCVQPDP, 0xfc1f07ff00000000, 0xfc14068800000000, 0x0, // VSX Scalar Convert with round Quad-Precision to Double-Precision format [using round to Odd] X-form (xscvqpdp VRT,VRB) 3741 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3742 {XSCVQPDPO, 0xfc1f07ff00000000, 0xfc14068900000000, 0x0, // VSX Scalar Convert with round Quad-Precision to Double-Precision format [using round to Odd] X-form (xscvqpdpo VRT,VRB) 3743 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3744 {XSCVQPSDZ, 0xfc1f07fe00000000, 0xfc19068800000000, 0x100000000, // VSX Scalar Convert with round to zero Quad-Precision to Signed Doubleword format X-form (xscvqpsdz VRT,VRB) 3745 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3746 {XSCVQPSWZ, 0xfc1f07fe00000000, 0xfc09068800000000, 0x100000000, // VSX Scalar Convert with round to zero Quad-Precision to Signed Word format X-form (xscvqpswz VRT,VRB) 3747 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3748 {XSCVQPUDZ, 0xfc1f07fe00000000, 0xfc11068800000000, 0x100000000, // VSX Scalar Convert with round to zero Quad-Precision to Unsigned Doubleword format X-form (xscvqpudz VRT,VRB) 3749 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3750 {XSCVQPUWZ, 0xfc1f07fe00000000, 0xfc01068800000000, 0x100000000, // VSX Scalar Convert with round to zero Quad-Precision to Unsigned Word format X-form (xscvqpuwz VRT,VRB) 3751 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3752 {XSCVSDQP, 0xfc1f07fe00000000, 0xfc0a068800000000, 0x100000000, // VSX Scalar Convert Signed Doubleword to Quad-Precision format X-form (xscvsdqp VRT,VRB) 3753 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3754 {XSCVUDQP, 0xfc1f07fe00000000, 0xfc02068800000000, 0x100000000, // VSX Scalar Convert Unsigned Doubleword to Quad-Precision format X-form (xscvudqp VRT,VRB) 3755 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3756 {XSDIVQP, 0xfc0007ff00000000, 0xfc00044800000000, 0x0, // VSX Scalar Divide Quad-Precision [using round to Odd] X-form (xsdivqp VRT,VRA,VRB) 3757 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3758 {XSDIVQPO, 0xfc0007ff00000000, 0xfc00044900000000, 0x0, // VSX Scalar Divide Quad-Precision [using round to Odd] X-form (xsdivqpo VRT,VRA,VRB) 3759 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3760 {XSIEXPDP, 0xfc0007fe00000000, 0xf000072c00000000, 0x0, // VSX Scalar Insert Exponent Double-Precision X-form (xsiexpdp XT,RA,RB) 3761 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3762 {XSIEXPQP, 0xfc0007fe00000000, 0xfc0006c800000000, 0x100000000, // VSX Scalar Insert Exponent Quad-Precision X-form (xsiexpqp VRT,VRA,VRB) 3763 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3764 {XSMADDQP, 0xfc0007ff00000000, 0xfc00030800000000, 0x0, // VSX Scalar Multiply-Add Quad-Precision [using round to Odd] X-form (xsmaddqp VRT,VRA,VRB) 3765 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3766 {XSMADDQPO, 0xfc0007ff00000000, 0xfc00030900000000, 0x0, // VSX Scalar Multiply-Add Quad-Precision [using round to Odd] X-form (xsmaddqpo VRT,VRA,VRB) 3767 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3768 {XSMAXCDP, 0xfc0007f800000000, 0xf000040000000000, 0x0, // VSX Scalar Maximum Type-C Double-Precision XX3-form (xsmaxcdp XT,XA,XB) 3769 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3770 {XSMAXJDP, 0xfc0007f800000000, 0xf000048000000000, 0x0, // VSX Scalar Maximum Type-J Double-Precision XX3-form (xsmaxjdp XT,XA,XB) 3771 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3772 {XSMINCDP, 0xfc0007f800000000, 0xf000044000000000, 0x0, // VSX Scalar Minimum Type-C Double-Precision XX3-form (xsmincdp XT,XA,XB) 3773 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3774 {XSMINJDP, 0xfc0007f800000000, 0xf00004c000000000, 0x0, // VSX Scalar Minimum Type-J Double-Precision XX3-form (xsminjdp XT,XA,XB) 3775 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3776 {XSMSUBQP, 0xfc0007ff00000000, 0xfc00034800000000, 0x0, // VSX Scalar Multiply-Subtract Quad-Precision [using round to Odd] X-form (xsmsubqp VRT,VRA,VRB) 3777 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3778 {XSMSUBQPO, 0xfc0007ff00000000, 0xfc00034900000000, 0x0, // VSX Scalar Multiply-Subtract Quad-Precision [using round to Odd] X-form (xsmsubqpo VRT,VRA,VRB) 3779 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3780 {XSMULQP, 0xfc0007ff00000000, 0xfc00004800000000, 0x0, // VSX Scalar Multiply Quad-Precision [using round to Odd] X-form (xsmulqp VRT,VRA,VRB) 3781 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3782 {XSMULQPO, 0xfc0007ff00000000, 0xfc00004900000000, 0x0, // VSX Scalar Multiply Quad-Precision [using round to Odd] X-form (xsmulqpo VRT,VRA,VRB) 3783 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3784 {XSNABSQP, 0xfc1f07fe00000000, 0xfc08064800000000, 0x0, // VSX Scalar Negative Absolute Quad-Precision X-form (xsnabsqp VRT,VRB) 3785 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3786 {XSNEGQP, 0xfc1f07fe00000000, 0xfc10064800000000, 0x100000000, // VSX Scalar Negate Quad-Precision X-form (xsnegqp VRT,VRB) 3787 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3788 {XSNMADDQP, 0xfc0007ff00000000, 0xfc00038800000000, 0x0, // VSX Scalar Negative Multiply-Add Quad-Precision [using round to Odd] X-form (xsnmaddqp VRT,VRA,VRB) 3789 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3790 {XSNMADDQPO, 0xfc0007ff00000000, 0xfc00038900000000, 0x0, // VSX Scalar Negative Multiply-Add Quad-Precision [using round to Odd] X-form (xsnmaddqpo VRT,VRA,VRB) 3791 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3792 {XSNMSUBQP, 0xfc0007ff00000000, 0xfc0003c800000000, 0x0, // VSX Scalar Negative Multiply-Subtract Quad-Precision [using round to Odd] X-form (xsnmsubqp VRT,VRA,VRB) 3793 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3794 {XSNMSUBQPO, 0xfc0007ff00000000, 0xfc0003c900000000, 0x0, // VSX Scalar Negative Multiply-Subtract Quad-Precision [using round to Odd] X-form (xsnmsubqpo VRT,VRA,VRB) 3795 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3796 {XSRQPI, 0xfc0001ff00000000, 0xfc00000a00000000, 0x1e000000000000, // VSX Scalar Round to Quad-Precision Integer [with Inexact] Z23-form (xsrqpi R,VRT,VRB,RMC) 3797 [6]*argField{ap_ImmUnsigned_15_15, ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_21_22}}, 3798 {XSRQPIX, 0xfc0001ff00000000, 0xfc00000b00000000, 0x1e000000000000, // VSX Scalar Round to Quad-Precision Integer [with Inexact] Z23-form (xsrqpix R,VRT,VRB,RMC) 3799 [6]*argField{ap_ImmUnsigned_15_15, ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_21_22}}, 3800 {XSRQPXP, 0xfc0001fe00000000, 0xfc00004a00000000, 0x1e000100000000, // VSX Scalar Round Quad-Precision to Double-Extended Precision Z23-form (xsrqpxp R,VRT,VRB,RMC) 3801 [6]*argField{ap_ImmUnsigned_15_15, ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_21_22}}, 3802 {XSSQRTQP, 0xfc1f07ff00000000, 0xfc1b064800000000, 0x0, // VSX Scalar Square Root Quad-Precision [using round to Odd] X-form (xssqrtqp VRT,VRB) 3803 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3804 {XSSQRTQPO, 0xfc1f07ff00000000, 0xfc1b064900000000, 0x0, // VSX Scalar Square Root Quad-Precision [using round to Odd] X-form (xssqrtqpo VRT,VRB) 3805 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3806 {XSSUBQP, 0xfc0007ff00000000, 0xfc00040800000000, 0x0, // VSX Scalar Subtract Quad-Precision [using round to Odd] X-form (xssubqp VRT,VRA,VRB) 3807 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3808 {XSSUBQPO, 0xfc0007ff00000000, 0xfc00040900000000, 0x0, // VSX Scalar Subtract Quad-Precision [using round to Odd] X-form (xssubqpo VRT,VRA,VRB) 3809 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3810 {XSTSTDCDP, 0xfc0007fc00000000, 0xf00005a800000000, 0x100000000, // VSX Scalar Test Data Class Double-Precision XX2-form (xststdcdp BF,XB,DCMX) 3811 [6]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_9_15}}, 3812 {XSTSTDCQP, 0xfc0007fe00000000, 0xfc00058800000000, 0x100000000, // VSX Scalar Test Data Class Quad-Precision X-form (xststdcqp BF,VRB,DCMX) 3813 [6]*argField{ap_CondRegField_6_8, ap_VecReg_16_20, ap_ImmUnsigned_9_15}}, 3814 {XSTSTDCSP, 0xfc0007fc00000000, 0xf00004a800000000, 0x100000000, // VSX Scalar Test Data Class Single-Precision XX2-form (xststdcsp BF,XB,DCMX) 3815 [6]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_9_15}}, 3816 {XSXEXPDP, 0xfc1f07fc00000000, 0xf000056c00000000, 0x100000000, // VSX Scalar Extract Exponent Double-Precision XX2-form (xsxexpdp RT,XB) 3817 [6]*argField{ap_Reg_6_10, ap_VecSReg_30_30_16_20}}, 3818 {XSXEXPQP, 0xfc1f07fe00000000, 0xfc02064800000000, 0x100000000, // VSX Scalar Extract Exponent Quad-Precision X-form (xsxexpqp VRT,VRB) 3819 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3820 {XSXSIGDP, 0xfc1f07fc00000000, 0xf001056c00000000, 0x100000000, // VSX Scalar Extract Significand Double-Precision XX2-form (xsxsigdp RT,XB) 3821 [6]*argField{ap_Reg_6_10, ap_VecSReg_30_30_16_20}}, 3822 {XSXSIGQP, 0xfc1f07fe00000000, 0xfc12064800000000, 0x100000000, // VSX Scalar Extract Significand Quad-Precision X-form (xsxsigqp VRT,VRB) 3823 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3824 {XVCVHPSP, 0xfc1f07fc00000000, 0xf018076c00000000, 0x0, // VSX Vector Convert Half-Precision to Single-Precision format XX2-form (xvcvhpsp XT,XB) 3825 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 3826 {XVCVSPHP, 0xfc1f07fc00000000, 0xf019076c00000000, 0x0, // VSX Vector Convert with round Single-Precision to Half-Precision format XX2-form (xvcvsphp XT,XB) 3827 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 3828 {XVIEXPDP, 0xfc0007f800000000, 0xf00007c000000000, 0x0, // VSX Vector Insert Exponent Double-Precision XX3-form (xviexpdp XT,XA,XB) 3829 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3830 {XVIEXPSP, 0xfc0007f800000000, 0xf00006c000000000, 0x0, // VSX Vector Insert Exponent Single-Precision XX3-form (xviexpsp XT,XA,XB) 3831 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3832 {XVTSTDCDP, 0xfc0007b800000000, 0xf00007a800000000, 0x0, // VSX Vector Test Data Class Double-Precision XX2-form (xvtstdcdp XT,XB,DCMX) 3833 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_25_25_29_29_11_15}}, 3834 {XVTSTDCSP, 0xfc0007b800000000, 0xf00006a800000000, 0x0, // VSX Vector Test Data Class Single-Precision XX2-form (xvtstdcsp XT,XB,DCMX) 3835 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_25_25_29_29_11_15}}, 3836 {XVXEXPDP, 0xfc1f07fc00000000, 0xf000076c00000000, 0x0, // VSX Vector Extract Exponent Double-Precision XX2-form (xvxexpdp XT,XB) 3837 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 3838 {XVXEXPSP, 0xfc1f07fc00000000, 0xf008076c00000000, 0x0, // VSX Vector Extract Exponent Single-Precision XX2-form (xvxexpsp XT,XB) 3839 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 3840 {XVXSIGDP, 0xfc1f07fc00000000, 0xf001076c00000000, 0x0, // VSX Vector Extract Significand Double-Precision XX2-form (xvxsigdp XT,XB) 3841 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 3842 {XVXSIGSP, 0xfc1f07fc00000000, 0xf009076c00000000, 0x0, // VSX Vector Extract Significand Single-Precision XX2-form (xvxsigsp XT,XB) 3843 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 3844 {XXBRD, 0xfc1f07fc00000000, 0xf017076c00000000, 0x0, // VSX Vector Byte-Reverse Doubleword XX2-form (xxbrd XT,XB) 3845 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 3846 {XXBRH, 0xfc1f07fc00000000, 0xf007076c00000000, 0x0, // VSX Vector Byte-Reverse Halfword XX2-form (xxbrh XT,XB) 3847 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 3848 {XXBRQ, 0xfc1f07fc00000000, 0xf01f076c00000000, 0x0, // VSX Vector Byte-Reverse Quadword XX2-form (xxbrq XT,XB) 3849 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 3850 {XXBRW, 0xfc1f07fc00000000, 0xf00f076c00000000, 0x0, // VSX Vector Byte-Reverse Word XX2-form (xxbrw XT,XB) 3851 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 3852 {XXEXTRACTUW, 0xfc0007fc00000000, 0xf000029400000000, 0x10000000000000, // VSX Vector Extract Unsigned Word XX2-form (xxextractuw XT,XB,UIM) 3853 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_12_15}}, 3854 {XXINSERTW, 0xfc0007fc00000000, 0xf00002d400000000, 0x10000000000000, // VSX Vector Insert Word XX2-form (xxinsertw XT,XB,UIM) 3855 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_12_15}}, 3856 {XXPERM, 0xfc0007f800000000, 0xf00000d000000000, 0x0, // VSX Vector Permute XX3-form (xxperm XT,XA,XB) 3857 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3858 {XXPERMR, 0xfc0007f800000000, 0xf00001d000000000, 0x0, // VSX Vector Permute Right-indexed XX3-form (xxpermr XT,XA,XB) 3859 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 3860 {XXSPLTIB, 0xfc1807fe00000000, 0xf00002d000000000, 0x0, // VSX Vector Splat Immediate Byte X-form (xxspltib XT,IMM8) 3861 [6]*argField{ap_VecSReg_31_31_6_10, ap_ImmUnsigned_13_20}}, 3862 {BCDADDCC, 0xfc0005ff00000000, 0x1000040100000000, 0x0, // Decimal Add Modulo VX-form (bcdadd. VRT,VRA,VRB,PS) 3863 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}}, 3864 {BCDSUBCC, 0xfc0005ff00000000, 0x1000044100000000, 0x0, // Decimal Subtract Modulo VX-form (bcdsub. VRT,VRA,VRB,PS) 3865 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}}, 3866 {BCTAR, 0xfc0007ff00000000, 0x4c00046000000000, 0xe00000000000, // Branch Conditional to Branch Target Address Register XL-form (bctar BO,BI,BH) 3867 [6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, 3868 {BCTARL, 0xfc0007ff00000000, 0x4c00046100000000, 0xe00000000000, // Branch Conditional to Branch Target Address Register XL-form (bctarl BO,BI,BH) 3869 [6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, 3870 {CLRBHRB, 0xfc0007fe00000000, 0x7c00035c00000000, 0x3fff80100000000, // Clear BHRB X-form (clrbhrb) 3871 [6]*argField{}}, 3872 {FMRGEW, 0xfc0007fe00000000, 0xfc00078c00000000, 0x100000000, // Floating Merge Even Word X-form (fmrgew FRT,FRA,FRB) 3873 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 3874 {FMRGOW, 0xfc0007fe00000000, 0xfc00068c00000000, 0x100000000, // Floating Merge Odd Word X-form (fmrgow FRT,FRA,FRB) 3875 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 3876 {ICBT, 0xfc0007fe00000000, 0x7c00002c00000000, 0x200000100000000, // Instruction Cache Block Touch X-form (icbt CT, RA, RB) 3877 [6]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, 3878 {LQARX, 0xfc0007fe00000000, 0x7c00022800000000, 0x0, // Load Quadword And Reserve Indexed X-form (lqarx RTp,RA,RB,EH) 3879 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}}, 3880 {LXSIWAX, 0xfc0007fe00000000, 0x7c00009800000000, 0x0, // Load VSX Scalar as Integer Word Algebraic Indexed X-form (lxsiwax XT,RA,RB) 3881 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3882 {LXSIWZX, 0xfc0007fe00000000, 0x7c00001800000000, 0x0, // Load VSX Scalar as Integer Word & Zero Indexed X-form (lxsiwzx XT,RA,RB) 3883 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3884 {LXSSPX, 0xfc0007fe00000000, 0x7c00041800000000, 0x0, // Load VSX Scalar Single-Precision Indexed X-form (lxsspx XT,RA,RB) 3885 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3886 {MFBHRBE, 0xfc0007fe00000000, 0x7c00025c00000000, 0x100000000, // Move From BHRB XFX-form (mfbhrbe RT,BHRBE) 3887 [6]*argField{ap_Reg_6_10, ap_SpReg_11_20}}, 3888 {MFVSRD, 0xfc0007fe00000000, 0x7c00006600000000, 0xf80000000000, // Move From VSR Doubleword X-form (mfvsrd RA,XS) 3889 [6]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}}, 3890 {MFVSRWZ, 0xfc0007fe00000000, 0x7c0000e600000000, 0xf80000000000, // Move From VSR Word and Zero X-form (mfvsrwz RA,XS) 3891 [6]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}}, 3892 {MSGCLR, 0xfc0007fe00000000, 0x7c0001dc00000000, 0x3ff000100000000, // Message Clear X-form (msgclr RB) 3893 [6]*argField{ap_Reg_16_20}}, 3894 {MSGCLRP, 0xfc0007fe00000000, 0x7c00015c00000000, 0x3ff000100000000, // Message Clear Privileged X-form (msgclrp RB) 3895 [6]*argField{ap_Reg_16_20}}, 3896 {MSGSND, 0xfc0007fe00000000, 0x7c00019c00000000, 0x3ff000100000000, // Message Send X-form (msgsnd RB) 3897 [6]*argField{ap_Reg_16_20}}, 3898 {MSGSNDP, 0xfc0007fe00000000, 0x7c00011c00000000, 0x3ff000100000000, // Message Send Privileged X-form (msgsndp RB) 3899 [6]*argField{ap_Reg_16_20}}, 3900 {MTVSRD, 0xfc0007fe00000000, 0x7c00016600000000, 0xf80000000000, // Move To VSR Doubleword X-form (mtvsrd XT,RA) 3901 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}}, 3902 {MTVSRWA, 0xfc0007fe00000000, 0x7c0001a600000000, 0xf80000000000, // Move To VSR Word Algebraic X-form (mtvsrwa XT,RA) 3903 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}}, 3904 {MTVSRWZ, 0xfc0007fe00000000, 0x7c0001e600000000, 0xf80000000000, // Move To VSR Word and Zero X-form (mtvsrwz XT,RA) 3905 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}}, 3906 {RFEBB, 0xfc0007fe00000000, 0x4c00012400000000, 0x3fff00100000000, // Return from Event Based Branch XL-form (rfebb S) 3907 [6]*argField{ap_ImmUnsigned_20_20}}, 3908 {STQCXCC, 0xfc0007ff00000000, 0x7c00016d00000000, 0x0, // Store Quadword Conditional Indexed X-form (stqcx. RSp,RA,RB) 3909 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3910 {STXSIWX, 0xfc0007fe00000000, 0x7c00011800000000, 0x0, // Store VSX Scalar as Integer Word Indexed X-form (stxsiwx XS,RA,RB) 3911 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3912 {STXSSPX, 0xfc0007fe00000000, 0x7c00051800000000, 0x0, // Store VSX Scalar Single-Precision Indexed X-form (stxsspx XS,RA,RB) 3913 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3914 {VADDCUQ, 0xfc0007ff00000000, 0x1000014000000000, 0x0, // Vector Add & write Carry Unsigned Quadword VX-form (vaddcuq VRT,VRA,VRB) 3915 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3916 {VADDECUQ, 0xfc00003f00000000, 0x1000003d00000000, 0x0, // Vector Add Extended & write Carry Unsigned Quadword VA-form (vaddecuq VRT,VRA,VRB,VRC) 3917 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3918 {VADDEUQM, 0xfc00003f00000000, 0x1000003c00000000, 0x0, // Vector Add Extended Unsigned Quadword Modulo VA-form (vaddeuqm VRT,VRA,VRB,VRC) 3919 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3920 {VADDUDM, 0xfc0007ff00000000, 0x100000c000000000, 0x0, // Vector Add Unsigned Doubleword Modulo VX-form (vaddudm VRT,VRA,VRB) 3921 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3922 {VADDUQM, 0xfc0007ff00000000, 0x1000010000000000, 0x0, // Vector Add Unsigned Quadword Modulo VX-form (vadduqm VRT,VRA,VRB) 3923 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3924 {VBPERMQ, 0xfc0007ff00000000, 0x1000054c00000000, 0x0, // Vector Bit Permute Quadword VX-form (vbpermq VRT,VRA,VRB) 3925 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3926 {VCIPHER, 0xfc0007ff00000000, 0x1000050800000000, 0x0, // Vector AES Cipher VX-form (vcipher VRT,VRA,VRB) 3927 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3928 {VCIPHERLAST, 0xfc0007ff00000000, 0x1000050900000000, 0x0, // Vector AES Cipher Last VX-form (vcipherlast VRT,VRA,VRB) 3929 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3930 {VCLZB, 0xfc0007ff00000000, 0x1000070200000000, 0x1f000000000000, // Vector Count Leading Zeros Byte VX-form (vclzb VRT,VRB) 3931 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3932 {VCLZD, 0xfc0007ff00000000, 0x100007c200000000, 0x1f000000000000, // Vector Count Leading Zeros Doubleword VX-form (vclzd VRT,VRB) 3933 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3934 {VCLZH, 0xfc0007ff00000000, 0x1000074200000000, 0x1f000000000000, // Vector Count Leading Zeros Halfword VX-form (vclzh VRT,VRB) 3935 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3936 {VCLZW, 0xfc0007ff00000000, 0x1000078200000000, 0x1f000000000000, // Vector Count Leading Zeros Word VX-form (vclzw VRT,VRB) 3937 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3938 {VCMPEQUD, 0xfc0007ff00000000, 0x100000c700000000, 0x0, // Vector Compare Equal Unsigned Doubleword VC-form (vcmpequd VRT,VRA,VRB) 3939 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3940 {VCMPEQUDCC, 0xfc0007ff00000000, 0x100004c700000000, 0x0, // Vector Compare Equal Unsigned Doubleword VC-form (vcmpequd. VRT,VRA,VRB) 3941 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3942 {VCMPGTSD, 0xfc0007ff00000000, 0x100003c700000000, 0x0, // Vector Compare Greater Than Signed Doubleword VC-form (vcmpgtsd VRT,VRA,VRB) 3943 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3944 {VCMPGTSDCC, 0xfc0007ff00000000, 0x100007c700000000, 0x0, // Vector Compare Greater Than Signed Doubleword VC-form (vcmpgtsd. VRT,VRA,VRB) 3945 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3946 {VCMPGTUD, 0xfc0007ff00000000, 0x100002c700000000, 0x0, // Vector Compare Greater Than Unsigned Doubleword VC-form (vcmpgtud VRT,VRA,VRB) 3947 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3948 {VCMPGTUDCC, 0xfc0007ff00000000, 0x100006c700000000, 0x0, // Vector Compare Greater Than Unsigned Doubleword VC-form (vcmpgtud. VRT,VRA,VRB) 3949 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3950 {VEQV, 0xfc0007ff00000000, 0x1000068400000000, 0x0, // Vector Logical Equivalence VX-form (veqv VRT,VRA,VRB) 3951 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3952 {VGBBD, 0xfc0007ff00000000, 0x1000050c00000000, 0x1f000000000000, // Vector Gather Bits by Bytes by Doubleword VX-form (vgbbd VRT,VRB) 3953 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3954 {VMAXSD, 0xfc0007ff00000000, 0x100001c200000000, 0x0, // Vector Maximum Signed Doubleword VX-form (vmaxsd VRT,VRA,VRB) 3955 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3956 {VMAXUD, 0xfc0007ff00000000, 0x100000c200000000, 0x0, // Vector Maximum Unsigned Doubleword VX-form (vmaxud VRT,VRA,VRB) 3957 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3958 {VMINSD, 0xfc0007ff00000000, 0x100003c200000000, 0x0, // Vector Minimum Signed Doubleword VX-form (vminsd VRT,VRA,VRB) 3959 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3960 {VMINUD, 0xfc0007ff00000000, 0x100002c200000000, 0x0, // Vector Minimum Unsigned Doubleword VX-form (vminud VRT,VRA,VRB) 3961 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3962 {VMRGEW, 0xfc0007ff00000000, 0x1000078c00000000, 0x0, // Vector Merge Even Word VX-form (vmrgew VRT,VRA,VRB) 3963 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3964 {VMRGOW, 0xfc0007ff00000000, 0x1000068c00000000, 0x0, // Vector Merge Odd Word VX-form (vmrgow VRT,VRA,VRB) 3965 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3966 {VMULESW, 0xfc0007ff00000000, 0x1000038800000000, 0x0, // Vector Multiply Even Signed Word VX-form (vmulesw VRT,VRA,VRB) 3967 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3968 {VMULEUW, 0xfc0007ff00000000, 0x1000028800000000, 0x0, // Vector Multiply Even Unsigned Word VX-form (vmuleuw VRT,VRA,VRB) 3969 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3970 {VMULOSW, 0xfc0007ff00000000, 0x1000018800000000, 0x0, // Vector Multiply Odd Signed Word VX-form (vmulosw VRT,VRA,VRB) 3971 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3972 {VMULOUW, 0xfc0007ff00000000, 0x1000008800000000, 0x0, // Vector Multiply Odd Unsigned Word VX-form (vmulouw VRT,VRA,VRB) 3973 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3974 {VMULUWM, 0xfc0007ff00000000, 0x1000008900000000, 0x0, // Vector Multiply Unsigned Word Modulo VX-form (vmuluwm VRT,VRA,VRB) 3975 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3976 {VNAND, 0xfc0007ff00000000, 0x1000058400000000, 0x0, // Vector Logical NAND VX-form (vnand VRT,VRA,VRB) 3977 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3978 {VNCIPHER, 0xfc0007ff00000000, 0x1000054800000000, 0x0, // Vector AES Inverse Cipher VX-form (vncipher VRT,VRA,VRB) 3979 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3980 {VNCIPHERLAST, 0xfc0007ff00000000, 0x1000054900000000, 0x0, // Vector AES Inverse Cipher Last VX-form (vncipherlast VRT,VRA,VRB) 3981 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3982 {VORC, 0xfc0007ff00000000, 0x1000054400000000, 0x0, // Vector Logical OR with Complement VX-form (vorc VRT,VRA,VRB) 3983 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3984 {VPERMXOR, 0xfc00003f00000000, 0x1000002d00000000, 0x0, // Vector Permute & Exclusive-OR VA-form (vpermxor VRT,VRA,VRB,VRC) 3985 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3986 {VPKSDSS, 0xfc0007ff00000000, 0x100005ce00000000, 0x0, // Vector Pack Signed Doubleword Signed Saturate VX-form (vpksdss VRT,VRA,VRB) 3987 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3988 {VPKSDUS, 0xfc0007ff00000000, 0x1000054e00000000, 0x0, // Vector Pack Signed Doubleword Unsigned Saturate VX-form (vpksdus VRT,VRA,VRB) 3989 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3990 {VPKUDUM, 0xfc0007ff00000000, 0x1000044e00000000, 0x0, // Vector Pack Unsigned Doubleword Unsigned Modulo VX-form (vpkudum VRT,VRA,VRB) 3991 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3992 {VPKUDUS, 0xfc0007ff00000000, 0x100004ce00000000, 0x0, // Vector Pack Unsigned Doubleword Unsigned Saturate VX-form (vpkudus VRT,VRA,VRB) 3993 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3994 {VPMSUMB, 0xfc0007ff00000000, 0x1000040800000000, 0x0, // Vector Polynomial Multiply-Sum Byte VX-form (vpmsumb VRT,VRA,VRB) 3995 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3996 {VPMSUMD, 0xfc0007ff00000000, 0x100004c800000000, 0x0, // Vector Polynomial Multiply-Sum Doubleword VX-form (vpmsumd VRT,VRA,VRB) 3997 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3998 {VPMSUMH, 0xfc0007ff00000000, 0x1000044800000000, 0x0, // Vector Polynomial Multiply-Sum Halfword VX-form (vpmsumh VRT,VRA,VRB) 3999 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4000 {VPMSUMW, 0xfc0007ff00000000, 0x1000048800000000, 0x0, // Vector Polynomial Multiply-Sum Word VX-form (vpmsumw VRT,VRA,VRB) 4001 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4002 {VPOPCNTB, 0xfc0007ff00000000, 0x1000070300000000, 0x1f000000000000, // Vector Population Count Byte VX-form (vpopcntb VRT,VRB) 4003 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4004 {VPOPCNTD, 0xfc0007ff00000000, 0x100007c300000000, 0x1f000000000000, // Vector Population Count Doubleword VX-form (vpopcntd VRT,VRB) 4005 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4006 {VPOPCNTH, 0xfc0007ff00000000, 0x1000074300000000, 0x1f000000000000, // Vector Population Count Halfword VX-form (vpopcnth VRT,VRB) 4007 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4008 {VPOPCNTW, 0xfc0007ff00000000, 0x1000078300000000, 0x1f000000000000, // Vector Population Count Word VX-form (vpopcntw VRT,VRB) 4009 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4010 {VRLD, 0xfc0007ff00000000, 0x100000c400000000, 0x0, // Vector Rotate Left Doubleword VX-form (vrld VRT,VRA,VRB) 4011 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4012 {VSBOX, 0xfc0007ff00000000, 0x100005c800000000, 0xf80000000000, // Vector AES SubBytes VX-form (vsbox VRT,VRA) 4013 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15}}, 4014 {VSHASIGMAD, 0xfc0007ff00000000, 0x100006c200000000, 0x0, // Vector SHA-512 Sigma Doubleword VX-form (vshasigmad VRT,VRA,ST,SIX) 4015 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_ImmUnsigned_16_16, ap_ImmUnsigned_17_20}}, 4016 {VSHASIGMAW, 0xfc0007ff00000000, 0x1000068200000000, 0x0, // Vector SHA-256 Sigma Word VX-form (vshasigmaw VRT,VRA,ST,SIX) 4017 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_ImmUnsigned_16_16, ap_ImmUnsigned_17_20}}, 4018 {VSLD, 0xfc0007ff00000000, 0x100005c400000000, 0x0, // Vector Shift Left Doubleword VX-form (vsld VRT,VRA,VRB) 4019 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4020 {VSRAD, 0xfc0007ff00000000, 0x100003c400000000, 0x0, // Vector Shift Right Algebraic Doubleword VX-form (vsrad VRT,VRA,VRB) 4021 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4022 {VSRD, 0xfc0007ff00000000, 0x100006c400000000, 0x0, // Vector Shift Right Doubleword VX-form (vsrd VRT,VRA,VRB) 4023 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4024 {VSUBCUQ, 0xfc0007ff00000000, 0x1000054000000000, 0x0, // Vector Subtract & write Carry-out Unsigned Quadword VX-form (vsubcuq VRT,VRA,VRB) 4025 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4026 {VSUBECUQ, 0xfc00003f00000000, 0x1000003f00000000, 0x0, // Vector Subtract Extended & write Carry-out Unsigned Quadword VA-form (vsubecuq VRT,VRA,VRB,VRC) 4027 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 4028 {VSUBEUQM, 0xfc00003f00000000, 0x1000003e00000000, 0x0, // Vector Subtract Extended Unsigned Quadword Modulo VA-form (vsubeuqm VRT,VRA,VRB,VRC) 4029 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 4030 {VSUBUDM, 0xfc0007ff00000000, 0x100004c000000000, 0x0, // Vector Subtract Unsigned Doubleword Modulo VX-form (vsubudm VRT,VRA,VRB) 4031 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4032 {VSUBUQM, 0xfc0007ff00000000, 0x1000050000000000, 0x0, // Vector Subtract Unsigned Quadword Modulo VX-form (vsubuqm VRT,VRA,VRB) 4033 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4034 {VUPKHSW, 0xfc0007ff00000000, 0x1000064e00000000, 0x1f000000000000, // Vector Unpack High Signed Word VX-form (vupkhsw VRT,VRB) 4035 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4036 {VUPKLSW, 0xfc0007ff00000000, 0x100006ce00000000, 0x1f000000000000, // Vector Unpack Low Signed Word VX-form (vupklsw VRT,VRB) 4037 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4038 {XSADDSP, 0xfc0007f800000000, 0xf000000000000000, 0x0, // VSX Scalar Add Single-Precision XX3-form (xsaddsp XT,XA,XB) 4039 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4040 {XSCVDPSPN, 0xfc0007fc00000000, 0xf000042c00000000, 0x1f000000000000, // VSX Scalar Convert Scalar Single-Precision to Vector Single-Precision format Non-signalling XX2-form (xscvdpspn XT,XB) 4041 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4042 {XSCVSPDPN, 0xfc0007fc00000000, 0xf000052c00000000, 0x1f000000000000, // VSX Scalar Convert Single-Precision to Double-Precision format Non-signalling XX2-form (xscvspdpn XT,XB) 4043 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4044 {XSCVSXDSP, 0xfc0007fc00000000, 0xf00004e000000000, 0x1f000000000000, // VSX Scalar Convert with round Signed Doubleword to Single-Precision format XX2-form (xscvsxdsp XT,XB) 4045 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4046 {XSCVUXDSP, 0xfc0007fc00000000, 0xf00004a000000000, 0x1f000000000000, // VSX Scalar Convert with round Unsigned Doubleword to Single-Precision XX2-form (xscvuxdsp XT,XB) 4047 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4048 {XSDIVSP, 0xfc0007f800000000, 0xf00000c000000000, 0x0, // VSX Scalar Divide Single-Precision XX3-form (xsdivsp XT,XA,XB) 4049 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4050 {XSMADDASP, 0xfc0007f800000000, 0xf000000800000000, 0x0, // VSX Scalar Multiply-Add Type-A Single-Precision XX3-form (xsmaddasp XT,XA,XB) 4051 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4052 {XSMADDMSP, 0xfc0007f800000000, 0xf000004800000000, 0x0, // VSX Scalar Multiply-Add Type-M Single-Precision XX3-form (xsmaddmsp XT,XA,XB) 4053 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4054 {XSMSUBASP, 0xfc0007f800000000, 0xf000008800000000, 0x0, // VSX Scalar Multiply-Subtract Type-A Single-Precision XX3-form (xsmsubasp XT,XA,XB) 4055 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4056 {XSMSUBMSP, 0xfc0007f800000000, 0xf00000c800000000, 0x0, // VSX Scalar Multiply-Subtract Type-M Single-Precision XX3-form (xsmsubmsp XT,XA,XB) 4057 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4058 {XSMULSP, 0xfc0007f800000000, 0xf000008000000000, 0x0, // VSX Scalar Multiply Single-Precision XX3-form (xsmulsp XT,XA,XB) 4059 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4060 {XSNMADDASP, 0xfc0007f800000000, 0xf000040800000000, 0x0, // VSX Scalar Negative Multiply-Add Type-A Single-Precision XX3-form (xsnmaddasp XT,XA,XB) 4061 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4062 {XSNMADDMSP, 0xfc0007f800000000, 0xf000044800000000, 0x0, // VSX Scalar Negative Multiply-Add Type-M Single-Precision XX3-form (xsnmaddmsp XT,XA,XB) 4063 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4064 {XSNMSUBASP, 0xfc0007f800000000, 0xf000048800000000, 0x0, // VSX Scalar Negative Multiply-Subtract Type-A Single-Precision XX3-form (xsnmsubasp XT,XA,XB) 4065 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4066 {XSNMSUBMSP, 0xfc0007f800000000, 0xf00004c800000000, 0x0, // VSX Scalar Negative Multiply-Subtract Type-M Single-Precision XX3-form (xsnmsubmsp XT,XA,XB) 4067 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4068 {XSRESP, 0xfc0007fc00000000, 0xf000006800000000, 0x1f000000000000, // VSX Scalar Reciprocal Estimate Single-Precision XX2-form (xsresp XT,XB) 4069 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4070 {XSRSP, 0xfc0007fc00000000, 0xf000046400000000, 0x1f000000000000, // VSX Scalar Round to Single-Precision XX2-form (xsrsp XT,XB) 4071 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4072 {XSRSQRTESP, 0xfc0007fc00000000, 0xf000002800000000, 0x1f000000000000, // VSX Scalar Reciprocal Square Root Estimate Single-Precision XX2-form (xsrsqrtesp XT,XB) 4073 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4074 {XSSQRTSP, 0xfc0007fc00000000, 0xf000002c00000000, 0x1f000000000000, // VSX Scalar Square Root Single-Precision XX2-form (xssqrtsp XT,XB) 4075 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4076 {XSSUBSP, 0xfc0007f800000000, 0xf000004000000000, 0x0, // VSX Scalar Subtract Single-Precision XX3-form (xssubsp XT,XA,XB) 4077 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4078 {XXLEQV, 0xfc0007f800000000, 0xf00005d000000000, 0x0, // VSX Vector Logical Equivalence XX3-form (xxleqv XT,XA,XB) 4079 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4080 {XXLNAND, 0xfc0007f800000000, 0xf000059000000000, 0x0, // VSX Vector Logical NAND XX3-form (xxlnand XT,XA,XB) 4081 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4082 {XXLORC, 0xfc0007f800000000, 0xf000055000000000, 0x0, // VSX Vector Logical OR with Complement XX3-form (xxlorc XT,XA,XB) 4083 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4084 {ADDG6S, 0xfc0003fe00000000, 0x7c00009400000000, 0x40100000000, // Add and Generate Sixes XO-form (addg6s RT,RA,RB) 4085 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4086 {BPERMD, 0xfc0007fe00000000, 0x7c0001f800000000, 0x100000000, // Bit Permute Doubleword X-form (bpermd RA,RS,RB) 4087 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 4088 {CBCDTD, 0xfc0007fe00000000, 0x7c00027400000000, 0xf80100000000, // Convert Binary Coded Decimal To Declets X-form (cbcdtd RA, RS) 4089 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 4090 {CDTBCD, 0xfc0007fe00000000, 0x7c00023400000000, 0xf80100000000, // Convert Declets To Binary Coded Decimal X-form (cdtbcd RA, RS) 4091 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 4092 {DCFFIX, 0xfc0007ff00000000, 0xec00064400000000, 0x1f000000000000, // DFP Convert From Fixed X-form (dcffix FRT,FRB) 4093 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4094 {DCFFIXCC, 0xfc0007ff00000000, 0xec00064500000000, 0x1f000000000000, // DFP Convert From Fixed X-form (dcffix. FRT,FRB) 4095 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4096 {DIVDE, 0xfc0007ff00000000, 0x7c00035200000000, 0x0, // Divide Doubleword Extended XO-form (divde RT,RA,RB) 4097 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4098 {DIVDECC, 0xfc0007ff00000000, 0x7c00035300000000, 0x0, // Divide Doubleword Extended XO-form (divde. RT,RA,RB) 4099 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4100 {DIVDEO, 0xfc0007ff00000000, 0x7c00075200000000, 0x0, // Divide Doubleword Extended XO-form (divdeo RT,RA,RB) 4101 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4102 {DIVDEOCC, 0xfc0007ff00000000, 0x7c00075300000000, 0x0, // Divide Doubleword Extended XO-form (divdeo. RT,RA,RB) 4103 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4104 {DIVDEU, 0xfc0007ff00000000, 0x7c00031200000000, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu RT,RA,RB) 4105 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4106 {DIVDEUCC, 0xfc0007ff00000000, 0x7c00031300000000, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu. RT,RA,RB) 4107 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4108 {DIVDEUO, 0xfc0007ff00000000, 0x7c00071200000000, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo RT,RA,RB) 4109 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4110 {DIVDEUOCC, 0xfc0007ff00000000, 0x7c00071300000000, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo. RT,RA,RB) 4111 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4112 {DIVWE, 0xfc0007ff00000000, 0x7c00035600000000, 0x0, // Divide Word Extended XO-form (divwe RT,RA,RB) 4113 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4114 {DIVWECC, 0xfc0007ff00000000, 0x7c00035700000000, 0x0, // Divide Word Extended XO-form (divwe. RT,RA,RB) 4115 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4116 {DIVWEO, 0xfc0007ff00000000, 0x7c00075600000000, 0x0, // Divide Word Extended XO-form (divweo RT,RA,RB) 4117 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4118 {DIVWEOCC, 0xfc0007ff00000000, 0x7c00075700000000, 0x0, // Divide Word Extended XO-form (divweo. RT,RA,RB) 4119 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4120 {DIVWEU, 0xfc0007ff00000000, 0x7c00031600000000, 0x0, // Divide Word Extended Unsigned XO-form (divweu RT,RA,RB) 4121 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4122 {DIVWEUCC, 0xfc0007ff00000000, 0x7c00031700000000, 0x0, // Divide Word Extended Unsigned XO-form (divweu. RT,RA,RB) 4123 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4124 {DIVWEUO, 0xfc0007ff00000000, 0x7c00071600000000, 0x0, // Divide Word Extended Unsigned XO-form (divweuo RT,RA,RB) 4125 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4126 {DIVWEUOCC, 0xfc0007ff00000000, 0x7c00071700000000, 0x0, // Divide Word Extended Unsigned XO-form (divweuo. RT,RA,RB) 4127 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4128 {FCFIDS, 0xfc0007ff00000000, 0xec00069c00000000, 0x1f000000000000, // Floating Convert with round Signed Doubleword to Single-Precision format X-form (fcfids FRT,FRB) 4129 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4130 {FCFIDSCC, 0xfc0007ff00000000, 0xec00069d00000000, 0x1f000000000000, // Floating Convert with round Signed Doubleword to Single-Precision format X-form (fcfids. FRT,FRB) 4131 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4132 {FCFIDU, 0xfc0007ff00000000, 0xfc00079c00000000, 0x1f000000000000, // Floating Convert with round Unsigned Doubleword to Double-Precision format X-form (fcfidu FRT,FRB) 4133 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4134 {FCFIDUCC, 0xfc0007ff00000000, 0xfc00079d00000000, 0x1f000000000000, // Floating Convert with round Unsigned Doubleword to Double-Precision format X-form (fcfidu. FRT,FRB) 4135 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4136 {FCFIDUS, 0xfc0007ff00000000, 0xec00079c00000000, 0x1f000000000000, // Floating Convert with round Unsigned Doubleword to Single-Precision format X-form (fcfidus FRT,FRB) 4137 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4138 {FCFIDUSCC, 0xfc0007ff00000000, 0xec00079d00000000, 0x1f000000000000, // Floating Convert with round Unsigned Doubleword to Single-Precision format X-form (fcfidus. FRT,FRB) 4139 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4140 {FCTIDU, 0xfc0007ff00000000, 0xfc00075c00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Unsigned Doubleword format X-form (fctidu FRT,FRB) 4141 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4142 {FCTIDUCC, 0xfc0007ff00000000, 0xfc00075d00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Unsigned Doubleword format X-form (fctidu. FRT,FRB) 4143 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4144 {FCTIDUZ, 0xfc0007ff00000000, 0xfc00075e00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Unsigned Doubleword format X-form (fctiduz FRT,FRB) 4145 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4146 {FCTIDUZCC, 0xfc0007ff00000000, 0xfc00075f00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Unsigned Doubleword format X-form (fctiduz. FRT,FRB) 4147 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4148 {FCTIWU, 0xfc0007ff00000000, 0xfc00011c00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Unsigned Word format X-form (fctiwu FRT,FRB) 4149 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4150 {FCTIWUCC, 0xfc0007ff00000000, 0xfc00011d00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Unsigned Word format X-form (fctiwu. FRT,FRB) 4151 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4152 {FCTIWUZ, 0xfc0007ff00000000, 0xfc00011e00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Unsigned Word format X-form (fctiwuz FRT,FRB) 4153 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4154 {FCTIWUZCC, 0xfc0007ff00000000, 0xfc00011f00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Unsigned Word format X-form (fctiwuz. FRT,FRB) 4155 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4156 {FTDIV, 0xfc0007fe00000000, 0xfc00010000000000, 0x60000100000000, // Floating Test for software Divide X-form (ftdiv BF,FRA,FRB) 4157 [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, 4158 {FTSQRT, 0xfc0007fe00000000, 0xfc00014000000000, 0x7f000100000000, // Floating Test for software Square Root X-form (ftsqrt BF,FRB) 4159 [6]*argField{ap_CondRegField_6_8, ap_FPReg_16_20}}, 4160 {LBARX, 0xfc0007fe00000000, 0x7c00006800000000, 0x0, // Load Byte And Reserve Indexed X-form (lbarx RT,RA,RB,EH) 4161 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}}, 4162 {LDBRX, 0xfc0007fe00000000, 0x7c00042800000000, 0x100000000, // Load Doubleword Byte-Reverse Indexed X-form (ldbrx RT,RA,RB) 4163 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4164 {LFIWZX, 0xfc0007fe00000000, 0x7c0006ee00000000, 0x100000000, // Load Floating-Point as Integer Word & Zero Indexed X-form (lfiwzx FRT,RA,RB) 4165 [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4166 {LHARX, 0xfc0007fe00000000, 0x7c0000e800000000, 0x0, // Load Halfword And Reserve Indexed Xform (lharx RT,RA,RB,EH) 4167 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}}, 4168 {LXSDX, 0xfc0007fe00000000, 0x7c00049800000000, 0x0, // Load VSX Scalar Doubleword Indexed X-form (lxsdx XT,RA,RB) 4169 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4170 {LXVD2X, 0xfc0007fe00000000, 0x7c00069800000000, 0x0, // Load VSX Vector Doubleword*2 Indexed X-form (lxvd2x XT,RA,RB) 4171 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4172 {LXVDSX, 0xfc0007fe00000000, 0x7c00029800000000, 0x0, // Load VSX Vector Doubleword & Splat Indexed X-form (lxvdsx XT,RA,RB) 4173 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4174 {LXVW4X, 0xfc0007fe00000000, 0x7c00061800000000, 0x0, // Load VSX Vector Word*4 Indexed X-form (lxvw4x XT,RA,RB) 4175 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4176 {POPCNTD, 0xfc0007fe00000000, 0x7c0003f400000000, 0xf80100000000, // Population Count Doubleword X-form (popcntd RA, RS) 4177 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 4178 {POPCNTW, 0xfc0007fe00000000, 0x7c0002f400000000, 0xf80100000000, // Population Count Words X-form (popcntw RA, RS) 4179 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 4180 {STBCXCC, 0xfc0007ff00000000, 0x7c00056d00000000, 0x0, // Store Byte Conditional Indexed X-form (stbcx. RS,RA,RB) 4181 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4182 {STDBRX, 0xfc0007fe00000000, 0x7c00052800000000, 0x100000000, // Store Doubleword Byte-Reverse Indexed X-form (stdbrx RS,RA,RB) 4183 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4184 {STHCXCC, 0xfc0007ff00000000, 0x7c0005ad00000000, 0x0, // Store Halfword Conditional Indexed X-form (sthcx. RS,RA,RB) 4185 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4186 {STXSDX, 0xfc0007fe00000000, 0x7c00059800000000, 0x0, // Store VSX Scalar Doubleword Indexed X-form (stxsdx XS,RA,RB) 4187 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4188 {STXVD2X, 0xfc0007fe00000000, 0x7c00079800000000, 0x0, // Store VSX Vector Doubleword*2 Indexed X-form (stxvd2x XS,RA,RB) 4189 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4190 {STXVW4X, 0xfc0007fe00000000, 0x7c00071800000000, 0x0, // Store VSX Vector Word*4 Indexed X-form (stxvw4x XS,RA,RB) 4191 [6]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4192 {XSABSDP, 0xfc0007fc00000000, 0xf000056400000000, 0x1f000000000000, // VSX Scalar Absolute Double-Precision XX2-form (xsabsdp XT,XB) 4193 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4194 {XSADDDP, 0xfc0007f800000000, 0xf000010000000000, 0x0, // VSX Scalar Add Double-Precision XX3-form (xsadddp XT,XA,XB) 4195 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4196 {XSCMPODP, 0xfc0007f800000000, 0xf000015800000000, 0x60000100000000, // VSX Scalar Compare Ordered Double-Precision XX3-form (xscmpodp BF,XA,XB) 4197 [6]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4198 {XSCMPUDP, 0xfc0007f800000000, 0xf000011800000000, 0x60000100000000, // VSX Scalar Compare Unordered Double-Precision XX3-form (xscmpudp BF,XA,XB) 4199 [6]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4200 {XSCPSGNDP, 0xfc0007f800000000, 0xf000058000000000, 0x0, // VSX Scalar Copy Sign Double-Precision XX3-form (xscpsgndp XT,XA,XB) 4201 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4202 {XSCVDPSP, 0xfc0007fc00000000, 0xf000042400000000, 0x1f000000000000, // VSX Scalar Convert with round Double-Precision to Single-Precision format XX2-form (xscvdpsp XT,XB) 4203 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4204 {XSCVDPSXDS, 0xfc0007fc00000000, 0xf000056000000000, 0x1f000000000000, // VSX Scalar Convert with round to zero Double-Precision to Signed Doubleword format XX2-form (xscvdpsxds XT,XB) 4205 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4206 {XSCVDPSXWS, 0xfc0007fc00000000, 0xf000016000000000, 0x1f000000000000, // VSX Scalar Convert with round to zero Double-Precision to Signed Word format XX2-form (xscvdpsxws XT,XB) 4207 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4208 {XSCVDPUXDS, 0xfc0007fc00000000, 0xf000052000000000, 0x1f000000000000, // VSX Scalar Convert with round to zero Double-Precision to Unsigned Doubleword format XX2-form (xscvdpuxds XT,XB) 4209 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4210 {XSCVDPUXWS, 0xfc0007fc00000000, 0xf000012000000000, 0x1f000000000000, // VSX Scalar Convert with round to zero Double-Precision to Unsigned Word format XX2-form (xscvdpuxws XT,XB) 4211 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4212 {XSCVSPDP, 0xfc0007fc00000000, 0xf000052400000000, 0x1f000000000000, // VSX Scalar Convert Single-Precision to Double-Precision format XX2-form (xscvspdp XT,XB) 4213 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4214 {XSCVSXDDP, 0xfc0007fc00000000, 0xf00005e000000000, 0x1f000000000000, // VSX Scalar Convert with round Signed Doubleword to Double-Precision format XX2-form (xscvsxddp XT,XB) 4215 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4216 {XSCVUXDDP, 0xfc0007fc00000000, 0xf00005a000000000, 0x1f000000000000, // VSX Scalar Convert with round Unsigned Doubleword to Double-Precision format XX2-form (xscvuxddp XT,XB) 4217 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4218 {XSDIVDP, 0xfc0007f800000000, 0xf00001c000000000, 0x0, // VSX Scalar Divide Double-Precision XX3-form (xsdivdp XT,XA,XB) 4219 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4220 {XSMADDADP, 0xfc0007f800000000, 0xf000010800000000, 0x0, // VSX Scalar Multiply-Add Type-A Double-Precision XX3-form (xsmaddadp XT,XA,XB) 4221 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4222 {XSMADDMDP, 0xfc0007f800000000, 0xf000014800000000, 0x0, // VSX Scalar Multiply-Add Type-M Double-Precision XX3-form (xsmaddmdp XT,XA,XB) 4223 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4224 {XSMAXDP, 0xfc0007f800000000, 0xf000050000000000, 0x0, // VSX Scalar Maximum Double-Precision XX3-form (xsmaxdp XT,XA,XB) 4225 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4226 {XSMINDP, 0xfc0007f800000000, 0xf000054000000000, 0x0, // VSX Scalar Minimum Double-Precision XX3-form (xsmindp XT,XA,XB) 4227 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4228 {XSMSUBADP, 0xfc0007f800000000, 0xf000018800000000, 0x0, // VSX Scalar Multiply-Subtract Type-A Double-Precision XX3-form (xsmsubadp XT,XA,XB) 4229 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4230 {XSMSUBMDP, 0xfc0007f800000000, 0xf00001c800000000, 0x0, // VSX Scalar Multiply-Subtract Type-M Double-Precision XX3-form (xsmsubmdp XT,XA,XB) 4231 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4232 {XSMULDP, 0xfc0007f800000000, 0xf000018000000000, 0x0, // VSX Scalar Multiply Double-Precision XX3-form (xsmuldp XT,XA,XB) 4233 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4234 {XSNABSDP, 0xfc0007fc00000000, 0xf00005a400000000, 0x1f000000000000, // VSX Scalar Negative Absolute Double-Precision XX2-form (xsnabsdp XT,XB) 4235 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4236 {XSNEGDP, 0xfc0007fc00000000, 0xf00005e400000000, 0x1f000000000000, // VSX Scalar Negate Double-Precision XX2-form (xsnegdp XT,XB) 4237 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4238 {XSNMADDADP, 0xfc0007f800000000, 0xf000050800000000, 0x0, // VSX Scalar Negative Multiply-Add Type-A Double-Precision XX3-form (xsnmaddadp XT,XA,XB) 4239 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4240 {XSNMADDMDP, 0xfc0007f800000000, 0xf000054800000000, 0x0, // VSX Scalar Negative Multiply-Add Type-M Double-Precision XX3-form (xsnmaddmdp XT,XA,XB) 4241 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4242 {XSNMSUBADP, 0xfc0007f800000000, 0xf000058800000000, 0x0, // VSX Scalar Negative Multiply-Subtract Type-A Double-Precision XX3-form (xsnmsubadp XT,XA,XB) 4243 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4244 {XSNMSUBMDP, 0xfc0007f800000000, 0xf00005c800000000, 0x0, // VSX Scalar Negative Multiply-Subtract Type-M Double-Precision XX3-form (xsnmsubmdp XT,XA,XB) 4245 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4246 {XSRDPI, 0xfc0007fc00000000, 0xf000012400000000, 0x1f000000000000, // VSX Scalar Round to Double-Precision Integer using round to Nearest Away XX2-form (xsrdpi XT,XB) 4247 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4248 {XSRDPIC, 0xfc0007fc00000000, 0xf00001ac00000000, 0x1f000000000000, // VSX Scalar Round to Double-Precision Integer exact using Current rounding mode XX2-form (xsrdpic XT,XB) 4249 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4250 {XSRDPIM, 0xfc0007fc00000000, 0xf00001e400000000, 0x1f000000000000, // VSX Scalar Round to Double-Precision Integer using round toward -Infinity XX2-form (xsrdpim XT,XB) 4251 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4252 {XSRDPIP, 0xfc0007fc00000000, 0xf00001a400000000, 0x1f000000000000, // VSX Scalar Round to Double-Precision Integer using round toward +Infinity XX2-form (xsrdpip XT,XB) 4253 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4254 {XSRDPIZ, 0xfc0007fc00000000, 0xf000016400000000, 0x1f000000000000, // VSX Scalar Round to Double-Precision Integer using round toward Zero XX2-form (xsrdpiz XT,XB) 4255 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4256 {XSREDP, 0xfc0007fc00000000, 0xf000016800000000, 0x1f000000000000, // VSX Scalar Reciprocal Estimate Double-Precision XX2-form (xsredp XT,XB) 4257 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4258 {XSRSQRTEDP, 0xfc0007fc00000000, 0xf000012800000000, 0x1f000000000000, // VSX Scalar Reciprocal Square Root Estimate Double-Precision XX2-form (xsrsqrtedp XT,XB) 4259 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4260 {XSSQRTDP, 0xfc0007fc00000000, 0xf000012c00000000, 0x1f000000000000, // VSX Scalar Square Root Double-Precision XX2-form (xssqrtdp XT,XB) 4261 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4262 {XSSUBDP, 0xfc0007f800000000, 0xf000014000000000, 0x0, // VSX Scalar Subtract Double-Precision XX3-form (xssubdp XT,XA,XB) 4263 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4264 {XSTDIVDP, 0xfc0007f800000000, 0xf00001e800000000, 0x60000100000000, // VSX Scalar Test for software Divide Double-Precision XX3-form (xstdivdp BF,XA,XB) 4265 [6]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4266 {XSTSQRTDP, 0xfc0007fc00000000, 0xf00001a800000000, 0x7f000100000000, // VSX Scalar Test for software Square Root Double-Precision XX2-form (xstsqrtdp BF,XB) 4267 [6]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}}, 4268 {XVABSDP, 0xfc0007fc00000000, 0xf000076400000000, 0x1f000000000000, // VSX Vector Absolute Value Double-Precision XX2-form (xvabsdp XT,XB) 4269 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4270 {XVABSSP, 0xfc0007fc00000000, 0xf000066400000000, 0x1f000000000000, // VSX Vector Absolute Value Single-Precision XX2-form (xvabssp XT,XB) 4271 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4272 {XVADDDP, 0xfc0007f800000000, 0xf000030000000000, 0x0, // VSX Vector Add Double-Precision XX3-form (xvadddp XT,XA,XB) 4273 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4274 {XVADDSP, 0xfc0007f800000000, 0xf000020000000000, 0x0, // VSX Vector Add Single-Precision XX3-form (xvaddsp XT,XA,XB) 4275 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4276 {XVCMPEQDP, 0xfc0007f800000000, 0xf000031800000000, 0x0, // VSX Vector Compare Equal To Double-Precision XX3-form (xvcmpeqdp XT,XA,XB) 4277 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4278 {XVCMPEQDPCC, 0xfc0007f800000000, 0xf000071800000000, 0x0, // VSX Vector Compare Equal To Double-Precision XX3-form (xvcmpeqdp. XT,XA,XB) 4279 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4280 {XVCMPEQSP, 0xfc0007f800000000, 0xf000021800000000, 0x0, // VSX Vector Compare Equal To Single-Precision XX3-form (xvcmpeqsp XT,XA,XB) 4281 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4282 {XVCMPEQSPCC, 0xfc0007f800000000, 0xf000061800000000, 0x0, // VSX Vector Compare Equal To Single-Precision XX3-form (xvcmpeqsp. XT,XA,XB) 4283 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4284 {XVCMPGEDP, 0xfc0007f800000000, 0xf000039800000000, 0x0, // VSX Vector Compare Greater Than or Equal To Double-Precision XX3-form (xvcmpgedp XT,XA,XB) 4285 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4286 {XVCMPGEDPCC, 0xfc0007f800000000, 0xf000079800000000, 0x0, // VSX Vector Compare Greater Than or Equal To Double-Precision XX3-form (xvcmpgedp. XT,XA,XB) 4287 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4288 {XVCMPGESP, 0xfc0007f800000000, 0xf000029800000000, 0x0, // VSX Vector Compare Greater Than or Equal To Single-Precision XX3-form (xvcmpgesp XT,XA,XB) 4289 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4290 {XVCMPGESPCC, 0xfc0007f800000000, 0xf000069800000000, 0x0, // VSX Vector Compare Greater Than or Equal To Single-Precision XX3-form (xvcmpgesp. XT,XA,XB) 4291 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4292 {XVCMPGTDP, 0xfc0007f800000000, 0xf000035800000000, 0x0, // VSX Vector Compare Greater Than Double-Precision XX3-form (xvcmpgtdp XT,XA,XB) 4293 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4294 {XVCMPGTDPCC, 0xfc0007f800000000, 0xf000075800000000, 0x0, // VSX Vector Compare Greater Than Double-Precision XX3-form (xvcmpgtdp. XT,XA,XB) 4295 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4296 {XVCMPGTSP, 0xfc0007f800000000, 0xf000025800000000, 0x0, // VSX Vector Compare Greater Than Single-Precision XX3-form (xvcmpgtsp XT,XA,XB) 4297 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4298 {XVCMPGTSPCC, 0xfc0007f800000000, 0xf000065800000000, 0x0, // VSX Vector Compare Greater Than Single-Precision XX3-form (xvcmpgtsp. XT,XA,XB) 4299 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4300 {XVCPSGNDP, 0xfc0007f800000000, 0xf000078000000000, 0x0, // VSX Vector Copy Sign Double-Precision XX3-form (xvcpsgndp XT,XA,XB) 4301 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4302 {XVCPSGNSP, 0xfc0007f800000000, 0xf000068000000000, 0x0, // VSX Vector Copy Sign Single-Precision XX3-form (xvcpsgnsp XT,XA,XB) 4303 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4304 {XVCVDPSP, 0xfc0007fc00000000, 0xf000062400000000, 0x1f000000000000, // VSX Vector Convert with round Double-Precision to Single-Precision format XX2-form (xvcvdpsp XT,XB) 4305 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4306 {XVCVDPSXDS, 0xfc0007fc00000000, 0xf000076000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Double-Precision to Signed Doubleword format XX2-form (xvcvdpsxds XT,XB) 4307 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4308 {XVCVDPSXWS, 0xfc0007fc00000000, 0xf000036000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Double-Precision to Signed Word format XX2-form (xvcvdpsxws XT,XB) 4309 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4310 {XVCVDPUXDS, 0xfc0007fc00000000, 0xf000072000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Double-Precision to Unsigned Doubleword format XX2-form (xvcvdpuxds XT,XB) 4311 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4312 {XVCVDPUXWS, 0xfc0007fc00000000, 0xf000032000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Double-Precision to Unsigned Word format XX2-form (xvcvdpuxws XT,XB) 4313 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4314 {XVCVSPDP, 0xfc0007fc00000000, 0xf000072400000000, 0x1f000000000000, // VSX Vector Convert Single-Precision to Double-Precision format XX2-form (xvcvspdp XT,XB) 4315 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4316 {XVCVSPSXDS, 0xfc0007fc00000000, 0xf000066000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Single-Precision to Signed Doubleword format XX2-form (xvcvspsxds XT,XB) 4317 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4318 {XVCVSPSXWS, 0xfc0007fc00000000, 0xf000026000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Single-Precision to Signed Word format XX2-form (xvcvspsxws XT,XB) 4319 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4320 {XVCVSPUXDS, 0xfc0007fc00000000, 0xf000062000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Single-Precision to Unsigned Doubleword format XX2-form (xvcvspuxds XT,XB) 4321 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4322 {XVCVSPUXWS, 0xfc0007fc00000000, 0xf000022000000000, 0x1f000000000000, // VSX Vector Convert with round to zero Single-Precision to Unsigned Word format XX2-form (xvcvspuxws XT,XB) 4323 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4324 {XVCVSXDDP, 0xfc0007fc00000000, 0xf00007e000000000, 0x1f000000000000, // VSX Vector Convert with round Signed Doubleword to Double-Precision format XX2-form (xvcvsxddp XT,XB) 4325 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4326 {XVCVSXDSP, 0xfc0007fc00000000, 0xf00006e000000000, 0x1f000000000000, // VSX Vector Convert with round Signed Doubleword to Single-Precision format XX2-form (xvcvsxdsp XT,XB) 4327 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4328 {XVCVSXWDP, 0xfc0007fc00000000, 0xf00003e000000000, 0x1f000000000000, // VSX Vector Convert Signed Word to Double-Precision format XX2-form (xvcvsxwdp XT,XB) 4329 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4330 {XVCVSXWSP, 0xfc0007fc00000000, 0xf00002e000000000, 0x1f000000000000, // VSX Vector Convert with round Signed Word to Single-Precision format XX2-form (xvcvsxwsp XT,XB) 4331 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4332 {XVCVUXDDP, 0xfc0007fc00000000, 0xf00007a000000000, 0x1f000000000000, // VSX Vector Convert with round Unsigned Doubleword to Double-Precision format XX2-form (xvcvuxddp XT,XB) 4333 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4334 {XVCVUXDSP, 0xfc0007fc00000000, 0xf00006a000000000, 0x1f000000000000, // VSX Vector Convert with round Unsigned Doubleword to Single-Precision format XX2-form (xvcvuxdsp XT,XB) 4335 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4336 {XVCVUXWDP, 0xfc0007fc00000000, 0xf00003a000000000, 0x1f000000000000, // VSX Vector Convert Unsigned Word to Double-Precision format XX2-form (xvcvuxwdp XT,XB) 4337 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4338 {XVCVUXWSP, 0xfc0007fc00000000, 0xf00002a000000000, 0x1f000000000000, // VSX Vector Convert with round Unsigned Word to Single-Precision format XX2-form (xvcvuxwsp XT,XB) 4339 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4340 {XVDIVDP, 0xfc0007f800000000, 0xf00003c000000000, 0x0, // VSX Vector Divide Double-Precision XX3-form (xvdivdp XT,XA,XB) 4341 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4342 {XVDIVSP, 0xfc0007f800000000, 0xf00002c000000000, 0x0, // VSX Vector Divide Single-Precision XX3-form (xvdivsp XT,XA,XB) 4343 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4344 {XVMADDADP, 0xfc0007f800000000, 0xf000030800000000, 0x0, // VSX Vector Multiply-Add Type-A Double-Precision XX3-form (xvmaddadp XT,XA,XB) 4345 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4346 {XVMADDASP, 0xfc0007f800000000, 0xf000020800000000, 0x0, // VSX Vector Multiply-Add Type-A Single-Precision XX3-form (xvmaddasp XT,XA,XB) 4347 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4348 {XVMADDMDP, 0xfc0007f800000000, 0xf000034800000000, 0x0, // VSX Vector Multiply-Add Type-M Double-Precision XX3-form (xvmaddmdp XT,XA,XB) 4349 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4350 {XVMADDMSP, 0xfc0007f800000000, 0xf000024800000000, 0x0, // VSX Vector Multiply-Add Type-M Single-Precision XX3-form (xvmaddmsp XT,XA,XB) 4351 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4352 {XVMAXDP, 0xfc0007f800000000, 0xf000070000000000, 0x0, // VSX Vector Maximum Double-Precision XX3-form (xvmaxdp XT,XA,XB) 4353 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4354 {XVMAXSP, 0xfc0007f800000000, 0xf000060000000000, 0x0, // VSX Vector Maximum Single-Precision XX3-form (xvmaxsp XT,XA,XB) 4355 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4356 {XVMINDP, 0xfc0007f800000000, 0xf000074000000000, 0x0, // VSX Vector Minimum Double-Precision XX3-form (xvmindp XT,XA,XB) 4357 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4358 {XVMINSP, 0xfc0007f800000000, 0xf000064000000000, 0x0, // VSX Vector Minimum Single-Precision XX3-form (xvminsp XT,XA,XB) 4359 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4360 {XVMSUBADP, 0xfc0007f800000000, 0xf000038800000000, 0x0, // VSX Vector Multiply-Subtract Type-A Double-Precision XX3-form (xvmsubadp XT,XA,XB) 4361 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4362 {XVMSUBASP, 0xfc0007f800000000, 0xf000028800000000, 0x0, // VSX Vector Multiply-Subtract Type-A Single-Precision XX3-form (xvmsubasp XT,XA,XB) 4363 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4364 {XVMSUBMDP, 0xfc0007f800000000, 0xf00003c800000000, 0x0, // VSX Vector Multiply-Subtract Type-M Double-Precision XX3-form (xvmsubmdp XT,XA,XB) 4365 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4366 {XVMSUBMSP, 0xfc0007f800000000, 0xf00002c800000000, 0x0, // VSX Vector Multiply-Subtract Type-M Single-Precision XX3-form (xvmsubmsp XT,XA,XB) 4367 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4368 {XVMULDP, 0xfc0007f800000000, 0xf000038000000000, 0x0, // VSX Vector Multiply Double-Precision XX3-form (xvmuldp XT,XA,XB) 4369 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4370 {XVMULSP, 0xfc0007f800000000, 0xf000028000000000, 0x0, // VSX Vector Multiply Single-Precision XX3-form (xvmulsp XT,XA,XB) 4371 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4372 {XVNABSDP, 0xfc0007fc00000000, 0xf00007a400000000, 0x1f000000000000, // VSX Vector Negative Absolute Double-Precision XX2-form (xvnabsdp XT,XB) 4373 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4374 {XVNABSSP, 0xfc0007fc00000000, 0xf00006a400000000, 0x1f000000000000, // VSX Vector Negative Absolute Single-Precision XX2-form (xvnabssp XT,XB) 4375 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4376 {XVNEGDP, 0xfc0007fc00000000, 0xf00007e400000000, 0x1f000000000000, // VSX Vector Negate Double-Precision XX2-form (xvnegdp XT,XB) 4377 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4378 {XVNEGSP, 0xfc0007fc00000000, 0xf00006e400000000, 0x1f000000000000, // VSX Vector Negate Single-Precision XX2-form (xvnegsp XT,XB) 4379 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4380 {XVNMADDADP, 0xfc0007f800000000, 0xf000070800000000, 0x0, // VSX Vector Negative Multiply-Add Type-A Double-Precision XX3-form (xvnmaddadp XT,XA,XB) 4381 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4382 {XVNMADDASP, 0xfc0007f800000000, 0xf000060800000000, 0x0, // VSX Vector Negative Multiply-Add Type-A Single-Precision XX3-form (xvnmaddasp XT,XA,XB) 4383 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4384 {XVNMADDMDP, 0xfc0007f800000000, 0xf000074800000000, 0x0, // VSX Vector Negative Multiply-Add Type-M Double-Precision XX3-form (xvnmaddmdp XT,XA,XB) 4385 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4386 {XVNMADDMSP, 0xfc0007f800000000, 0xf000064800000000, 0x0, // VSX Vector Negative Multiply-Add Type-M Single-Precision XX3-form (xvnmaddmsp XT,XA,XB) 4387 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4388 {XVNMSUBADP, 0xfc0007f800000000, 0xf000078800000000, 0x0, // VSX Vector Negative Multiply-Subtract Type-A Double-Precision XX3-form (xvnmsubadp XT,XA,XB) 4389 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4390 {XVNMSUBASP, 0xfc0007f800000000, 0xf000068800000000, 0x0, // VSX Vector Negative Multiply-Subtract Type-A Single-Precision XX3-form (xvnmsubasp XT,XA,XB) 4391 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4392 {XVNMSUBMDP, 0xfc0007f800000000, 0xf00007c800000000, 0x0, // VSX Vector Negative Multiply-Subtract Type-M Double-Precision XX3-form (xvnmsubmdp XT,XA,XB) 4393 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4394 {XVNMSUBMSP, 0xfc0007f800000000, 0xf00006c800000000, 0x0, // VSX Vector Negative Multiply-Subtract Type-M Single-Precision XX3-form (xvnmsubmsp XT,XA,XB) 4395 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4396 {XVRDPI, 0xfc0007fc00000000, 0xf000032400000000, 0x1f000000000000, // VSX Vector Round to Double-Precision Integer using round to Nearest Away XX2-form (xvrdpi XT,XB) 4397 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4398 {XVRDPIC, 0xfc0007fc00000000, 0xf00003ac00000000, 0x1f000000000000, // VSX Vector Round to Double-Precision Integer Exact using Current rounding mode XX2-form (xvrdpic XT,XB) 4399 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4400 {XVRDPIM, 0xfc0007fc00000000, 0xf00003e400000000, 0x1f000000000000, // VSX Vector Round to Double-Precision Integer using round toward -Infinity XX2-form (xvrdpim XT,XB) 4401 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4402 {XVRDPIP, 0xfc0007fc00000000, 0xf00003a400000000, 0x1f000000000000, // VSX Vector Round to Double-Precision Integer using round toward +Infinity XX2-form (xvrdpip XT,XB) 4403 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4404 {XVRDPIZ, 0xfc0007fc00000000, 0xf000036400000000, 0x1f000000000000, // VSX Vector Round to Double-Precision Integer using round toward Zero XX2-form (xvrdpiz XT,XB) 4405 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4406 {XVREDP, 0xfc0007fc00000000, 0xf000036800000000, 0x1f000000000000, // VSX Vector Reciprocal Estimate Double-Precision XX2-form (xvredp XT,XB) 4407 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4408 {XVRESP, 0xfc0007fc00000000, 0xf000026800000000, 0x1f000000000000, // VSX Vector Reciprocal Estimate Single-Precision XX2-form (xvresp XT,XB) 4409 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4410 {XVRSPI, 0xfc0007fc00000000, 0xf000022400000000, 0x1f000000000000, // VSX Vector Round to Single-Precision Integer using round to Nearest Away XX2-form (xvrspi XT,XB) 4411 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4412 {XVRSPIC, 0xfc0007fc00000000, 0xf00002ac00000000, 0x1f000000000000, // VSX Vector Round to Single-Precision Integer Exact using Current rounding mode XX2-form (xvrspic XT,XB) 4413 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4414 {XVRSPIM, 0xfc0007fc00000000, 0xf00002e400000000, 0x1f000000000000, // VSX Vector Round to Single-Precision Integer using round toward -Infinity XX2-form (xvrspim XT,XB) 4415 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4416 {XVRSPIP, 0xfc0007fc00000000, 0xf00002a400000000, 0x1f000000000000, // VSX Vector Round to Single-Precision Integer using round toward +Infinity XX2-form (xvrspip XT,XB) 4417 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4418 {XVRSPIZ, 0xfc0007fc00000000, 0xf000026400000000, 0x1f000000000000, // VSX Vector Round to Single-Precision Integer using round toward Zero XX2-form (xvrspiz XT,XB) 4419 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4420 {XVRSQRTEDP, 0xfc0007fc00000000, 0xf000032800000000, 0x1f000000000000, // VSX Vector Reciprocal Square Root Estimate Double-Precision XX2-form (xvrsqrtedp XT,XB) 4421 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4422 {XVRSQRTESP, 0xfc0007fc00000000, 0xf000022800000000, 0x1f000000000000, // VSX Vector Reciprocal Square Root Estimate Single-Precision XX2-form (xvrsqrtesp XT,XB) 4423 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4424 {XVSQRTDP, 0xfc0007fc00000000, 0xf000032c00000000, 0x1f000000000000, // VSX Vector Square Root Double-Precision XX2-form (xvsqrtdp XT,XB) 4425 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4426 {XVSQRTSP, 0xfc0007fc00000000, 0xf000022c00000000, 0x1f000000000000, // VSX Vector Square Root Single-Precision XX2-form (xvsqrtsp XT,XB) 4427 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4428 {XVSUBDP, 0xfc0007f800000000, 0xf000034000000000, 0x0, // VSX Vector Subtract Double-Precision XX3-form (xvsubdp XT,XA,XB) 4429 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4430 {XVSUBSP, 0xfc0007f800000000, 0xf000024000000000, 0x0, // VSX Vector Subtract Single-Precision XX3-form (xvsubsp XT,XA,XB) 4431 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4432 {XVTDIVDP, 0xfc0007f800000000, 0xf00003e800000000, 0x60000100000000, // VSX Vector Test for software Divide Double-Precision XX3-form (xvtdivdp BF,XA,XB) 4433 [6]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4434 {XVTDIVSP, 0xfc0007f800000000, 0xf00002e800000000, 0x60000100000000, // VSX Vector Test for software Divide Single-Precision XX3-form (xvtdivsp BF,XA,XB) 4435 [6]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4436 {XVTSQRTDP, 0xfc0007fc00000000, 0xf00003a800000000, 0x7f000100000000, // VSX Vector Test for software Square Root Double-Precision XX2-form (xvtsqrtdp BF,XB) 4437 [6]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}}, 4438 {XVTSQRTSP, 0xfc0007fc00000000, 0xf00002a800000000, 0x7f000100000000, // VSX Vector Test for software Square Root Single-Precision XX2-form (xvtsqrtsp BF,XB) 4439 [6]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}}, 4440 {XXLAND, 0xfc0007f800000000, 0xf000041000000000, 0x0, // VSX Vector Logical AND XX3-form (xxland XT,XA,XB) 4441 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4442 {XXLANDC, 0xfc0007f800000000, 0xf000045000000000, 0x0, // VSX Vector Logical AND with Complement XX3-form (xxlandc XT,XA,XB) 4443 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4444 {XXLNOR, 0xfc0007f800000000, 0xf000051000000000, 0x0, // VSX Vector Logical NOR XX3-form (xxlnor XT,XA,XB) 4445 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4446 {XXLOR, 0xfc0007f800000000, 0xf000049000000000, 0x0, // VSX Vector Logical OR XX3-form (xxlor XT,XA,XB) 4447 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4448 {XXLXOR, 0xfc0007f800000000, 0xf00004d000000000, 0x0, // VSX Vector Logical XOR XX3-form (xxlxor XT,XA,XB) 4449 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4450 {XXMRGHW, 0xfc0007f800000000, 0xf000009000000000, 0x0, // VSX Vector Merge High Word XX3-form (xxmrghw XT,XA,XB) 4451 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4452 {XXMRGLW, 0xfc0007f800000000, 0xf000019000000000, 0x0, // VSX Vector Merge Low Word XX3-form (xxmrglw XT,XA,XB) 4453 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4454 {XXPERMDI, 0xfc0004f800000000, 0xf000005000000000, 0x0, // VSX Vector Permute Doubleword Immediate XX3-form (xxpermdi XT,XA,XB,DM) 4455 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_22_23}}, 4456 {XXSEL, 0xfc00003000000000, 0xf000003000000000, 0x0, // VSX Vector Select XX4-form (xxsel XT,XA,XB,XC) 4457 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_VecSReg_28_28_21_25}}, 4458 {XXSLDWI, 0xfc0004f800000000, 0xf000001000000000, 0x0, // VSX Vector Shift Left Double by Word Immediate XX3-form (xxsldwi XT,XA,XB,SHW) 4459 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_22_23}}, 4460 {XXSPLTW, 0xfc0007fc00000000, 0xf000029000000000, 0x1c000000000000, // VSX Vector Splat Word XX2-form (xxspltw XT,XB,UIM) 4461 [6]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_14_15}}, 4462 {CMPB, 0xfc0007fe00000000, 0x7c0003f800000000, 0x100000000, // Compare Bytes X-form (cmpb RA,RS,RB) 4463 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 4464 {DADD, 0xfc0007ff00000000, 0xec00000400000000, 0x0, // DFP Add X-form (dadd FRT,FRA,FRB) 4465 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4466 {DADDCC, 0xfc0007ff00000000, 0xec00000500000000, 0x0, // DFP Add X-form (dadd. FRT,FRA,FRB) 4467 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4468 {DADDQ, 0xfc0007ff00000000, 0xfc00000400000000, 0x0, // DFP Add Quad X-form (daddq FRTp,FRAp,FRBp) 4469 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4470 {DADDQCC, 0xfc0007ff00000000, 0xfc00000500000000, 0x0, // DFP Add Quad X-form (daddq. FRTp,FRAp,FRBp) 4471 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4472 {DCFFIXQ, 0xfc0007ff00000000, 0xfc00064400000000, 0x1f000000000000, // DFP Convert From Fixed Quad X-form (dcffixq FRTp,FRB) 4473 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4474 {DCFFIXQCC, 0xfc0007ff00000000, 0xfc00064500000000, 0x1f000000000000, // DFP Convert From Fixed Quad X-form (dcffixq. FRTp,FRB) 4475 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4476 {DCMPO, 0xfc0007fe00000000, 0xec00010400000000, 0x60000100000000, // DFP Compare Ordered X-form (dcmpo BF,FRA,FRB) 4477 [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, 4478 {DCMPOQ, 0xfc0007fe00000000, 0xfc00010400000000, 0x60000100000000, // DFP Compare Ordered Quad X-form (dcmpoq BF,FRAp,FRBp) 4479 [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, 4480 {DCMPU, 0xfc0007fe00000000, 0xec00050400000000, 0x60000100000000, // DFP Compare Unordered X-form (dcmpu BF,FRA,FRB) 4481 [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, 4482 {DCMPUQ, 0xfc0007fe00000000, 0xfc00050400000000, 0x60000100000000, // DFP Compare Unordered Quad X-form (dcmpuq BF,FRAp,FRBp) 4483 [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, 4484 {DCTDP, 0xfc0007ff00000000, 0xec00020400000000, 0x1f000000000000, // DFP Convert To DFP Long X-form (dctdp FRT,FRB) 4485 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4486 {DCTDPCC, 0xfc0007ff00000000, 0xec00020500000000, 0x1f000000000000, // DFP Convert To DFP Long X-form (dctdp. FRT,FRB) 4487 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4488 {DCTFIX, 0xfc0007ff00000000, 0xec00024400000000, 0x1f000000000000, // DFP Convert To Fixed X-form (dctfix FRT,FRB) 4489 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4490 {DCTFIXCC, 0xfc0007ff00000000, 0xec00024500000000, 0x1f000000000000, // DFP Convert To Fixed X-form (dctfix. FRT,FRB) 4491 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4492 {DCTFIXQ, 0xfc0007ff00000000, 0xfc00024400000000, 0x1f000000000000, // DFP Convert To Fixed Quad X-form (dctfixq FRT,FRBp) 4493 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4494 {DCTFIXQCC, 0xfc0007ff00000000, 0xfc00024500000000, 0x1f000000000000, // DFP Convert To Fixed Quad X-form (dctfixq. FRT,FRBp) 4495 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4496 {DCTQPQ, 0xfc0007ff00000000, 0xfc00020400000000, 0x1f000000000000, // DFP Convert To DFP Extended X-form (dctqpq FRTp,FRB) 4497 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4498 {DCTQPQCC, 0xfc0007ff00000000, 0xfc00020500000000, 0x1f000000000000, // DFP Convert To DFP Extended X-form (dctqpq. FRTp,FRB) 4499 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4500 {DDEDPD, 0xfc0007ff00000000, 0xec00028400000000, 0x7000000000000, // DFP Decode DPD To BCD X-form (ddedpd SP,FRT,FRB) 4501 [6]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}}, 4502 {DDEDPDCC, 0xfc0007ff00000000, 0xec00028500000000, 0x7000000000000, // DFP Decode DPD To BCD X-form (ddedpd. SP,FRT,FRB) 4503 [6]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}}, 4504 {DDEDPDQ, 0xfc0007ff00000000, 0xfc00028400000000, 0x7000000000000, // DFP Decode DPD To BCD Quad X-form (ddedpdq SP,FRTp,FRBp) 4505 [6]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}}, 4506 {DDEDPDQCC, 0xfc0007ff00000000, 0xfc00028500000000, 0x7000000000000, // DFP Decode DPD To BCD Quad X-form (ddedpdq. SP,FRTp,FRBp) 4507 [6]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}}, 4508 {DDIV, 0xfc0007ff00000000, 0xec00044400000000, 0x0, // DFP Divide X-form (ddiv FRT,FRA,FRB) 4509 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4510 {DDIVCC, 0xfc0007ff00000000, 0xec00044500000000, 0x0, // DFP Divide X-form (ddiv. FRT,FRA,FRB) 4511 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4512 {DDIVQ, 0xfc0007ff00000000, 0xfc00044400000000, 0x0, // DFP Divide Quad X-form (ddivq FRTp,FRAp,FRBp) 4513 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4514 {DDIVQCC, 0xfc0007ff00000000, 0xfc00044500000000, 0x0, // DFP Divide Quad X-form (ddivq. FRTp,FRAp,FRBp) 4515 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4516 {DENBCD, 0xfc0007ff00000000, 0xec00068400000000, 0xf000000000000, // DFP Encode BCD To DPD X-form (denbcd S,FRT,FRB) 4517 [6]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}}, 4518 {DENBCDCC, 0xfc0007ff00000000, 0xec00068500000000, 0xf000000000000, // DFP Encode BCD To DPD X-form (denbcd. S,FRT,FRB) 4519 [6]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}}, 4520 {DENBCDQ, 0xfc0007ff00000000, 0xfc00068400000000, 0xf000000000000, // DFP Encode BCD To DPD Quad X-form (denbcdq S,FRTp,FRBp) 4521 [6]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}}, 4522 {DENBCDQCC, 0xfc0007ff00000000, 0xfc00068500000000, 0xf000000000000, // DFP Encode BCD To DPD Quad X-form (denbcdq. S,FRTp,FRBp) 4523 [6]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}}, 4524 {DIEX, 0xfc0007ff00000000, 0xec0006c400000000, 0x0, // DFP Insert Biased Exponent X-form (diex FRT,FRA,FRB) 4525 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4526 {DIEXCC, 0xfc0007ff00000000, 0xec0006c500000000, 0x0, // DFP Insert Biased Exponent X-form (diex. FRT,FRA,FRB) 4527 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4528 {DIEXQCC, 0xfc0007ff00000000, 0xfc0006c500000000, 0x0, // DFP Insert Biased Exponent Quad X-form (diexq. FRTp,FRA,FRBp) 4529 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4530 {DIEXQ, 0xfc0007fe00000000, 0xfc0006c400000000, 0x0, // DFP Insert Biased Exponent Quad X-form (diexq FRTp,FRA,FRBp) 4531 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4532 {DMUL, 0xfc0007ff00000000, 0xec00004400000000, 0x0, // DFP Multiply X-form (dmul FRT,FRA,FRB) 4533 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4534 {DMULCC, 0xfc0007ff00000000, 0xec00004500000000, 0x0, // DFP Multiply X-form (dmul. FRT,FRA,FRB) 4535 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4536 {DMULQ, 0xfc0007ff00000000, 0xfc00004400000000, 0x0, // DFP Multiply Quad X-form (dmulq FRTp,FRAp,FRBp) 4537 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4538 {DMULQCC, 0xfc0007ff00000000, 0xfc00004500000000, 0x0, // DFP Multiply Quad X-form (dmulq. FRTp,FRAp,FRBp) 4539 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4540 {DQUA, 0xfc0001ff00000000, 0xec00000600000000, 0x0, // DFP Quantize Z23-form (dqua FRT,FRA,FRB,RMC) 4541 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4542 {DQUACC, 0xfc0001ff00000000, 0xec00000700000000, 0x0, // DFP Quantize Z23-form (dqua. FRT,FRA,FRB,RMC) 4543 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4544 {DQUAI, 0xfc0001ff00000000, 0xec00008600000000, 0x0, // DFP Quantize Immediate Z23-form (dquai TE,FRT,FRB,RMC) 4545 [6]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4546 {DQUAICC, 0xfc0001ff00000000, 0xec00008700000000, 0x0, // DFP Quantize Immediate Z23-form (dquai. TE,FRT,FRB,RMC) 4547 [6]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4548 {DQUAIQ, 0xfc0001ff00000000, 0xfc00008600000000, 0x0, // DFP Quantize Immediate Quad Z23-form (dquaiq TE,FRTp,FRBp,RMC) 4549 [6]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4550 {DQUAIQCC, 0xfc0001ff00000000, 0xfc00008700000000, 0x0, // DFP Quantize Immediate Quad Z23-form (dquaiq. TE,FRTp,FRBp,RMC) 4551 [6]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4552 {DQUAQ, 0xfc0001ff00000000, 0xfc00000600000000, 0x0, // DFP Quantize Quad Z23-form (dquaq FRTp,FRAp,FRBp,RMC) 4553 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4554 {DQUAQCC, 0xfc0001ff00000000, 0xfc00000700000000, 0x0, // DFP Quantize Quad Z23-form (dquaq. FRTp,FRAp,FRBp,RMC) 4555 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4556 {DRDPQ, 0xfc0007ff00000000, 0xfc00060400000000, 0x1f000000000000, // DFP Round To DFP Long X-form (drdpq FRTp,FRBp) 4557 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4558 {DRDPQCC, 0xfc0007ff00000000, 0xfc00060500000000, 0x1f000000000000, // DFP Round To DFP Long X-form (drdpq. FRTp,FRBp) 4559 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4560 {DRINTN, 0xfc0001ff00000000, 0xec0001c600000000, 0x1e000000000000, // DFP Round To FP Integer Without Inexact Z23-form (drintn R,FRT,FRB,RMC) 4561 [6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4562 {DRINTNCC, 0xfc0001ff00000000, 0xec0001c700000000, 0x1e000000000000, // DFP Round To FP Integer Without Inexact Z23-form (drintn. R,FRT,FRB,RMC) 4563 [6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4564 {DRINTNQ, 0xfc0001ff00000000, 0xfc0001c600000000, 0x1e000000000000, // DFP Round To FP Integer Without Inexact Quad Z23-form (drintnq R,FRTp,FRBp,RMC) 4565 [6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4566 {DRINTNQCC, 0xfc0001ff00000000, 0xfc0001c700000000, 0x1e000000000000, // DFP Round To FP Integer Without Inexact Quad Z23-form (drintnq. R,FRTp,FRBp,RMC) 4567 [6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4568 {DRINTX, 0xfc0001ff00000000, 0xec0000c600000000, 0x1e000000000000, // DFP Round To FP Integer With Inexact Z23-form (drintx R,FRT,FRB,RMC) 4569 [6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4570 {DRINTXCC, 0xfc0001ff00000000, 0xec0000c700000000, 0x1e000000000000, // DFP Round To FP Integer With Inexact Z23-form (drintx. R,FRT,FRB,RMC) 4571 [6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4572 {DRINTXQ, 0xfc0001ff00000000, 0xfc0000c600000000, 0x1e000000000000, // DFP Round To FP Integer With Inexact Quad Z23-form (drintxq R,FRTp,FRBp,RMC) 4573 [6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4574 {DRINTXQCC, 0xfc0001ff00000000, 0xfc0000c700000000, 0x1e000000000000, // DFP Round To FP Integer With Inexact Quad Z23-form (drintxq. R,FRTp,FRBp,RMC) 4575 [6]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4576 {DRRND, 0xfc0001ff00000000, 0xec00004600000000, 0x0, // DFP Reround Z23-form (drrnd FRT,FRA,FRB,RMC) 4577 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4578 {DRRNDCC, 0xfc0001ff00000000, 0xec00004700000000, 0x0, // DFP Reround Z23-form (drrnd. FRT,FRA,FRB,RMC) 4579 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4580 {DRRNDQ, 0xfc0001ff00000000, 0xfc00004600000000, 0x0, // DFP Reround Quad Z23-form (drrndq FRTp,FRA,FRBp,RMC) 4581 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4582 {DRRNDQCC, 0xfc0001ff00000000, 0xfc00004700000000, 0x0, // DFP Reround Quad Z23-form (drrndq. FRTp,FRA,FRBp,RMC) 4583 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4584 {DRSP, 0xfc0007ff00000000, 0xec00060400000000, 0x1f000000000000, // DFP Round To DFP Short X-form (drsp FRT,FRB) 4585 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4586 {DRSPCC, 0xfc0007ff00000000, 0xec00060500000000, 0x1f000000000000, // DFP Round To DFP Short X-form (drsp. FRT,FRB) 4587 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4588 {DSCLI, 0xfc0003ff00000000, 0xec00008400000000, 0x0, // DFP Shift Significand Left Immediate Z22-form (dscli FRT,FRA,SH) 4589 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, 4590 {DSCLICC, 0xfc0003ff00000000, 0xec00008500000000, 0x0, // DFP Shift Significand Left Immediate Z22-form (dscli. FRT,FRA,SH) 4591 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, 4592 {DSCLIQ, 0xfc0003ff00000000, 0xfc00008400000000, 0x0, // DFP Shift Significand Left Immediate Quad Z22-form (dscliq FRTp,FRAp,SH) 4593 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, 4594 {DSCLIQCC, 0xfc0003ff00000000, 0xfc00008500000000, 0x0, // DFP Shift Significand Left Immediate Quad Z22-form (dscliq. FRTp,FRAp,SH) 4595 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, 4596 {DSCRI, 0xfc0003ff00000000, 0xec0000c400000000, 0x0, // DFP Shift Significand Right Immediate Z22-form (dscri FRT,FRA,SH) 4597 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, 4598 {DSCRICC, 0xfc0003ff00000000, 0xec0000c500000000, 0x0, // DFP Shift Significand Right Immediate Z22-form (dscri. FRT,FRA,SH) 4599 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, 4600 {DSCRIQ, 0xfc0003ff00000000, 0xfc0000c400000000, 0x0, // DFP Shift Significand Right Immediate Quad Z22-form (dscriq FRTp,FRAp,SH) 4601 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, 4602 {DSCRIQCC, 0xfc0003ff00000000, 0xfc0000c500000000, 0x0, // DFP Shift Significand Right Immediate Quad Z22-form (dscriq. FRTp,FRAp,SH) 4603 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, 4604 {DSUB, 0xfc0007ff00000000, 0xec00040400000000, 0x0, // DFP Subtract X-form (dsub FRT,FRA,FRB) 4605 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4606 {DSUBCC, 0xfc0007ff00000000, 0xec00040500000000, 0x0, // DFP Subtract X-form (dsub. FRT,FRA,FRB) 4607 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4608 {DSUBQ, 0xfc0007ff00000000, 0xfc00040400000000, 0x0, // DFP Subtract Quad X-form (dsubq FRTp,FRAp,FRBp) 4609 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4610 {DSUBQCC, 0xfc0007ff00000000, 0xfc00040500000000, 0x0, // DFP Subtract Quad X-form (dsubq. FRTp,FRAp,FRBp) 4611 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4612 {DTSTDC, 0xfc0003fe00000000, 0xec00018400000000, 0x60000100000000, // DFP Test Data Class Z22-form (dtstdc BF,FRA,DCM) 4613 [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, 4614 {DTSTDCQ, 0xfc0003fe00000000, 0xfc00018400000000, 0x60000100000000, // DFP Test Data Class Quad Z22-form (dtstdcq BF,FRAp,DCM) 4615 [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, 4616 {DTSTDG, 0xfc0003fe00000000, 0xec0001c400000000, 0x60000100000000, // DFP Test Data Group Z22-form (dtstdg BF,FRA,DGM) 4617 [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, 4618 {DTSTDGQ, 0xfc0003fe00000000, 0xfc0001c400000000, 0x60000100000000, // DFP Test Data Group Quad Z22-form (dtstdgq BF,FRAp,DGM) 4619 [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, 4620 {DTSTEX, 0xfc0007fe00000000, 0xec00014400000000, 0x60000100000000, // DFP Test Exponent X-form (dtstex BF,FRA,FRB) 4621 [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, 4622 {DTSTEXQ, 0xfc0007fe00000000, 0xfc00014400000000, 0x60000100000000, // DFP Test Exponent Quad X-form (dtstexq BF,FRAp,FRBp) 4623 [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, 4624 {DTSTSF, 0xfc0007fe00000000, 0xec00054400000000, 0x60000100000000, // DFP Test Significance X-form (dtstsf BF,FRA,FRB) 4625 [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, 4626 {DTSTSFQ, 0xfc0007fe00000000, 0xfc00054400000000, 0x60000100000000, // DFP Test Significance Quad X-form (dtstsfq BF,FRA,FRBp) 4627 [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, 4628 {DXEX, 0xfc0007ff00000000, 0xec0002c400000000, 0x1f000000000000, // DFP Extract Biased Exponent X-form (dxex FRT,FRB) 4629 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4630 {DXEXCC, 0xfc0007ff00000000, 0xec0002c500000000, 0x1f000000000000, // DFP Extract Biased Exponent X-form (dxex. FRT,FRB) 4631 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4632 {DXEXQ, 0xfc0007ff00000000, 0xfc0002c400000000, 0x1f000000000000, // DFP Extract Biased Exponent Quad X-form (dxexq FRT,FRBp) 4633 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4634 {DXEXQCC, 0xfc0007ff00000000, 0xfc0002c500000000, 0x1f000000000000, // DFP Extract Biased Exponent Quad X-form (dxexq. FRT,FRBp) 4635 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4636 {FCPSGN, 0xfc0007ff00000000, 0xfc00001000000000, 0x0, // Floating Copy Sign X-form (fcpsgn FRT, FRA, FRB) 4637 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4638 {FCPSGNCC, 0xfc0007ff00000000, 0xfc00001100000000, 0x0, // Floating Copy Sign X-form (fcpsgn. FRT, FRA, FRB) 4639 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4640 {LBZCIX, 0xfc0007fe00000000, 0x7c0006aa00000000, 0x100000000, // Load Byte & Zero Caching Inhibited Indexed X-form (lbzcix RT,RA,RB) 4641 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4642 {LDCIX, 0xfc0007fe00000000, 0x7c0006ea00000000, 0x100000000, // Load Doubleword Caching Inhibited Indexed X-form (ldcix RT,RA,RB) 4643 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4644 {LFDP, 0xfc00000300000000, 0xe400000000000000, 0x0, // Load Floating-Point Double Pair DS-form (lfdp FRTp,DS(RA)) 4645 [6]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, 4646 {LFDPX, 0xfc0007fe00000000, 0x7c00062e00000000, 0x100000000, // Load Floating-Point Double Pair Indexed X-form (lfdpx FRTp,RA,RB) 4647 [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4648 {LFIWAX, 0xfc0007fe00000000, 0x7c0006ae00000000, 0x100000000, // Load Floating-Point as Integer Word Algebraic Indexed X-form (lfiwax FRT,RA,RB) 4649 [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4650 {LHZCIX, 0xfc0007fe00000000, 0x7c00066a00000000, 0x100000000, // Load Halfword & Zero Caching Inhibited Indexed X-form (lhzcix RT,RA,RB) 4651 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4652 {LWZCIX, 0xfc0007fe00000000, 0x7c00062a00000000, 0x100000000, // Load Word & Zero Caching Inhibited Indexed X-form (lwzcix RT,RA,RB) 4653 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4654 {PRTYD, 0xfc0007fe00000000, 0x7c00017400000000, 0xf80100000000, // Parity Doubleword X-form (prtyd RA,RS) 4655 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 4656 {PRTYW, 0xfc0007fe00000000, 0x7c00013400000000, 0xf80100000000, // Parity Word X-form (prtyw RA,RS) 4657 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 4658 {SLBFEECC, 0xfc0007ff00000000, 0x7c0007a700000000, 0x1f000000000000, // SLB Find Entry ESID X-form (slbfee. RT,RB) 4659 [6]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4660 {STBCIX, 0xfc0007fe00000000, 0x7c0007aa00000000, 0x100000000, // Store Byte Caching Inhibited Indexed X-form (stbcix RS,RA,RB) 4661 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4662 {STDCIX, 0xfc0007fe00000000, 0x7c0007ea00000000, 0x100000000, // Store Doubleword Caching Inhibited Indexed X-form (stdcix RS,RA,RB) 4663 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4664 {STFDP, 0xfc00000300000000, 0xf400000000000000, 0x0, // Store Floating-Point Double Pair DS-form (stfdp FRSp,DS(RA)) 4665 [6]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, 4666 {STFDPX, 0xfc0007fe00000000, 0x7c00072e00000000, 0x100000000, // Store Floating-Point Double Pair Indexed X-form (stfdpx FRSp,RA,RB) 4667 [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4668 {STHCIX, 0xfc0007fe00000000, 0x7c00076a00000000, 0x100000000, // Store Halfword Caching Inhibited Indexed X-form (sthcix RS,RA,RB) 4669 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4670 {STWCIX, 0xfc0007fe00000000, 0x7c00072a00000000, 0x100000000, // Store Word Caching Inhibited Indexed X-form (stwcix RS,RA,RB) 4671 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4672 {ISEL, 0xfc00003e00000000, 0x7c00001e00000000, 0x100000000, // Integer Select A-form (isel RT,RA,RB,BC) 4673 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_CondRegBit_21_25}}, 4674 {LVEBX, 0xfc0007fe00000000, 0x7c00000e00000000, 0x100000000, // Load Vector Element Byte Indexed X-form (lvebx VRT,RA,RB) 4675 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4676 {LVEHX, 0xfc0007fe00000000, 0x7c00004e00000000, 0x100000000, // Load Vector Element Halfword Indexed X-form (lvehx VRT,RA,RB) 4677 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4678 {LVEWX, 0xfc0007fe00000000, 0x7c00008e00000000, 0x100000000, // Load Vector Element Word Indexed X-form (lvewx VRT,RA,RB) 4679 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4680 {LVSL, 0xfc0007fe00000000, 0x7c00000c00000000, 0x100000000, // Load Vector for Shift Left Indexed X-form (lvsl VRT,RA,RB) 4681 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4682 {LVSR, 0xfc0007fe00000000, 0x7c00004c00000000, 0x100000000, // Load Vector for Shift Right Indexed X-form (lvsr VRT,RA,RB) 4683 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4684 {LVX, 0xfc0007fe00000000, 0x7c0000ce00000000, 0x100000000, // Load Vector Indexed X-form (lvx VRT,RA,RB) 4685 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4686 {LVXL, 0xfc0007fe00000000, 0x7c0002ce00000000, 0x100000000, // Load Vector Indexed Last X-form (lvxl VRT,RA,RB) 4687 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4688 {MFVSCR, 0xfc0007ff00000000, 0x1000060400000000, 0x1ff80000000000, // Move From Vector Status and Control Register VX-form (mfvscr VRT) 4689 [6]*argField{ap_VecReg_6_10}}, 4690 {MTVSCR, 0xfc0007ff00000000, 0x1000064400000000, 0x3ff000000000000, // Move To Vector Status and Control Register VX-form (mtvscr VRB) 4691 [6]*argField{ap_VecReg_16_20}}, 4692 {STVEBX, 0xfc0007fe00000000, 0x7c00010e00000000, 0x100000000, // Store Vector Element Byte Indexed X-form (stvebx VRS,RA,RB) 4693 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4694 {STVEHX, 0xfc0007fe00000000, 0x7c00014e00000000, 0x100000000, // Store Vector Element Halfword Indexed X-form (stvehx VRS,RA,RB) 4695 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4696 {STVEWX, 0xfc0007fe00000000, 0x7c00018e00000000, 0x100000000, // Store Vector Element Word Indexed X-form (stvewx VRS,RA,RB) 4697 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4698 {STVX, 0xfc0007fe00000000, 0x7c0001ce00000000, 0x100000000, // Store Vector Indexed X-form (stvx VRS,RA,RB) 4699 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4700 {STVXL, 0xfc0007fe00000000, 0x7c0003ce00000000, 0x100000000, // Store Vector Indexed Last X-form (stvxl VRS,RA,RB) 4701 [6]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4702 {TLBIEL, 0xfc0007fe00000000, 0x7c00022400000000, 0x10000100000000, // TLB Invalidate Entry Local X-form (tlbiel RB,RS,RIC,PRS,R) 4703 [6]*argField{ap_Reg_16_20, ap_Reg_6_10, ap_ImmUnsigned_12_13, ap_ImmUnsigned_14_14, ap_ImmUnsigned_15_15}}, 4704 {VADDCUW, 0xfc0007ff00000000, 0x1000018000000000, 0x0, // Vector Add & write Carry Unsigned Word VX-form (vaddcuw VRT,VRA,VRB) 4705 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4706 {VADDFP, 0xfc0007ff00000000, 0x1000000a00000000, 0x0, // Vector Add Floating-Point VX-form (vaddfp VRT,VRA,VRB) 4707 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4708 {VADDSBS, 0xfc0007ff00000000, 0x1000030000000000, 0x0, // Vector Add Signed Byte Saturate VX-form (vaddsbs VRT,VRA,VRB) 4709 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4710 {VADDSHS, 0xfc0007ff00000000, 0x1000034000000000, 0x0, // Vector Add Signed Halfword Saturate VX-form (vaddshs VRT,VRA,VRB) 4711 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4712 {VADDSWS, 0xfc0007ff00000000, 0x1000038000000000, 0x0, // Vector Add Signed Word Saturate VX-form (vaddsws VRT,VRA,VRB) 4713 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4714 {VADDUBM, 0xfc0007ff00000000, 0x1000000000000000, 0x0, // Vector Add Unsigned Byte Modulo VX-form (vaddubm VRT,VRA,VRB) 4715 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4716 {VADDUBS, 0xfc0007ff00000000, 0x1000020000000000, 0x0, // Vector Add Unsigned Byte Saturate VX-form (vaddubs VRT,VRA,VRB) 4717 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4718 {VADDUHM, 0xfc0007ff00000000, 0x1000004000000000, 0x0, // Vector Add Unsigned Halfword Modulo VX-form (vadduhm VRT,VRA,VRB) 4719 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4720 {VADDUHS, 0xfc0007ff00000000, 0x1000024000000000, 0x0, // Vector Add Unsigned Halfword Saturate VX-form (vadduhs VRT,VRA,VRB) 4721 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4722 {VADDUWM, 0xfc0007ff00000000, 0x1000008000000000, 0x0, // Vector Add Unsigned Word Modulo VX-form (vadduwm VRT,VRA,VRB) 4723 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4724 {VADDUWS, 0xfc0007ff00000000, 0x1000028000000000, 0x0, // Vector Add Unsigned Word Saturate VX-form (vadduws VRT,VRA,VRB) 4725 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4726 {VAND, 0xfc0007ff00000000, 0x1000040400000000, 0x0, // Vector Logical AND VX-form (vand VRT,VRA,VRB) 4727 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4728 {VANDC, 0xfc0007ff00000000, 0x1000044400000000, 0x0, // Vector Logical AND with Complement VX-form (vandc VRT,VRA,VRB) 4729 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4730 {VAVGSB, 0xfc0007ff00000000, 0x1000050200000000, 0x0, // Vector Average Signed Byte VX-form (vavgsb VRT,VRA,VRB) 4731 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4732 {VAVGSH, 0xfc0007ff00000000, 0x1000054200000000, 0x0, // Vector Average Signed Halfword VX-form (vavgsh VRT,VRA,VRB) 4733 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4734 {VAVGSW, 0xfc0007ff00000000, 0x1000058200000000, 0x0, // Vector Average Signed Word VX-form (vavgsw VRT,VRA,VRB) 4735 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4736 {VAVGUB, 0xfc0007ff00000000, 0x1000040200000000, 0x0, // Vector Average Unsigned Byte VX-form (vavgub VRT,VRA,VRB) 4737 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4738 {VAVGUH, 0xfc0007ff00000000, 0x1000044200000000, 0x0, // Vector Average Unsigned Halfword VX-form (vavguh VRT,VRA,VRB) 4739 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4740 {VAVGUW, 0xfc0007ff00000000, 0x1000048200000000, 0x0, // Vector Average Unsigned Word VX-form (vavguw VRT,VRA,VRB) 4741 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4742 {VCFSX, 0xfc0007ff00000000, 0x1000034a00000000, 0x0, // Vector Convert with round to nearest From Signed Word to floating-point format VX-form (vcfsx VRT,VRB,UIM) 4743 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}}, 4744 {VCFUX, 0xfc0007ff00000000, 0x1000030a00000000, 0x0, // Vector Convert with round to nearest From Unsigned Word to floating-point format VX-form (vcfux VRT,VRB,UIM) 4745 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}}, 4746 {VCMPBFP, 0xfc0007ff00000000, 0x100003c600000000, 0x0, // Vector Compare Bounds Floating-Point VC-form (vcmpbfp VRT,VRA,VRB) 4747 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4748 {VCMPBFPCC, 0xfc0007ff00000000, 0x100007c600000000, 0x0, // Vector Compare Bounds Floating-Point VC-form (vcmpbfp. VRT,VRA,VRB) 4749 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4750 {VCMPEQFP, 0xfc0007ff00000000, 0x100000c600000000, 0x0, // Vector Compare Equal Floating-Point VC-form (vcmpeqfp VRT,VRA,VRB) 4751 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4752 {VCMPEQFPCC, 0xfc0007ff00000000, 0x100004c600000000, 0x0, // Vector Compare Equal Floating-Point VC-form (vcmpeqfp. VRT,VRA,VRB) 4753 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4754 {VCMPEQUB, 0xfc0007ff00000000, 0x1000000600000000, 0x0, // Vector Compare Equal Unsigned Byte VC-form (vcmpequb VRT,VRA,VRB) 4755 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4756 {VCMPEQUBCC, 0xfc0007ff00000000, 0x1000040600000000, 0x0, // Vector Compare Equal Unsigned Byte VC-form (vcmpequb. VRT,VRA,VRB) 4757 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4758 {VCMPEQUH, 0xfc0007ff00000000, 0x1000004600000000, 0x0, // Vector Compare Equal Unsigned Halfword VC-form (vcmpequh VRT,VRA,VRB) 4759 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4760 {VCMPEQUHCC, 0xfc0007ff00000000, 0x1000044600000000, 0x0, // Vector Compare Equal Unsigned Halfword VC-form (vcmpequh. VRT,VRA,VRB) 4761 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4762 {VCMPEQUW, 0xfc0007ff00000000, 0x1000008600000000, 0x0, // Vector Compare Equal Unsigned Word VC-form (vcmpequw VRT,VRA,VRB) 4763 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4764 {VCMPEQUWCC, 0xfc0007ff00000000, 0x1000048600000000, 0x0, // Vector Compare Equal Unsigned Word VC-form (vcmpequw. VRT,VRA,VRB) 4765 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4766 {VCMPGEFP, 0xfc0007ff00000000, 0x100001c600000000, 0x0, // Vector Compare Greater Than or Equal Floating-Point VC-form (vcmpgefp VRT,VRA,VRB) 4767 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4768 {VCMPGEFPCC, 0xfc0007ff00000000, 0x100005c600000000, 0x0, // Vector Compare Greater Than or Equal Floating-Point VC-form (vcmpgefp. VRT,VRA,VRB) 4769 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4770 {VCMPGTFP, 0xfc0007ff00000000, 0x100002c600000000, 0x0, // Vector Compare Greater Than Floating-Point VC-form (vcmpgtfp VRT,VRA,VRB) 4771 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4772 {VCMPGTFPCC, 0xfc0007ff00000000, 0x100006c600000000, 0x0, // Vector Compare Greater Than Floating-Point VC-form (vcmpgtfp. VRT,VRA,VRB) 4773 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4774 {VCMPGTSB, 0xfc0007ff00000000, 0x1000030600000000, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb VRT,VRA,VRB) 4775 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4776 {VCMPGTSBCC, 0xfc0007ff00000000, 0x1000070600000000, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb. VRT,VRA,VRB) 4777 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4778 {VCMPGTSH, 0xfc0007ff00000000, 0x1000034600000000, 0x0, // Vector Compare Greater Than Signed Halfword VC-form (vcmpgtsh VRT,VRA,VRB) 4779 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4780 {VCMPGTSHCC, 0xfc0007ff00000000, 0x1000074600000000, 0x0, // Vector Compare Greater Than Signed Halfword VC-form (vcmpgtsh. VRT,VRA,VRB) 4781 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4782 {VCMPGTSW, 0xfc0007ff00000000, 0x1000038600000000, 0x0, // Vector Compare Greater Than Signed Word VC-form (vcmpgtsw VRT,VRA,VRB) 4783 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4784 {VCMPGTSWCC, 0xfc0007ff00000000, 0x1000078600000000, 0x0, // Vector Compare Greater Than Signed Word VC-form (vcmpgtsw. VRT,VRA,VRB) 4785 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4786 {VCMPGTUB, 0xfc0007ff00000000, 0x1000020600000000, 0x0, // Vector Compare Greater Than Unsigned Byte VC-form (vcmpgtub VRT,VRA,VRB) 4787 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4788 {VCMPGTUBCC, 0xfc0007ff00000000, 0x1000060600000000, 0x0, // Vector Compare Greater Than Unsigned Byte VC-form (vcmpgtub. VRT,VRA,VRB) 4789 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4790 {VCMPGTUH, 0xfc0007ff00000000, 0x1000024600000000, 0x0, // Vector Compare Greater Than Unsigned Halfword VC-form (vcmpgtuh VRT,VRA,VRB) 4791 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4792 {VCMPGTUHCC, 0xfc0007ff00000000, 0x1000064600000000, 0x0, // Vector Compare Greater Than Unsigned Halfword VC-form (vcmpgtuh. VRT,VRA,VRB) 4793 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4794 {VCMPGTUW, 0xfc0007ff00000000, 0x1000028600000000, 0x0, // Vector Compare Greater Than Unsigned Word VC-form (vcmpgtuw VRT,VRA,VRB) 4795 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4796 {VCMPGTUWCC, 0xfc0007ff00000000, 0x1000068600000000, 0x0, // Vector Compare Greater Than Unsigned Word VC-form (vcmpgtuw. VRT,VRA,VRB) 4797 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4798 {VCTSXS, 0xfc0007ff00000000, 0x100003ca00000000, 0x0, // Vector Convert with round to zero from floating-point To Signed Word format Saturate VX-form (vctsxs VRT,VRB,UIM) 4799 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}}, 4800 {VCTUXS, 0xfc0007ff00000000, 0x1000038a00000000, 0x0, // Vector Convert with round to zero from floating-point To Unsigned Word format Saturate VX-form (vctuxs VRT,VRB,UIM) 4801 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}}, 4802 {VEXPTEFP, 0xfc0007ff00000000, 0x1000018a00000000, 0x1f000000000000, // Vector 2 Raised to the Exponent Estimate Floating-Point VX-form (vexptefp VRT,VRB) 4803 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4804 {VLOGEFP, 0xfc0007ff00000000, 0x100001ca00000000, 0x1f000000000000, // Vector Log Base 2 Estimate Floating-Point VX-form (vlogefp VRT,VRB) 4805 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4806 {VMADDFP, 0xfc00003f00000000, 0x1000002e00000000, 0x0, // Vector Multiply-Add Floating-Point VA-form (vmaddfp VRT,VRA,VRC,VRB) 4807 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_21_25, ap_VecReg_16_20}}, 4808 {VMAXFP, 0xfc0007ff00000000, 0x1000040a00000000, 0x0, // Vector Maximum Floating-Point VX-form (vmaxfp VRT,VRA,VRB) 4809 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4810 {VMAXSB, 0xfc0007ff00000000, 0x1000010200000000, 0x0, // Vector Maximum Signed Byte VX-form (vmaxsb VRT,VRA,VRB) 4811 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4812 {VMAXSH, 0xfc0007ff00000000, 0x1000014200000000, 0x0, // Vector Maximum Signed Halfword VX-form (vmaxsh VRT,VRA,VRB) 4813 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4814 {VMAXSW, 0xfc0007ff00000000, 0x1000018200000000, 0x0, // Vector Maximum Signed Word VX-form (vmaxsw VRT,VRA,VRB) 4815 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4816 {VMAXUB, 0xfc0007ff00000000, 0x1000000200000000, 0x0, // Vector Maximum Unsigned Byte VX-form (vmaxub VRT,VRA,VRB) 4817 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4818 {VMAXUH, 0xfc0007ff00000000, 0x1000004200000000, 0x0, // Vector Maximum Unsigned Halfword VX-form (vmaxuh VRT,VRA,VRB) 4819 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4820 {VMAXUW, 0xfc0007ff00000000, 0x1000008200000000, 0x0, // Vector Maximum Unsigned Word VX-form (vmaxuw VRT,VRA,VRB) 4821 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4822 {VMHADDSHS, 0xfc00003f00000000, 0x1000002000000000, 0x0, // Vector Multiply-High-Add Signed Halfword Saturate VA-form (vmhaddshs VRT,VRA,VRB,VRC) 4823 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 4824 {VMHRADDSHS, 0xfc00003f00000000, 0x1000002100000000, 0x0, // Vector Multiply-High-Round-Add Signed Halfword Saturate VA-form (vmhraddshs VRT,VRA,VRB,VRC) 4825 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 4826 {VMINFP, 0xfc0007ff00000000, 0x1000044a00000000, 0x0, // Vector Minimum Floating-Point VX-form (vminfp VRT,VRA,VRB) 4827 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4828 {VMINSB, 0xfc0007ff00000000, 0x1000030200000000, 0x0, // Vector Minimum Signed Byte VX-form (vminsb VRT,VRA,VRB) 4829 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4830 {VMINSH, 0xfc0007ff00000000, 0x1000034200000000, 0x0, // Vector Minimum Signed Halfword VX-form (vminsh VRT,VRA,VRB) 4831 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4832 {VMINSW, 0xfc0007ff00000000, 0x1000038200000000, 0x0, // Vector Minimum Signed Word VX-form (vminsw VRT,VRA,VRB) 4833 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4834 {VMINUB, 0xfc0007ff00000000, 0x1000020200000000, 0x0, // Vector Minimum Unsigned Byte VX-form (vminub VRT,VRA,VRB) 4835 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4836 {VMINUH, 0xfc0007ff00000000, 0x1000024200000000, 0x0, // Vector Minimum Unsigned Halfword VX-form (vminuh VRT,VRA,VRB) 4837 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4838 {VMINUW, 0xfc0007ff00000000, 0x1000028200000000, 0x0, // Vector Minimum Unsigned Word VX-form (vminuw VRT,VRA,VRB) 4839 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4840 {VMLADDUHM, 0xfc00003f00000000, 0x1000002200000000, 0x0, // Vector Multiply-Low-Add Unsigned Halfword Modulo VA-form (vmladduhm VRT,VRA,VRB,VRC) 4841 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 4842 {VMRGHB, 0xfc0007ff00000000, 0x1000000c00000000, 0x0, // Vector Merge High Byte VX-form (vmrghb VRT,VRA,VRB) 4843 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4844 {VMRGHH, 0xfc0007ff00000000, 0x1000004c00000000, 0x0, // Vector Merge High Halfword VX-form (vmrghh VRT,VRA,VRB) 4845 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4846 {VMRGHW, 0xfc0007ff00000000, 0x1000008c00000000, 0x0, // Vector Merge High Word VX-form (vmrghw VRT,VRA,VRB) 4847 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4848 {VMRGLB, 0xfc0007ff00000000, 0x1000010c00000000, 0x0, // Vector Merge Low Byte VX-form (vmrglb VRT,VRA,VRB) 4849 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4850 {VMRGLH, 0xfc0007ff00000000, 0x1000014c00000000, 0x0, // Vector Merge Low Halfword VX-form (vmrglh VRT,VRA,VRB) 4851 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4852 {VMRGLW, 0xfc0007ff00000000, 0x1000018c00000000, 0x0, // Vector Merge Low Word VX-form (vmrglw VRT,VRA,VRB) 4853 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4854 {VMSUMMBM, 0xfc00003f00000000, 0x1000002500000000, 0x0, // Vector Multiply-Sum Mixed Byte Modulo VA-form (vmsummbm VRT,VRA,VRB,VRC) 4855 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 4856 {VMSUMSHM, 0xfc00003f00000000, 0x1000002800000000, 0x0, // Vector Multiply-Sum Signed Halfword Modulo VA-form (vmsumshm VRT,VRA,VRB,VRC) 4857 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 4858 {VMSUMSHS, 0xfc00003f00000000, 0x1000002900000000, 0x0, // Vector Multiply-Sum Signed Halfword Saturate VA-form (vmsumshs VRT,VRA,VRB,VRC) 4859 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 4860 {VMSUMUBM, 0xfc00003f00000000, 0x1000002400000000, 0x0, // Vector Multiply-Sum Unsigned Byte Modulo VA-form (vmsumubm VRT,VRA,VRB,VRC) 4861 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 4862 {VMSUMUHM, 0xfc00003f00000000, 0x1000002600000000, 0x0, // Vector Multiply-Sum Unsigned Halfword Modulo VA-form (vmsumuhm VRT,VRA,VRB,VRC) 4863 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 4864 {VMSUMUHS, 0xfc00003f00000000, 0x1000002700000000, 0x0, // Vector Multiply-Sum Unsigned Halfword Saturate VA-form (vmsumuhs VRT,VRA,VRB,VRC) 4865 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 4866 {VMULESB, 0xfc0007ff00000000, 0x1000030800000000, 0x0, // Vector Multiply Even Signed Byte VX-form (vmulesb VRT,VRA,VRB) 4867 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4868 {VMULESH, 0xfc0007ff00000000, 0x1000034800000000, 0x0, // Vector Multiply Even Signed Halfword VX-form (vmulesh VRT,VRA,VRB) 4869 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4870 {VMULEUB, 0xfc0007ff00000000, 0x1000020800000000, 0x0, // Vector Multiply Even Unsigned Byte VX-form (vmuleub VRT,VRA,VRB) 4871 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4872 {VMULEUH, 0xfc0007ff00000000, 0x1000024800000000, 0x0, // Vector Multiply Even Unsigned Halfword VX-form (vmuleuh VRT,VRA,VRB) 4873 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4874 {VMULOSB, 0xfc0007ff00000000, 0x1000010800000000, 0x0, // Vector Multiply Odd Signed Byte VX-form (vmulosb VRT,VRA,VRB) 4875 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4876 {VMULOSH, 0xfc0007ff00000000, 0x1000014800000000, 0x0, // Vector Multiply Odd Signed Halfword VX-form (vmulosh VRT,VRA,VRB) 4877 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4878 {VMULOUB, 0xfc0007ff00000000, 0x1000000800000000, 0x0, // Vector Multiply Odd Unsigned Byte VX-form (vmuloub VRT,VRA,VRB) 4879 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4880 {VMULOUH, 0xfc0007ff00000000, 0x1000004800000000, 0x0, // Vector Multiply Odd Unsigned Halfword VX-form (vmulouh VRT,VRA,VRB) 4881 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4882 {VNMSUBFP, 0xfc00003f00000000, 0x1000002f00000000, 0x0, // Vector Negative Multiply-Subtract Floating-Point VA-form (vnmsubfp VRT,VRA,VRC,VRB) 4883 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_21_25, ap_VecReg_16_20}}, 4884 {VNOR, 0xfc0007ff00000000, 0x1000050400000000, 0x0, // Vector Logical NOR VX-form (vnor VRT,VRA,VRB) 4885 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4886 {VOR, 0xfc0007ff00000000, 0x1000048400000000, 0x0, // Vector Logical OR VX-form (vor VRT,VRA,VRB) 4887 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4888 {VPERM, 0xfc00003f00000000, 0x1000002b00000000, 0x0, // Vector Permute VA-form (vperm VRT,VRA,VRB,VRC) 4889 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 4890 {VPKPX, 0xfc0007ff00000000, 0x1000030e00000000, 0x0, // Vector Pack Pixel VX-form (vpkpx VRT,VRA,VRB) 4891 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4892 {VPKSHSS, 0xfc0007ff00000000, 0x1000018e00000000, 0x0, // Vector Pack Signed Halfword Signed Saturate VX-form (vpkshss VRT,VRA,VRB) 4893 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4894 {VPKSHUS, 0xfc0007ff00000000, 0x1000010e00000000, 0x0, // Vector Pack Signed Halfword Unsigned Saturate VX-form (vpkshus VRT,VRA,VRB) 4895 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4896 {VPKSWSS, 0xfc0007ff00000000, 0x100001ce00000000, 0x0, // Vector Pack Signed Word Signed Saturate VX-form (vpkswss VRT,VRA,VRB) 4897 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4898 {VPKSWUS, 0xfc0007ff00000000, 0x1000014e00000000, 0x0, // Vector Pack Signed Word Unsigned Saturate VX-form (vpkswus VRT,VRA,VRB) 4899 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4900 {VPKUHUM, 0xfc0007ff00000000, 0x1000000e00000000, 0x0, // Vector Pack Unsigned Halfword Unsigned Modulo VX-form (vpkuhum VRT,VRA,VRB) 4901 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4902 {VPKUHUS, 0xfc0007ff00000000, 0x1000008e00000000, 0x0, // Vector Pack Unsigned Halfword Unsigned Saturate VX-form (vpkuhus VRT,VRA,VRB) 4903 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4904 {VPKUWUM, 0xfc0007ff00000000, 0x1000004e00000000, 0x0, // Vector Pack Unsigned Word Unsigned Modulo VX-form (vpkuwum VRT,VRA,VRB) 4905 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4906 {VPKUWUS, 0xfc0007ff00000000, 0x100000ce00000000, 0x0, // Vector Pack Unsigned Word Unsigned Saturate VX-form (vpkuwus VRT,VRA,VRB) 4907 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4908 {VREFP, 0xfc0007ff00000000, 0x1000010a00000000, 0x1f000000000000, // Vector Reciprocal Estimate Floating-Point VX-form (vrefp VRT,VRB) 4909 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4910 {VRFIM, 0xfc0007ff00000000, 0x100002ca00000000, 0x1f000000000000, // Vector Round to Floating-Point Integer toward -Infinity VX-form (vrfim VRT,VRB) 4911 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4912 {VRFIN, 0xfc0007ff00000000, 0x1000020a00000000, 0x1f000000000000, // Vector Round to Floating-Point Integer Nearest VX-form (vrfin VRT,VRB) 4913 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4914 {VRFIP, 0xfc0007ff00000000, 0x1000028a00000000, 0x1f000000000000, // Vector Round to Floating-Point Integer toward +Infinity VX-form (vrfip VRT,VRB) 4915 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4916 {VRFIZ, 0xfc0007ff00000000, 0x1000024a00000000, 0x1f000000000000, // Vector Round to Floating-Point Integer toward Zero VX-form (vrfiz VRT,VRB) 4917 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4918 {VRLB, 0xfc0007ff00000000, 0x1000000400000000, 0x0, // Vector Rotate Left Byte VX-form (vrlb VRT,VRA,VRB) 4919 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4920 {VRLH, 0xfc0007ff00000000, 0x1000004400000000, 0x0, // Vector Rotate Left Halfword VX-form (vrlh VRT,VRA,VRB) 4921 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4922 {VRLW, 0xfc0007ff00000000, 0x1000008400000000, 0x0, // Vector Rotate Left Word VX-form (vrlw VRT,VRA,VRB) 4923 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4924 {VRSQRTEFP, 0xfc0007ff00000000, 0x1000014a00000000, 0x1f000000000000, // Vector Reciprocal Square Root Estimate Floating-Point VX-form (vrsqrtefp VRT,VRB) 4925 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4926 {VSEL, 0xfc00003f00000000, 0x1000002a00000000, 0x0, // Vector Select VA-form (vsel VRT,VRA,VRB,VRC) 4927 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 4928 {VSL, 0xfc0007ff00000000, 0x100001c400000000, 0x0, // Vector Shift Left VX-form (vsl VRT,VRA,VRB) 4929 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4930 {VSLB, 0xfc0007ff00000000, 0x1000010400000000, 0x0, // Vector Shift Left Byte VX-form (vslb VRT,VRA,VRB) 4931 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4932 {VSLDOI, 0xfc00003f00000000, 0x1000002c00000000, 0x40000000000, // Vector Shift Left Double by Octet Immediate VA-form (vsldoi VRT,VRA,VRB,SHB) 4933 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_25}}, 4934 {VSLH, 0xfc0007ff00000000, 0x1000014400000000, 0x0, // Vector Shift Left Halfword VX-form (vslh VRT,VRA,VRB) 4935 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4936 {VSLO, 0xfc0007ff00000000, 0x1000040c00000000, 0x0, // Vector Shift Left by Octet VX-form (vslo VRT,VRA,VRB) 4937 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4938 {VSLW, 0xfc0007ff00000000, 0x1000018400000000, 0x0, // Vector Shift Left Word VX-form (vslw VRT,VRA,VRB) 4939 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4940 {VSPLTB, 0xfc0007ff00000000, 0x1000020c00000000, 0x10000000000000, // Vector Splat Byte VX-form (vspltb VRT,VRB,UIM) 4941 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}}, 4942 {VSPLTH, 0xfc0007ff00000000, 0x1000024c00000000, 0x18000000000000, // Vector Splat Halfword VX-form (vsplth VRT,VRB,UIM) 4943 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_13_15}}, 4944 {VSPLTISB, 0xfc0007ff00000000, 0x1000030c00000000, 0xf80000000000, // Vector Splat Immediate Signed Byte VX-form (vspltisb VRT,SIM) 4945 [6]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}}, 4946 {VSPLTISH, 0xfc0007ff00000000, 0x1000034c00000000, 0xf80000000000, // Vector Splat Immediate Signed Halfword VX-form (vspltish VRT,SIM) 4947 [6]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}}, 4948 {VSPLTISW, 0xfc0007ff00000000, 0x1000038c00000000, 0xf80000000000, // Vector Splat Immediate Signed Word VX-form (vspltisw VRT,SIM) 4949 [6]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}}, 4950 {VSPLTW, 0xfc0007ff00000000, 0x1000028c00000000, 0x1c000000000000, // Vector Splat Word VX-form (vspltw VRT,VRB,UIM) 4951 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_14_15}}, 4952 {VSR, 0xfc0007ff00000000, 0x100002c400000000, 0x0, // Vector Shift Right VX-form (vsr VRT,VRA,VRB) 4953 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4954 {VSRAB, 0xfc0007ff00000000, 0x1000030400000000, 0x0, // Vector Shift Right Algebraic Byte VX-form (vsrab VRT,VRA,VRB) 4955 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4956 {VSRAH, 0xfc0007ff00000000, 0x1000034400000000, 0x0, // Vector Shift Right Algebraic Halfword VX-form (vsrah VRT,VRA,VRB) 4957 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4958 {VSRAW, 0xfc0007ff00000000, 0x1000038400000000, 0x0, // Vector Shift Right Algebraic Word VX-form (vsraw VRT,VRA,VRB) 4959 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4960 {VSRB, 0xfc0007ff00000000, 0x1000020400000000, 0x0, // Vector Shift Right Byte VX-form (vsrb VRT,VRA,VRB) 4961 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4962 {VSRH, 0xfc0007ff00000000, 0x1000024400000000, 0x0, // Vector Shift Right Halfword VX-form (vsrh VRT,VRA,VRB) 4963 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4964 {VSRO, 0xfc0007ff00000000, 0x1000044c00000000, 0x0, // Vector Shift Right by Octet VX-form (vsro VRT,VRA,VRB) 4965 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4966 {VSRW, 0xfc0007ff00000000, 0x1000028400000000, 0x0, // Vector Shift Right Word VX-form (vsrw VRT,VRA,VRB) 4967 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4968 {VSUBCUW, 0xfc0007ff00000000, 0x1000058000000000, 0x0, // Vector Subtract & Write Carry-out Unsigned Word VX-form (vsubcuw VRT,VRA,VRB) 4969 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4970 {VSUBFP, 0xfc0007ff00000000, 0x1000004a00000000, 0x0, // Vector Subtract Floating-Point VX-form (vsubfp VRT,VRA,VRB) 4971 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4972 {VSUBSBS, 0xfc0007ff00000000, 0x1000070000000000, 0x0, // Vector Subtract Signed Byte Saturate VX-form (vsubsbs VRT,VRA,VRB) 4973 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4974 {VSUBSHS, 0xfc0007ff00000000, 0x1000074000000000, 0x0, // Vector Subtract Signed Halfword Saturate VX-form (vsubshs VRT,VRA,VRB) 4975 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4976 {VSUBSWS, 0xfc0007ff00000000, 0x1000078000000000, 0x0, // Vector Subtract Signed Word Saturate VX-form (vsubsws VRT,VRA,VRB) 4977 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4978 {VSUBUBM, 0xfc0007ff00000000, 0x1000040000000000, 0x0, // Vector Subtract Unsigned Byte Modulo VX-form (vsububm VRT,VRA,VRB) 4979 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4980 {VSUBUBS, 0xfc0007ff00000000, 0x1000060000000000, 0x0, // Vector Subtract Unsigned Byte Saturate VX-form (vsububs VRT,VRA,VRB) 4981 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4982 {VSUBUHM, 0xfc0007ff00000000, 0x1000044000000000, 0x0, // Vector Subtract Unsigned Halfword Modulo VX-form (vsubuhm VRT,VRA,VRB) 4983 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4984 {VSUBUHS, 0xfc0007ff00000000, 0x1000064000000000, 0x0, // Vector Subtract Unsigned Halfword Saturate VX-form (vsubuhs VRT,VRA,VRB) 4985 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4986 {VSUBUWM, 0xfc0007ff00000000, 0x1000048000000000, 0x0, // Vector Subtract Unsigned Word Modulo VX-form (vsubuwm VRT,VRA,VRB) 4987 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4988 {VSUBUWS, 0xfc0007ff00000000, 0x1000068000000000, 0x0, // Vector Subtract Unsigned Word Saturate VX-form (vsubuws VRT,VRA,VRB) 4989 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4990 {VSUM2SWS, 0xfc0007ff00000000, 0x1000068800000000, 0x0, // Vector Sum across Half Signed Word Saturate VX-form (vsum2sws VRT,VRA,VRB) 4991 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4992 {VSUM4SBS, 0xfc0007ff00000000, 0x1000070800000000, 0x0, // Vector Sum across Quarter Signed Byte Saturate VX-form (vsum4sbs VRT,VRA,VRB) 4993 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4994 {VSUM4SHS, 0xfc0007ff00000000, 0x1000064800000000, 0x0, // Vector Sum across Quarter Signed Halfword Saturate VX-form (vsum4shs VRT,VRA,VRB) 4995 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4996 {VSUM4UBS, 0xfc0007ff00000000, 0x1000060800000000, 0x0, // Vector Sum across Quarter Unsigned Byte Saturate VX-form (vsum4ubs VRT,VRA,VRB) 4997 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4998 {VSUMSWS, 0xfc0007ff00000000, 0x1000078800000000, 0x0, // Vector Sum across Signed Word Saturate VX-form (vsumsws VRT,VRA,VRB) 4999 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 5000 {VUPKHPX, 0xfc0007ff00000000, 0x1000034e00000000, 0x1f000000000000, // Vector Unpack High Pixel VX-form (vupkhpx VRT,VRB) 5001 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 5002 {VUPKHSB, 0xfc0007ff00000000, 0x1000020e00000000, 0x1f000000000000, // Vector Unpack High Signed Byte VX-form (vupkhsb VRT,VRB) 5003 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 5004 {VUPKHSH, 0xfc0007ff00000000, 0x1000024e00000000, 0x1f000000000000, // Vector Unpack High Signed Halfword VX-form (vupkhsh VRT,VRB) 5005 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 5006 {VUPKLPX, 0xfc0007ff00000000, 0x100003ce00000000, 0x1f000000000000, // Vector Unpack Low Pixel VX-form (vupklpx VRT,VRB) 5007 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 5008 {VUPKLSB, 0xfc0007ff00000000, 0x1000028e00000000, 0x1f000000000000, // Vector Unpack Low Signed Byte VX-form (vupklsb VRT,VRB) 5009 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 5010 {VUPKLSH, 0xfc0007ff00000000, 0x100002ce00000000, 0x1f000000000000, // Vector Unpack Low Signed Halfword VX-form (vupklsh VRT,VRB) 5011 [6]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 5012 {VXOR, 0xfc0007ff00000000, 0x100004c400000000, 0x0, // Vector Logical XOR VX-form (vxor VRT,VRA,VRB) 5013 [6]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 5014 {FRE, 0xfc00003f00000000, 0xfc00003000000000, 0x1f07c000000000, // Floating Reciprocal Estimate A-form (fre FRT,FRB) 5015 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5016 {FRECC, 0xfc00003f00000000, 0xfc00003100000000, 0x1f07c000000000, // Floating Reciprocal Estimate A-form (fre. FRT,FRB) 5017 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5018 {FRIM, 0xfc0007ff00000000, 0xfc0003d000000000, 0x1f000000000000, // Floating Round to Integer Minus X-form (frim FRT,FRB) 5019 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5020 {FRIMCC, 0xfc0007ff00000000, 0xfc0003d100000000, 0x1f000000000000, // Floating Round to Integer Minus X-form (frim. FRT,FRB) 5021 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5022 {FRIN, 0xfc0007ff00000000, 0xfc00031000000000, 0x1f000000000000, // Floating Round to Integer Nearest X-form (frin FRT,FRB) 5023 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5024 {FRINCC, 0xfc0007ff00000000, 0xfc00031100000000, 0x1f000000000000, // Floating Round to Integer Nearest X-form (frin. FRT,FRB) 5025 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5026 {FRIP, 0xfc0007ff00000000, 0xfc00039000000000, 0x1f000000000000, // Floating Round to Integer Plus X-form (frip FRT,FRB) 5027 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5028 {FRIPCC, 0xfc0007ff00000000, 0xfc00039100000000, 0x1f000000000000, // Floating Round to Integer Plus X-form (frip. FRT,FRB) 5029 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5030 {FRIZ, 0xfc0007ff00000000, 0xfc00035000000000, 0x1f000000000000, // Floating Round to Integer Toward Zero X-form (friz FRT,FRB) 5031 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5032 {FRIZCC, 0xfc0007ff00000000, 0xfc00035100000000, 0x1f000000000000, // Floating Round to Integer Toward Zero X-form (friz. FRT,FRB) 5033 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5034 {FRSQRTES, 0xfc00003f00000000, 0xec00003400000000, 0x1f07c000000000, // Floating Reciprocal Square Root Estimate Single A-form (frsqrtes FRT,FRB) 5035 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5036 {FRSQRTESCC, 0xfc00003f00000000, 0xec00003500000000, 0x1f07c000000000, // Floating Reciprocal Square Root Estimate Single A-form (frsqrtes. FRT,FRB) 5037 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5038 {HRFID, 0xfc0007fe00000000, 0x4c00022400000000, 0x3fff80100000000, // Return From Interrupt Doubleword Hypervisor XL-form (hrfid) 5039 [6]*argField{}}, 5040 {POPCNTB, 0xfc0007fe00000000, 0x7c0000f400000000, 0xf80100000000, // Population Count Bytes X-form (popcntb RA, RS) 5041 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 5042 {MFOCRF, 0xfc1007fe00000000, 0x7c10002600000000, 0x80100000000, // Move From One Condition Register Field XFX-form (mfocrf RT,FXM) 5043 [6]*argField{ap_Reg_6_10, ap_ImmUnsigned_12_19}}, 5044 {MTOCRF, 0xfc1007fe00000000, 0x7c10012000000000, 0x80100000000, // Move To One Condition Register Field XFX-form (mtocrf FXM,RS) 5045 [6]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}}, 5046 {SLBMFEE, 0xfc0007fe00000000, 0x7c00072600000000, 0x1e000100000000, // SLB Move From Entry ESID X-form (slbmfee RT,RB) 5047 [6]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 5048 {SLBMFEV, 0xfc0007fe00000000, 0x7c0006a600000000, 0x1e000100000000, // SLB Move From Entry VSID X-form (slbmfev RT,RB) 5049 [6]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 5050 {SLBMTE, 0xfc0007fe00000000, 0x7c00032400000000, 0x1f000100000000, // SLB Move To Entry X-form (slbmte RS,RB) 5051 [6]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 5052 {RFSCV, 0xfc0007fe00000000, 0x4c0000a400000000, 0x3fff80100000000, // Return From System Call Vectored XL-form (rfscv) 5053 [6]*argField{}}, 5054 {SCV, 0xfc00000300000000, 0x4400000100000000, 0x3fff01c00000000, // System Call Vectored SC-form (scv LEV) 5055 [6]*argField{ap_ImmUnsigned_20_26}}, 5056 {LQ, 0xfc00000000000000, 0xe000000000000000, 0xf00000000, // Load Quadword DQ-form (lq RTp,DQ(RA)) 5057 [6]*argField{ap_Reg_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}}, 5058 {STQ, 0xfc00000300000000, 0xf800000200000000, 0x0, // Store Quadword DS-form (stq RSp,DS(RA)) 5059 [6]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, 5060 {CNTLZD, 0xfc0007ff00000000, 0x7c00007400000000, 0xf80000000000, // Count Leading Zeros Doubleword X-form (cntlzd RA,RS) 5061 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 5062 {CNTLZDCC, 0xfc0007ff00000000, 0x7c00007500000000, 0xf80000000000, // Count Leading Zeros Doubleword X-form (cntlzd. RA,RS) 5063 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 5064 {DCBF, 0xfc0007fe00000000, 0x7c0000ac00000000, 0x300000100000000, // Data Cache Block Flush X-form (dcbf RA,RB,L) 5065 [6]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_8_10}}, 5066 {DCBST, 0xfc0007fe00000000, 0x7c00006c00000000, 0x3e0000100000000, // Data Cache Block Store X-form (dcbst RA,RB) 5067 [6]*argField{ap_Reg_11_15, ap_Reg_16_20}}, 5068 {DCBT, 0xfc0007fe00000000, 0x7c00022c00000000, 0x100000000, // Data Cache Block Touch X-form (dcbt RA,RB,TH) 5069 [6]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_6_10}}, 5070 {DCBTST, 0xfc0007fe00000000, 0x7c0001ec00000000, 0x100000000, // Data Cache Block Touch for Store X-form (dcbtst RA,RB,TH) 5071 [6]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_6_10}}, 5072 {DIVD, 0xfc0007ff00000000, 0x7c0003d200000000, 0x0, // Divide Doubleword XO-form (divd RT,RA,RB) 5073 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5074 {DIVDCC, 0xfc0007ff00000000, 0x7c0003d300000000, 0x0, // Divide Doubleword XO-form (divd. RT,RA,RB) 5075 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5076 {DIVDO, 0xfc0007ff00000000, 0x7c0007d200000000, 0x0, // Divide Doubleword XO-form (divdo RT,RA,RB) 5077 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5078 {DIVDOCC, 0xfc0007ff00000000, 0x7c0007d300000000, 0x0, // Divide Doubleword XO-form (divdo. RT,RA,RB) 5079 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5080 {DIVDU, 0xfc0007ff00000000, 0x7c00039200000000, 0x0, // Divide Doubleword Unsigned XO-form (divdu RT,RA,RB) 5081 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5082 {DIVDUCC, 0xfc0007ff00000000, 0x7c00039300000000, 0x0, // Divide Doubleword Unsigned XO-form (divdu. RT,RA,RB) 5083 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5084 {DIVDUO, 0xfc0007ff00000000, 0x7c00079200000000, 0x0, // Divide Doubleword Unsigned XO-form (divduo RT,RA,RB) 5085 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5086 {DIVDUOCC, 0xfc0007ff00000000, 0x7c00079300000000, 0x0, // Divide Doubleword Unsigned XO-form (divduo. RT,RA,RB) 5087 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5088 {DIVW, 0xfc0007ff00000000, 0x7c0003d600000000, 0x0, // Divide Word XO-form (divw RT,RA,RB) 5089 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5090 {DIVWCC, 0xfc0007ff00000000, 0x7c0003d700000000, 0x0, // Divide Word XO-form (divw. RT,RA,RB) 5091 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5092 {DIVWO, 0xfc0007ff00000000, 0x7c0007d600000000, 0x0, // Divide Word XO-form (divwo RT,RA,RB) 5093 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5094 {DIVWOCC, 0xfc0007ff00000000, 0x7c0007d700000000, 0x0, // Divide Word XO-form (divwo. RT,RA,RB) 5095 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5096 {DIVWU, 0xfc0007ff00000000, 0x7c00039600000000, 0x0, // Divide Word Unsigned XO-form (divwu RT,RA,RB) 5097 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5098 {DIVWUCC, 0xfc0007ff00000000, 0x7c00039700000000, 0x0, // Divide Word Unsigned XO-form (divwu. RT,RA,RB) 5099 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5100 {DIVWUO, 0xfc0007ff00000000, 0x7c00079600000000, 0x0, // Divide Word Unsigned XO-form (divwuo RT,RA,RB) 5101 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5102 {DIVWUOCC, 0xfc0007ff00000000, 0x7c00079700000000, 0x0, // Divide Word Unsigned XO-form (divwuo. RT,RA,RB) 5103 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5104 {EIEIO, 0xfc0007fe00000000, 0x7c0006ac00000000, 0x3fff80100000000, // Enforce In-order Execution of I/O X-form (eieio) 5105 [6]*argField{}}, 5106 {EXTSB, 0xfc0007ff00000000, 0x7c00077400000000, 0xf80000000000, // Extend Sign Byte X-form (extsb RA,RS) 5107 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 5108 {EXTSBCC, 0xfc0007ff00000000, 0x7c00077500000000, 0xf80000000000, // Extend Sign Byte X-form (extsb. RA,RS) 5109 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 5110 {EXTSW, 0xfc0007ff00000000, 0x7c0007b400000000, 0xf80000000000, // Extend Sign Word X-form (extsw RA,RS) 5111 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 5112 {EXTSWCC, 0xfc0007ff00000000, 0x7c0007b500000000, 0xf80000000000, // Extend Sign Word X-form (extsw. RA,RS) 5113 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 5114 {FADDS, 0xfc00003f00000000, 0xec00002a00000000, 0x7c000000000, // Floating Add Single A-form (fadds FRT,FRA,FRB) 5115 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 5116 {FADDSCC, 0xfc00003f00000000, 0xec00002b00000000, 0x7c000000000, // Floating Add Single A-form (fadds. FRT,FRA,FRB) 5117 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 5118 {FCFID, 0xfc0007ff00000000, 0xfc00069c00000000, 0x1f000000000000, // Floating Convert with round Signed Doubleword to Double-Precision format X-form (fcfid FRT,FRB) 5119 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5120 {FCFIDCC, 0xfc0007ff00000000, 0xfc00069d00000000, 0x1f000000000000, // Floating Convert with round Signed Doubleword to Double-Precision format X-form (fcfid. FRT,FRB) 5121 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5122 {FCTID, 0xfc0007ff00000000, 0xfc00065c00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Signed Doubleword format X-form (fctid FRT,FRB) 5123 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5124 {FCTIDCC, 0xfc0007ff00000000, 0xfc00065d00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Signed Doubleword format X-form (fctid. FRT,FRB) 5125 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5126 {FCTIDZ, 0xfc0007ff00000000, 0xfc00065e00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Signed Doubleword format X-form (fctidz FRT,FRB) 5127 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5128 {FCTIDZCC, 0xfc0007ff00000000, 0xfc00065f00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Signed Doubleword format X-form (fctidz. FRT,FRB) 5129 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5130 {FDIVS, 0xfc00003f00000000, 0xec00002400000000, 0x7c000000000, // Floating Divide Single A-form (fdivs FRT,FRA,FRB) 5131 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 5132 {FDIVSCC, 0xfc00003f00000000, 0xec00002500000000, 0x7c000000000, // Floating Divide Single A-form (fdivs. FRT,FRA,FRB) 5133 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 5134 {FMADDS, 0xfc00003f00000000, 0xec00003a00000000, 0x0, // Floating Multiply-Add Single A-form (fmadds FRT,FRA,FRC,FRB) 5135 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 5136 {FMADDSCC, 0xfc00003f00000000, 0xec00003b00000000, 0x0, // Floating Multiply-Add Single A-form (fmadds. FRT,FRA,FRC,FRB) 5137 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 5138 {FMSUBS, 0xfc00003f00000000, 0xec00003800000000, 0x0, // Floating Multiply-Subtract Single A-form (fmsubs FRT,FRA,FRC,FRB) 5139 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 5140 {FMSUBSCC, 0xfc00003f00000000, 0xec00003900000000, 0x0, // Floating Multiply-Subtract Single A-form (fmsubs. FRT,FRA,FRC,FRB) 5141 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 5142 {FMULS, 0xfc00003f00000000, 0xec00003200000000, 0xf80000000000, // Floating Multiply Single A-form (fmuls FRT,FRA,FRC) 5143 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}}, 5144 {FMULSCC, 0xfc00003f00000000, 0xec00003300000000, 0xf80000000000, // Floating Multiply Single A-form (fmuls. FRT,FRA,FRC) 5145 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}}, 5146 {FNMADDS, 0xfc00003f00000000, 0xec00003e00000000, 0x0, // Floating Negative Multiply-Add Single A-form (fnmadds FRT,FRA,FRC,FRB) 5147 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 5148 {FNMADDSCC, 0xfc00003f00000000, 0xec00003f00000000, 0x0, // Floating Negative Multiply-Add Single A-form (fnmadds. FRT,FRA,FRC,FRB) 5149 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 5150 {FNMSUBS, 0xfc00003f00000000, 0xec00003c00000000, 0x0, // Floating Negative Multiply-Subtract Single A-form (fnmsubs FRT,FRA,FRC,FRB) 5151 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 5152 {FNMSUBSCC, 0xfc00003f00000000, 0xec00003d00000000, 0x0, // Floating Negative Multiply-Subtract Single A-form (fnmsubs. FRT,FRA,FRC,FRB) 5153 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 5154 {FRES, 0xfc00003f00000000, 0xec00003000000000, 0x1f07c000000000, // Floating Reciprocal Estimate Single A-form (fres FRT,FRB) 5155 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5156 {FRESCC, 0xfc00003f00000000, 0xec00003100000000, 0x1f07c000000000, // Floating Reciprocal Estimate Single A-form (fres. FRT,FRB) 5157 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5158 {FRSQRTE, 0xfc00003f00000000, 0xfc00003400000000, 0x1f07c000000000, // Floating Reciprocal Square Root Estimate A-form (frsqrte FRT,FRB) 5159 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5160 {FRSQRTECC, 0xfc00003f00000000, 0xfc00003500000000, 0x1f07c000000000, // Floating Reciprocal Square Root Estimate A-form (frsqrte. FRT,FRB) 5161 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5162 {FSEL, 0xfc00003f00000000, 0xfc00002e00000000, 0x0, // Floating Select A-form (fsel FRT,FRA,FRC,FRB) 5163 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 5164 {FSELCC, 0xfc00003f00000000, 0xfc00002f00000000, 0x0, // Floating Select A-form (fsel. FRT,FRA,FRC,FRB) 5165 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 5166 {FSQRTS, 0xfc00003f00000000, 0xec00002c00000000, 0x1f07c000000000, // Floating Square Root Single A-form (fsqrts FRT,FRB) 5167 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5168 {FSQRTSCC, 0xfc00003f00000000, 0xec00002d00000000, 0x1f07c000000000, // Floating Square Root Single A-form (fsqrts. FRT,FRB) 5169 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5170 {FSUBS, 0xfc00003f00000000, 0xec00002800000000, 0x7c000000000, // Floating Subtract Single A-form (fsubs FRT,FRA,FRB) 5171 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 5172 {FSUBSCC, 0xfc00003f00000000, 0xec00002900000000, 0x7c000000000, // Floating Subtract Single A-form (fsubs. FRT,FRA,FRB) 5173 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 5174 {ICBI, 0xfc0007fe00000000, 0x7c0007ac00000000, 0x3e0000100000000, // Instruction Cache Block Invalidate X-form (icbi RA,RB) 5175 [6]*argField{ap_Reg_11_15, ap_Reg_16_20}}, 5176 {LD, 0xfc00000300000000, 0xe800000000000000, 0x0, // Load Doubleword DS-form (ld RT,DS(RA)) 5177 [6]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, 5178 {LDARX, 0xfc0007fe00000000, 0x7c0000a800000000, 0x0, // Load Doubleword And Reserve Indexed X-form (ldarx RT,RA,RB,EH) 5179 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}}, 5180 {LDU, 0xfc00000300000000, 0xe800000100000000, 0x0, // Load Doubleword with Update DS-form (ldu RT,DS(RA)) 5181 [6]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, 5182 {LDUX, 0xfc0007fe00000000, 0x7c00006a00000000, 0x100000000, // Load Doubleword with Update Indexed X-form (ldux RT,RA,RB) 5183 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5184 {LDX, 0xfc0007fe00000000, 0x7c00002a00000000, 0x100000000, // Load Doubleword Indexed X-form (ldx RT,RA,RB) 5185 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5186 {LWA, 0xfc00000300000000, 0xe800000200000000, 0x0, // Load Word Algebraic DS-form (lwa RT,DS(RA)) 5187 [6]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, 5188 {LWARX, 0xfc0007fe00000000, 0x7c00002800000000, 0x0, // Load Word & Reserve Indexed X-form (lwarx RT,RA,RB,EH) 5189 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}}, 5190 {LWAUX, 0xfc0007fe00000000, 0x7c0002ea00000000, 0x100000000, // Load Word Algebraic with Update Indexed X-form (lwaux RT,RA,RB) 5191 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5192 {LWAX, 0xfc0007fe00000000, 0x7c0002aa00000000, 0x100000000, // Load Word Algebraic Indexed X-form (lwax RT,RA,RB) 5193 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5194 {MFTB, 0xfc0007fe00000000, 0x7c0002e600000000, 0x100000000, // Move From Time Base XFX-form (mftb RT,TBR) 5195 [6]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}}, 5196 {MTMSRD, 0xfc0007fe00000000, 0x7c00016400000000, 0x1ef80100000000, // Move To MSR Doubleword X-form (mtmsrd RS,L) 5197 [6]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}}, 5198 {MULHD, 0xfc0003ff00000000, 0x7c00009200000000, 0x40000000000, // Multiply High Doubleword XO-form (mulhd RT,RA,RB) 5199 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5200 {MULHDCC, 0xfc0003ff00000000, 0x7c00009300000000, 0x40000000000, // Multiply High Doubleword XO-form (mulhd. RT,RA,RB) 5201 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5202 {MULHDU, 0xfc0003ff00000000, 0x7c00001200000000, 0x40000000000, // Multiply High Doubleword Unsigned XO-form (mulhdu RT,RA,RB) 5203 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5204 {MULHDUCC, 0xfc0003ff00000000, 0x7c00001300000000, 0x40000000000, // Multiply High Doubleword Unsigned XO-form (mulhdu. RT,RA,RB) 5205 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5206 {MULHW, 0xfc0003ff00000000, 0x7c00009600000000, 0x40000000000, // Multiply High Word XO-form (mulhw RT,RA,RB) 5207 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5208 {MULHWCC, 0xfc0003ff00000000, 0x7c00009700000000, 0x40000000000, // Multiply High Word XO-form (mulhw. RT,RA,RB) 5209 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5210 {MULHWU, 0xfc0003ff00000000, 0x7c00001600000000, 0x40000000000, // Multiply High Word Unsigned XO-form (mulhwu RT,RA,RB) 5211 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5212 {MULHWUCC, 0xfc0003ff00000000, 0x7c00001700000000, 0x40000000000, // Multiply High Word Unsigned XO-form (mulhwu. RT,RA,RB) 5213 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5214 {MULLD, 0xfc0007ff00000000, 0x7c0001d200000000, 0x0, // Multiply Low Doubleword XO-form (mulld RT,RA,RB) 5215 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5216 {MULLDCC, 0xfc0007ff00000000, 0x7c0001d300000000, 0x0, // Multiply Low Doubleword XO-form (mulld. RT,RA,RB) 5217 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5218 {MULLDO, 0xfc0007ff00000000, 0x7c0005d200000000, 0x0, // Multiply Low Doubleword XO-form (mulldo RT,RA,RB) 5219 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5220 {MULLDOCC, 0xfc0007ff00000000, 0x7c0005d300000000, 0x0, // Multiply Low Doubleword XO-form (mulldo. RT,RA,RB) 5221 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5222 {RFID, 0xfc0007fe00000000, 0x4c00002400000000, 0x3fff80100000000, // Return from Interrupt Doubleword XL-form (rfid) 5223 [6]*argField{}}, 5224 {RLDCL, 0xfc00001f00000000, 0x7800001000000000, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl RA,RS,RB,MB) 5225 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}}, 5226 {RLDCLCC, 0xfc00001f00000000, 0x7800001100000000, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl. RA,RS,RB,MB) 5227 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}}, 5228 {RLDCR, 0xfc00001f00000000, 0x7800001200000000, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr RA,RS,RB,ME) 5229 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}}, 5230 {RLDCRCC, 0xfc00001f00000000, 0x7800001300000000, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr. RA,RS,RB,ME) 5231 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}}, 5232 {RLDIC, 0xfc00001d00000000, 0x7800000800000000, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic RA,RS,SH,MB) 5233 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, 5234 {RLDICCC, 0xfc00001d00000000, 0x7800000900000000, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic. RA,RS,SH,MB) 5235 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, 5236 {RLDICL, 0xfc00001d00000000, 0x7800000000000000, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl RA,RS,SH,MB) 5237 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, 5238 {RLDICLCC, 0xfc00001d00000000, 0x7800000100000000, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl. RA,RS,SH,MB) 5239 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, 5240 {RLDICR, 0xfc00001d00000000, 0x7800000400000000, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr RA,RS,SH,ME) 5241 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, 5242 {RLDICRCC, 0xfc00001d00000000, 0x7800000500000000, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr. RA,RS,SH,ME) 5243 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, 5244 {RLDIMI, 0xfc00001d00000000, 0x7800000c00000000, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi RA,RS,SH,MB) 5245 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, 5246 {RLDIMICC, 0xfc00001d00000000, 0x7800000d00000000, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi. RA,RS,SH,MB) 5247 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, 5248 {SC, 0xfc00000200000000, 0x4400000200000000, 0x3fff01d00000000, // System Call SC-form (sc LEV) 5249 [6]*argField{ap_ImmUnsigned_20_26}}, 5250 {SLBIA, 0xfc0007fe00000000, 0x7c0003e400000000, 0x31ff80100000000, // SLB Invalidate All X-form (slbia IH) 5251 [6]*argField{ap_ImmUnsigned_8_10}}, 5252 {SLBIE, 0xfc0007fe00000000, 0x7c00036400000000, 0x3ff000100000000, // SLB Invalidate Entry X-form (slbie RB) 5253 [6]*argField{ap_Reg_16_20}}, 5254 {SLD, 0xfc0007ff00000000, 0x7c00003600000000, 0x0, // Shift Left Doubleword X-form (sld RA,RS,RB) 5255 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5256 {SLDCC, 0xfc0007ff00000000, 0x7c00003700000000, 0x0, // Shift Left Doubleword X-form (sld. RA,RS,RB) 5257 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5258 {SRAD, 0xfc0007ff00000000, 0x7c00063400000000, 0x0, // Shift Right Algebraic Doubleword X-form (srad RA,RS,RB) 5259 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5260 {SRADCC, 0xfc0007ff00000000, 0x7c00063500000000, 0x0, // Shift Right Algebraic Doubleword X-form (srad. RA,RS,RB) 5261 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5262 {SRADI, 0xfc0007fd00000000, 0x7c00067400000000, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi RA,RS,SH) 5263 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}}, 5264 {SRADICC, 0xfc0007fd00000000, 0x7c00067500000000, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi. RA,RS,SH) 5265 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}}, 5266 {SRD, 0xfc0007ff00000000, 0x7c00043600000000, 0x0, // Shift Right Doubleword X-form (srd RA,RS,RB) 5267 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5268 {SRDCC, 0xfc0007ff00000000, 0x7c00043700000000, 0x0, // Shift Right Doubleword X-form (srd. RA,RS,RB) 5269 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5270 {STD, 0xfc00000300000000, 0xf800000000000000, 0x0, // Store Doubleword DS-form (std RS,DS(RA)) 5271 [6]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, 5272 {STDCXCC, 0xfc0007ff00000000, 0x7c0001ad00000000, 0x0, // Store Doubleword Conditional Indexed X-form (stdcx. RS,RA,RB) 5273 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5274 {STDU, 0xfc00000300000000, 0xf800000100000000, 0x0, // Store Doubleword with Update DS-form (stdu RS,DS(RA)) 5275 [6]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, 5276 {STDUX, 0xfc0007fe00000000, 0x7c00016a00000000, 0x100000000, // Store Doubleword with Update Indexed X-form (stdux RS,RA,RB) 5277 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5278 {STDX, 0xfc0007fe00000000, 0x7c00012a00000000, 0x100000000, // Store Doubleword Indexed X-form (stdx RS,RA,RB) 5279 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5280 {STFIWX, 0xfc0007fe00000000, 0x7c0007ae00000000, 0x100000000, // Store Floating-Point as Integer Word Indexed X-form (stfiwx FRS,RA,RB) 5281 [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5282 {STWCXCC, 0xfc0007ff00000000, 0x7c00012d00000000, 0x0, // Store Word Conditional Indexed X-form (stwcx. RS,RA,RB) 5283 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5284 {SUBF, 0xfc0007ff00000000, 0x7c00005000000000, 0x0, // Subtract From XO-form (subf RT,RA,RB) 5285 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5286 {SUBFCC, 0xfc0007ff00000000, 0x7c00005100000000, 0x0, // Subtract From XO-form (subf. RT,RA,RB) 5287 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5288 {SUBFO, 0xfc0007ff00000000, 0x7c00045000000000, 0x0, // Subtract From XO-form (subfo RT,RA,RB) 5289 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5290 {SUBFOCC, 0xfc0007ff00000000, 0x7c00045100000000, 0x0, // Subtract From XO-form (subfo. RT,RA,RB) 5291 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5292 {TD, 0xfc0007fe00000000, 0x7c00008800000000, 0x100000000, // Trap Doubleword X-form (td TO,RA,RB) 5293 [6]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5294 {TDI, 0xfc00000000000000, 0x800000000000000, 0x0, // Trap Doubleword Immediate D-form (tdi TO,RA,SI) 5295 [6]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, 5296 {TLBSYNC, 0xfc0007fe00000000, 0x7c00046c00000000, 0x3fff80100000000, // TLB Synchronize X-form (tlbsync) 5297 [6]*argField{}}, 5298 {FCTIW, 0xfc0007ff00000000, 0xfc00001c00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Signed Word format X-form (fctiw FRT,FRB) 5299 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5300 {FCTIWCC, 0xfc0007ff00000000, 0xfc00001d00000000, 0x1f000000000000, // Floating Convert with round Double-Precision To Signed Word format X-form (fctiw. FRT,FRB) 5301 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5302 {FCTIWZ, 0xfc0007ff00000000, 0xfc00001e00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Signed Word fomat X-form (fctiwz FRT,FRB) 5303 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5304 {FCTIWZCC, 0xfc0007ff00000000, 0xfc00001f00000000, 0x1f000000000000, // Floating Convert with truncate Double-Precision To Signed Word fomat X-form (fctiwz. FRT,FRB) 5305 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5306 {FSQRT, 0xfc00003f00000000, 0xfc00002c00000000, 0x1f07c000000000, // Floating Square Root A-form (fsqrt FRT,FRB) 5307 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5308 {FSQRTCC, 0xfc00003f00000000, 0xfc00002d00000000, 0x1f07c000000000, // Floating Square Root A-form (fsqrt. FRT,FRB) 5309 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5310 {ADD, 0xfc0007ff00000000, 0x7c00021400000000, 0x0, // Add XO-form (add RT,RA,RB) 5311 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5312 {ADDCC, 0xfc0007ff00000000, 0x7c00021500000000, 0x0, // Add XO-form (add. RT,RA,RB) 5313 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5314 {ADDO, 0xfc0007ff00000000, 0x7c00061400000000, 0x0, // Add XO-form (addo RT,RA,RB) 5315 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5316 {ADDOCC, 0xfc0007ff00000000, 0x7c00061500000000, 0x0, // Add XO-form (addo. RT,RA,RB) 5317 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5318 {ADDC, 0xfc0007ff00000000, 0x7c00001400000000, 0x0, // Add Carrying XO-form (addc RT,RA,RB) 5319 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5320 {ADDCCC, 0xfc0007ff00000000, 0x7c00001500000000, 0x0, // Add Carrying XO-form (addc. RT,RA,RB) 5321 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5322 {ADDCO, 0xfc0007ff00000000, 0x7c00041400000000, 0x0, // Add Carrying XO-form (addco RT,RA,RB) 5323 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5324 {ADDCOCC, 0xfc0007ff00000000, 0x7c00041500000000, 0x0, // Add Carrying XO-form (addco. RT,RA,RB) 5325 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5326 {ADDE, 0xfc0007ff00000000, 0x7c00011400000000, 0x0, // Add Extended XO-form (adde RT,RA,RB) 5327 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5328 {ADDECC, 0xfc0007ff00000000, 0x7c00011500000000, 0x0, // Add Extended XO-form (adde. RT,RA,RB) 5329 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5330 {ADDEO, 0xfc0007ff00000000, 0x7c00051400000000, 0x0, // Add Extended XO-form (addeo RT,RA,RB) 5331 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5332 {ADDEOCC, 0xfc0007ff00000000, 0x7c00051500000000, 0x0, // Add Extended XO-form (addeo. RT,RA,RB) 5333 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5334 {LI, 0xfc1f000000000000, 0x3800000000000000, 0x0, // Add Immediate D-form (li RT,SI) 5335 [6]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}}, 5336 {ADDI, 0xfc00000000000000, 0x3800000000000000, 0x0, // Add Immediate D-form (addi RT,RA,SI) 5337 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, 5338 {ADDIC, 0xfc00000000000000, 0x3000000000000000, 0x0, // Add Immediate Carrying D-formy (addic RT,RA,SI) 5339 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, 5340 {ADDICCC, 0xfc00000000000000, 0x3400000000000000, 0x0, // Add Immediate Carrying and Record D-form (addic. RT,RA,SI) 5341 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, 5342 {LIS, 0xfc1f000000000000, 0x3c00000000000000, 0x0, // Add Immediate Shifted D-form (lis RT,SI) 5343 [6]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}}, 5344 {ADDIS, 0xfc00000000000000, 0x3c00000000000000, 0x0, // Add Immediate Shifted D-form (addis RT,RA,SI) 5345 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, 5346 {ADDME, 0xfc0007ff00000000, 0x7c0001d400000000, 0xf80000000000, // Add to Minus One Extended XO-form (addme RT,RA) 5347 [6]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 5348 {ADDMECC, 0xfc0007ff00000000, 0x7c0001d500000000, 0xf80000000000, // Add to Minus One Extended XO-form (addme. RT,RA) 5349 [6]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 5350 {ADDMEO, 0xfc0007ff00000000, 0x7c0005d400000000, 0xf80000000000, // Add to Minus One Extended XO-form (addmeo RT,RA) 5351 [6]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 5352 {ADDMEOCC, 0xfc0007ff00000000, 0x7c0005d500000000, 0xf80000000000, // Add to Minus One Extended XO-form (addmeo. RT,RA) 5353 [6]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 5354 {ADDZE, 0xfc0007ff00000000, 0x7c00019400000000, 0xf80000000000, // Add to Zero Extended XO-form (addze RT,RA) 5355 [6]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 5356 {ADDZECC, 0xfc0007ff00000000, 0x7c00019500000000, 0xf80000000000, // Add to Zero Extended XO-form (addze. RT,RA) 5357 [6]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 5358 {ADDZEO, 0xfc0007ff00000000, 0x7c00059400000000, 0xf80000000000, // Add to Zero Extended XO-form (addzeo RT,RA) 5359 [6]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 5360 {ADDZEOCC, 0xfc0007ff00000000, 0x7c00059500000000, 0xf80000000000, // Add to Zero Extended XO-form (addzeo. RT,RA) 5361 [6]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 5362 {AND, 0xfc0007ff00000000, 0x7c00003800000000, 0x0, // AND X-form (and RA,RS,RB) 5363 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5364 {ANDCC, 0xfc0007ff00000000, 0x7c00003900000000, 0x0, // AND X-form (and. RA,RS,RB) 5365 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5366 {ANDC, 0xfc0007ff00000000, 0x7c00007800000000, 0x0, // AND with Complement X-form (andc RA,RS,RB) 5367 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5368 {ANDCCC, 0xfc0007ff00000000, 0x7c00007900000000, 0x0, // AND with Complement X-form (andc. RA,RS,RB) 5369 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5370 {ANDICC, 0xfc00000000000000, 0x7000000000000000, 0x0, // AND Immediate D-form (andi. RA,RS,UI) 5371 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, 5372 {ANDISCC, 0xfc00000000000000, 0x7400000000000000, 0x0, // AND Immediate Shifted D-form (andis. RA,RS,UI) 5373 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, 5374 {B, 0xfc00000300000000, 0x4800000000000000, 0x0, // Branch I-form (b target_addr) 5375 [6]*argField{ap_PCRel_6_29_shift2}}, 5376 {BA, 0xfc00000300000000, 0x4800000200000000, 0x0, // Branch I-form (ba target_addr) 5377 [6]*argField{ap_Label_6_29_shift2}}, 5378 {BL, 0xfc00000300000000, 0x4800000100000000, 0x0, // Branch I-form (bl target_addr) 5379 [6]*argField{ap_PCRel_6_29_shift2}}, 5380 {BLA, 0xfc00000300000000, 0x4800000300000000, 0x0, // Branch I-form (bla target_addr) 5381 [6]*argField{ap_Label_6_29_shift2}}, 5382 {BC, 0xfc00000300000000, 0x4000000000000000, 0x0, // Branch Conditional B-form (bc BO,BI,target_addr) 5383 [6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}}, 5384 {BCA, 0xfc00000300000000, 0x4000000200000000, 0x0, // Branch Conditional B-form (bca BO,BI,target_addr) 5385 [6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}}, 5386 {BCL, 0xfc00000300000000, 0x4000000100000000, 0x0, // Branch Conditional B-form (bcl BO,BI,target_addr) 5387 [6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}}, 5388 {BCLA, 0xfc00000300000000, 0x4000000300000000, 0x0, // Branch Conditional B-form (bcla BO,BI,target_addr) 5389 [6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}}, 5390 {BCCTR, 0xfc0007ff00000000, 0x4c00042000000000, 0xe00000000000, // Branch Conditional to Count Register XL-form (bcctr BO,BI,BH) 5391 [6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, 5392 {BCCTRL, 0xfc0007ff00000000, 0x4c00042100000000, 0xe00000000000, // Branch Conditional to Count Register XL-form (bcctrl BO,BI,BH) 5393 [6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, 5394 {BCLR, 0xfc0007ff00000000, 0x4c00002000000000, 0xe00000000000, // Branch Conditional to Link Register XL-form (bclr BO,BI,BH) 5395 [6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, 5396 {BCLRL, 0xfc0007ff00000000, 0x4c00002100000000, 0xe00000000000, // Branch Conditional to Link Register XL-form (bclrl BO,BI,BH) 5397 [6]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, 5398 {CMPW, 0xfc2007fe00000000, 0x7c00000000000000, 0x40000100000000, // Compare X-form (cmpw BF,RA,RB) 5399 [6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 5400 {CMPD, 0xfc2007fe00000000, 0x7c20000000000000, 0x40000100000000, // Compare X-form (cmpd BF,RA,RB) 5401 [6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 5402 {CMP, 0xfc0007fe00000000, 0x7c00000000000000, 0x40000100000000, // Compare X-form (cmp BF,L,RA,RB) 5403 [6]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_Reg_16_20}}, 5404 {CMPWI, 0xfc20000000000000, 0x2c00000000000000, 0x40000000000000, // Compare Immediate D-form (cmpwi BF,RA,SI) 5405 [6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}}, 5406 {CMPDI, 0xfc20000000000000, 0x2c20000000000000, 0x40000000000000, // Compare Immediate D-form (cmpdi BF,RA,SI) 5407 [6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}}, 5408 {CMPI, 0xfc00000000000000, 0x2c00000000000000, 0x40000000000000, // Compare Immediate D-form (cmpi BF,L,RA,SI) 5409 [6]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, 5410 {CMPLW, 0xfc2007fe00000000, 0x7c00004000000000, 0x40000100000000, // Compare Logical X-form (cmplw BF,RA,RB) 5411 [6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 5412 {CMPLD, 0xfc2007fe00000000, 0x7c20004000000000, 0x40000100000000, // Compare Logical X-form (cmpld BF,RA,RB) 5413 [6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 5414 {CMPL, 0xfc0007fe00000000, 0x7c00004000000000, 0x40000100000000, // Compare Logical X-form (cmpl BF,L,RA,RB) 5415 [6]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_Reg_16_20}}, 5416 {CMPLWI, 0xfc20000000000000, 0x2800000000000000, 0x40000000000000, // Compare Logical Immediate D-form (cmplwi BF,RA,UI) 5417 [6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}}, 5418 {CMPLDI, 0xfc20000000000000, 0x2820000000000000, 0x40000000000000, // Compare Logical Immediate D-form (cmpldi BF,RA,UI) 5419 [6]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}}, 5420 {CMPLI, 0xfc00000000000000, 0x2800000000000000, 0x40000000000000, // Compare Logical Immediate D-form (cmpli BF,L,RA,UI) 5421 [6]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_ImmUnsigned_16_31}}, 5422 {CNTLZW, 0xfc0007ff00000000, 0x7c00003400000000, 0xf80000000000, // Count Leading Zeros Word X-form (cntlzw RA,RS) 5423 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 5424 {CNTLZWCC, 0xfc0007ff00000000, 0x7c00003500000000, 0xf80000000000, // Count Leading Zeros Word X-form (cntlzw. RA,RS) 5425 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 5426 {CRAND, 0xfc0007fe00000000, 0x4c00020200000000, 0x100000000, // Condition Register AND XL-form (crand BT,BA,BB) 5427 [6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, 5428 {CRANDC, 0xfc0007fe00000000, 0x4c00010200000000, 0x100000000, // Condition Register AND with Complement XL-form (crandc BT,BA,BB) 5429 [6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, 5430 {CREQV, 0xfc0007fe00000000, 0x4c00024200000000, 0x100000000, // Condition Register Equivalent XL-form (creqv BT,BA,BB) 5431 [6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, 5432 {CRNAND, 0xfc0007fe00000000, 0x4c0001c200000000, 0x100000000, // Condition Register NAND XL-form (crnand BT,BA,BB) 5433 [6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, 5434 {CRNOR, 0xfc0007fe00000000, 0x4c00004200000000, 0x100000000, // Condition Register NOR XL-form (crnor BT,BA,BB) 5435 [6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, 5436 {CROR, 0xfc0007fe00000000, 0x4c00038200000000, 0x100000000, // Condition Register OR XL-form (cror BT,BA,BB) 5437 [6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, 5438 {CRORC, 0xfc0007fe00000000, 0x4c00034200000000, 0x100000000, // Condition Register OR with Complement XL-form (crorc BT,BA,BB) 5439 [6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, 5440 {CRXOR, 0xfc0007fe00000000, 0x4c00018200000000, 0x100000000, // Condition Register XOR XL-form (crxor BT,BA,BB) 5441 [6]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, 5442 {DCBZ, 0xfc0007fe00000000, 0x7c0007ec00000000, 0x3e0000100000000, // Data Cache Block set to Zero X-form (dcbz RA,RB) 5443 [6]*argField{ap_Reg_11_15, ap_Reg_16_20}}, 5444 {EQV, 0xfc0007ff00000000, 0x7c00023800000000, 0x0, // Equivalent X-form (eqv RA,RS,RB) 5445 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5446 {EQVCC, 0xfc0007ff00000000, 0x7c00023900000000, 0x0, // Equivalent X-form (eqv. RA,RS,RB) 5447 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5448 {EXTSH, 0xfc0007ff00000000, 0x7c00073400000000, 0xf80000000000, // Extend Sign Halfword X-form (extsh RA,RS) 5449 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 5450 {EXTSHCC, 0xfc0007ff00000000, 0x7c00073500000000, 0xf80000000000, // Extend Sign Halfword X-form (extsh. RA,RS) 5451 [6]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 5452 {FABS, 0xfc0007ff00000000, 0xfc00021000000000, 0x1f000000000000, // Floating Absolute Value X-form (fabs FRT,FRB) 5453 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5454 {FABSCC, 0xfc0007ff00000000, 0xfc00021100000000, 0x1f000000000000, // Floating Absolute Value X-form (fabs. FRT,FRB) 5455 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5456 {FADD, 0xfc00003f00000000, 0xfc00002a00000000, 0x7c000000000, // Floating Add A-form (fadd FRT,FRA,FRB) 5457 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 5458 {FADDCC, 0xfc00003f00000000, 0xfc00002b00000000, 0x7c000000000, // Floating Add A-form (fadd. FRT,FRA,FRB) 5459 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 5460 {FCMPO, 0xfc0007fe00000000, 0xfc00004000000000, 0x60000100000000, // Floating Compare Ordered X-form (fcmpo BF,FRA,FRB) 5461 [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, 5462 {FCMPU, 0xfc0007fe00000000, 0xfc00000000000000, 0x60000100000000, // Floating Compare Unordered X-form (fcmpu BF,FRA,FRB) 5463 [6]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, 5464 {FDIV, 0xfc00003f00000000, 0xfc00002400000000, 0x7c000000000, // Floating Divide A-form (fdiv FRT,FRA,FRB) 5465 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 5466 {FDIVCC, 0xfc00003f00000000, 0xfc00002500000000, 0x7c000000000, // Floating Divide A-form (fdiv. FRT,FRA,FRB) 5467 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 5468 {FMADD, 0xfc00003f00000000, 0xfc00003a00000000, 0x0, // Floating Multiply-Add A-form (fmadd FRT,FRA,FRC,FRB) 5469 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 5470 {FMADDCC, 0xfc00003f00000000, 0xfc00003b00000000, 0x0, // Floating Multiply-Add A-form (fmadd. FRT,FRA,FRC,FRB) 5471 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 5472 {FMR, 0xfc0007ff00000000, 0xfc00009000000000, 0x1f000000000000, // Floating Move Register X-form (fmr FRT,FRB) 5473 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5474 {FMRCC, 0xfc0007ff00000000, 0xfc00009100000000, 0x1f000000000000, // Floating Move Register X-form (fmr. FRT,FRB) 5475 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5476 {FMSUB, 0xfc00003f00000000, 0xfc00003800000000, 0x0, // Floating Multiply-Subtract A-form (fmsub FRT,FRA,FRC,FRB) 5477 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 5478 {FMSUBCC, 0xfc00003f00000000, 0xfc00003900000000, 0x0, // Floating Multiply-Subtract A-form (fmsub. FRT,FRA,FRC,FRB) 5479 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 5480 {FMUL, 0xfc00003f00000000, 0xfc00003200000000, 0xf80000000000, // Floating Multiply A-form (fmul FRT,FRA,FRC) 5481 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}}, 5482 {FMULCC, 0xfc00003f00000000, 0xfc00003300000000, 0xf80000000000, // Floating Multiply A-form (fmul. FRT,FRA,FRC) 5483 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}}, 5484 {FNABS, 0xfc0007ff00000000, 0xfc00011000000000, 0x1f000000000000, // Floating Negative Absolute Value X-form (fnabs FRT,FRB) 5485 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5486 {FNABSCC, 0xfc0007ff00000000, 0xfc00011100000000, 0x1f000000000000, // Floating Negative Absolute Value X-form (fnabs. FRT,FRB) 5487 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5488 {FNEG, 0xfc0007ff00000000, 0xfc00005000000000, 0x1f000000000000, // Floating Negate X-form (fneg FRT,FRB) 5489 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5490 {FNEGCC, 0xfc0007ff00000000, 0xfc00005100000000, 0x1f000000000000, // Floating Negate X-form (fneg. FRT,FRB) 5491 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5492 {FNMADD, 0xfc00003f00000000, 0xfc00003e00000000, 0x0, // Floating Negative Multiply-Add A-form (fnmadd FRT,FRA,FRC,FRB) 5493 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 5494 {FNMADDCC, 0xfc00003f00000000, 0xfc00003f00000000, 0x0, // Floating Negative Multiply-Add A-form (fnmadd. FRT,FRA,FRC,FRB) 5495 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 5496 {FNMSUB, 0xfc00003f00000000, 0xfc00003c00000000, 0x0, // Floating Negative Multiply-Subtract A-form (fnmsub FRT,FRA,FRC,FRB) 5497 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 5498 {FNMSUBCC, 0xfc00003f00000000, 0xfc00003d00000000, 0x0, // Floating Negative Multiply-Subtract A-form (fnmsub. FRT,FRA,FRC,FRB) 5499 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 5500 {FRSP, 0xfc0007ff00000000, 0xfc00001800000000, 0x1f000000000000, // Floating Round to Single-Precision X-form (frsp FRT,FRB) 5501 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5502 {FRSPCC, 0xfc0007ff00000000, 0xfc00001900000000, 0x1f000000000000, // Floating Round to Single-Precision X-form (frsp. FRT,FRB) 5503 [6]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 5504 {FSUB, 0xfc00003f00000000, 0xfc00002800000000, 0x7c000000000, // Floating Subtract A-form (fsub FRT,FRA,FRB) 5505 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 5506 {FSUBCC, 0xfc00003f00000000, 0xfc00002900000000, 0x7c000000000, // Floating Subtract A-form (fsub. FRT,FRA,FRB) 5507 [6]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 5508 {ISYNC, 0xfc0007fe00000000, 0x4c00012c00000000, 0x3fff80100000000, // Instruction Synchronize XL-form (isync) 5509 [6]*argField{}}, 5510 {LBZ, 0xfc00000000000000, 0x8800000000000000, 0x0, // Load Byte and Zero D-form (lbz RT,D(RA)) 5511 [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5512 {LBZU, 0xfc00000000000000, 0x8c00000000000000, 0x0, // Load Byte and Zero with Update D-form (lbzu RT,D(RA)) 5513 [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5514 {LBZUX, 0xfc0007fe00000000, 0x7c0000ee00000000, 0x100000000, // Load Byte and Zero with Update Indexed X-form (lbzux RT,RA,RB) 5515 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5516 {LBZX, 0xfc0007fe00000000, 0x7c0000ae00000000, 0x100000000, // Load Byte and Zero Indexed X-form (lbzx RT,RA,RB) 5517 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5518 {LFD, 0xfc00000000000000, 0xc800000000000000, 0x0, // Load Floating-Point Double D-form (lfd FRT,D(RA)) 5519 [6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5520 {LFDU, 0xfc00000000000000, 0xcc00000000000000, 0x0, // Load Floating-Point Double with Update D-form (lfdu FRT,D(RA)) 5521 [6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5522 {LFDUX, 0xfc0007fe00000000, 0x7c0004ee00000000, 0x100000000, // Load Floating-Point Double with Update Indexed X-form (lfdux FRT,RA,RB) 5523 [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5524 {LFDX, 0xfc0007fe00000000, 0x7c0004ae00000000, 0x100000000, // Load Floating-Point Double Indexed X-form (lfdx FRT,RA,RB) 5525 [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5526 {LFS, 0xfc00000000000000, 0xc000000000000000, 0x0, // Load Floating-Point Single D-form (lfs FRT,D(RA)) 5527 [6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5528 {LFSU, 0xfc00000000000000, 0xc400000000000000, 0x0, // Load Floating-Point Single with Update D-form (lfsu FRT,D(RA)) 5529 [6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5530 {LFSUX, 0xfc0007fe00000000, 0x7c00046e00000000, 0x100000000, // Load Floating-Point Single with Update Indexed X-form (lfsux FRT,RA,RB) 5531 [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5532 {LFSX, 0xfc0007fe00000000, 0x7c00042e00000000, 0x100000000, // Load Floating-Point Single Indexed X-form (lfsx FRT,RA,RB) 5533 [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5534 {LHA, 0xfc00000000000000, 0xa800000000000000, 0x0, // Load Halfword Algebraic D-form (lha RT,D(RA)) 5535 [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5536 {LHAU, 0xfc00000000000000, 0xac00000000000000, 0x0, // Load Halfword Algebraic with Update D-form (lhau RT,D(RA)) 5537 [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5538 {LHAUX, 0xfc0007fe00000000, 0x7c0002ee00000000, 0x100000000, // Load Halfword Algebraic with Update Indexed X-form (lhaux RT,RA,RB) 5539 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5540 {LHAX, 0xfc0007fe00000000, 0x7c0002ae00000000, 0x100000000, // Load Halfword Algebraic Indexed X-form (lhax RT,RA,RB) 5541 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5542 {LHBRX, 0xfc0007fe00000000, 0x7c00062c00000000, 0x100000000, // Load Halfword Byte-Reverse Indexed X-form (lhbrx RT,RA,RB) 5543 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5544 {LHZ, 0xfc00000000000000, 0xa000000000000000, 0x0, // Load Halfword and Zero D-form (lhz RT,D(RA)) 5545 [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5546 {LHZU, 0xfc00000000000000, 0xa400000000000000, 0x0, // Load Halfword and Zero with Update D-form (lhzu RT,D(RA)) 5547 [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5548 {LHZUX, 0xfc0007fe00000000, 0x7c00026e00000000, 0x100000000, // Load Halfword and Zero with Update Indexed X-form (lhzux RT,RA,RB) 5549 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5550 {LHZX, 0xfc0007fe00000000, 0x7c00022e00000000, 0x100000000, // Load Halfword and Zero Indexed X-form (lhzx RT,RA,RB) 5551 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5552 {LMW, 0xfc00000000000000, 0xb800000000000000, 0x0, // Load Multiple Word D-form (lmw RT,D(RA)) 5553 [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5554 {LSWI, 0xfc0007fe00000000, 0x7c0004aa00000000, 0x100000000, // Load String Word Immediate X-form (lswi RT,RA,NB) 5555 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, 5556 {LSWX, 0xfc0007fe00000000, 0x7c00042a00000000, 0x100000000, // Load String Word Indexed X-form (lswx RT,RA,RB) 5557 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5558 {LWBRX, 0xfc0007fe00000000, 0x7c00042c00000000, 0x100000000, // Load Word Byte-Reverse Indexed X-form (lwbrx RT,RA,RB) 5559 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5560 {LWZ, 0xfc00000000000000, 0x8000000000000000, 0x0, // Load Word and Zero D-form (lwz RT,D(RA)) 5561 [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5562 {LWZU, 0xfc00000000000000, 0x8400000000000000, 0x0, // Load Word and Zero with Update D-form (lwzu RT,D(RA)) 5563 [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5564 {LWZUX, 0xfc0007fe00000000, 0x7c00006e00000000, 0x100000000, // Load Word and Zero with Update Indexed X-form (lwzux RT,RA,RB) 5565 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5566 {LWZX, 0xfc0007fe00000000, 0x7c00002e00000000, 0x100000000, // Load Word and Zero Indexed X-form (lwzx RT,RA,RB) 5567 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5568 {MCRF, 0xfc0007fe00000000, 0x4c00000000000000, 0x63f80100000000, // Move Condition Register Field XL-form (mcrf BF,BFA) 5569 [6]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}}, 5570 {MCRFS, 0xfc0007fe00000000, 0xfc00008000000000, 0x63f80100000000, // Move to Condition Register from FPSCR X-form (mcrfs BF,BFA) 5571 [6]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}}, 5572 {MFCR, 0xfc1007fe00000000, 0x7c00002600000000, 0xff80100000000, // Move From Condition Register XFX-form (mfcr RT) 5573 [6]*argField{ap_Reg_6_10}}, 5574 {MFFS, 0xfc1f07ff00000000, 0xfc00048e00000000, 0xf80000000000, // Move From FPSCR X-form (mffs FRT) 5575 [6]*argField{ap_FPReg_6_10}}, 5576 {MFFSCC, 0xfc1f07ff00000000, 0xfc00048f00000000, 0xf80000000000, // Move From FPSCR X-form (mffs. FRT) 5577 [6]*argField{ap_FPReg_6_10}}, 5578 {MFMSR, 0xfc0007fe00000000, 0x7c0000a600000000, 0x1ff80100000000, // Move From MSR X-form (mfmsr RT) 5579 [6]*argField{ap_Reg_6_10}}, 5580 {MFSPR, 0xfc0007fe00000000, 0x7c0002a600000000, 0x100000000, // Move From Special Purpose Register XFX-form (mfspr RT,SPR) 5581 [6]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}}, 5582 {MTCRF, 0xfc1007fe00000000, 0x7c00012000000000, 0x80100000000, // Move To Condition Register Fields XFX-form (mtcrf FXM,RS) 5583 [6]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}}, 5584 {MTFSB0, 0xfc0007ff00000000, 0xfc00008c00000000, 0x1ff80000000000, // Move To FPSCR Bit 0 X-form (mtfsb0 BT) 5585 [6]*argField{ap_ImmUnsigned_6_10}}, 5586 {MTFSB0CC, 0xfc0007ff00000000, 0xfc00008d00000000, 0x1ff80000000000, // Move To FPSCR Bit 0 X-form (mtfsb0. BT) 5587 [6]*argField{ap_ImmUnsigned_6_10}}, 5588 {MTFSB1, 0xfc0007ff00000000, 0xfc00004c00000000, 0x1ff80000000000, // Move To FPSCR Bit 1 X-form (mtfsb1 BT) 5589 [6]*argField{ap_ImmUnsigned_6_10}}, 5590 {MTFSB1CC, 0xfc0007ff00000000, 0xfc00004d00000000, 0x1ff80000000000, // Move To FPSCR Bit 1 X-form (mtfsb1. BT) 5591 [6]*argField{ap_ImmUnsigned_6_10}}, 5592 {MTFSF, 0xfc0007ff00000000, 0xfc00058e00000000, 0x0, // Move To FPSCR Fields XFL-form (mtfsf FLM,FRB,L,W) 5593 [6]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}}, 5594 {MTFSFCC, 0xfc0007ff00000000, 0xfc00058f00000000, 0x0, // Move To FPSCR Fields XFL-form (mtfsf. FLM,FRB,L,W) 5595 [6]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}}, 5596 {MTFSFI, 0xfc0007ff00000000, 0xfc00010c00000000, 0x7e080000000000, // Move To FPSCR Field Immediate X-form (mtfsfi BF,U,W) 5597 [6]*argField{ap_ImmUnsigned_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}}, 5598 {MTFSFICC, 0xfc0007ff00000000, 0xfc00010d00000000, 0x7e080000000000, // Move To FPSCR Field Immediate X-form (mtfsfi. BF,U,W) 5599 [6]*argField{ap_ImmUnsigned_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}}, 5600 {MTMSR, 0xfc0007fe00000000, 0x7c00012400000000, 0x1ef80100000000, // Move To MSR X-form (mtmsr RS,L) 5601 [6]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}}, 5602 {MTSPR, 0xfc0007fe00000000, 0x7c0003a600000000, 0x100000000, // Move To Special Purpose Register XFX-form (mtspr SPR,RS) 5603 [6]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}}, 5604 {MULLI, 0xfc00000000000000, 0x1c00000000000000, 0x0, // Multiply Low Immediate D-form (mulli RT,RA,SI) 5605 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, 5606 {MULLW, 0xfc0007ff00000000, 0x7c0001d600000000, 0x0, // Multiply Low Word XO-form (mullw RT,RA,RB) 5607 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5608 {MULLWCC, 0xfc0007ff00000000, 0x7c0001d700000000, 0x0, // Multiply Low Word XO-form (mullw. RT,RA,RB) 5609 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5610 {MULLWO, 0xfc0007ff00000000, 0x7c0005d600000000, 0x0, // Multiply Low Word XO-form (mullwo RT,RA,RB) 5611 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5612 {MULLWOCC, 0xfc0007ff00000000, 0x7c0005d700000000, 0x0, // Multiply Low Word XO-form (mullwo. RT,RA,RB) 5613 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5614 {NAND, 0xfc0007ff00000000, 0x7c0003b800000000, 0x0, // NAND X-form (nand RA,RS,RB) 5615 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5616 {NANDCC, 0xfc0007ff00000000, 0x7c0003b900000000, 0x0, // NAND X-form (nand. RA,RS,RB) 5617 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5618 {NEG, 0xfc0007ff00000000, 0x7c0000d000000000, 0xf80000000000, // Negate XO-form (neg RT,RA) 5619 [6]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 5620 {NEGCC, 0xfc0007ff00000000, 0x7c0000d100000000, 0xf80000000000, // Negate XO-form (neg. RT,RA) 5621 [6]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 5622 {NEGO, 0xfc0007ff00000000, 0x7c0004d000000000, 0xf80000000000, // Negate XO-form (nego RT,RA) 5623 [6]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 5624 {NEGOCC, 0xfc0007ff00000000, 0x7c0004d100000000, 0xf80000000000, // Negate XO-form (nego. RT,RA) 5625 [6]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 5626 {NOR, 0xfc0007ff00000000, 0x7c0000f800000000, 0x0, // NOR X-form (nor RA,RS,RB) 5627 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5628 {NORCC, 0xfc0007ff00000000, 0x7c0000f900000000, 0x0, // NOR X-form (nor. RA,RS,RB) 5629 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5630 {OR, 0xfc0007ff00000000, 0x7c00037800000000, 0x0, // OR X-form (or RA,RS,RB) 5631 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5632 {ORCC, 0xfc0007ff00000000, 0x7c00037900000000, 0x0, // OR X-form (or. RA,RS,RB) 5633 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5634 {ORC, 0xfc0007ff00000000, 0x7c00033800000000, 0x0, // OR with Complement X-form (orc RA,RS,RB) 5635 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5636 {ORCCC, 0xfc0007ff00000000, 0x7c00033900000000, 0x0, // OR with Complement X-form (orc. RA,RS,RB) 5637 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5638 {NOP, 0xffffffff00000000, 0x6000000000000000, 0x0, // OR Immediate D-form (nop) 5639 [6]*argField{}}, 5640 {ORI, 0xfc00000000000000, 0x6000000000000000, 0x0, // OR Immediate D-form (ori RA,RS,UI) 5641 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, 5642 {ORIS, 0xfc00000000000000, 0x6400000000000000, 0x0, // OR Immediate Shifted D-form (oris RA,RS,UI) 5643 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, 5644 {RLWIMI, 0xfc00000100000000, 0x5000000000000000, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi RA,RS,SH,MB,ME) 5645 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, 5646 {RLWIMICC, 0xfc00000100000000, 0x5000000100000000, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi. RA,RS,SH,MB,ME) 5647 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, 5648 {RLWINM, 0xfc00000100000000, 0x5400000000000000, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm RA,RS,SH,MB,ME) 5649 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, 5650 {RLWINMCC, 0xfc00000100000000, 0x5400000100000000, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm. RA,RS,SH,MB,ME) 5651 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, 5652 {RLWNM, 0xfc00000100000000, 0x5c00000000000000, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm RA,RS,RB,MB,ME) 5653 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, 5654 {RLWNMCC, 0xfc00000100000000, 0x5c00000100000000, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm. RA,RS,RB,MB,ME) 5655 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, 5656 {SLW, 0xfc0007ff00000000, 0x7c00003000000000, 0x0, // Shift Left Word X-form (slw RA,RS,RB) 5657 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5658 {SLWCC, 0xfc0007ff00000000, 0x7c00003100000000, 0x0, // Shift Left Word X-form (slw. RA,RS,RB) 5659 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5660 {SRAW, 0xfc0007ff00000000, 0x7c00063000000000, 0x0, // Shift Right Algebraic Word X-form (sraw RA,RS,RB) 5661 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5662 {SRAWCC, 0xfc0007ff00000000, 0x7c00063100000000, 0x0, // Shift Right Algebraic Word X-form (sraw. RA,RS,RB) 5663 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5664 {SRAWI, 0xfc0007ff00000000, 0x7c00067000000000, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi RA,RS,SH) 5665 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}}, 5666 {SRAWICC, 0xfc0007ff00000000, 0x7c00067100000000, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi. RA,RS,SH) 5667 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}}, 5668 {SRW, 0xfc0007ff00000000, 0x7c00043000000000, 0x0, // Shift Right Word X-form (srw RA,RS,RB) 5669 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5670 {SRWCC, 0xfc0007ff00000000, 0x7c00043100000000, 0x0, // Shift Right Word X-form (srw. RA,RS,RB) 5671 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5672 {STB, 0xfc00000000000000, 0x9800000000000000, 0x0, // Store Byte D-form (stb RS,D(RA)) 5673 [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5674 {STBU, 0xfc00000000000000, 0x9c00000000000000, 0x0, // Store Byte with Update D-form (stbu RS,D(RA)) 5675 [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5676 {STBUX, 0xfc0007fe00000000, 0x7c0001ee00000000, 0x100000000, // Store Byte with Update Indexed X-form (stbux RS,RA,RB) 5677 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5678 {STBX, 0xfc0007fe00000000, 0x7c0001ae00000000, 0x100000000, // Store Byte Indexed X-form (stbx RS,RA,RB) 5679 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5680 {STFD, 0xfc00000000000000, 0xd800000000000000, 0x0, // Store Floating-Point Double D-form (stfd FRS,D(RA)) 5681 [6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5682 {STFDU, 0xfc00000000000000, 0xdc00000000000000, 0x0, // Store Floating-Point Double with Update D-form (stfdu FRS,D(RA)) 5683 [6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5684 {STFDUX, 0xfc0007fe00000000, 0x7c0005ee00000000, 0x100000000, // Store Floating-Point Double with Update Indexed X-form (stfdux FRS,RA,RB) 5685 [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5686 {STFDX, 0xfc0007fe00000000, 0x7c0005ae00000000, 0x100000000, // Store Floating-Point Double Indexed X-form (stfdx FRS,RA,RB) 5687 [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5688 {STFS, 0xfc00000000000000, 0xd000000000000000, 0x0, // Store Floating-Point Single D-form (stfs FRS,D(RA)) 5689 [6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5690 {STFSU, 0xfc00000000000000, 0xd400000000000000, 0x0, // Store Floating-Point Single with Update D-form (stfsu FRS,D(RA)) 5691 [6]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5692 {STFSUX, 0xfc0007fe00000000, 0x7c00056e00000000, 0x100000000, // Store Floating-Point Single with Update Indexed X-form (stfsux FRS,RA,RB) 5693 [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5694 {STFSX, 0xfc0007fe00000000, 0x7c00052e00000000, 0x100000000, // Store Floating-Point Single Indexed X-form (stfsx FRS,RA,RB) 5695 [6]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5696 {STH, 0xfc00000000000000, 0xb000000000000000, 0x0, // Store Halfword D-form (sth RS,D(RA)) 5697 [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5698 {STHBRX, 0xfc0007fe00000000, 0x7c00072c00000000, 0x100000000, // Store Halfword Byte-Reverse Indexed X-form (sthbrx RS,RA,RB) 5699 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5700 {STHU, 0xfc00000000000000, 0xb400000000000000, 0x0, // Store Halfword with Update D-form (sthu RS,D(RA)) 5701 [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5702 {STHUX, 0xfc0007fe00000000, 0x7c00036e00000000, 0x100000000, // Store Halfword with Update Indexed X-form (sthux RS,RA,RB) 5703 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5704 {STHX, 0xfc0007fe00000000, 0x7c00032e00000000, 0x100000000, // Store Halfword Indexed X-form (sthx RS,RA,RB) 5705 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5706 {STMW, 0xfc00000000000000, 0xbc00000000000000, 0x0, // Store Multiple Word D-form (stmw RS,D(RA)) 5707 [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5708 {STSWI, 0xfc0007fe00000000, 0x7c0005aa00000000, 0x100000000, // Store String Word Immediate X-form (stswi RS,RA,NB) 5709 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, 5710 {STSWX, 0xfc0007fe00000000, 0x7c00052a00000000, 0x100000000, // Store String Word Indexed X-form (stswx RS,RA,RB) 5711 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5712 {STW, 0xfc00000000000000, 0x9000000000000000, 0x0, // Store Word D-form (stw RS,D(RA)) 5713 [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5714 {STWBRX, 0xfc0007fe00000000, 0x7c00052c00000000, 0x100000000, // Store Word Byte-Reverse Indexed X-form (stwbrx RS,RA,RB) 5715 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5716 {STWU, 0xfc00000000000000, 0x9400000000000000, 0x0, // Store Word with Update D-form (stwu RS,D(RA)) 5717 [6]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 5718 {STWUX, 0xfc0007fe00000000, 0x7c00016e00000000, 0x100000000, // Store Word with Update Indexed X-form (stwux RS,RA,RB) 5719 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5720 {STWX, 0xfc0007fe00000000, 0x7c00012e00000000, 0x100000000, // Store Word Indexed X-form (stwx RS,RA,RB) 5721 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5722 {SUBFC, 0xfc0007ff00000000, 0x7c00001000000000, 0x0, // Subtract From Carrying XO-form (subfc RT,RA,RB) 5723 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5724 {SUBFCCC, 0xfc0007ff00000000, 0x7c00001100000000, 0x0, // Subtract From Carrying XO-form (subfc. RT,RA,RB) 5725 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5726 {SUBFCO, 0xfc0007ff00000000, 0x7c00041000000000, 0x0, // Subtract From Carrying XO-form (subfco RT,RA,RB) 5727 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5728 {SUBFCOCC, 0xfc0007ff00000000, 0x7c00041100000000, 0x0, // Subtract From Carrying XO-form (subfco. RT,RA,RB) 5729 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5730 {SUBFE, 0xfc0007ff00000000, 0x7c00011000000000, 0x0, // Subtract From Extended XO-form (subfe RT,RA,RB) 5731 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5732 {SUBFECC, 0xfc0007ff00000000, 0x7c00011100000000, 0x0, // Subtract From Extended XO-form (subfe. RT,RA,RB) 5733 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5734 {SUBFEO, 0xfc0007ff00000000, 0x7c00051000000000, 0x0, // Subtract From Extended XO-form (subfeo RT,RA,RB) 5735 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5736 {SUBFEOCC, 0xfc0007ff00000000, 0x7c00051100000000, 0x0, // Subtract From Extended XO-form (subfeo. RT,RA,RB) 5737 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5738 {SUBFIC, 0xfc00000000000000, 0x2000000000000000, 0x0, // Subtract From Immediate Carrying D-form (subfic RT,RA,SI) 5739 [6]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, 5740 {SUBFME, 0xfc0007ff00000000, 0x7c0001d000000000, 0xf80000000000, // Subtract From Minus One Extended XO-form (subfme RT,RA) 5741 [6]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 5742 {SUBFMECC, 0xfc0007ff00000000, 0x7c0001d100000000, 0xf80000000000, // Subtract From Minus One Extended XO-form (subfme. RT,RA) 5743 [6]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 5744 {SUBFMEO, 0xfc0007ff00000000, 0x7c0005d000000000, 0xf80000000000, // Subtract From Minus One Extended XO-form (subfmeo RT,RA) 5745 [6]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 5746 {SUBFMEOCC, 0xfc0007ff00000000, 0x7c0005d100000000, 0xf80000000000, // Subtract From Minus One Extended XO-form (subfmeo. RT,RA) 5747 [6]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 5748 {SUBFZE, 0xfc0007ff00000000, 0x7c00019000000000, 0xf80000000000, // Subtract From Zero Extended XO-form (subfze RT,RA) 5749 [6]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 5750 {SUBFZECC, 0xfc0007ff00000000, 0x7c00019100000000, 0xf80000000000, // Subtract From Zero Extended XO-form (subfze. RT,RA) 5751 [6]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 5752 {SUBFZEO, 0xfc0007ff00000000, 0x7c00059000000000, 0xf80000000000, // Subtract From Zero Extended XO-form (subfzeo RT,RA) 5753 [6]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 5754 {SUBFZEOCC, 0xfc0007ff00000000, 0x7c00059100000000, 0xf80000000000, // Subtract From Zero Extended XO-form (subfzeo. RT,RA) 5755 [6]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 5756 {SYNC, 0xfc0007fe00000000, 0x7c0004ac00000000, 0x31cf80100000000, // Synchronize X-form (sync L,SC) 5757 [6]*argField{ap_ImmUnsigned_8_10, ap_ImmUnsigned_14_15}}, 5758 {TLBIE, 0xfc0007fe00000000, 0x7c00026400000000, 0x10000100000000, // TLB Invalidate Entry X-form (tlbie RB,RS,RIC,PRS,R) 5759 [6]*argField{ap_Reg_16_20, ap_Reg_6_10, ap_ImmUnsigned_12_13, ap_ImmUnsigned_14_14, ap_ImmUnsigned_15_15}}, 5760 {TW, 0xfc0007fe00000000, 0x7c00000800000000, 0x100000000, // Trap Word X-form (tw TO,RA,RB) 5761 [6]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5762 {TWI, 0xfc00000000000000, 0xc00000000000000, 0x0, // Trap Word Immediate D-form (twi TO,RA,SI) 5763 [6]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, 5764 {XOR, 0xfc0007ff00000000, 0x7c00027800000000, 0x0, // XOR X-form (xor RA,RS,RB) 5765 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5766 {XORCC, 0xfc0007ff00000000, 0x7c00027900000000, 0x0, // XOR X-form (xor. RA,RS,RB) 5767 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 5768 {XORI, 0xfc00000000000000, 0x6800000000000000, 0x0, // XOR Immediate D-form (xori RA,RS,UI) 5769 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, 5770 {XORIS, 0xfc00000000000000, 0x6c00000000000000, 0x0, // XOR Immediate Shifted D-form (xoris RA,RS,UI) 5771 [6]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, 5772} 5773