1 /* pdp1_defs.h: 18b PDP simulator definitions 2 3 Copyright (c) 1993-2010, Robert M. Supnik 4 5 Permission is hereby granted, free of charge, to any person obtaining a 6 copy of this software and associated documentation files (the "Software"), 7 to deal in the Software without restriction, including without limitation 8 the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 and/or sell copies of the Software, and to permit persons to whom the 10 Software is furnished to do so, subject to the following conditions: 11 12 The above copyright notice and this permission notice shall be included in 13 all copies or substantial portions of the Software. 14 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 22 Except as contained in this notice, the name of Robert M Supnik shall not be 23 used in advertising or otherwise to promote the sale, use or other dealings 24 in this Software without prior written authorization from Robert M Supnik. 25 26 22-May-10 RMS Added check for 64b definitions 27 21-Dec-06 RMS Added 16-channel sequence break support 28 22-Jul-05 RMS Fixed definition of CPLS_DPY 29 08-Feb-04 PLB Added support for display 30 08-Dec-03 RMS Added support for parallel drum 31 18-Oct-03 RMS Added DECtape off reel message 32 22-Jul-03 RMS Updated for "hardware" RIM loader 33 Revised to detect I/O wait hang 34 05-Dec-02 RMS Added IOT skip support (required by drum) 35 14-Apr-99 RMS Changed t_addr to unsigned 36 37 The PDP-1 was Digital's first computer. The system design evolved during 38 its life, and as a result, specifications are sketchy or contradictory. 39 This simulator is based on the 1962 maintenance manual. 40 41 This simulator implements the following options: 42 43 Automatic multiply/divide Type 10 44 Memory extension control Type 15 45 Parallel drum Type 23 46 Serial drum Type 24 47 Graphic display Type 30 48 Line printer control Type 62 49 Microtape (DECtape) control Type 550 50 */ 51 52 #ifndef _PDP1_DEFS_H_ 53 #define _PDP1_DEFS_H_ 0 54 55 #include "sim_defs.h" 56 57 #if defined(USE_INT64) || defined(USE_ADDR64) 58 #error "PDP-1 does not support 64b values!" 59 #endif 60 61 /* Simulator stop codes */ 62 63 #define STOP_RSRV 1 /* must be 1 */ 64 #define STOP_HALT 2 /* HALT */ 65 #define STOP_IBKPT 3 /* breakpoint */ 66 #define STOP_XCT 4 /* nested XCT's */ 67 #define STOP_IND 5 /* nested indirects */ 68 #define STOP_WAIT 6 /* IO wait hang */ 69 #define STOP_DTOFF 7 /* DECtape off reel */ 70 #define ERR_RMV 10 /* restrict mode viol */ 71 72 /* Memory */ 73 74 #define ASIZE 16 /* address bits */ 75 #define MAXMEMSIZE (1u << ASIZE) /* max mem size */ 76 #define AMASK (MAXMEMSIZE - 1) /* address mask */ 77 #define MEMSIZE (cpu_unit.capac) /* actual memory size */ 78 #define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE) 79 80 /* Architectural constants */ 81 82 #define SIGN 0400000 /* sign */ 83 #define DMASK 0777777 /* data mask */ 84 #define DAMASK 0007777 /* direct addr */ 85 #define EPCMASK (AMASK & ~DAMASK) /* extended addr */ 86 #define IA 0010000 /* indirect flag */ 87 #define IO_WAIT 0010000 /* I/O sync wait */ 88 #define IO_CPLS 0004000 /* completion pulse */ 89 #define OP_DAC 0240000 /* DAC */ 90 #define OP_DIO 0320000 /* DIO */ 91 #define OP_JMP 0600000 /* JMP */ 92 #define GEN_CPLS(x) (((x) ^ ((x) << 1)) & IO_WAIT) /* completion pulse? */ 93 94 /* Program flags/sense switches */ 95 96 #define PF_V_L 7 97 #define PF_V_RNG 6 98 #define PF_L (1u << PF_V_L) 99 #define PF_RNG (1u << PF_V_RNG) 100 #define PF_SS_1 0040 101 #define PF_SS_2 0020 102 #define PF_SS_3 0010 103 #define PF_SS_4 0004 104 #define PF_SS_5 0002 105 #define PF_SS_6 0001 106 #define PF_VR_ALL 0377 107 #define PF_SS_ALL 0077 108 109 /* Restict mode */ 110 111 #define RTB_IOT 0400000 112 #define RTB_ILL 0200000 113 #define RTB_HLT 0100000 114 #define RTB_DBK 0040000 115 #define RTB_CHR 0020000 116 #define RTB_MB_MASK 0017777 117 118 #define RM45_V_BNK 14 119 #define RM45_M_BNK 003 120 #define RM48_V_BNK 12 121 #define RM48_M_BNK 017 122 123 #define RN45_SIZE 4 124 125 /* IOT subroutine return codes */ 126 127 #define IOT_V_SKP 18 /* skip */ 128 #define IOT_SKP (1 << IOT_V_SKP) 129 #define IOT_V_REASON (IOT_V_SKP + 1) /* reason */ 130 #define IOT_REASON (1 << IOT_V_REASON) 131 #define IORETURN(f,v) ((f)? (v): SCPE_OK) /* stop on error */ 132 133 /* I/O status flags */ 134 135 #define IOS_V_LPN 17 /* light pen */ 136 #define IOS_V_PTR 16 /* paper tape reader */ 137 #define IOS_V_TTO 15 /* typewriter out */ 138 #define IOS_V_TTI 14 /* typewriter in */ 139 #define IOS_V_PTP 13 /* paper tape punch */ 140 #define IOS_V_DRM 12 /* drum */ 141 #define IOS_V_SQB 11 /* sequence break */ 142 #define IOS_V_PNT 3 /* print done */ 143 #define IOS_V_SPC 2 /* space done */ 144 #define IOS_V_DCS 1 /* data comm sys */ 145 #define IOS_V_DRP 0 /* parallel drum busy */ 146 147 #define IOS_LPN (1 << IOS_V_LPN) 148 #define IOS_PTR (1 << IOS_V_PTR) 149 #define IOS_TTO (1 << IOS_V_TTO) 150 #define IOS_TTI (1 << IOS_V_TTI) 151 #define IOS_PTP (1 << IOS_V_PTP) 152 #define IOS_DRM (1 << IOS_V_DRM) 153 #define IOS_SQB (1 << IOS_V_SQB) 154 #define IOS_PNT (1 << IOS_V_PNT) 155 #define IOS_SPC (1 << IOS_V_SPC) 156 #define IOS_DCS (1 << IOS_V_DCS) 157 #define IOS_DRP (1 << IOS_V_DRP) 158 159 /* Completion pulses */ 160 161 #define CPLS_V_PTR 5 162 #define CPLS_V_PTP 4 163 #define CPLS_V_TTO 3 164 #define CPLS_V_LPT 2 165 #define CPLS_V_DPY 1 166 #define CPLS_PTR (1 << CPLS_V_PTR) 167 #define CPLS_PTP (1 << CPLS_V_PTP) 168 #define CPLS_TTO (1 << CPLS_V_TTO) 169 #define CPLS_LPT (1 << CPLS_V_LPT) 170 #define CPLS_DPY (1 << CPLS_V_DPY) 171 172 /* One channel sequence break */ 173 174 #define SB_V_IP 0 /* in progress */ 175 #define SB_V_RQ 1 /* request */ 176 #define SB_V_ON 2 /* enabled */ 177 178 #define SB_IP (1 << SB_V_IP) 179 #define SB_RQ (1 << SB_V_RQ) 180 #define SB_ON (1 << SB_V_ON) 181 182 /* 16 channel sequence break */ 183 184 #define SBS_LVLS 16 /* num levels */ 185 #define SBS_LVL_MASK (SBS_LVLS - 1) 186 #define SBS_LVL_RMV 14 /* restrict level */ 187 #define SBS_MASK(x) (1u << (SBS_LVLS - 1 - (x))) /* level to mask */ 188 189 /* Timers */ 190 191 #define TMR_CLK 0 192 193 /* Device routines */ 194 195 t_stat dev_req_int (int32 lvl); 196 t_stat dev_set_sbs (UNIT *uptr, int32 val, char *cptr, void *desc); 197 t_stat dev_show_sbs (FILE *st, UNIT *uptr, int32 val, void *desc); 198 199 #endif 200