1 /* 2 * kernel internal memory management definitions for arm 3 */ 4 #pragma once 5 6 #define _MI_PAGING_LEVELS 2 7 #define _MI_HAS_NO_EXECUTE 1 8 9 /* Memory layout base addresses */ 10 #define MI_USER_PROBE_ADDRESS (PVOID)0x7FFF0000 11 #define MI_DEFAULT_SYSTEM_RANGE_START (PVOID)0x80000000 12 #define HYPER_SPACE 0xC0500000 13 #define HYPER_SPACE_END 0xC08FFFFF 14 #define MI_SYSTEM_CACHE_WS_START (PVOID)0xC0C00000 15 #define MI_PAGED_POOL_START (PVOID)0xE1000000 16 #define MI_NONPAGED_POOL_END (PVOID)0xFFBE0000 17 #define MI_DEBUG_MAPPING (PVOID)0xFFBFF000 18 #define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFF 19 20 #define PTE_PER_PAGE 256 21 #define PDE_PER_PAGE 4096 22 #define PPE_PER_PAGE 1 23 24 /* Misc address definitions */ 25 #define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(NULL) 26 #define MM_HIGHEST_VAD_ADDRESS \ 27 (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE)) 28 #define MI_MAPPING_RANGE_START ((ULONG)HYPER_SPACE) 29 #define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \ 30 MI_HYPERSPACE_PTES * PAGE_SIZE) 31 #define MI_DUMMY_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \ 32 PAGE_SIZE) 33 #define MI_VAD_BITMAP (PMMPTE)(MI_DUMMY_PTE + \ 34 PAGE_SIZE) 35 #define MI_WORKING_SET_LIST (PMMPTE)(MI_VAD_BITMAP + \ 36 PAGE_SIZE) 37 38 /* Memory sizes */ 39 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255 * _1MB) >> PAGE_SHIFT) 40 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19 * _1MB) >> PAGE_SHIFT) 41 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32 * _1MB) >> PAGE_SHIFT) 42 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST_BOOST ((256 * _1MB) >> PAGE_SHIFT) 43 #define MI_MIN_INIT_PAGED_POOLSIZE (32 * _1MB) 44 #define MI_MAX_INIT_NONPAGED_POOL_SIZE (128 * _1MB) 45 #define MI_MAX_NONPAGED_POOL_SIZE (128 * _1MB) 46 #define MI_SYSTEM_VIEW_SIZE (32 * _1MB) 47 #define MI_SESSION_VIEW_SIZE (48 * _1MB) 48 #define MI_SESSION_POOL_SIZE (16 * _1MB) 49 #define MI_SESSION_IMAGE_SIZE (8 * _1MB) 50 #define MI_SESSION_WORKING_SET_SIZE (4 * _1MB) 51 #define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \ 52 MI_SESSION_POOL_SIZE + \ 53 MI_SESSION_IMAGE_SIZE + \ 54 MI_SESSION_WORKING_SET_SIZE) 55 #define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB) 56 #define MI_ALLOCATION_FRAGMENT (64 * _1KB) 57 #define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB) 58 59 /* Misc constants */ 60 #define MM_PTE_SOFTWARE_PROTECTION_BITS 6 61 #define MI_MIN_SECONDARY_COLORS 8 62 #define MI_SECONDARY_COLORS 64 63 #define MI_MAX_SECONDARY_COLORS 1024 64 #define MI_MAX_FREE_PAGE_LISTS 4 65 #define MI_HYPERSPACE_PTES (256 - 1) /* Dee PDR definition */ 66 #define MI_ZERO_PTES (32) /* Dee PDR definition */ 67 #define MI_MAX_ZERO_BITS 21 68 #define SESSION_POOL_LOOKASIDES 26 // CHECKME 69 70 /* MMPTE related defines */ 71 #define MM_EMPTY_PTE_LIST ((ULONG)0xFFFFF) 72 #define MM_EMPTY_LIST ((ULONG_PTR)-1) 73 74 75 /* Easy accessing PFN in PTE */ 76 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber) 77 78 /* Macros for portable PTE modification */ 79 #define MI_MAKE_DIRTY_PAGE(x) 80 #define MI_MAKE_CLEAN_PAGE(x) 81 #define MI_MAKE_ACCESSED_PAGE(x) 82 #define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.Cached = 0) 83 #define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.Buffered = 0) 84 #define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.Buffered = 1) 85 #define MI_IS_PAGE_LARGE(x) FALSE 86 #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.ReadOnly == 0) 87 #define MI_IS_PAGE_COPY_ON_WRITE(x)FALSE 88 #define MI_IS_PAGE_EXECUTABLE(x) TRUE 89 #define MI_IS_PAGE_DIRTY(x) TRUE 90 #define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1) 91 #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.ReadOnly = 0) 92 93 /* Macros to identify the page fault reason from the error code */ 94 #define MI_IS_NOT_PRESENT_FAULT(FaultCode) TRUE 95 #define MI_IS_WRITE_ACCESS(FaultCode) TRUE 96 #define MI_IS_INSTRUCTION_FETCH(FaultCode) FALSE 97 98 /* Convert an address to a corresponding PTE */ 99 #define MiAddressToPte(x) \ 100 ((PMMPTE)(PTE_BASE + (((ULONG)(x) >> 12) << 2))) 101 102 /* Convert an address to a corresponding PDE */ 103 #define MiAddressToPde(x) \ 104 ((PMMPDE)(PDE_BASE + (((ULONG)(x) >> 20) << 2))) 105 106 /* Convert an address to a corresponding PTE offset/index */ 107 #define MiAddressToPteOffset(x) \ 108 ((((ULONG)(x)) << 12) >> 24) 109 110 /* Convert an address to a corresponding PDE offset/index */ 111 #define MiAddressToPdeOffset(x) \ 112 (((ULONG)(x)) >> 20) 113 #define MiGetPdeOffset MiAddressToPdeOffset 114 115 /* Convert a PTE/PDE into a corresponding address */ 116 #define MiPteToAddress(_Pte) ((PVOID)((ULONG)(_Pte) << 10)) 117 #define MiPdeToAddress(_Pde) ((PVOID)((ULONG)(_Pde) << 18)) 118 119 /* Translate between P*Es */ 120 #define MiPdeToPte(_Pde) ((PMMPTE)0) /* FIXME */ 121 #define MiPteToPde(_Pte) ((PMMPDE)0) /* FIXME */ 122 123 /* Check P*E boundaries */ 124 #define MiIsPteOnPdeBoundary(PointerPte) \ 125 ((((ULONG_PTR)PointerPte) & (PAGE_SIZE - 1)) == 0) 126 127 // 128 // Decodes a Prototype PTE into the underlying PTE 129 // 130 #define MiProtoPteToPte(x) \ 131 (PMMPTE)((ULONG_PTR)MmPagedPoolStart + \ 132 (((x)->u.Proto.ProtoAddressHigh << 9) | (x)->u.Proto.ProtoAddressLow << 2)) 133 134 // 135 // Decodes a Prototype PTE into the underlying PTE 136 // 137 #define MiSubsectionPteToSubsection(x) \ 138 ((x)->u.Subsect.WhichPool == PagedPool) ? \ 139 (PMMPTE)((ULONG_PTR)MmSubsectionBase + \ 140 (((x)->u.Subsect.SubsectionAddressHigh << 7) | \ 141 (x)->u.Subsect.SubsectionAddressLow << 3)) : \ 142 (PMMPTE)((ULONG_PTR)MmNonPagedPoolEnd - \ 143 (((x)->u.Subsect.SubsectionAddressHigh << 7) | \ 144 (x)->u.Subsect.SubsectionAddressLow << 3)) 145 146 // 147 // Number of bits corresponding to the area that a coarse page table occupies (1KB) 148 // 149 #define CPT_SHIFT 10 150 151 /* See PDR definition */ 152 #define MI_ZERO_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \ 153 PAGE_SIZE) 154 155