1 /*
2 * i386 virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef I386_CPU_H
21 #define I386_CPU_H
22
23 #include "sysemu/tcg.h"
24 #include "cpu-qom.h"
25 #include "kvm/hyperv-proto.h"
26 #include "exec/cpu-defs.h"
27 #include "hw/i386/topology.h"
28 #include "qapi/qapi-types-common.h"
29 #include "qemu/cpu-float.h"
30 #include "qemu/timer.h"
31
32 #define XEN_NR_VIRQS 24
33
34 #define KVM_HAVE_MCE_INJECTION 1
35
36 /* support for self modifying code even if the modified instruction is
37 close to the modifying instruction */
38 #define TARGET_HAS_PRECISE_SMC
39
40 #ifdef TARGET_X86_64
41 #define I386_ELF_MACHINE EM_X86_64
42 #define ELF_MACHINE_UNAME "x86_64"
43 #else
44 #define I386_ELF_MACHINE EM_386
45 #define ELF_MACHINE_UNAME "i686"
46 #endif
47
48 enum {
49 R_EAX = 0,
50 R_ECX = 1,
51 R_EDX = 2,
52 R_EBX = 3,
53 R_ESP = 4,
54 R_EBP = 5,
55 R_ESI = 6,
56 R_EDI = 7,
57 R_R8 = 8,
58 R_R9 = 9,
59 R_R10 = 10,
60 R_R11 = 11,
61 R_R12 = 12,
62 R_R13 = 13,
63 R_R14 = 14,
64 R_R15 = 15,
65
66 R_AL = 0,
67 R_CL = 1,
68 R_DL = 2,
69 R_BL = 3,
70 R_AH = 4,
71 R_CH = 5,
72 R_DH = 6,
73 R_BH = 7,
74 };
75
76 typedef enum X86Seg {
77 R_ES = 0,
78 R_CS = 1,
79 R_SS = 2,
80 R_DS = 3,
81 R_FS = 4,
82 R_GS = 5,
83 R_LDTR = 6,
84 R_TR = 7,
85 } X86Seg;
86
87 /* segment descriptor fields */
88 #define DESC_G_SHIFT 23
89 #define DESC_G_MASK (1 << DESC_G_SHIFT)
90 #define DESC_B_SHIFT 22
91 #define DESC_B_MASK (1 << DESC_B_SHIFT)
92 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
93 #define DESC_L_MASK (1 << DESC_L_SHIFT)
94 #define DESC_AVL_SHIFT 20
95 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT)
96 #define DESC_P_SHIFT 15
97 #define DESC_P_MASK (1 << DESC_P_SHIFT)
98 #define DESC_DPL_SHIFT 13
99 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
100 #define DESC_S_SHIFT 12
101 #define DESC_S_MASK (1 << DESC_S_SHIFT)
102 #define DESC_TYPE_SHIFT 8
103 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
104 #define DESC_A_MASK (1 << 8)
105
106 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
107 #define DESC_C_MASK (1 << 10) /* code: conforming */
108 #define DESC_R_MASK (1 << 9) /* code: readable */
109
110 #define DESC_E_MASK (1 << 10) /* data: expansion direction */
111 #define DESC_W_MASK (1 << 9) /* data: writable */
112
113 #define DESC_TSS_BUSY_MASK (1 << 9)
114
115 /* eflags masks */
116 #define CC_C 0x0001
117 #define CC_P 0x0004
118 #define CC_A 0x0010
119 #define CC_Z 0x0040
120 #define CC_S 0x0080
121 #define CC_O 0x0800
122
123 #define TF_SHIFT 8
124 #define IOPL_SHIFT 12
125 #define VM_SHIFT 17
126
127 #define TF_MASK 0x00000100
128 #define IF_MASK 0x00000200
129 #define DF_MASK 0x00000400
130 #define IOPL_MASK 0x00003000
131 #define NT_MASK 0x00004000
132 #define RF_MASK 0x00010000
133 #define VM_MASK 0x00020000
134 #define AC_MASK 0x00040000
135 #define VIF_MASK 0x00080000
136 #define VIP_MASK 0x00100000
137 #define ID_MASK 0x00200000
138
139 /* hidden flags - used internally by qemu to represent additional cpu
140 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We
141 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit
142 positions to ease oring with eflags. */
143 /* current cpl */
144 #define HF_CPL_SHIFT 0
145 /* true if hardware interrupts must be disabled for next instruction */
146 #define HF_INHIBIT_IRQ_SHIFT 3
147 /* 16 or 32 segments */
148 #define HF_CS32_SHIFT 4
149 #define HF_SS32_SHIFT 5
150 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
151 #define HF_ADDSEG_SHIFT 6
152 /* copy of CR0.PE (protected mode) */
153 #define HF_PE_SHIFT 7
154 #define HF_TF_SHIFT 8 /* must be same as eflags */
155 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
156 #define HF_EM_SHIFT 10
157 #define HF_TS_SHIFT 11
158 #define HF_IOPL_SHIFT 12 /* must be same as eflags */
159 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
160 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
161 #define HF_RF_SHIFT 16 /* must be same as eflags */
162 #define HF_VM_SHIFT 17 /* must be same as eflags */
163 #define HF_AC_SHIFT 18 /* must be same as eflags */
164 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */
165 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */
166 #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */
167 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */
168 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */
169 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */
170 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */
171 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */
172 #define HF_UMIP_SHIFT 27 /* CR4.UMIP */
173 #define HF_AVX_EN_SHIFT 28 /* AVX Enabled (CR4+XCR0) */
174
175 #define HF_CPL_MASK (3 << HF_CPL_SHIFT)
176 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
177 #define HF_CS32_MASK (1 << HF_CS32_SHIFT)
178 #define HF_SS32_MASK (1 << HF_SS32_SHIFT)
179 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
180 #define HF_PE_MASK (1 << HF_PE_SHIFT)
181 #define HF_TF_MASK (1 << HF_TF_SHIFT)
182 #define HF_MP_MASK (1 << HF_MP_SHIFT)
183 #define HF_EM_MASK (1 << HF_EM_SHIFT)
184 #define HF_TS_MASK (1 << HF_TS_SHIFT)
185 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
186 #define HF_LMA_MASK (1 << HF_LMA_SHIFT)
187 #define HF_CS64_MASK (1 << HF_CS64_SHIFT)
188 #define HF_RF_MASK (1 << HF_RF_SHIFT)
189 #define HF_VM_MASK (1 << HF_VM_SHIFT)
190 #define HF_AC_MASK (1 << HF_AC_SHIFT)
191 #define HF_SMM_MASK (1 << HF_SMM_SHIFT)
192 #define HF_SVME_MASK (1 << HF_SVME_SHIFT)
193 #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT)
194 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
195 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
196 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
197 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
198 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
199 #define HF_UMIP_MASK (1 << HF_UMIP_SHIFT)
200 #define HF_AVX_EN_MASK (1 << HF_AVX_EN_SHIFT)
201
202 /* hflags2 */
203
204 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
205 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */
206 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */
207 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */
208 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
209 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */
210 #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */
211 #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */
212 #define HF2_VGIF_SHIFT 8 /* Can take VIRQ*/
213
214 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
215 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
216 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
217 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
218 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
219 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
220 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT)
221 #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT)
222 #define HF2_VGIF_MASK (1 << HF2_VGIF_SHIFT)
223
224 #define CR0_PE_SHIFT 0
225 #define CR0_MP_SHIFT 1
226
227 #define CR0_PE_MASK (1U << 0)
228 #define CR0_MP_MASK (1U << 1)
229 #define CR0_EM_MASK (1U << 2)
230 #define CR0_TS_MASK (1U << 3)
231 #define CR0_ET_MASK (1U << 4)
232 #define CR0_NE_MASK (1U << 5)
233 #define CR0_WP_MASK (1U << 16)
234 #define CR0_AM_MASK (1U << 18)
235 #define CR0_NW_MASK (1U << 29)
236 #define CR0_CD_MASK (1U << 30)
237 #define CR0_PG_MASK (1U << 31)
238
239 #define CR4_VME_MASK (1U << 0)
240 #define CR4_PVI_MASK (1U << 1)
241 #define CR4_TSD_MASK (1U << 2)
242 #define CR4_DE_MASK (1U << 3)
243 #define CR4_PSE_MASK (1U << 4)
244 #define CR4_PAE_MASK (1U << 5)
245 #define CR4_MCE_MASK (1U << 6)
246 #define CR4_PGE_MASK (1U << 7)
247 #define CR4_PCE_MASK (1U << 8)
248 #define CR4_OSFXSR_SHIFT 9
249 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
250 #define CR4_OSXMMEXCPT_MASK (1U << 10)
251 #define CR4_UMIP_MASK (1U << 11)
252 #define CR4_LA57_MASK (1U << 12)
253 #define CR4_VMXE_MASK (1U << 13)
254 #define CR4_SMXE_MASK (1U << 14)
255 #define CR4_FSGSBASE_MASK (1U << 16)
256 #define CR4_PCIDE_MASK (1U << 17)
257 #define CR4_OSXSAVE_MASK (1U << 18)
258 #define CR4_SMEP_MASK (1U << 20)
259 #define CR4_SMAP_MASK (1U << 21)
260 #define CR4_PKE_MASK (1U << 22)
261 #define CR4_PKS_MASK (1U << 24)
262 #define CR4_LAM_SUP_MASK (1U << 28)
263
264 #ifdef TARGET_X86_64
265 #define CR4_FRED_MASK (1ULL << 32)
266 #else
267 #define CR4_FRED_MASK 0
268 #endif
269
270 #ifdef TARGET_X86_64
271 #define CR4_FRED_MASK (1ULL << 32)
272 #else
273 #define CR4_FRED_MASK 0
274 #endif
275
276 #define CR4_RESERVED_MASK \
277 (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \
278 | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \
279 | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \
280 | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \
281 | CR4_LA57_MASK \
282 | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \
283 | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK \
284 | CR4_LAM_SUP_MASK | CR4_FRED_MASK))
285
286 #define DR6_BD (1 << 13)
287 #define DR6_BS (1 << 14)
288 #define DR6_BT (1 << 15)
289 #define DR6_FIXED_1 0xffff0ff0
290
291 #define DR7_GD (1 << 13)
292 #define DR7_TYPE_SHIFT 16
293 #define DR7_LEN_SHIFT 18
294 #define DR7_FIXED_1 0x00000400
295 #define DR7_GLOBAL_BP_MASK 0xaa
296 #define DR7_LOCAL_BP_MASK 0x55
297 #define DR7_MAX_BP 4
298 #define DR7_TYPE_BP_INST 0x0
299 #define DR7_TYPE_DATA_WR 0x1
300 #define DR7_TYPE_IO_RW 0x2
301 #define DR7_TYPE_DATA_RW 0x3
302
303 #define DR_RESERVED_MASK 0xffffffff00000000ULL
304
305 #define PG_PRESENT_BIT 0
306 #define PG_RW_BIT 1
307 #define PG_USER_BIT 2
308 #define PG_PWT_BIT 3
309 #define PG_PCD_BIT 4
310 #define PG_ACCESSED_BIT 5
311 #define PG_DIRTY_BIT 6
312 #define PG_PSE_BIT 7
313 #define PG_GLOBAL_BIT 8
314 #define PG_PSE_PAT_BIT 12
315 #define PG_PKRU_BIT 59
316 #define PG_NX_BIT 63
317
318 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
319 #define PG_RW_MASK (1 << PG_RW_BIT)
320 #define PG_USER_MASK (1 << PG_USER_BIT)
321 #define PG_PWT_MASK (1 << PG_PWT_BIT)
322 #define PG_PCD_MASK (1 << PG_PCD_BIT)
323 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
324 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
325 #define PG_PSE_MASK (1 << PG_PSE_BIT)
326 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
327 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
328 #define PG_ADDRESS_MASK 0x000ffffffffff000LL
329 #define PG_HI_USER_MASK 0x7ff0000000000000LL
330 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
331 #define PG_NX_MASK (1ULL << PG_NX_BIT)
332
333 #define PG_ERROR_W_BIT 1
334
335 #define PG_ERROR_P_MASK 0x01
336 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
337 #define PG_ERROR_U_MASK 0x04
338 #define PG_ERROR_RSVD_MASK 0x08
339 #define PG_ERROR_I_D_MASK 0x10
340 #define PG_ERROR_PK_MASK 0x20
341
342 #define PG_MODE_PAE (1 << 0)
343 #define PG_MODE_LMA (1 << 1)
344 #define PG_MODE_NXE (1 << 2)
345 #define PG_MODE_PSE (1 << 3)
346 #define PG_MODE_LA57 (1 << 4)
347 #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15)
348
349 /* Bits of CR4 that do not affect the NPT page format. */
350 #define PG_MODE_WP (1 << 16)
351 #define PG_MODE_PKE (1 << 17)
352 #define PG_MODE_PKS (1 << 18)
353 #define PG_MODE_SMEP (1 << 19)
354
355 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
356 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
357 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */
358
359 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
360 #define MCE_BANKS_DEF 10
361
362 #define MCG_CAP_BANKS_MASK 0xff
363
364 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
365 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
366 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
367 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */
368
369 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */
370
371 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
372 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
373 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
374 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */
375 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
376 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
377 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
378 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
379 #define MCI_STATUS_AR (1ULL<<55) /* Action required */
380 #define MCI_STATUS_DEFERRED (1ULL<<44) /* Deferred error */
381 #define MCI_STATUS_POISON (1ULL<<43) /* Poisoned data consumed */
382
383 /* MISC register defines */
384 #define MCM_ADDR_SEGOFF 0 /* segment offset */
385 #define MCM_ADDR_LINEAR 1 /* linear address */
386 #define MCM_ADDR_PHYS 2 /* physical address */
387 #define MCM_ADDR_MEM 3 /* memory address */
388 #define MCM_ADDR_GENERIC 7 /* generic */
389
390 #define MSR_IA32_TSC 0x10
391 #define MSR_IA32_APICBASE 0x1b
392 #define MSR_IA32_APICBASE_BSP (1<<8)
393 #define MSR_IA32_APICBASE_ENABLE (1<<11)
394 #define MSR_IA32_APICBASE_EXTD (1 << 10)
395 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
396 #define MSR_IA32_APICBASE_RESERVED \
397 (~(uint64_t)(MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE \
398 | MSR_IA32_APICBASE_EXTD | MSR_IA32_APICBASE_BASE))
399
400 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
401 #define MSR_TSC_ADJUST 0x0000003b
402 #define MSR_IA32_SPEC_CTRL 0x48
403 #define MSR_VIRT_SSBD 0xc001011f
404 #define MSR_IA32_PRED_CMD 0x49
405 #define MSR_IA32_UCODE_REV 0x8b
406 #define MSR_IA32_CORE_CAPABILITY 0xcf
407
408 #define MSR_IA32_ARCH_CAPABILITIES 0x10a
409 #define ARCH_CAP_TSX_CTRL_MSR (1<<7)
410
411 #define MSR_IA32_PERF_CAPABILITIES 0x345
412 #define PERF_CAP_LBR_FMT 0x3f
413
414 #define MSR_IA32_TSX_CTRL 0x122
415 #define MSR_IA32_TSCDEADLINE 0x6e0
416 #define MSR_IA32_PKRS 0x6e1
417 #define MSR_RAPL_POWER_UNIT 0x00000606
418 #define MSR_PKG_POWER_LIMIT 0x00000610
419 #define MSR_PKG_ENERGY_STATUS 0x00000611
420 #define MSR_PKG_POWER_INFO 0x00000614
421 #define MSR_ARCH_LBR_CTL 0x000014ce
422 #define MSR_ARCH_LBR_DEPTH 0x000014cf
423 #define MSR_ARCH_LBR_FROM_0 0x00001500
424 #define MSR_ARCH_LBR_TO_0 0x00001600
425 #define MSR_ARCH_LBR_INFO_0 0x00001200
426
427 #define FEATURE_CONTROL_LOCKED (1<<0)
428 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1ULL << 1)
429 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
430 #define FEATURE_CONTROL_SGX_LC (1ULL << 17)
431 #define FEATURE_CONTROL_SGX (1ULL << 18)
432 #define FEATURE_CONTROL_LMCE (1<<20)
433
434 #define MSR_IA32_SGXLEPUBKEYHASH0 0x8c
435 #define MSR_IA32_SGXLEPUBKEYHASH1 0x8d
436 #define MSR_IA32_SGXLEPUBKEYHASH2 0x8e
437 #define MSR_IA32_SGXLEPUBKEYHASH3 0x8f
438
439 #define MSR_P6_PERFCTR0 0xc1
440
441 #define MSR_IA32_SMBASE 0x9e
442 #define MSR_SMI_COUNT 0x34
443 #define MSR_CORE_THREAD_COUNT 0x35
444 #define MSR_MTRRcap 0xfe
445 #define MSR_MTRRcap_VCNT 8
446 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
447 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
448
449 #define MSR_IA32_SYSENTER_CS 0x174
450 #define MSR_IA32_SYSENTER_ESP 0x175
451 #define MSR_IA32_SYSENTER_EIP 0x176
452
453 #define MSR_MCG_CAP 0x179
454 #define MSR_MCG_STATUS 0x17a
455 #define MSR_MCG_CTL 0x17b
456 #define MSR_MCG_EXT_CTL 0x4d0
457
458 #define MSR_P6_EVNTSEL0 0x186
459
460 #define MSR_IA32_PERF_STATUS 0x198
461
462 #define MSR_IA32_MISC_ENABLE 0x1a0
463 /* Indicates good rep/movs microcode on some processors: */
464 #define MSR_IA32_MISC_ENABLE_DEFAULT 1
465 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
466
467 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
468 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
469
470 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
471
472 #define MSR_MTRRfix64K_00000 0x250
473 #define MSR_MTRRfix16K_80000 0x258
474 #define MSR_MTRRfix16K_A0000 0x259
475 #define MSR_MTRRfix4K_C0000 0x268
476 #define MSR_MTRRfix4K_C8000 0x269
477 #define MSR_MTRRfix4K_D0000 0x26a
478 #define MSR_MTRRfix4K_D8000 0x26b
479 #define MSR_MTRRfix4K_E0000 0x26c
480 #define MSR_MTRRfix4K_E8000 0x26d
481 #define MSR_MTRRfix4K_F0000 0x26e
482 #define MSR_MTRRfix4K_F8000 0x26f
483
484 #define MSR_PAT 0x277
485
486 #define MSR_MTRRdefType 0x2ff
487
488 #define MSR_CORE_PERF_FIXED_CTR0 0x309
489 #define MSR_CORE_PERF_FIXED_CTR1 0x30a
490 #define MSR_CORE_PERF_FIXED_CTR2 0x30b
491 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
492 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
493 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
494 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
495
496 #define MSR_MC0_CTL 0x400
497 #define MSR_MC0_STATUS 0x401
498 #define MSR_MC0_ADDR 0x402
499 #define MSR_MC0_MISC 0x403
500
501 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560
502 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561
503 #define MSR_IA32_RTIT_CTL 0x570
504 #define MSR_IA32_RTIT_STATUS 0x571
505 #define MSR_IA32_RTIT_CR3_MATCH 0x572
506 #define MSR_IA32_RTIT_ADDR0_A 0x580
507 #define MSR_IA32_RTIT_ADDR0_B 0x581
508 #define MSR_IA32_RTIT_ADDR1_A 0x582
509 #define MSR_IA32_RTIT_ADDR1_B 0x583
510 #define MSR_IA32_RTIT_ADDR2_A 0x584
511 #define MSR_IA32_RTIT_ADDR2_B 0x585
512 #define MSR_IA32_RTIT_ADDR3_A 0x586
513 #define MSR_IA32_RTIT_ADDR3_B 0x587
514 #define MAX_RTIT_ADDRS 8
515
516 #define MSR_EFER 0xc0000080
517
518 #define MSR_EFER_SCE (1 << 0)
519 #define MSR_EFER_LME (1 << 8)
520 #define MSR_EFER_LMA (1 << 10)
521 #define MSR_EFER_NXE (1 << 11)
522 #define MSR_EFER_SVME (1 << 12)
523 #define MSR_EFER_FFXSR (1 << 14)
524
525 #define MSR_EFER_RESERVED\
526 (~(target_ulong)(MSR_EFER_SCE | MSR_EFER_LME\
527 | MSR_EFER_LMA | MSR_EFER_NXE | MSR_EFER_SVME\
528 | MSR_EFER_FFXSR))
529
530 #define MSR_STAR 0xc0000081
531 #define MSR_LSTAR 0xc0000082
532 #define MSR_CSTAR 0xc0000083
533 #define MSR_FMASK 0xc0000084
534 #define MSR_FSBASE 0xc0000100
535 #define MSR_GSBASE 0xc0000101
536 #define MSR_KERNELGSBASE 0xc0000102
537 #define MSR_TSC_AUX 0xc0000103
538 #define MSR_AMD64_TSC_RATIO 0xc0000104
539
540 #define MSR_AMD64_TSC_RATIO_DEFAULT 0x100000000ULL
541
542 #define MSR_VM_HSAVE_PA 0xc0010117
543
544 #define MSR_IA32_XFD 0x000001c4
545 #define MSR_IA32_XFD_ERR 0x000001c5
546
547 /* FRED MSRs */
548 #define MSR_IA32_FRED_RSP0 0x000001cc /* Stack level 0 regular stack pointer */
549 #define MSR_IA32_FRED_RSP1 0x000001cd /* Stack level 1 regular stack pointer */
550 #define MSR_IA32_FRED_RSP2 0x000001ce /* Stack level 2 regular stack pointer */
551 #define MSR_IA32_FRED_RSP3 0x000001cf /* Stack level 3 regular stack pointer */
552 #define MSR_IA32_FRED_STKLVLS 0x000001d0 /* FRED exception stack levels */
553 #define MSR_IA32_FRED_SSP1 0x000001d1 /* Stack level 1 shadow stack pointer in ring 0 */
554 #define MSR_IA32_FRED_SSP2 0x000001d2 /* Stack level 2 shadow stack pointer in ring 0 */
555 #define MSR_IA32_FRED_SSP3 0x000001d3 /* Stack level 3 shadow stack pointer in ring 0 */
556 #define MSR_IA32_FRED_CONFIG 0x000001d4 /* FRED Entrypoint and interrupt stack level */
557
558 #define MSR_IA32_BNDCFGS 0x00000d90
559 #define MSR_IA32_XSS 0x00000da0
560 #define MSR_IA32_UMWAIT_CONTROL 0xe1
561
562 #define MSR_IA32_VMX_BASIC 0x00000480
563 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
564 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
565 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
566 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
567 #define MSR_IA32_VMX_MISC 0x00000485
568 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
569 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
570 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
571 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
572 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
573 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
574 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
575 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
576 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
577 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
578 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
579 #define MSR_IA32_VMX_VMFUNC 0x00000491
580
581 #define MSR_APIC_START 0x00000800
582 #define MSR_APIC_END 0x000008ff
583
584 #define XSTATE_FP_BIT 0
585 #define XSTATE_SSE_BIT 1
586 #define XSTATE_YMM_BIT 2
587 #define XSTATE_BNDREGS_BIT 3
588 #define XSTATE_BNDCSR_BIT 4
589 #define XSTATE_OPMASK_BIT 5
590 #define XSTATE_ZMM_Hi256_BIT 6
591 #define XSTATE_Hi16_ZMM_BIT 7
592 #define XSTATE_PKRU_BIT 9
593 #define XSTATE_ARCH_LBR_BIT 15
594 #define XSTATE_XTILE_CFG_BIT 17
595 #define XSTATE_XTILE_DATA_BIT 18
596
597 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
598 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
599 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
600 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
601 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
602 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
603 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
604 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
605 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
606 #define XSTATE_ARCH_LBR_MASK (1ULL << XSTATE_ARCH_LBR_BIT)
607 #define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT)
608 #define XSTATE_XTILE_DATA_MASK (1ULL << XSTATE_XTILE_DATA_BIT)
609
610 #define XSTATE_DYNAMIC_MASK (XSTATE_XTILE_DATA_MASK)
611
612 #define ESA_FEATURE_ALIGN64_BIT 1
613 #define ESA_FEATURE_XFD_BIT 2
614
615 #define ESA_FEATURE_ALIGN64_MASK (1U << ESA_FEATURE_ALIGN64_BIT)
616 #define ESA_FEATURE_XFD_MASK (1U << ESA_FEATURE_XFD_BIT)
617
618
619 /* CPUID feature bits available in XCR0 */
620 #define CPUID_XSTATE_XCR0_MASK (XSTATE_FP_MASK | XSTATE_SSE_MASK | \
621 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | \
622 XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | \
623 XSTATE_ZMM_Hi256_MASK | \
624 XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK | \
625 XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_MASK)
626
627 /* CPUID feature words */
628 typedef enum FeatureWord {
629 FEAT_1_EDX, /* CPUID[1].EDX */
630 FEAT_1_ECX, /* CPUID[1].ECX */
631 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */
632 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */
633 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */
634 FEAT_7_1_EAX, /* CPUID[EAX=7,ECX=1].EAX */
635 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
636 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
637 FEAT_8000_0007_EBX, /* CPUID[8000_0007].EBX */
638 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
639 FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */
640 FEAT_8000_0021_EAX, /* CPUID[8000_0021].EAX */
641 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
642 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
643 FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */
644 FEAT_SVM, /* CPUID[8000_000A].EDX */
645 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */
646 FEAT_6_EAX, /* CPUID[6].EAX */
647 FEAT_XSAVE_XCR0_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
648 FEAT_XSAVE_XCR0_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
649 FEAT_ARCH_CAPABILITIES,
650 FEAT_CORE_CAPABILITY,
651 FEAT_PERF_CAPABILITIES,
652 FEAT_VMX_PROCBASED_CTLS,
653 FEAT_VMX_SECONDARY_CTLS,
654 FEAT_VMX_PINBASED_CTLS,
655 FEAT_VMX_EXIT_CTLS,
656 FEAT_VMX_ENTRY_CTLS,
657 FEAT_VMX_MISC,
658 FEAT_VMX_EPT_VPID_CAPS,
659 FEAT_VMX_BASIC,
660 FEAT_VMX_VMFUNC,
661 FEAT_14_0_ECX,
662 FEAT_SGX_12_0_EAX, /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */
663 FEAT_SGX_12_0_EBX, /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */
664 FEAT_SGX_12_1_EAX, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */
665 FEAT_XSAVE_XSS_LO, /* CPUID[EAX=0xd,ECX=1].ECX */
666 FEAT_XSAVE_XSS_HI, /* CPUID[EAX=0xd,ECX=1].EDX */
667 FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */
668 FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */
669 FEATURE_WORDS,
670 } FeatureWord;
671
672 typedef uint64_t FeatureWordArray[FEATURE_WORDS];
673 uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
674
675 /* cpuid_features bits */
676 #define CPUID_FP87 (1U << 0)
677 #define CPUID_VME (1U << 1)
678 #define CPUID_DE (1U << 2)
679 #define CPUID_PSE (1U << 3)
680 #define CPUID_TSC (1U << 4)
681 #define CPUID_MSR (1U << 5)
682 #define CPUID_PAE (1U << 6)
683 #define CPUID_MCE (1U << 7)
684 #define CPUID_CX8 (1U << 8)
685 #define CPUID_APIC (1U << 9)
686 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */
687 #define CPUID_MTRR (1U << 12)
688 #define CPUID_PGE (1U << 13)
689 #define CPUID_MCA (1U << 14)
690 #define CPUID_CMOV (1U << 15)
691 #define CPUID_PAT (1U << 16)
692 #define CPUID_PSE36 (1U << 17)
693 #define CPUID_PN (1U << 18)
694 #define CPUID_CLFLUSH (1U << 19)
695 #define CPUID_DTS (1U << 21)
696 #define CPUID_ACPI (1U << 22)
697 #define CPUID_MMX (1U << 23)
698 #define CPUID_FXSR (1U << 24)
699 #define CPUID_SSE (1U << 25)
700 #define CPUID_SSE2 (1U << 26)
701 #define CPUID_SS (1U << 27)
702 #define CPUID_HT (1U << 28)
703 #define CPUID_TM (1U << 29)
704 #define CPUID_IA64 (1U << 30)
705 #define CPUID_PBE (1U << 31)
706
707 #define CPUID_EXT_SSE3 (1U << 0)
708 #define CPUID_EXT_PCLMULQDQ (1U << 1)
709 #define CPUID_EXT_DTES64 (1U << 2)
710 #define CPUID_EXT_MONITOR (1U << 3)
711 #define CPUID_EXT_DSCPL (1U << 4)
712 #define CPUID_EXT_VMX (1U << 5)
713 #define CPUID_EXT_SMX (1U << 6)
714 #define CPUID_EXT_EST (1U << 7)
715 #define CPUID_EXT_TM2 (1U << 8)
716 #define CPUID_EXT_SSSE3 (1U << 9)
717 #define CPUID_EXT_CID (1U << 10)
718 #define CPUID_EXT_FMA (1U << 12)
719 #define CPUID_EXT_CX16 (1U << 13)
720 #define CPUID_EXT_XTPR (1U << 14)
721 #define CPUID_EXT_PDCM (1U << 15)
722 #define CPUID_EXT_PCID (1U << 17)
723 #define CPUID_EXT_DCA (1U << 18)
724 #define CPUID_EXT_SSE41 (1U << 19)
725 #define CPUID_EXT_SSE42 (1U << 20)
726 #define CPUID_EXT_X2APIC (1U << 21)
727 #define CPUID_EXT_MOVBE (1U << 22)
728 #define CPUID_EXT_POPCNT (1U << 23)
729 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
730 #define CPUID_EXT_AES (1U << 25)
731 #define CPUID_EXT_XSAVE (1U << 26)
732 #define CPUID_EXT_OSXSAVE (1U << 27)
733 #define CPUID_EXT_AVX (1U << 28)
734 #define CPUID_EXT_F16C (1U << 29)
735 #define CPUID_EXT_RDRAND (1U << 30)
736 #define CPUID_EXT_HYPERVISOR (1U << 31)
737
738 #define CPUID_EXT2_FPU (1U << 0)
739 #define CPUID_EXT2_VME (1U << 1)
740 #define CPUID_EXT2_DE (1U << 2)
741 #define CPUID_EXT2_PSE (1U << 3)
742 #define CPUID_EXT2_TSC (1U << 4)
743 #define CPUID_EXT2_MSR (1U << 5)
744 #define CPUID_EXT2_PAE (1U << 6)
745 #define CPUID_EXT2_MCE (1U << 7)
746 #define CPUID_EXT2_CX8 (1U << 8)
747 #define CPUID_EXT2_APIC (1U << 9)
748 #define CPUID_EXT2_SYSCALL (1U << 11)
749 #define CPUID_EXT2_MTRR (1U << 12)
750 #define CPUID_EXT2_PGE (1U << 13)
751 #define CPUID_EXT2_MCA (1U << 14)
752 #define CPUID_EXT2_CMOV (1U << 15)
753 #define CPUID_EXT2_PAT (1U << 16)
754 #define CPUID_EXT2_PSE36 (1U << 17)
755 #define CPUID_EXT2_MP (1U << 19)
756 #define CPUID_EXT2_NX (1U << 20)
757 #define CPUID_EXT2_MMXEXT (1U << 22)
758 #define CPUID_EXT2_MMX (1U << 23)
759 #define CPUID_EXT2_FXSR (1U << 24)
760 #define CPUID_EXT2_FFXSR (1U << 25)
761 #define CPUID_EXT2_PDPE1GB (1U << 26)
762 #define CPUID_EXT2_RDTSCP (1U << 27)
763 #define CPUID_EXT2_LM (1U << 29)
764 #define CPUID_EXT2_3DNOWEXT (1U << 30)
765 #define CPUID_EXT2_3DNOW (1U << 31)
766
767 /* CPUID[8000_0001].EDX bits that are aliases of CPUID[1].EDX bits on AMD CPUs */
768 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
769 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
770 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
771 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
772 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
773 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
774 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
775 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
776 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
777
778 #define CPUID_EXT3_LAHF_LM (1U << 0)
779 #define CPUID_EXT3_CMP_LEG (1U << 1)
780 #define CPUID_EXT3_SVM (1U << 2)
781 #define CPUID_EXT3_EXTAPIC (1U << 3)
782 #define CPUID_EXT3_CR8LEG (1U << 4)
783 #define CPUID_EXT3_ABM (1U << 5)
784 #define CPUID_EXT3_SSE4A (1U << 6)
785 #define CPUID_EXT3_MISALIGNSSE (1U << 7)
786 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
787 #define CPUID_EXT3_OSVW (1U << 9)
788 #define CPUID_EXT3_IBS (1U << 10)
789 #define CPUID_EXT3_XOP (1U << 11)
790 #define CPUID_EXT3_SKINIT (1U << 12)
791 #define CPUID_EXT3_WDT (1U << 13)
792 #define CPUID_EXT3_LWP (1U << 15)
793 #define CPUID_EXT3_FMA4 (1U << 16)
794 #define CPUID_EXT3_TCE (1U << 17)
795 #define CPUID_EXT3_NODEID (1U << 19)
796 #define CPUID_EXT3_TBM (1U << 21)
797 #define CPUID_EXT3_TOPOEXT (1U << 22)
798 #define CPUID_EXT3_PERFCORE (1U << 23)
799 #define CPUID_EXT3_PERFNB (1U << 24)
800
801 #define CPUID_SVM_NPT (1U << 0)
802 #define CPUID_SVM_LBRV (1U << 1)
803 #define CPUID_SVM_SVMLOCK (1U << 2)
804 #define CPUID_SVM_NRIPSAVE (1U << 3)
805 #define CPUID_SVM_TSCSCALE (1U << 4)
806 #define CPUID_SVM_VMCBCLEAN (1U << 5)
807 #define CPUID_SVM_FLUSHASID (1U << 6)
808 #define CPUID_SVM_DECODEASSIST (1U << 7)
809 #define CPUID_SVM_PAUSEFILTER (1U << 10)
810 #define CPUID_SVM_PFTHRESHOLD (1U << 12)
811 #define CPUID_SVM_AVIC (1U << 13)
812 #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15)
813 #define CPUID_SVM_VGIF (1U << 16)
814 #define CPUID_SVM_VNMI (1U << 25)
815 #define CPUID_SVM_SVME_ADDR_CHK (1U << 28)
816
817 /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
818 #define CPUID_7_0_EBX_FSGSBASE (1U << 0)
819 /* Support TSC adjust MSR */
820 #define CPUID_7_0_EBX_TSC_ADJUST (1U << 1)
821 /* Support SGX */
822 #define CPUID_7_0_EBX_SGX (1U << 2)
823 /* 1st Group of Advanced Bit Manipulation Extensions */
824 #define CPUID_7_0_EBX_BMI1 (1U << 3)
825 /* Hardware Lock Elision */
826 #define CPUID_7_0_EBX_HLE (1U << 4)
827 /* Intel Advanced Vector Extensions 2 */
828 #define CPUID_7_0_EBX_AVX2 (1U << 5)
829 /* Supervisor-mode Execution Prevention */
830 #define CPUID_7_0_EBX_SMEP (1U << 7)
831 /* 2nd Group of Advanced Bit Manipulation Extensions */
832 #define CPUID_7_0_EBX_BMI2 (1U << 8)
833 /* Enhanced REP MOVSB/STOSB */
834 #define CPUID_7_0_EBX_ERMS (1U << 9)
835 /* Invalidate Process-Context Identifier */
836 #define CPUID_7_0_EBX_INVPCID (1U << 10)
837 /* Restricted Transactional Memory */
838 #define CPUID_7_0_EBX_RTM (1U << 11)
839 /* Memory Protection Extension */
840 #define CPUID_7_0_EBX_MPX (1U << 14)
841 /* AVX-512 Foundation */
842 #define CPUID_7_0_EBX_AVX512F (1U << 16)
843 /* AVX-512 Doubleword & Quadword Instruction */
844 #define CPUID_7_0_EBX_AVX512DQ (1U << 17)
845 /* Read Random SEED */
846 #define CPUID_7_0_EBX_RDSEED (1U << 18)
847 /* ADCX and ADOX instructions */
848 #define CPUID_7_0_EBX_ADX (1U << 19)
849 /* Supervisor Mode Access Prevention */
850 #define CPUID_7_0_EBX_SMAP (1U << 20)
851 /* AVX-512 Integer Fused Multiply Add */
852 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
853 /* Flush a Cache Line Optimized */
854 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
855 /* Cache Line Write Back */
856 #define CPUID_7_0_EBX_CLWB (1U << 24)
857 /* Intel Processor Trace */
858 #define CPUID_7_0_EBX_INTEL_PT (1U << 25)
859 /* AVX-512 Prefetch */
860 #define CPUID_7_0_EBX_AVX512PF (1U << 26)
861 /* AVX-512 Exponential and Reciprocal */
862 #define CPUID_7_0_EBX_AVX512ER (1U << 27)
863 /* AVX-512 Conflict Detection */
864 #define CPUID_7_0_EBX_AVX512CD (1U << 28)
865 /* SHA1/SHA256 Instruction Extensions */
866 #define CPUID_7_0_EBX_SHA_NI (1U << 29)
867 /* AVX-512 Byte and Word Instructions */
868 #define CPUID_7_0_EBX_AVX512BW (1U << 30)
869 /* AVX-512 Vector Length Extensions */
870 #define CPUID_7_0_EBX_AVX512VL (1U << 31)
871
872 /* AVX-512 Vector Byte Manipulation Instruction */
873 #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1)
874 /* User-Mode Instruction Prevention */
875 #define CPUID_7_0_ECX_UMIP (1U << 2)
876 /* Protection Keys for User-mode Pages */
877 #define CPUID_7_0_ECX_PKU (1U << 3)
878 /* OS Enable Protection Keys */
879 #define CPUID_7_0_ECX_OSPKE (1U << 4)
880 /* UMONITOR/UMWAIT/TPAUSE Instructions */
881 #define CPUID_7_0_ECX_WAITPKG (1U << 5)
882 /* Additional AVX-512 Vector Byte Manipulation Instruction */
883 #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6)
884 /* Galois Field New Instructions */
885 #define CPUID_7_0_ECX_GFNI (1U << 8)
886 /* Vector AES Instructions */
887 #define CPUID_7_0_ECX_VAES (1U << 9)
888 /* Carry-Less Multiplication Quadword */
889 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
890 /* Vector Neural Network Instructions */
891 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
892 /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */
893 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
894 /* POPCNT for vectors of DW/QW */
895 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14)
896 /* 5-level Page Tables */
897 #define CPUID_7_0_ECX_LA57 (1U << 16)
898 /* Read Processor ID */
899 #define CPUID_7_0_ECX_RDPID (1U << 22)
900 /* Bus Lock Debug Exception */
901 #define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24)
902 /* Cache Line Demote Instruction */
903 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25)
904 /* Move Doubleword as Direct Store Instruction */
905 #define CPUID_7_0_ECX_MOVDIRI (1U << 27)
906 /* Move 64 Bytes as Direct Store Instruction */
907 #define CPUID_7_0_ECX_MOVDIR64B (1U << 28)
908 /* Support SGX Launch Control */
909 #define CPUID_7_0_ECX_SGX_LC (1U << 30)
910 /* Protection Keys for Supervisor-mode Pages */
911 #define CPUID_7_0_ECX_PKS (1U << 31)
912
913 /* AVX512 Neural Network Instructions */
914 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
915 /* AVX512 Multiply Accumulation Single Precision */
916 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
917 /* Fast Short Rep Mov */
918 #define CPUID_7_0_EDX_FSRM (1U << 4)
919 /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */
920 #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)
921 /* SERIALIZE instruction */
922 #define CPUID_7_0_EDX_SERIALIZE (1U << 14)
923 /* TSX Suspend Load Address Tracking instruction */
924 #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
925 /* Architectural LBRs */
926 #define CPUID_7_0_EDX_ARCH_LBR (1U << 19)
927 /* AMX_BF16 instruction */
928 #define CPUID_7_0_EDX_AMX_BF16 (1U << 22)
929 /* AVX512_FP16 instruction */
930 #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23)
931 /* AMX tile (two-dimensional register) */
932 #define CPUID_7_0_EDX_AMX_TILE (1U << 24)
933 /* AMX_INT8 instruction */
934 #define CPUID_7_0_EDX_AMX_INT8 (1U << 25)
935 /* Speculation Control */
936 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
937 /* Single Thread Indirect Branch Predictors */
938 #define CPUID_7_0_EDX_STIBP (1U << 27)
939 /* Flush L1D cache */
940 #define CPUID_7_0_EDX_FLUSH_L1D (1U << 28)
941 /* Arch Capabilities */
942 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
943 /* Core Capability */
944 #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30)
945 /* Speculative Store Bypass Disable */
946 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
947
948 /* AVX VNNI Instruction */
949 #define CPUID_7_1_EAX_AVX_VNNI (1U << 4)
950 /* AVX512 BFloat16 Instruction */
951 #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
952 /* CMPCCXADD Instructions */
953 #define CPUID_7_1_EAX_CMPCCXADD (1U << 7)
954 /* Fast Zero REP MOVS */
955 #define CPUID_7_1_EAX_FZRM (1U << 10)
956 /* Fast Short REP STOS */
957 #define CPUID_7_1_EAX_FSRS (1U << 11)
958 /* Fast Short REP CMPS/SCAS */
959 #define CPUID_7_1_EAX_FSRC (1U << 12)
960 /* Support Tile Computational Operations on FP16 Numbers */
961 #define CPUID_7_1_EAX_AMX_FP16 (1U << 21)
962 /* Support for VPMADD52[H,L]UQ */
963 #define CPUID_7_1_EAX_AVX_IFMA (1U << 23)
964 /* Linear Address Masking */
965 #define CPUID_7_1_EAX_LAM (1U << 26)
966
967 /* Support for VPDPB[SU,UU,SS]D[,S] */
968 #define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4)
969 /* AVX NE CONVERT Instructions */
970 #define CPUID_7_1_EDX_AVX_NE_CONVERT (1U << 5)
971 /* AMX COMPLEX Instructions */
972 #define CPUID_7_1_EDX_AMX_COMPLEX (1U << 8)
973 /* PREFETCHIT0/1 Instructions */
974 #define CPUID_7_1_EDX_PREFETCHITI (1U << 14)
975 /* Flexible return and event delivery (FRED) */
976 #define CPUID_7_1_EAX_FRED (1U << 17)
977 /* Load into IA32_KERNEL_GS_BASE (LKGS) */
978 #define CPUID_7_1_EAX_LKGS (1U << 18)
979 /* Non-Serializing Write to Model Specific Register (WRMSRNS) */
980 #define CPUID_7_1_EAX_WRMSRNS (1U << 19)
981
982 /* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */
983 #define CPUID_7_2_EDX_MCDT_NO (1U << 5)
984
985 /* XFD Extend Feature Disabled */
986 #define CPUID_D_1_EAX_XFD (1U << 4)
987
988 /* Packets which contain IP payload have LIP values */
989 #define CPUID_14_0_ECX_LIP (1U << 31)
990
991 /* RAS Features */
992 #define CPUID_8000_0007_EBX_OVERFLOW_RECOV (1U << 0)
993 #define CPUID_8000_0007_EBX_SUCCOR (1U << 1)
994
995 /* CLZERO instruction */
996 #define CPUID_8000_0008_EBX_CLZERO (1U << 0)
997 /* Always save/restore FP error pointers */
998 #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2)
999 /* Write back and do not invalidate cache */
1000 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
1001 /* Indirect Branch Prediction Barrier */
1002 #define CPUID_8000_0008_EBX_IBPB (1U << 12)
1003 /* Indirect Branch Restricted Speculation */
1004 #define CPUID_8000_0008_EBX_IBRS (1U << 14)
1005 /* Single Thread Indirect Branch Predictors */
1006 #define CPUID_8000_0008_EBX_STIBP (1U << 15)
1007 /* STIBP mode has enhanced performance and may be left always on */
1008 #define CPUID_8000_0008_EBX_STIBP_ALWAYS_ON (1U << 17)
1009 /* Speculative Store Bypass Disable */
1010 #define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24)
1011 /* Paravirtualized Speculative Store Bypass Disable MSR */
1012 #define CPUID_8000_0008_EBX_VIRT_SSBD (1U << 25)
1013 /* Predictive Store Forwarding Disable */
1014 #define CPUID_8000_0008_EBX_AMD_PSFD (1U << 28)
1015
1016 /* Processor ignores nested data breakpoints */
1017 #define CPUID_8000_0021_EAX_No_NESTED_DATA_BP (1U << 0)
1018 /* LFENCE is always serializing */
1019 #define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2)
1020 /* Null Selector Clears Base */
1021 #define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE (1U << 6)
1022 /* Automatic IBRS */
1023 #define CPUID_8000_0021_EAX_AUTO_IBRS (1U << 8)
1024
1025 #define CPUID_XSAVE_XSAVEOPT (1U << 0)
1026 #define CPUID_XSAVE_XSAVEC (1U << 1)
1027 #define CPUID_XSAVE_XGETBV1 (1U << 2)
1028 #define CPUID_XSAVE_XSAVES (1U << 3)
1029
1030 #define CPUID_6_EAX_ARAT (1U << 2)
1031
1032 /* CPUID[0x80000007].EDX flags: */
1033 #define CPUID_APM_INVTSC (1U << 8)
1034
1035 #define CPUID_VENDOR_SZ 12
1036
1037 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
1038 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
1039 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
1040 #define CPUID_VENDOR_INTEL "GenuineIntel"
1041
1042 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */
1043 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
1044 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
1045 #define CPUID_VENDOR_AMD "AuthenticAMD"
1046
1047 #define CPUID_VENDOR_VIA "CentaurHauls"
1048
1049 #define CPUID_VENDOR_HYGON "HygonGenuine"
1050
1051 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
1052 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
1053 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
1054 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
1055 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
1056 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
1057
1058 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */
1059 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */
1060
1061 /* CPUID[0xB].ECX level types */
1062 #define CPUID_B_ECX_TOPO_LEVEL_INVALID 0
1063 #define CPUID_B_ECX_TOPO_LEVEL_SMT 1
1064 #define CPUID_B_ECX_TOPO_LEVEL_CORE 2
1065
1066 /* COUID[0x1F].ECX level types */
1067 #define CPUID_1F_ECX_TOPO_LEVEL_INVALID CPUID_B_ECX_TOPO_LEVEL_INVALID
1068 #define CPUID_1F_ECX_TOPO_LEVEL_SMT CPUID_B_ECX_TOPO_LEVEL_SMT
1069 #define CPUID_1F_ECX_TOPO_LEVEL_CORE CPUID_B_ECX_TOPO_LEVEL_CORE
1070 #define CPUID_1F_ECX_TOPO_LEVEL_MODULE 3
1071 #define CPUID_1F_ECX_TOPO_LEVEL_DIE 5
1072
1073 /* MSR Feature Bits */
1074 #define MSR_ARCH_CAP_RDCL_NO (1U << 0)
1075 #define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
1076 #define MSR_ARCH_CAP_RSBA (1U << 2)
1077 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
1078 #define MSR_ARCH_CAP_SSB_NO (1U << 4)
1079 #define MSR_ARCH_CAP_MDS_NO (1U << 5)
1080 #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6)
1081 #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7)
1082 #define MSR_ARCH_CAP_TAA_NO (1U << 8)
1083 #define MSR_ARCH_CAP_SBDR_SSDP_NO (1U << 13)
1084 #define MSR_ARCH_CAP_FBSDP_NO (1U << 14)
1085 #define MSR_ARCH_CAP_PSDP_NO (1U << 15)
1086 #define MSR_ARCH_CAP_FB_CLEAR (1U << 17)
1087 #define MSR_ARCH_CAP_PBRSB_NO (1U << 24)
1088
1089 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
1090
1091 /* VMX MSR features */
1092 #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull
1093 #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32)
1094 #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32)
1095 #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49)
1096 #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54)
1097 #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55)
1098 #define MSR_VMX_BASIC_ANY_ERRCODE (1ULL << 56)
1099 #define MSR_VMX_BASIC_NESTED_EXCEPTION (1ULL << 58)
1100
1101 #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full
1102 #define MSR_VMX_MISC_STORE_LMA (1ULL << 5)
1103 #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6)
1104 #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7)
1105 #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8)
1106 #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull
1107 #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29)
1108 #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30)
1109
1110 #define MSR_VMX_EPT_EXECONLY (1ULL << 0)
1111 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6)
1112 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7)
1113 #define MSR_VMX_EPT_UC (1ULL << 8)
1114 #define MSR_VMX_EPT_WB (1ULL << 14)
1115 #define MSR_VMX_EPT_2MB (1ULL << 16)
1116 #define MSR_VMX_EPT_1GB (1ULL << 17)
1117 #define MSR_VMX_EPT_INVEPT (1ULL << 20)
1118 #define MSR_VMX_EPT_AD_BITS (1ULL << 21)
1119 #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22)
1120 #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25)
1121 #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26)
1122 #define MSR_VMX_EPT_INVVPID (1ULL << 32)
1123 #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40)
1124 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41)
1125 #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42)
1126 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43)
1127
1128 #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0)
1129
1130
1131 /* VMX controls */
1132 #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
1133 #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008
1134 #define VMX_CPU_BASED_HLT_EXITING 0x00000080
1135 #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200
1136 #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400
1137 #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800
1138 #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000
1139 #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000
1140 #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000
1141 #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000
1142 #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000
1143 #define VMX_CPU_BASED_TPR_SHADOW 0x00200000
1144 #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
1145 #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000
1146 #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000
1147 #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000
1148 #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
1149 #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000
1150 #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000
1151 #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000
1152 #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
1153
1154 #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
1155 #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002
1156 #define VMX_SECONDARY_EXEC_DESC 0x00000004
1157 #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008
1158 #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
1159 #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020
1160 #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040
1161 #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
1162 #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
1163 #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
1164 #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
1165 #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800
1166 #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
1167 #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000
1168 #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000
1169 #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000
1170 #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000
1171 #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000
1172 #define VMX_SECONDARY_EXEC_XSAVES 0x00100000
1173 #define VMX_SECONDARY_EXEC_TSC_SCALING 0x02000000
1174 #define VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE 0x04000000
1175
1176 #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001
1177 #define VMX_PIN_BASED_NMI_EXITING 0x00000008
1178 #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020
1179 #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
1180 #define VMX_PIN_BASED_POSTED_INTR 0x00000080
1181
1182 #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
1183 #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
1184 #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
1185 #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
1186 #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000
1187 #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000
1188 #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000
1189 #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000
1190 #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
1191 #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000
1192 #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000
1193 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
1194 #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000
1195
1196 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
1197 #define VMX_VM_ENTRY_IA32E_MODE 0x00000200
1198 #define VMX_VM_ENTRY_SMM 0x00000400
1199 #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
1200 #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
1201 #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000
1202 #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000
1203 #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000
1204 #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000
1205 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
1206 #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000
1207
1208 /* Supported Hyper-V Enlightenments */
1209 #define HYPERV_FEAT_RELAXED 0
1210 #define HYPERV_FEAT_VAPIC 1
1211 #define HYPERV_FEAT_TIME 2
1212 #define HYPERV_FEAT_CRASH 3
1213 #define HYPERV_FEAT_RESET 4
1214 #define HYPERV_FEAT_VPINDEX 5
1215 #define HYPERV_FEAT_RUNTIME 6
1216 #define HYPERV_FEAT_SYNIC 7
1217 #define HYPERV_FEAT_STIMER 8
1218 #define HYPERV_FEAT_FREQUENCIES 9
1219 #define HYPERV_FEAT_REENLIGHTENMENT 10
1220 #define HYPERV_FEAT_TLBFLUSH 11
1221 #define HYPERV_FEAT_EVMCS 12
1222 #define HYPERV_FEAT_IPI 13
1223 #define HYPERV_FEAT_STIMER_DIRECT 14
1224 #define HYPERV_FEAT_AVIC 15
1225 #define HYPERV_FEAT_SYNDBG 16
1226 #define HYPERV_FEAT_MSR_BITMAP 17
1227 #define HYPERV_FEAT_XMM_INPUT 18
1228 #define HYPERV_FEAT_TLBFLUSH_EXT 19
1229 #define HYPERV_FEAT_TLBFLUSH_DIRECT 20
1230
1231 #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY
1232 #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF
1233 #endif
1234
1235 #define EXCP00_DIVZ 0
1236 #define EXCP01_DB 1
1237 #define EXCP02_NMI 2
1238 #define EXCP03_INT3 3
1239 #define EXCP04_INTO 4
1240 #define EXCP05_BOUND 5
1241 #define EXCP06_ILLOP 6
1242 #define EXCP07_PREX 7
1243 #define EXCP08_DBLE 8
1244 #define EXCP09_XERR 9
1245 #define EXCP0A_TSS 10
1246 #define EXCP0B_NOSEG 11
1247 #define EXCP0C_STACK 12
1248 #define EXCP0D_GPF 13
1249 #define EXCP0E_PAGE 14
1250 #define EXCP10_COPR 16
1251 #define EXCP11_ALGN 17
1252 #define EXCP12_MCHK 18
1253
1254 #define EXCP_VMEXIT 0x100 /* only for system emulation */
1255 #define EXCP_SYSCALL 0x101 /* only for user emulation */
1256 #define EXCP_VSYSCALL 0x102 /* only for user emulation */
1257
1258 /* i386-specific interrupt pending bits. */
1259 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
1260 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
1261 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
1262 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
1263 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
1264 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
1265 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
1266
1267 /* Use a clearer name for this. */
1268 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
1269
1270 #define CC_OP_HAS_EFLAGS(op) ((op) >= CC_OP_EFLAGS && (op) <= CC_OP_ADCOX)
1271
1272 /* Instead of computing the condition codes after each x86 instruction,
1273 * QEMU just stores one operand (called CC_SRC), the result
1274 * (called CC_DST) and the type of operation (called CC_OP). When the
1275 * condition codes are needed, the condition codes can be calculated
1276 * using this information. Condition codes are not generated if they
1277 * are only needed for conditional branches.
1278 */
1279 typedef enum {
1280 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
1281 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */
1282 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */
1283 CC_OP_ADOX, /* CC_SRC2 = O, CC_SRC = rest. */
1284 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */
1285 CC_OP_CLR, /* Z and P set, all other flags clear. */
1286
1287 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
1288 CC_OP_MULW,
1289 CC_OP_MULL,
1290 CC_OP_MULQ,
1291
1292 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1293 CC_OP_ADDW,
1294 CC_OP_ADDL,
1295 CC_OP_ADDQ,
1296
1297 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1298 CC_OP_ADCW,
1299 CC_OP_ADCL,
1300 CC_OP_ADCQ,
1301
1302 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1303 CC_OP_SUBW,
1304 CC_OP_SUBL,
1305 CC_OP_SUBQ,
1306
1307 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1308 CC_OP_SBBW,
1309 CC_OP_SBBL,
1310 CC_OP_SBBQ,
1311
1312 CC_OP_LOGICB, /* modify all flags, CC_DST = res */
1313 CC_OP_LOGICW,
1314 CC_OP_LOGICL,
1315 CC_OP_LOGICQ,
1316
1317 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
1318 CC_OP_INCW,
1319 CC_OP_INCL,
1320 CC_OP_INCQ,
1321
1322 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
1323 CC_OP_DECW,
1324 CC_OP_DECL,
1325 CC_OP_DECQ,
1326
1327 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
1328 CC_OP_SHLW,
1329 CC_OP_SHLL,
1330 CC_OP_SHLQ,
1331
1332 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
1333 CC_OP_SARW,
1334 CC_OP_SARL,
1335 CC_OP_SARQ,
1336
1337 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
1338 CC_OP_BMILGW,
1339 CC_OP_BMILGL,
1340 CC_OP_BMILGQ,
1341
1342 /*
1343 * Note that only CC_OP_POPCNT (i.e. the one with MO_TL size)
1344 * is used or implemented, because the translation needs
1345 * to zero-extend CC_DST anyway.
1346 */
1347 CC_OP_POPCNTB__, /* Z via CC_DST, all other flags clear. */
1348 CC_OP_POPCNTW__,
1349 CC_OP_POPCNTL__,
1350 CC_OP_POPCNTQ__,
1351 CC_OP_POPCNT = sizeof(target_ulong) == 8 ? CC_OP_POPCNTQ__ : CC_OP_POPCNTL__,
1352
1353 CC_OP_NB,
1354 } CCOp;
1355 QEMU_BUILD_BUG_ON(CC_OP_NB >= 128);
1356
1357 typedef struct SegmentCache {
1358 uint32_t selector;
1359 target_ulong base;
1360 uint32_t limit;
1361 uint32_t flags;
1362 } SegmentCache;
1363
1364 typedef union MMXReg {
1365 uint8_t _b_MMXReg[64 / 8];
1366 uint16_t _w_MMXReg[64 / 16];
1367 uint32_t _l_MMXReg[64 / 32];
1368 uint64_t _q_MMXReg[64 / 64];
1369 float32 _s_MMXReg[64 / 32];
1370 float64 _d_MMXReg[64 / 64];
1371 } MMXReg;
1372
1373 typedef union XMMReg {
1374 uint64_t _q_XMMReg[128 / 64];
1375 } XMMReg;
1376
1377 typedef union YMMReg {
1378 uint64_t _q_YMMReg[256 / 64];
1379 XMMReg _x_YMMReg[256 / 128];
1380 } YMMReg;
1381
1382 typedef union ZMMReg {
1383 uint8_t _b_ZMMReg[512 / 8];
1384 uint16_t _w_ZMMReg[512 / 16];
1385 uint32_t _l_ZMMReg[512 / 32];
1386 uint64_t _q_ZMMReg[512 / 64];
1387 float16 _h_ZMMReg[512 / 16];
1388 float32 _s_ZMMReg[512 / 32];
1389 float64 _d_ZMMReg[512 / 64];
1390 XMMReg _x_ZMMReg[512 / 128];
1391 YMMReg _y_ZMMReg[512 / 256];
1392 } ZMMReg;
1393
1394 typedef struct BNDReg {
1395 uint64_t lb;
1396 uint64_t ub;
1397 } BNDReg;
1398
1399 typedef struct BNDCSReg {
1400 uint64_t cfgu;
1401 uint64_t sts;
1402 } BNDCSReg;
1403
1404 #define BNDCFG_ENABLE 1ULL
1405 #define BNDCFG_BNDPRESERVE 2ULL
1406 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK
1407
1408 #if HOST_BIG_ENDIAN
1409 #define ZMM_B(n) _b_ZMMReg[63 - (n)]
1410 #define ZMM_W(n) _w_ZMMReg[31 - (n)]
1411 #define ZMM_L(n) _l_ZMMReg[15 - (n)]
1412 #define ZMM_H(n) _h_ZMMReg[31 - (n)]
1413 #define ZMM_S(n) _s_ZMMReg[15 - (n)]
1414 #define ZMM_Q(n) _q_ZMMReg[7 - (n)]
1415 #define ZMM_D(n) _d_ZMMReg[7 - (n)]
1416 #define ZMM_X(n) _x_ZMMReg[3 - (n)]
1417 #define ZMM_Y(n) _y_ZMMReg[1 - (n)]
1418
1419 #define XMM_Q(n) _q_XMMReg[1 - (n)]
1420
1421 #define YMM_Q(n) _q_YMMReg[3 - (n)]
1422 #define YMM_X(n) _x_YMMReg[1 - (n)]
1423
1424 #define MMX_B(n) _b_MMXReg[7 - (n)]
1425 #define MMX_W(n) _w_MMXReg[3 - (n)]
1426 #define MMX_L(n) _l_MMXReg[1 - (n)]
1427 #define MMX_S(n) _s_MMXReg[1 - (n)]
1428 #else
1429 #define ZMM_B(n) _b_ZMMReg[n]
1430 #define ZMM_W(n) _w_ZMMReg[n]
1431 #define ZMM_L(n) _l_ZMMReg[n]
1432 #define ZMM_H(n) _h_ZMMReg[n]
1433 #define ZMM_S(n) _s_ZMMReg[n]
1434 #define ZMM_Q(n) _q_ZMMReg[n]
1435 #define ZMM_D(n) _d_ZMMReg[n]
1436 #define ZMM_X(n) _x_ZMMReg[n]
1437 #define ZMM_Y(n) _y_ZMMReg[n]
1438
1439 #define XMM_Q(n) _q_XMMReg[n]
1440
1441 #define YMM_Q(n) _q_YMMReg[n]
1442 #define YMM_X(n) _x_YMMReg[n]
1443
1444 #define MMX_B(n) _b_MMXReg[n]
1445 #define MMX_W(n) _w_MMXReg[n]
1446 #define MMX_L(n) _l_MMXReg[n]
1447 #define MMX_S(n) _s_MMXReg[n]
1448 #endif
1449 #define MMX_Q(n) _q_MMXReg[n]
1450
1451 typedef union {
1452 floatx80 d __attribute__((aligned(16)));
1453 MMXReg mmx;
1454 } FPReg;
1455
1456 typedef struct {
1457 uint64_t base;
1458 uint64_t mask;
1459 } MTRRVar;
1460
1461 #define CPU_NB_REGS64 16
1462 #define CPU_NB_REGS32 8
1463
1464 #ifdef TARGET_X86_64
1465 #define CPU_NB_REGS CPU_NB_REGS64
1466 #else
1467 #define CPU_NB_REGS CPU_NB_REGS32
1468 #endif
1469
1470 #define MAX_FIXED_COUNTERS 3
1471 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
1472
1473 #define TARGET_INSN_START_EXTRA_WORDS 1
1474
1475 #define NB_OPMASK_REGS 8
1476
1477 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish
1478 * that APIC ID hasn't been set yet
1479 */
1480 #define UNASSIGNED_APIC_ID 0xFFFFFFFF
1481
1482 typedef struct X86LegacyXSaveArea {
1483 uint16_t fcw;
1484 uint16_t fsw;
1485 uint8_t ftw;
1486 uint8_t reserved;
1487 uint16_t fpop;
1488 union {
1489 struct {
1490 uint64_t fpip;
1491 uint64_t fpdp;
1492 };
1493 struct {
1494 uint32_t fip;
1495 uint32_t fcs;
1496 uint32_t foo;
1497 uint32_t fos;
1498 };
1499 };
1500 uint32_t mxcsr;
1501 uint32_t mxcsr_mask;
1502 FPReg fpregs[8];
1503 uint8_t xmm_regs[16][16];
1504 uint32_t hw_reserved[12];
1505 uint32_t sw_reserved[12];
1506 } X86LegacyXSaveArea;
1507
1508 QEMU_BUILD_BUG_ON(sizeof(X86LegacyXSaveArea) != 512);
1509
1510 typedef struct X86XSaveHeader {
1511 uint64_t xstate_bv;
1512 uint64_t xcomp_bv;
1513 uint64_t reserve0;
1514 uint8_t reserved[40];
1515 } X86XSaveHeader;
1516
1517 /* Ext. save area 2: AVX State */
1518 typedef struct XSaveAVX {
1519 uint8_t ymmh[16][16];
1520 } XSaveAVX;
1521
1522 /* Ext. save area 3: BNDREG */
1523 typedef struct XSaveBNDREG {
1524 BNDReg bnd_regs[4];
1525 } XSaveBNDREG;
1526
1527 /* Ext. save area 4: BNDCSR */
1528 typedef union XSaveBNDCSR {
1529 BNDCSReg bndcsr;
1530 uint8_t data[64];
1531 } XSaveBNDCSR;
1532
1533 /* Ext. save area 5: Opmask */
1534 typedef struct XSaveOpmask {
1535 uint64_t opmask_regs[NB_OPMASK_REGS];
1536 } XSaveOpmask;
1537
1538 /* Ext. save area 6: ZMM_Hi256 */
1539 typedef struct XSaveZMM_Hi256 {
1540 uint8_t zmm_hi256[16][32];
1541 } XSaveZMM_Hi256;
1542
1543 /* Ext. save area 7: Hi16_ZMM */
1544 typedef struct XSaveHi16_ZMM {
1545 uint8_t hi16_zmm[16][64];
1546 } XSaveHi16_ZMM;
1547
1548 /* Ext. save area 9: PKRU state */
1549 typedef struct XSavePKRU {
1550 uint32_t pkru;
1551 uint32_t padding;
1552 } XSavePKRU;
1553
1554 /* Ext. save area 17: AMX XTILECFG state */
1555 typedef struct XSaveXTILECFG {
1556 uint8_t xtilecfg[64];
1557 } XSaveXTILECFG;
1558
1559 /* Ext. save area 18: AMX XTILEDATA state */
1560 typedef struct XSaveXTILEDATA {
1561 uint8_t xtiledata[8][1024];
1562 } XSaveXTILEDATA;
1563
1564 typedef struct {
1565 uint64_t from;
1566 uint64_t to;
1567 uint64_t info;
1568 } LBREntry;
1569
1570 #define ARCH_LBR_NR_ENTRIES 32
1571
1572 /* Ext. save area 19: Supervisor mode Arch LBR state */
1573 typedef struct XSavesArchLBR {
1574 uint64_t lbr_ctl;
1575 uint64_t lbr_depth;
1576 uint64_t ler_from;
1577 uint64_t ler_to;
1578 uint64_t ler_info;
1579 LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
1580 } XSavesArchLBR;
1581
1582 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
1583 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
1584 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
1585 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
1586 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
1587 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
1588 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
1589 QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) != 0x40);
1590 QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) != 0x2000);
1591 QEMU_BUILD_BUG_ON(sizeof(XSavesArchLBR) != 0x328);
1592
1593 typedef struct ExtSaveArea {
1594 uint32_t feature, bits;
1595 uint32_t offset, size;
1596 uint32_t ecx;
1597 } ExtSaveArea;
1598
1599 #define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1)
1600
1601 extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT];
1602
1603 typedef enum TPRAccess {
1604 TPR_ACCESS_READ,
1605 TPR_ACCESS_WRITE,
1606 } TPRAccess;
1607
1608 /* Cache information data structures: */
1609
1610 enum CacheType {
1611 DATA_CACHE,
1612 INSTRUCTION_CACHE,
1613 UNIFIED_CACHE
1614 };
1615
1616 typedef struct CPUCacheInfo {
1617 enum CacheType type;
1618 uint8_t level;
1619 /* Size in bytes */
1620 uint32_t size;
1621 /* Line size, in bytes */
1622 uint16_t line_size;
1623 /*
1624 * Associativity.
1625 * Note: representation of fully-associative caches is not implemented
1626 */
1627 uint8_t associativity;
1628 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */
1629 uint8_t partitions;
1630 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */
1631 uint32_t sets;
1632 /*
1633 * Lines per tag.
1634 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006].
1635 * (Is this synonym to @partitions?)
1636 */
1637 uint8_t lines_per_tag;
1638
1639 /* Self-initializing cache */
1640 bool self_init;
1641 /*
1642 * WBINVD/INVD is not guaranteed to act upon lower level caches of
1643 * non-originating threads sharing this cache.
1644 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0]
1645 */
1646 bool no_invd_sharing;
1647 /*
1648 * Cache is inclusive of lower cache levels.
1649 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1].
1650 */
1651 bool inclusive;
1652 /*
1653 * A complex function is used to index the cache, potentially using all
1654 * address bits. CPUID[4].EDX[bit 2].
1655 */
1656 bool complex_indexing;
1657
1658 /*
1659 * Cache Topology. The level that cache is shared in.
1660 * Used to encode CPUID[4].EAX[bits 25:14] or
1661 * CPUID[0x8000001D].EAX[bits 25:14].
1662 */
1663 enum CPUTopoLevel share_level;
1664 } CPUCacheInfo;
1665
1666
1667 typedef struct CPUCaches {
1668 CPUCacheInfo *l1d_cache;
1669 CPUCacheInfo *l1i_cache;
1670 CPUCacheInfo *l2_cache;
1671 CPUCacheInfo *l3_cache;
1672 } CPUCaches;
1673
1674 typedef struct HVFX86LazyFlags {
1675 target_ulong result;
1676 target_ulong auxbits;
1677 } HVFX86LazyFlags;
1678
1679 typedef struct CPUArchState {
1680 /* standard registers */
1681 target_ulong regs[CPU_NB_REGS];
1682 target_ulong eip;
1683 target_ulong eflags; /* eflags register. During CPU emulation, CC
1684 flags and DF are set to zero because they are
1685 stored elsewhere */
1686
1687 /* emulator internal eflags handling */
1688 target_ulong cc_dst;
1689 target_ulong cc_src;
1690 target_ulong cc_src2;
1691 uint32_t cc_op;
1692 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
1693 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
1694 are known at translation time. */
1695 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
1696
1697 /* segments */
1698 SegmentCache segs[6]; /* selector values */
1699 SegmentCache ldt;
1700 SegmentCache tr;
1701 SegmentCache gdt; /* only base and limit are used */
1702 SegmentCache idt; /* only base and limit are used */
1703
1704 target_ulong cr[5]; /* NOTE: cr1 is unused */
1705
1706 bool pdptrs_valid;
1707 uint64_t pdptrs[4];
1708 int32_t a20_mask;
1709
1710 BNDReg bnd_regs[4];
1711 BNDCSReg bndcs_regs;
1712 uint64_t msr_bndcfgs;
1713 uint64_t efer;
1714
1715 /* Beginning of state preserved by INIT (dummy marker). */
1716 struct {} start_init_save;
1717
1718 /* FPU state */
1719 unsigned int fpstt; /* top of stack index */
1720 uint16_t fpus;
1721 uint16_t fpuc;
1722 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
1723 FPReg fpregs[8];
1724 /* KVM-only so far */
1725 uint16_t fpop;
1726 uint16_t fpcs;
1727 uint16_t fpds;
1728 uint64_t fpip;
1729 uint64_t fpdp;
1730
1731 /* emulator internal variables */
1732 float_status fp_status;
1733 floatx80 ft0;
1734
1735 float_status mmx_status; /* for 3DNow! float ops */
1736 float_status sse_status;
1737 uint32_t mxcsr;
1738 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32] QEMU_ALIGNED(16);
1739 ZMMReg xmm_t0 QEMU_ALIGNED(16);
1740 MMXReg mmx_t0;
1741
1742 uint64_t opmask_regs[NB_OPMASK_REGS];
1743 #ifdef TARGET_X86_64
1744 uint8_t xtilecfg[64];
1745 uint8_t xtiledata[8192];
1746 #endif
1747
1748 /* sysenter registers */
1749 uint32_t sysenter_cs;
1750 target_ulong sysenter_esp;
1751 target_ulong sysenter_eip;
1752 uint64_t star;
1753
1754 uint64_t vm_hsave;
1755
1756 #ifdef TARGET_X86_64
1757 target_ulong lstar;
1758 target_ulong cstar;
1759 target_ulong fmask;
1760 target_ulong kernelgsbase;
1761
1762 /* FRED MSRs */
1763 uint64_t fred_rsp0;
1764 uint64_t fred_rsp1;
1765 uint64_t fred_rsp2;
1766 uint64_t fred_rsp3;
1767 uint64_t fred_stklvls;
1768 uint64_t fred_ssp1;
1769 uint64_t fred_ssp2;
1770 uint64_t fred_ssp3;
1771 uint64_t fred_config;
1772 #endif
1773
1774 uint64_t tsc_adjust;
1775 uint64_t tsc_deadline;
1776 uint64_t tsc_aux;
1777
1778 uint64_t xcr0;
1779
1780 uint64_t mcg_status;
1781 uint64_t msr_ia32_misc_enable;
1782 uint64_t msr_ia32_feature_control;
1783 uint64_t msr_ia32_sgxlepubkeyhash[4];
1784
1785 uint64_t msr_fixed_ctr_ctrl;
1786 uint64_t msr_global_ctrl;
1787 uint64_t msr_global_status;
1788 uint64_t msr_global_ovf_ctrl;
1789 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
1790 uint64_t msr_gp_counters[MAX_GP_COUNTERS];
1791 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1792
1793 uint64_t pat;
1794 uint32_t smbase;
1795 uint64_t msr_smi_count;
1796
1797 uint32_t pkru;
1798 uint32_t pkrs;
1799 uint32_t tsx_ctrl;
1800
1801 uint64_t spec_ctrl;
1802 uint64_t amd_tsc_scale_msr;
1803 uint64_t virt_ssbd;
1804
1805 /* End of state preserved by INIT (dummy marker). */
1806 struct {} end_init_save;
1807
1808 uint64_t system_time_msr;
1809 uint64_t wall_clock_msr;
1810 uint64_t steal_time_msr;
1811 uint64_t async_pf_en_msr;
1812 uint64_t async_pf_int_msr;
1813 uint64_t pv_eoi_en_msr;
1814 uint64_t poll_control_msr;
1815
1816 /* Partition-wide HV MSRs, will be updated only on the first vcpu */
1817 uint64_t msr_hv_hypercall;
1818 uint64_t msr_hv_guest_os_id;
1819 uint64_t msr_hv_tsc;
1820 uint64_t msr_hv_syndbg_control;
1821 uint64_t msr_hv_syndbg_status;
1822 uint64_t msr_hv_syndbg_send_page;
1823 uint64_t msr_hv_syndbg_recv_page;
1824 uint64_t msr_hv_syndbg_pending_page;
1825 uint64_t msr_hv_syndbg_options;
1826
1827 /* Per-VCPU HV MSRs */
1828 uint64_t msr_hv_vapic;
1829 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS];
1830 uint64_t msr_hv_runtime;
1831 uint64_t msr_hv_synic_control;
1832 uint64_t msr_hv_synic_evt_page;
1833 uint64_t msr_hv_synic_msg_page;
1834 uint64_t msr_hv_synic_sint[HV_SINT_COUNT];
1835 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT];
1836 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT];
1837 uint64_t msr_hv_reenlightenment_control;
1838 uint64_t msr_hv_tsc_emulation_control;
1839 uint64_t msr_hv_tsc_emulation_status;
1840
1841 uint64_t msr_rtit_ctrl;
1842 uint64_t msr_rtit_status;
1843 uint64_t msr_rtit_output_base;
1844 uint64_t msr_rtit_output_mask;
1845 uint64_t msr_rtit_cr3_match;
1846 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
1847
1848 /* Per-VCPU XFD MSRs */
1849 uint64_t msr_xfd;
1850 uint64_t msr_xfd_err;
1851
1852 /* Per-VCPU Arch LBR MSRs */
1853 uint64_t msr_lbr_ctl;
1854 uint64_t msr_lbr_depth;
1855 LBREntry lbr_records[ARCH_LBR_NR_ENTRIES];
1856
1857 /* exception/interrupt handling */
1858 int error_code;
1859 int exception_is_int;
1860 target_ulong exception_next_eip;
1861 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */
1862 union {
1863 struct CPUBreakpoint *cpu_breakpoint[4];
1864 struct CPUWatchpoint *cpu_watchpoint[4];
1865 }; /* break/watchpoints for dr[0..3] */
1866 int old_exception; /* exception in flight */
1867
1868 uint64_t vm_vmcb;
1869 uint64_t tsc_offset;
1870 uint64_t intercept;
1871 uint16_t intercept_cr_read;
1872 uint16_t intercept_cr_write;
1873 uint16_t intercept_dr_read;
1874 uint16_t intercept_dr_write;
1875 uint32_t intercept_exceptions;
1876 uint64_t nested_cr3;
1877 uint32_t nested_pg_mode;
1878 uint8_t v_tpr;
1879 uint32_t int_ctl;
1880
1881 /* KVM states, automatically cleared on reset */
1882 uint8_t nmi_injected;
1883 uint8_t nmi_pending;
1884
1885 uintptr_t retaddr;
1886
1887 /* RAPL MSR */
1888 uint64_t msr_rapl_power_unit;
1889 uint64_t msr_pkg_energy_status;
1890
1891 /* Fields up to this point are cleared by a CPU reset */
1892 struct {} end_reset_fields;
1893
1894 /* Fields after this point are preserved across CPU reset. */
1895
1896 /* processor features (e.g. for CPUID insn) */
1897 /* Minimum cpuid leaf 7 value */
1898 uint32_t cpuid_level_func7;
1899 /* Actual cpuid leaf 7 value */
1900 uint32_t cpuid_min_level_func7;
1901 /* Minimum level/xlevel/xlevel2, based on CPU model + features */
1902 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
1903 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */
1904 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
1905 /* Actual level/xlevel/xlevel2 value: */
1906 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
1907 uint32_t cpuid_vendor1;
1908 uint32_t cpuid_vendor2;
1909 uint32_t cpuid_vendor3;
1910 uint32_t cpuid_version;
1911 FeatureWordArray features;
1912 /* Features that were explicitly enabled/disabled */
1913 FeatureWordArray user_features;
1914 uint32_t cpuid_model[12];
1915 /* Cache information for CPUID. When legacy-cache=on, the cache data
1916 * on each CPUID leaf will be different, because we keep compatibility
1917 * with old QEMU versions.
1918 */
1919 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
1920
1921 /* MTRRs */
1922 uint64_t mtrr_fixed[11];
1923 uint64_t mtrr_deftype;
1924 MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1925
1926 /* For KVM */
1927 uint32_t mp_state;
1928 int32_t exception_nr;
1929 int32_t interrupt_injected;
1930 uint8_t soft_interrupt;
1931 uint8_t exception_pending;
1932 uint8_t exception_injected;
1933 uint8_t has_error_code;
1934 uint8_t exception_has_payload;
1935 uint64_t exception_payload;
1936 uint8_t triple_fault_pending;
1937 uint32_t ins_len;
1938 uint32_t sipi_vector;
1939 bool tsc_valid;
1940 int64_t tsc_khz;
1941 int64_t user_tsc_khz; /* for sanity check only */
1942 uint64_t apic_bus_freq;
1943 uint64_t tsc;
1944 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
1945 void *xsave_buf;
1946 uint32_t xsave_buf_len;
1947 #endif
1948 #if defined(CONFIG_KVM)
1949 struct kvm_nested_state *nested_state;
1950 MemoryRegion *xen_vcpu_info_mr;
1951 void *xen_vcpu_info_hva;
1952 uint64_t xen_vcpu_info_gpa;
1953 uint64_t xen_vcpu_info_default_gpa;
1954 uint64_t xen_vcpu_time_info_gpa;
1955 uint64_t xen_vcpu_runstate_gpa;
1956 uint8_t xen_vcpu_callback_vector;
1957 bool xen_callback_asserted;
1958 uint16_t xen_virq[XEN_NR_VIRQS];
1959 uint64_t xen_singleshot_timer_ns;
1960 QEMUTimer *xen_singleshot_timer;
1961 uint64_t xen_periodic_timer_period;
1962 QEMUTimer *xen_periodic_timer;
1963 QemuMutex xen_timers_lock;
1964 #endif
1965 #if defined(CONFIG_HVF)
1966 HVFX86LazyFlags hvf_lflags;
1967 void *hvf_mmio_buf;
1968 #endif
1969
1970 uint64_t mcg_cap;
1971 uint64_t mcg_ctl;
1972 uint64_t mcg_ext_ctl;
1973 uint64_t mce_banks[MCE_BANKS_DEF*4];
1974 uint64_t xstate_bv;
1975
1976 /* vmstate */
1977 uint16_t fpus_vmstate;
1978 uint16_t fptag_vmstate;
1979 uint16_t fpregs_format_vmstate;
1980
1981 uint64_t xss;
1982 uint32_t umwait;
1983
1984 TPRAccess tpr_access_type;
1985
1986 /* Number of dies within this CPU package. */
1987 unsigned nr_dies;
1988
1989 /* Number of modules within one die. */
1990 unsigned nr_modules;
1991
1992 /* Bitmap of available CPU topology levels for this CPU. */
1993 DECLARE_BITMAP(avail_cpu_topo, CPU_TOPO_LEVEL_MAX);
1994 } CPUX86State;
1995
1996 struct kvm_msrs;
1997
1998 /**
1999 * X86CPU:
2000 * @env: #CPUX86State
2001 * @migratable: If set, only migratable flags will be accepted when "enforce"
2002 * mode is used, and only migratable flags will be included in the "host"
2003 * CPU model.
2004 *
2005 * An x86 CPU.
2006 */
2007 struct ArchCPU {
2008 CPUState parent_obj;
2009
2010 CPUX86State env;
2011 VMChangeStateEntry *vmsentry;
2012
2013 uint64_t ucode_rev;
2014
2015 uint32_t hyperv_spinlock_attempts;
2016 char *hyperv_vendor;
2017 bool hyperv_synic_kvm_only;
2018 uint64_t hyperv_features;
2019 bool hyperv_passthrough;
2020 OnOffAuto hyperv_no_nonarch_cs;
2021 uint32_t hyperv_vendor_id[3];
2022 uint32_t hyperv_interface_id[4];
2023 uint32_t hyperv_limits[3];
2024 bool hyperv_enforce_cpuid;
2025 uint32_t hyperv_ver_id_build;
2026 uint16_t hyperv_ver_id_major;
2027 uint16_t hyperv_ver_id_minor;
2028 uint32_t hyperv_ver_id_sp;
2029 uint8_t hyperv_ver_id_sb;
2030 uint32_t hyperv_ver_id_sn;
2031
2032 bool check_cpuid;
2033 bool enforce_cpuid;
2034 /*
2035 * Force features to be enabled even if the host doesn't support them.
2036 * This is dangerous and should be done only for testing CPUID
2037 * compatibility.
2038 */
2039 bool force_features;
2040 bool expose_kvm;
2041 bool expose_tcg;
2042 bool migratable;
2043 bool migrate_smi_count;
2044 bool max_features; /* Enable all supported features automatically */
2045 uint32_t apic_id;
2046
2047 /* Enables publishing of TSC increment and Local APIC bus frequencies to
2048 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */
2049 bool vmware_cpuid_freq;
2050
2051 /* if true the CPUID code directly forward host cache leaves to the guest */
2052 bool cache_info_passthrough;
2053
2054 /* if true the CPUID code directly forwards
2055 * host monitor/mwait leaves to the guest */
2056 struct {
2057 uint32_t eax;
2058 uint32_t ebx;
2059 uint32_t ecx;
2060 uint32_t edx;
2061 } mwait;
2062
2063 /* Features that were filtered out because of missing host capabilities */
2064 FeatureWordArray filtered_features;
2065
2066 /* Enable PMU CPUID bits. This can't be enabled by default yet because
2067 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
2068 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
2069 * capabilities) directly to the guest.
2070 */
2071 bool enable_pmu;
2072
2073 /*
2074 * Enable LBR_FMT bits of IA32_PERF_CAPABILITIES MSR.
2075 * This can't be initialized with a default because it doesn't have
2076 * stable ABI support yet. It is only allowed to pass all LBR_FMT bits
2077 * returned by kvm_arch_get_supported_msr_feature()(which depends on both
2078 * host CPU and kernel capabilities) to the guest.
2079 */
2080 uint64_t lbr_fmt;
2081
2082 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is
2083 * disabled by default to avoid breaking migration between QEMU with
2084 * different LMCE configurations.
2085 */
2086 bool enable_lmce;
2087
2088 /* Compatibility bits for old machine types.
2089 * If true present virtual l3 cache for VM, the vcpus in the same virtual
2090 * socket share an virtual l3 cache.
2091 */
2092 bool enable_l3_cache;
2093
2094 /* Compatibility bits for old machine types.
2095 * If true present L1 cache as per-thread, not per-core.
2096 */
2097 bool l1_cache_per_core;
2098
2099 /* Compatibility bits for old machine types.
2100 * If true present the old cache topology information
2101 */
2102 bool legacy_cache;
2103
2104 /* Compatibility bits for old machine types.
2105 * If true decode the CPUID Function 0x8000001E_ECX to support multiple
2106 * nodes per processor
2107 */
2108 bool legacy_multi_node;
2109
2110 /* Compatibility bits for old machine types: */
2111 bool enable_cpuid_0xb;
2112
2113 /* Enable auto level-increase for all CPUID leaves */
2114 bool full_cpuid_auto_level;
2115
2116 /* Only advertise CPUID leaves defined by the vendor */
2117 bool vendor_cpuid_only;
2118
2119 /* Only advertise TOPOEXT features that AMD defines */
2120 bool amd_topoext_features_only;
2121
2122 /* Enable auto level-increase for Intel Processor Trace leave */
2123 bool intel_pt_auto_level;
2124
2125 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */
2126 bool fill_mtrr_mask;
2127
2128 /* if true override the phys_bits value with a value read from the host */
2129 bool host_phys_bits;
2130
2131 /* if set, limit maximum value for phys_bits when host_phys_bits is true */
2132 uint8_t host_phys_bits_limit;
2133
2134 /* Forcefully disable KVM PV features not exposed in guest CPUIDs */
2135 bool kvm_pv_enforce_cpuid;
2136
2137 /* Number of physical address bits supported */
2138 uint32_t phys_bits;
2139
2140 /*
2141 * Number of guest physical address bits available. Usually this is
2142 * identical to host physical address bits. With NPT or EPT 4-level
2143 * paging, guest physical address space might be restricted to 48 bits
2144 * even if the host cpu supports more physical address bits.
2145 */
2146 uint32_t guest_phys_bits;
2147
2148 /* in order to simplify APIC support, we leave this pointer to the
2149 user */
2150 struct DeviceState *apic_state;
2151 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
2152 Notifier machine_done;
2153
2154 struct kvm_msrs *kvm_msr_buf;
2155
2156 int32_t node_id; /* NUMA node this CPU belongs to */
2157 int32_t socket_id;
2158 int32_t die_id;
2159 int32_t module_id;
2160 int32_t core_id;
2161 int32_t thread_id;
2162
2163 int32_t hv_max_vps;
2164
2165 bool xen_vapic;
2166 };
2167
2168 typedef struct X86CPUModel X86CPUModel;
2169
2170 /**
2171 * X86CPUClass:
2172 * @cpu_def: CPU model definition
2173 * @host_cpuid_required: Whether CPU model requires cpuid from host.
2174 * @ordering: Ordering on the "-cpu help" CPU model list.
2175 * @migration_safe: See CpuDefinitionInfo::migration_safe
2176 * @static_model: See CpuDefinitionInfo::static
2177 * @parent_realize: The parent class' realize handler.
2178 * @parent_phases: The parent class' reset phase handlers.
2179 *
2180 * An x86 CPU model or family.
2181 */
2182 struct X86CPUClass {
2183 CPUClass parent_class;
2184
2185 /*
2186 * CPU definition, automatically loaded by instance_init if not NULL.
2187 * Should be eventually replaced by subclass-specific property defaults.
2188 */
2189 X86CPUModel *model;
2190
2191 bool host_cpuid_required;
2192 int ordering;
2193 bool migration_safe;
2194 bool static_model;
2195
2196 /*
2197 * Optional description of CPU model.
2198 * If unavailable, cpu_def->model_id is used.
2199 */
2200 const char *model_description;
2201
2202 DeviceRealize parent_realize;
2203 DeviceUnrealize parent_unrealize;
2204 ResettablePhases parent_phases;
2205 };
2206
2207 #ifndef CONFIG_USER_ONLY
2208 extern const VMStateDescription vmstate_x86_cpu;
2209 #endif
2210
2211 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
2212
2213 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
2214 int cpuid, DumpState *s);
2215 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
2216 int cpuid, DumpState *s);
2217 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
2218 DumpState *s);
2219 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
2220 DumpState *s);
2221
2222 bool x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
2223 Error **errp);
2224
2225 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags);
2226
2227 int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
2228 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
2229
2230 void x86_cpu_list(void);
2231 int cpu_x86_support_mca_broadcast(CPUX86State *env);
2232
2233 #ifndef CONFIG_USER_ONLY
2234 hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
2235 MemTxAttrs *attrs);
2236 int cpu_get_pic_interrupt(CPUX86State *s);
2237
2238 /* MS-DOS compatibility mode FPU exception support */
2239 void x86_register_ferr_irq(qemu_irq irq);
2240 void fpu_check_raise_ferr_irq(CPUX86State *s);
2241 void cpu_set_ignne(void);
2242 void cpu_clear_ignne(void);
2243 #endif
2244
2245 /* mpx_helper.c */
2246 void cpu_sync_bndcs_hflags(CPUX86State *env);
2247
2248 /* this function must always be used to load data in the segment
2249 cache: it synchronizes the hflags with the segment cache values */
cpu_x86_load_seg_cache(CPUX86State * env,X86Seg seg_reg,unsigned int selector,target_ulong base,unsigned int limit,unsigned int flags)2250 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
2251 X86Seg seg_reg, unsigned int selector,
2252 target_ulong base,
2253 unsigned int limit,
2254 unsigned int flags)
2255 {
2256 SegmentCache *sc;
2257 unsigned int new_hflags;
2258
2259 sc = &env->segs[seg_reg];
2260 sc->selector = selector;
2261 sc->base = base;
2262 sc->limit = limit;
2263 sc->flags = flags;
2264
2265 /* update the hidden flags */
2266 {
2267 if (seg_reg == R_CS) {
2268 #ifdef TARGET_X86_64
2269 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
2270 /* long mode */
2271 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
2272 env->hflags &= ~(HF_ADDSEG_MASK);
2273 } else
2274 #endif
2275 {
2276 /* legacy / compatibility case */
2277 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
2278 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
2279 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
2280 new_hflags;
2281 }
2282 }
2283 if (seg_reg == R_SS) {
2284 int cpl = (flags >> DESC_DPL_SHIFT) & 3;
2285 #if HF_CPL_MASK != 3
2286 #error HF_CPL_MASK is hardcoded
2287 #endif
2288 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
2289 /* Possibly switch between BNDCFGS and BNDCFGU */
2290 cpu_sync_bndcs_hflags(env);
2291 }
2292 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
2293 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
2294 if (env->hflags & HF_CS64_MASK) {
2295 /* zero base assumed for DS, ES and SS in long mode */
2296 } else if (!(env->cr[0] & CR0_PE_MASK) ||
2297 (env->eflags & VM_MASK) ||
2298 !(env->hflags & HF_CS32_MASK)) {
2299 /* XXX: try to avoid this test. The problem comes from the
2300 fact that is real mode or vm86 mode we only modify the
2301 'base' and 'selector' fields of the segment cache to go
2302 faster. A solution may be to force addseg to one in
2303 translate-i386.c. */
2304 new_hflags |= HF_ADDSEG_MASK;
2305 } else {
2306 new_hflags |= ((env->segs[R_DS].base |
2307 env->segs[R_ES].base |
2308 env->segs[R_SS].base) != 0) <<
2309 HF_ADDSEG_SHIFT;
2310 }
2311 env->hflags = (env->hflags &
2312 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
2313 }
2314 }
2315
cpu_x86_load_seg_cache_sipi(X86CPU * cpu,uint8_t sipi_vector)2316 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
2317 uint8_t sipi_vector)
2318 {
2319 CPUState *cs = CPU(cpu);
2320 CPUX86State *env = &cpu->env;
2321
2322 env->eip = 0;
2323 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
2324 sipi_vector << 12,
2325 env->segs[R_CS].limit,
2326 env->segs[R_CS].flags);
2327 cs->halted = 0;
2328 }
2329
2330 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
2331 target_ulong *base, unsigned int *limit,
2332 unsigned int *flags);
2333
2334 /* op_helper.c */
2335 /* used for debug or cpu save/restore */
2336
2337 /* cpu-exec.c */
2338 /*
2339 * The following helpers are only usable in user mode simulation.
2340 * The host pointers should come from lock_user().
2341 */
2342 void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector);
2343 void cpu_x86_fsave(CPUX86State *s, void *host, size_t len);
2344 void cpu_x86_frstor(CPUX86State *s, void *host, size_t len);
2345 void cpu_x86_fxsave(CPUX86State *s, void *host, size_t len);
2346 void cpu_x86_fxrstor(CPUX86State *s, void *host, size_t len);
2347 void cpu_x86_xsave(CPUX86State *s, void *host, size_t len, uint64_t rbfm);
2348 bool cpu_x86_xrstor(CPUX86State *s, void *host, size_t len, uint64_t rbfm);
2349
2350 /* cpu.c */
2351 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
2352 uint32_t vendor2, uint32_t vendor3);
2353 typedef struct PropValue {
2354 const char *prop, *value;
2355 } PropValue;
2356 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props);
2357
2358 void x86_cpu_after_reset(X86CPU *cpu);
2359
2360 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env);
2361
2362 /* cpu.c other functions (cpuid) */
2363 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2364 uint32_t *eax, uint32_t *ebx,
2365 uint32_t *ecx, uint32_t *edx);
2366 void cpu_clear_apic_feature(CPUX86State *env);
2367 void cpu_set_apic_feature(CPUX86State *env);
2368 void host_cpuid(uint32_t function, uint32_t count,
2369 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
2370 bool cpu_has_x2apic_feature(CPUX86State *env);
2371
2372 /* helper.c */
2373 void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
2374 void cpu_sync_avx_hflag(CPUX86State *env);
2375
2376 #ifndef CONFIG_USER_ONLY
x86_asidx_from_attrs(CPUState * cs,MemTxAttrs attrs)2377 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
2378 {
2379 return !!attrs.secure;
2380 }
2381
cpu_addressspace(CPUState * cs,MemTxAttrs attrs)2382 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs)
2383 {
2384 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs));
2385 }
2386
2387 /*
2388 * load efer and update the corresponding hflags. XXX: do consistency
2389 * checks with cpuid bits?
2390 */
2391 void cpu_load_efer(CPUX86State *env, uint64_t val);
2392 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
2393 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
2394 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
2395 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
2396 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
2397 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
2398 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
2399 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
2400 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
2401 #endif
2402
2403 /* will be suppressed */
2404 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
2405 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
2406 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
2407 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
2408
2409 /* hw/pc.c */
2410 uint64_t cpu_get_tsc(CPUX86State *env);
2411
2412 #define CPU_RESOLVING_TYPE TYPE_X86_CPU
2413
2414 #ifdef TARGET_X86_64
2415 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
2416 #else
2417 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
2418 #endif
2419
2420 #define cpu_list x86_cpu_list
2421
2422 /* MMU modes definitions */
2423 #define MMU_KSMAP64_IDX 0
2424 #define MMU_KSMAP32_IDX 1
2425 #define MMU_USER64_IDX 2
2426 #define MMU_USER32_IDX 3
2427 #define MMU_KNOSMAP64_IDX 4
2428 #define MMU_KNOSMAP32_IDX 5
2429 #define MMU_PHYS_IDX 6
2430 #define MMU_NESTED_IDX 7
2431
2432 #ifdef CONFIG_USER_ONLY
2433 #ifdef TARGET_X86_64
2434 #define MMU_USER_IDX MMU_USER64_IDX
2435 #else
2436 #define MMU_USER_IDX MMU_USER32_IDX
2437 #endif
2438 #endif
2439
is_mmu_index_smap(int mmu_index)2440 static inline bool is_mmu_index_smap(int mmu_index)
2441 {
2442 return (mmu_index & ~1) == MMU_KSMAP64_IDX;
2443 }
2444
is_mmu_index_user(int mmu_index)2445 static inline bool is_mmu_index_user(int mmu_index)
2446 {
2447 return (mmu_index & ~1) == MMU_USER64_IDX;
2448 }
2449
is_mmu_index_32(int mmu_index)2450 static inline bool is_mmu_index_32(int mmu_index)
2451 {
2452 assert(mmu_index < MMU_PHYS_IDX);
2453 return mmu_index & 1;
2454 }
2455
2456 int x86_mmu_index_pl(CPUX86State *env, unsigned pl);
2457 int cpu_mmu_index_kernel(CPUX86State *env);
2458
2459 #define CC_DST (env->cc_dst)
2460 #define CC_SRC (env->cc_src)
2461 #define CC_SRC2 (env->cc_src2)
2462 #define CC_OP (env->cc_op)
2463
2464 #include "exec/cpu-all.h"
2465 #include "svm.h"
2466
2467 #if !defined(CONFIG_USER_ONLY)
2468 #include "hw/i386/apic.h"
2469 #endif
2470
cpu_get_tb_cpu_state(CPUX86State * env,vaddr * pc,uint64_t * cs_base,uint32_t * flags)2471 static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc,
2472 uint64_t *cs_base, uint32_t *flags)
2473 {
2474 *flags = env->hflags |
2475 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
2476 if (env->hflags & HF_CS64_MASK) {
2477 *cs_base = 0;
2478 *pc = env->eip;
2479 } else {
2480 *cs_base = env->segs[R_CS].base;
2481 *pc = (uint32_t)(*cs_base + env->eip);
2482 }
2483 }
2484
2485 void do_cpu_init(X86CPU *cpu);
2486
2487 #define MCE_INJECT_BROADCAST 1
2488 #define MCE_INJECT_UNCOND_AO 2
2489
2490 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
2491 uint64_t status, uint64_t mcg_status, uint64_t addr,
2492 uint64_t misc, int flags);
2493
2494 uint32_t cpu_cc_compute_all(CPUX86State *env1);
2495
cpu_compute_eflags(CPUX86State * env)2496 static inline uint32_t cpu_compute_eflags(CPUX86State *env)
2497 {
2498 uint32_t eflags = env->eflags;
2499 if (tcg_enabled()) {
2500 eflags |= cpu_cc_compute_all(env) | (env->df & DF_MASK);
2501 }
2502 return eflags;
2503 }
2504
cpu_get_mem_attrs(CPUX86State * env)2505 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
2506 {
2507 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
2508 }
2509
x86_get_a20_mask(CPUX86State * env)2510 static inline int32_t x86_get_a20_mask(CPUX86State *env)
2511 {
2512 if (env->hflags & HF_SMM_MASK) {
2513 return -1;
2514 } else {
2515 return env->a20_mask;
2516 }
2517 }
2518
cpu_has_vmx(CPUX86State * env)2519 static inline bool cpu_has_vmx(CPUX86State *env)
2520 {
2521 return env->features[FEAT_1_ECX] & CPUID_EXT_VMX;
2522 }
2523
cpu_has_svm(CPUX86State * env)2524 static inline bool cpu_has_svm(CPUX86State *env)
2525 {
2526 return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM;
2527 }
2528
2529 /*
2530 * In order for a vCPU to enter VMX operation it must have CR4.VMXE set.
2531 * Since it was set, CR4.VMXE must remain set as long as vCPU is in
2532 * VMX operation. This is because CR4.VMXE is one of the bits set
2533 * in MSR_IA32_VMX_CR4_FIXED1.
2534 *
2535 * There is one exception to above statement when vCPU enters SMM mode.
2536 * When a vCPU enters SMM mode, it temporarily exit VMX operation and
2537 * may also reset CR4.VMXE during execution in SMM mode.
2538 * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation
2539 * and CR4.VMXE is restored to it's original value of being set.
2540 *
2541 * Therefore, when vCPU is not in SMM mode, we can infer whether
2542 * VMX is being used by examining CR4.VMXE. Otherwise, we cannot
2543 * know for certain.
2544 */
cpu_vmx_maybe_enabled(CPUX86State * env)2545 static inline bool cpu_vmx_maybe_enabled(CPUX86State *env)
2546 {
2547 return cpu_has_vmx(env) &&
2548 ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK));
2549 }
2550
2551 /* excp_helper.c */
2552 int get_pg_mode(CPUX86State *env);
2553
2554 /* fpu_helper.c */
2555 void update_fp_status(CPUX86State *env);
2556 void update_mxcsr_status(CPUX86State *env);
2557 void update_mxcsr_from_sse_status(CPUX86State *env);
2558
cpu_set_mxcsr(CPUX86State * env,uint32_t mxcsr)2559 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
2560 {
2561 env->mxcsr = mxcsr;
2562 if (tcg_enabled()) {
2563 update_mxcsr_status(env);
2564 }
2565 }
2566
cpu_set_fpuc(CPUX86State * env,uint16_t fpuc)2567 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
2568 {
2569 env->fpuc = fpuc;
2570 if (tcg_enabled()) {
2571 update_fp_status(env);
2572 }
2573 }
2574
2575 /* svm_helper.c */
2576 #ifdef CONFIG_USER_ONLY
2577 static inline void
cpu_svm_check_intercept_param(CPUX86State * env1,uint32_t type,uint64_t param,uintptr_t retaddr)2578 cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2579 uint64_t param, uintptr_t retaddr)
2580 { /* no-op */ }
2581 static inline bool
cpu_svm_has_intercept(CPUX86State * env,uint32_t type)2582 cpu_svm_has_intercept(CPUX86State *env, uint32_t type)
2583 { return false; }
2584 #else
2585 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2586 uint64_t param, uintptr_t retaddr);
2587 bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type);
2588 #endif
2589
2590 /* apic.c */
2591 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
2592 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
2593 TPRAccess access);
2594
2595 /* Special values for X86CPUVersion: */
2596
2597 /* Resolve to latest CPU version */
2598 #define CPU_VERSION_LATEST -1
2599
2600 /*
2601 * Resolve to version defined by current machine type.
2602 * See x86_cpu_set_default_version()
2603 */
2604 #define CPU_VERSION_AUTO -2
2605
2606 /* Don't resolve to any versioned CPU models, like old QEMU versions */
2607 #define CPU_VERSION_LEGACY 0
2608
2609 typedef int X86CPUVersion;
2610
2611 /*
2612 * Set default CPU model version for CPU models having
2613 * version == CPU_VERSION_AUTO.
2614 */
2615 void x86_cpu_set_default_version(X86CPUVersion version);
2616
2617 #ifndef CONFIG_USER_ONLY
2618
2619 void do_cpu_sipi(X86CPU *cpu);
2620
2621 #define APIC_DEFAULT_ADDRESS 0xfee00000
2622 #define APIC_SPACE_SIZE 0x100000
2623
2624 /* cpu-dump.c */
2625 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags);
2626
2627 #endif
2628
2629 /* cpu.c */
2630 bool cpu_is_bsp(X86CPU *cpu);
2631
2632 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen);
2633 void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen);
2634 uint32_t xsave_area_size(uint64_t mask, bool compacted);
2635 void x86_update_hflags(CPUX86State* env);
2636
hyperv_feat_enabled(X86CPU * cpu,int feat)2637 static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat)
2638 {
2639 return !!(cpu->hyperv_features & BIT(feat));
2640 }
2641
cr4_reserved_bits(CPUX86State * env)2642 static inline uint64_t cr4_reserved_bits(CPUX86State *env)
2643 {
2644 uint64_t reserved_bits = CR4_RESERVED_MASK;
2645 if (!env->features[FEAT_XSAVE]) {
2646 reserved_bits |= CR4_OSXSAVE_MASK;
2647 }
2648 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMEP)) {
2649 reserved_bits |= CR4_SMEP_MASK;
2650 }
2651 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) {
2652 reserved_bits |= CR4_SMAP_MASK;
2653 }
2654 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE)) {
2655 reserved_bits |= CR4_FSGSBASE_MASK;
2656 }
2657 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) {
2658 reserved_bits |= CR4_PKE_MASK;
2659 }
2660 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57)) {
2661 reserved_bits |= CR4_LA57_MASK;
2662 }
2663 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) {
2664 reserved_bits |= CR4_UMIP_MASK;
2665 }
2666 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) {
2667 reserved_bits |= CR4_PKS_MASK;
2668 }
2669 if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_LAM)) {
2670 reserved_bits |= CR4_LAM_SUP_MASK;
2671 }
2672 if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED)) {
2673 reserved_bits |= CR4_FRED_MASK;
2674 }
2675 return reserved_bits;
2676 }
2677
ctl_has_irq(CPUX86State * env)2678 static inline bool ctl_has_irq(CPUX86State *env)
2679 {
2680 uint32_t int_prio;
2681 uint32_t tpr;
2682
2683 int_prio = (env->int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT;
2684 tpr = env->int_ctl & V_TPR_MASK;
2685
2686 if (env->int_ctl & V_IGN_TPR_MASK) {
2687 return (env->int_ctl & V_IRQ_MASK);
2688 }
2689
2690 return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr);
2691 }
2692
2693 #if defined(TARGET_X86_64) && \
2694 defined(CONFIG_USER_ONLY) && \
2695 defined(CONFIG_LINUX)
2696 # define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20)
2697 #endif
2698
2699 #endif /* I386_CPU_H */
2700