xref: /netbsd/sys/arch/x86/x86/hypervreg.h (revision afdb7e40)
1 /*	$NetBSD: hypervreg.h,v 1.1 2019/02/15 08:54:01 nonaka Exp $	*/
2 /*	$OpenBSD: hypervreg.h,v 1.10 2017/01/05 13:17:22 mikeb Exp $	*/
3 
4 /*-
5  * Copyright (c) 2009-2012,2016 Microsoft Corp.
6  * Copyright (c) 2012 NetApp Inc.
7  * Copyright (c) 2012 Citrix Inc.
8  * All rights reserved.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice unmodified, this list of conditions, and the following
15  *    disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #ifndef _X86_HYPERVREG_H_
33 #define _X86_HYPERVREG_H_
34 
35 /*
36  * Hyper-V Synthetic MSRs
37  */
38 
39 #define MSR_HV_GUEST_OS_ID		0x40000000
40 #define MSR_HV_GUESTID_BUILD_MASK	0xffffULL
41 #define MSR_HV_GUESTID_VERSION_MASK	0x0000ffffffff0000ULL
42 #define MSR_HV_GUESTID_VERSION_SHIFT	16
43 #define MSR_HV_GUESTID_OSID_MASK	0x00ff000000000000ULL
44 #define MSR_HV_GUESTID_OSID_SHIFT	48
45 #define MSR_HV_GUESTID_OSTYPE_MASK	0x7f00000000000000ULL
46 #define MSR_HV_GUESTID_OSTYPE_SHIFT	56
47 #define MSR_HV_GUESTID_OPENSRC		0x8000000000000000ULL
48 #define MSR_HV_GUESTID_OSID_OPENBSD	0x0001000000000000ULL
49 #define MSR_HV_GUESTID_OSID_NETBSD	0x0002000000000000ULL
50 #define MSR_HV_GUESTID_OSTYPE_LINUX	\
51 	((0x01ULL << MSR_HV_GUESTID_OSTYPE_SHIFT) | MSR_HV_GUESTID_OPENSRC)
52 #define MSR_HV_GUESTID_OSTYPE_FREEBSD	\
53 	((0x02ULL << MSR_HV_GUESTID_OSTYPE_SHIFT) | MSR_HV_GUESTID_OPENSRC)
54 #define MSR_HV_GUESTID_OSTYPE_OPENBSD	\
55 	((0x02ULL << MSR_HV_GUESTID_OSTYPE_SHIFT) | MSR_HV_GUESTID_OPENSRC | \
56 	 MSR_HV_GUESTID_OSID_OPENBSD)
57 #define MSR_HV_GUESTID_OSTYPE_NETBSD	\
58 	((0x02ULL << MSR_HV_GUESTID_OSTYPE_SHIFT) | MSR_HV_GUESTID_OPENSRC | \
59 	 MSR_HV_GUESTID_OSID_NETBSD)
60 
61 #define MSR_HV_HYPERCALL		0x40000001
62 #define MSR_HV_HYPERCALL_ENABLE		0x0001ULL
63 #define MSR_HV_HYPERCALL_RSVD_MASK	0x0ffeULL
64 #define MSR_HV_HYPERCALL_PGSHIFT	12
65 
66 #define MSR_HV_VP_INDEX			0x40000002
67 
68 #define MSR_HV_TIME_REF_COUNT		0x40000020
69 
70 #define MSR_HV_REFERENCE_TSC		0x40000021
71 #define MSR_HV_REFTSC_ENABLE		0x0001ULL
72 #define MSR_HV_REFTSC_RSVD_MASK		0x0ffeULL
73 #define MSR_HV_REFTSC_PGSHIFT		12
74 
75 #define MSR_HV_TSC_FREQUENCY		0x40000022
76 
77 #define MSR_HV_APIC_FREQUENCY		0x40000023
78 
79 #define MSR_HV_SCONTROL			0x40000080
80 #define MSR_HV_SCTRL_ENABLE		0x0001ULL
81 #define MSR_HV_SCTRL_RSVD_MASK		0xfffffffffffffffeULL
82 
83 #define MSR_HV_SIEFP			0x40000082
84 #define MSR_HV_SIEFP_ENABLE		0x0001ULL
85 #define MSR_HV_SIEFP_RSVD_MASK		0x0ffeULL
86 #define MSR_HV_SIEFP_PGSHIFT		12
87 
88 #define MSR_HV_SIMP			0x40000083
89 #define MSR_HV_SIMP_ENABLE		0x0001ULL
90 #define MSR_HV_SIMP_RSVD_MASK		0x0ffeULL
91 #define MSR_HV_SIMP_PGSHIFT		12
92 
93 #define MSR_HV_EOM			0x40000084
94 
95 #define MSR_HV_SINT0			0x40000090
96 #define MSR_HV_SINT_VECTOR_MASK		0x00ffULL
97 #define MSR_HV_SINT_RSVD1_MASK		0xff00ULL
98 #define MSR_HV_SINT_MASKED		0x00010000ULL
99 #define MSR_HV_SINT_AUTOEOI		0x00020000ULL
100 #define MSR_HV_SINT_RSVD2_MASK		0xfffffffffffc0000ULL
101 #define MSR_HV_SINT_RSVD_MASK		(MSR_HV_SINT_RSVD1_MASK |	\
102 					 MSR_HV_SINT_RSVD2_MASK)
103 
104 #define MSR_HV_STIMER0_CONFIG		0x400000b0
105 #define MSR_HV_STIMER_CFG_ENABLE	0x0001ULL
106 #define MSR_HV_STIMER_CFG_PERIODIC	0x0002ULL
107 #define MSR_HV_STIMER_CFG_LAZY		0x0004ULL
108 #define MSR_HV_STIMER_CFG_AUTOEN	0x0008ULL
109 #define MSR_HV_STIMER_CFG_SINT_MASK	0x000f0000ULL
110 #define MSR_HV_STIMER_CFG_SINT_SHIFT	16
111 
112 #define MSR_HV_STIMER0_COUNT		0x400000b1
113 
114 /*
115  * CPUID leaves
116  */
117 
118 #define CPUID_LEAF_HV_MAXLEAF		0x40000000
119 
120 #define CPUID_LEAF_HV_INTERFACE		0x40000001
121 #define CPUID_HV_IFACE_HYPERV		0x31237648	/* HV#1 */
122 
123 #define CPUID_LEAF_HV_IDENTITY		0x40000002
124 
125 #define CPUID_LEAF_HV_FEATURES		0x40000003
126 /* EAX: features */
127 #define CPUID_HV_MSR_TIME_REFCNT	0x0002	/* MSR_HV_TIME_REF_COUNT */
128 #define CPUID_HV_MSR_SYNIC		0x0004	/* MSRs for SynIC */
129 #define CPUID_HV_MSR_SYNTIMER		0x0008	/* MSRs for SynTimer */
130 #define CPUID_HV_MSR_APIC		0x0010	/* MSR_HV_{EOI,ICR,TPR} */
131 #define CPUID_HV_MSR_HYPERCALL		0x0020	/* MSR_HV_GUEST_OS_ID
132 						 * MSR_HV_HYPERCALL */
133 #define CPUID_HV_MSR_VP_INDEX		0x0040	/* MSR_HV_VP_INDEX */
134 #define CPUID_HV_MSR_REFERENCE_TSC	0x0200	/* MSR_HV_REFERENCE_TSC */
135 #define CPUID_HV_MSR_GUEST_IDLE		0x0400	/* MSR_HV_GUEST_IDLE */
136 #define CPUID_HV_MSR_TIME_FREQ		0x0800	/* MSR_HV_xxx_FREQUENCY */
137 /* ECX: power management features */
138 #define CPUPM_HV_CSTATE_MASK		0x000f	/* deepest C-state */
139 #define CPUPM_HV_C3_HPET		0x0010	/* C3 requires HPET */
140 #define CPUPM_HV_CSTATE(f)		((f) & CPUPM_HV_CSTATE_MASK)
141 /* EDX: features3 */
142 #define CPUID3_HV_MWAIT			0x0001	/* MWAIT */
143 #define CPUID3_HV_XMM_HYPERCALL		0x0010	/* Hypercall input through
144 						 * XMM regs */
145 #define CPUID3_HV_GUEST_IDLE		0x0020	/* guest idle */
146 #define CPUID3_HV_NUMA			0x0080	/* NUMA distance query */
147 #define CPUID3_HV_TIME_FREQ		0x0100	/* timer frequency query
148 						 * (TSC, LAPIC) */
149 #define CPUID3_HV_MSR_CRASH		0x0400	/* MSRs for guest crash */
150 
151 #define CPUID_LEAF_HV_RECOMMENDS	0x40000004
152 #define CPUID_LEAF_HV_LIMITS		0x40000005
153 #define CPUID_LEAF_HV_HWFEATURES	0x40000006
154 
155 #endif /* _X86_HYPERVREG_H_ */
156