1 /* gameplaySP 2 * 3 * Copyright (C) 2006 Exophase <exophase@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 18 */ 19 20 #ifndef CPU_H 21 #define CPU_H 22 23 // System mode and user mode are represented as the same here 24 25 typedef enum 26 { 27 MODE_USER, 28 MODE_IRQ, 29 MODE_FIQ, 30 MODE_SUPERVISOR, 31 MODE_ABORT, 32 MODE_UNDEFINED, 33 MODE_INVALID 34 } cpu_mode_type; 35 36 typedef enum 37 { 38 CPU_ALERT_NONE, 39 CPU_ALERT_HALT, 40 CPU_ALERT_SMC, 41 CPU_ALERT_IRQ 42 } cpu_alert_type; 43 44 typedef enum 45 { 46 CPU_ACTIVE, 47 CPU_HALT, 48 CPU_STOP 49 } cpu_halt_type; 50 51 typedef enum 52 { 53 IRQ_NONE = 0x0000, 54 IRQ_VBLANK = 0x0001, 55 IRQ_HBLANK = 0x0002, 56 IRQ_VCOUNT = 0x0004, 57 IRQ_TIMER0 = 0x0008, 58 IRQ_TIMER1 = 0x0010, 59 IRQ_TIMER2 = 0x0020, 60 IRQ_TIMER3 = 0x0040, 61 IRQ_SERIAL = 0x0080, 62 IRQ_DMA0 = 0x0100, 63 IRQ_DMA1 = 0x0200, 64 IRQ_DMA2 = 0x0400, 65 IRQ_DMA3 = 0x0800, 66 IRQ_KEYPAD = 0x1000, 67 IRQ_GAMEPAK = 0x2000 68 } irq_type; 69 70 typedef enum 71 { 72 REG_SP = 13, 73 REG_LR = 14, 74 REG_PC = 15, 75 REG_N_FLAG = 16, 76 REG_Z_FLAG = 17, 77 REG_C_FLAG = 18, 78 REG_V_FLAG = 19, 79 REG_CPSR = 20, 80 REG_SAVE = 21, 81 REG_SAVE2 = 22, 82 REG_SAVE3 = 23, 83 CPU_MODE = 29, 84 CPU_HALT_STATE = 30, 85 CHANGED_PC_STATUS = 31 86 } ext_reg_numbers; 87 88 typedef enum 89 { 90 TRANSLATION_REGION_RAM, 91 TRANSLATION_REGION_ROM, 92 TRANSLATION_REGION_BIOS 93 } translation_region_type; 94 95 extern u32 instruction_count; 96 extern u32 last_instruction; 97 98 void execute_arm(u32 cycles); 99 void raise_interrupt(irq_type irq_raised); 100 void set_cpu_mode(cpu_mode_type new_mode); 101 102 u32 execute_load_u8(u32 address); 103 u32 execute_load_u16(u32 address); 104 u32 execute_load_u32(u32 address); 105 u32 execute_load_s8(u32 address); 106 u32 execute_load_s16(u32 address); 107 void execute_store_u8(u32 address, u32 source); 108 void execute_store_u16(u32 address, u32 source); 109 void execute_store_u32(u32 address, u32 source); 110 u32 execute_arm_translate(u32 cycles); 111 void init_translater(void); 112 void cpu_write_savestate(void); 113 void cpu_read_savestate(void); 114 115 u8 *block_lookup_address_arm(u32 pc); 116 u8 *block_lookup_address_thumb(u32 pc); 117 s32 translate_block_arm(u32 pc, translation_region_type translation_region, 118 u32 smc_enable); 119 s32 translate_block_thumb(u32 pc, translation_region_type translation_region, 120 u32 smc_enable); 121 122 #if defined(PSP) 123 124 #define ROM_TRANSLATION_CACHE_SIZE (1024 * 512 * 4) 125 #define RAM_TRANSLATION_CACHE_SIZE (1024 * 384) 126 #define BIOS_TRANSLATION_CACHE_SIZE (1024 * 128) 127 #define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024) 128 129 #else 130 131 #define ROM_TRANSLATION_CACHE_SIZE (1024 * 512 * 4 * 5) 132 #define RAM_TRANSLATION_CACHE_SIZE (1024 * 384 * 2) 133 #define BIOS_TRANSLATION_CACHE_SIZE (1024 * 128 * 2) 134 #define TRANSLATION_CACHE_LIMIT_THRESHOLD (1024 * 32) 135 136 #endif 137 138 #if defined(HAVE_MMAP) 139 extern u8* rom_translation_cache; 140 extern u8* ram_translation_cache; 141 extern u8* bios_translation_cache; 142 #elif defined(_3DS) 143 #define rom_translation_cache ((u8*)0x02000000 - ROM_TRANSLATION_CACHE_SIZE) 144 #define ram_translation_cache (rom_translation_cache - RAM_TRANSLATION_CACHE_SIZE) 145 #define bios_translation_cache (ram_translation_cache - BIOS_TRANSLATION_CACHE_SIZE) 146 extern u8* rom_translation_cache_ptr; 147 extern u8* ram_translation_cache_ptr; 148 extern u8* bios_translation_cache_ptr; 149 #elif defined(VITA) 150 extern u8* rom_translation_cache; 151 extern u8* ram_translation_cache; 152 extern u8* bios_translation_cache; 153 extern int sceBlock; 154 #else 155 extern u8 rom_translation_cache[ROM_TRANSLATION_CACHE_SIZE]; 156 extern u8 ram_translation_cache[RAM_TRANSLATION_CACHE_SIZE]; 157 extern u8 bios_translation_cache[BIOS_TRANSLATION_CACHE_SIZE]; 158 #endif 159 extern u8 *rom_translation_ptr; 160 extern u8 *ram_translation_ptr; 161 extern u8 *bios_translation_ptr; 162 163 #define MAX_TRANSLATION_GATES 8 164 165 extern u32 idle_loop_target_pc; 166 extern u32 force_pc_update_target; 167 extern u32 iwram_stack_optimize; 168 extern u32 allow_smc_ram_u8; 169 extern u32 allow_smc_ram_u16; 170 extern u32 allow_smc_ram_u32; 171 extern u32 direct_map_vram; 172 extern u32 translation_gate_targets; 173 extern u32 translation_gate_target_pc[MAX_TRANSLATION_GATES]; 174 175 extern u32 in_interrupt; 176 177 #define ROM_BRANCH_HASH_SIZE (1024 * 64) 178 179 /* EDIT: Shouldn't this be extern ?! */ 180 extern u32 *rom_branch_hash[ROM_BRANCH_HASH_SIZE]; 181 182 void flush_translation_cache_rom(void); 183 void flush_translation_cache_ram(void); 184 void flush_translation_cache_bios(void); 185 void dump_translation_cache(void); 186 187 extern u32 reg_mode[7][7]; 188 extern u32 spsr[6]; 189 190 extern u32 cpu_modes[32]; 191 extern const u32 psr_masks[16]; 192 193 extern u32 memory_region_access_read_u8[16]; 194 extern u32 memory_region_access_read_s8[16]; 195 extern u32 memory_region_access_read_u16[16]; 196 extern u32 memory_region_access_read_s16[16]; 197 extern u32 memory_region_access_read_u32[16]; 198 extern u32 memory_region_access_write_u8[16]; 199 extern u32 memory_region_access_write_u16[16]; 200 extern u32 memory_region_access_write_u32[16]; 201 extern u32 memory_reads_u8; 202 extern u32 memory_reads_s8; 203 extern u32 memory_reads_u16; 204 extern u32 memory_reads_s16; 205 extern u32 memory_reads_u32; 206 extern u32 memory_writes_u8; 207 extern u32 memory_writes_u16; 208 extern u32 memory_writes_u32; 209 210 void init_cpu(void); 211 void move_reg(); 212 213 #endif 214