1 #ifndef _CPU_H_ 2 #define _CPU_H_ 3 4 extern int cpu, cpu_manufacturer; 5 6 /*808x class CPUs*/ 7 #define CPU_8088 0 8 #define CPU_8086 1 9 10 /*286 class CPUs*/ 11 #define CPU_286 2 12 13 /*386 class CPUs*/ 14 #define CPU_386SX 3 15 #define CPU_386DX 4 16 #define CPU_486SLC 5 17 #define CPU_486DLC 6 18 19 /*486 class CPUs*/ 20 #define CPU_i486SX 7 21 #define CPU_Am486SX 8 22 #define CPU_Cx486S 9 23 #define CPU_i486DX 10 24 #define CPU_Am486DX 11 25 #define CPU_Cx486DX 12 26 #define CPU_iDX4 13 27 #define CPU_Cx5x86 14 28 29 /*586 class CPUs*/ 30 #define CPU_WINCHIP 15 31 #define CPU_PENTIUM 16 32 #define CPU_PENTIUMMMX 17 33 #define CPU_Cx6x86 18 34 #define CPU_Cx6x86MX 19 35 #define CPU_Cx6x86L 20 36 #define CPU_CxGX1 21 37 38 #define MANU_INTEL 0 39 #define MANU_AMD 1 40 #define MANU_CYRIX 2 41 #define MANU_IDT 3 42 43 extern int timing_rr; 44 extern int timing_mr, timing_mrl; 45 extern int timing_rm, timing_rml; 46 extern int timing_mm, timing_mml; 47 extern int timing_bt, timing_bnt; 48 49 extern int timing_int, timing_int_rm, timing_int_v86, timing_int_pm, timing_int_pm_outer; 50 extern int timing_iret_rm, timing_iret_v86, timing_iret_pm, timing_iret_pm_outer; 51 extern int timing_call_rm, timing_call_pm, timing_call_pm_gate, timing_call_pm_gate_inner; 52 extern int timing_retf_rm, timing_retf_pm, timing_retf_pm_outer; 53 extern int timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate; 54 55 extern int timing_misaligned; 56 57 typedef struct 58 { 59 char name[32]; 60 int cpu_type; 61 int speed; 62 int rspeed; 63 int multi; 64 int pci_speed; 65 uint32_t edx_reset; 66 uint32_t cpuid_model; 67 uint16_t cyrix_id; 68 int cpu_flags; 69 int mem_read_cycles, mem_write_cycles; 70 int cache_read_cycles, cache_write_cycles; 71 int atclk_div; 72 } CPU; 73 74 extern CPU cpus_8088[]; 75 extern CPU cpus_8086[]; 76 extern CPU cpus_286[]; 77 extern CPU cpus_i386SX[]; 78 extern CPU cpus_i386DX[]; 79 extern CPU cpus_Am386SX[]; 80 extern CPU cpus_Am386DX[]; 81 extern CPU cpus_486SLC[]; 82 extern CPU cpus_486DLC[]; 83 extern CPU cpus_i486[]; 84 extern CPU cpus_Am486[]; 85 extern CPU cpus_Cx486[]; 86 extern CPU cpus_WinChip[]; 87 extern CPU cpus_Pentium5V[]; 88 extern CPU cpus_PentiumS5[]; 89 extern CPU cpus_Pentium[]; 90 extern CPU cpus_6x86[]; 91 92 extern CPU cpus_pcjr[]; 93 extern CPU cpus_europc[]; 94 extern CPU cpus_pc1512[]; 95 extern CPU cpus_ibmat[]; 96 extern CPU cpus_ibmxt286[]; 97 extern CPU cpus_ps1_m2011[]; 98 extern CPU cpus_ps2_m30_286[]; 99 extern CPU cpus_acer[]; 100 101 extern int cpu_iscyrix; 102 extern int cpu_16bitbus; 103 extern int cpu_busspeed; 104 extern int cpu_multi; 105 /*Cyrix 5x86/6x86 only has data misalignment penalties when crossing 8-byte boundaries*/ 106 extern int cpu_cyrix_alignment; 107 108 extern int cpu_hasrdtsc; 109 extern int cpu_hasMSR; 110 extern int cpu_hasMMX; 111 extern int cpu_hasCR4; 112 extern int cpu_hasVME; 113 extern int cpu_hasCX8; 114 115 #define CR4_TSD (1 << 2) 116 #define CR4_DE (1 << 3) 117 #define CR4_MCE (1 << 6) 118 #define CR4_PCE (1 << 8) 119 120 extern uint64_t cpu_CR4_mask; 121 122 #define CPU_SUPPORTS_DYNAREC 1 123 #define CPU_REQUIRES_DYNAREC 2 124 125 extern int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l; 126 extern int cpu_prefetch_cycles, cpu_prefetch_width, cpu_mem_prefetch_cycles, cpu_rom_prefetch_cycles; 127 extern int cpu_waitstates; 128 extern int cpu_cache_int_enabled, cpu_cache_ext_enabled; 129 130 extern uint64_t tsc; 131 132 void cyrix_write(uint16_t addr, uint8_t val, void *priv); 133 uint8_t cyrix_read(uint16_t addr, void *priv); 134 135 extern int is8086; 136 137 void cpu_CPUID(); 138 void cpu_RDMSR(); 139 void cpu_WRMSR(); 140 141 extern int cpu_use_dynarec; 142 143 extern int xt_cpu_multi; 144 145 extern int isa_cycles; 146 #define ISA_CYCLES(x) (x * isa_cycles) 147 148 void cpu_update_waitstates(); 149 void cpu_set(); 150 void cpu_set_edx(); 151 void cpu_set_turbo(int turbo); 152 int cpu_get_speed(); 153 154 extern int has_vlb; 155 156 #endif 157