1 /*
2 Hatari - m68000.h
3
4 This file is distributed under the GNU General Public License, version 2
5 or at your option any later version. Read the file gpl.txt for details.
6 */
7
8 /* 2007/11/10 [NP] Add pairing for lsr / dbcc (and all variants */
9 /* working on register, not on memory). */
10 /* 2008/01/07 [NP] Use PairingArray to store all valid pairing */
11 /* combinations (in m68000.c) */
12 /* 2010/04/05 [NP] Rework the pairing code to take BusCyclePenalty */
13 /* into account when using d8(an,ix). */
14 /* 2010/05/07 [NP] Add BusCyclePenalty to LastInstrCycles to detect*/
15 /* a possible pairing between add.l (a5,d1.w),d0 */
16 /* and move.b 7(a5,d1.w),d5. */
17
18
19 #ifndef HATARI_M68000_H
20 #define HATARI_M68000_H
21
22 #include "cycles.h" /* for nCyclesMainCounter */
23 #include "sysdeps.h"
24 #include "memory.h"
25 #include "newcpu.h" /* for regs */
26 #include "cycInt.h"
27 #include "log.h"
28
29
30 /* 68000 Register defines */
31 enum {
32 REG_D0, /* D0.. */
33 REG_D1,
34 REG_D2,
35 REG_D3,
36 REG_D4,
37 REG_D5,
38 REG_D6,
39 REG_D7, /* ..D7 */
40 REG_A0, /* A0.. */
41 REG_A1,
42 REG_A2,
43 REG_A3,
44 REG_A4,
45 REG_A5,
46 REG_A6,
47 REG_A7 /* ..A7 (also SP) */
48 };
49
50 /* 68000 Condition code's */
51 #define SR_AUX 0x0010
52 #define SR_NEG 0x0008
53 #define SR_ZERO 0x0004
54 #define SR_OVERFLOW 0x0002
55 #define SR_CARRY 0x0001
56
57 #define SR_CLEAR_AUX 0xffef
58 #define SR_CLEAR_NEG 0xfff7
59 #define SR_CLEAR_ZERO 0xfffb
60 #define SR_CLEAR_OVERFLOW 0xfffd
61 #define SR_CLEAR_CARRY 0xfffe
62
63 #define SR_CCODE_MASK (SR_AUX|SR_NEG|SR_ZERO|SR_OVERFLOW|SR_CARRY)
64 #define SR_MASK 0xFFE0
65
66 #define SR_TRACEMODE 0x8000
67 #define SR_SUPERMODE 0x2000
68 #define SR_IPL 0x0700
69
70 #define SR_CLEAR_IPL 0xf8ff
71 #define SR_CLEAR_TRACEMODE 0x7fff
72 #define SR_CLEAR_SUPERMODE 0xdfff
73
74 /* Exception numbers most commonly used in ST */
75 #define EXCEPTION_NR_BUSERROR 2
76 #define EXCEPTION_NR_ADDRERROR 3
77 #define EXCEPTION_NR_ILLEGALINS 4
78 #define EXCEPTION_NR_DIVZERO 5
79 #define EXCEPTION_NR_CHK 6
80 #define EXCEPTION_NR_TRAPV 7
81 #define EXCEPTION_NR_TRACE 9
82 #define EXCEPTION_NR_LINE_A 10
83 #define EXCEPTION_NR_LINE_F 11
84 #define EXCEPTION_NR_HBLANK 26 /* Level 2 interrupt */
85 #define EXCEPTION_NR_VBLANK 28 /* Level 4 interrupt */
86 #define EXCEPTION_NR_MFP_DSP 30 /* Level 6 interrupt */
87 #define EXCEPTION_NR_TRAP0 32
88 #define EXCEPTION_NR_TRAP1 33
89 #define EXCEPTION_NR_TRAP2 34
90 #define EXCEPTION_NR_TRAP13 45
91 #define EXCEPTION_NR_TRAP14 46
92
93
94 /* Size of 68000 instructions */
95 #define MAX_68000_INSTRUCTION_SIZE 10 /* Longest 68000 instruction is 10 bytes(6+4) */
96 #define MIN_68000_INSTRUCTION_SIZE 2 /* Smallest 68000 instruction is 2 bytes(ie NOP) */
97
98 /* Illegal Opcode used to help emulation. eg. free entries are 8 to 15 inc' */
99 #define GEMDOS_OPCODE 8 /* Free op-code to intercept GemDOS trap */
100 #define SYSINIT_OPCODE 10 /* Free op-code to initialize system (connected drives etc.) */
101 #define VDI_OPCODE 12 /* Free op-code to call VDI handlers AFTER Trap#2 */
102
103 /* Illegal opcodes used for Native Features emulation:
104 * http://wiki.aranym.org/natfeats/proposal#special_opcodes
105 */
106 #define NATFEAT_ID_OPCODE 0x7300
107 #define NATFEAT_CALL_OPCODE 0x7301
108
109
110 /* Ugly hacks to adapt the main code to the different CPU cores: */
111
112 #define Regs regs.regs
113
114
115 # define M68000_GetPC() m68k_getpc()
116
117 # define M68000_InstrPC regs.instruction_pc
118 # define M68000_CurrentOpcode regs.opcode
119
120 # define M68000_SetSpecial(flags) set_special(flags)
121 # define M68000_UnsetSpecial(flags) unset_special(flags)
122
123
124 /* Some define's for bus error (see newcpu.c) */
125 /* Bus error read/write mode */
126 #define BUS_ERROR_WRITE 0
127 #define BUS_ERROR_READ 1
128 /* Bus error access size */
129 #define BUS_ERROR_SIZE_BYTE 1
130 #define BUS_ERROR_SIZE_WORD 2
131 #define BUS_ERROR_SIZE_LONG 4
132 /* Bus error access type */
133 #define BUS_ERROR_ACCESS_INSTR 0
134 #define BUS_ERROR_ACCESS_DATA 1
135
136
137 /* Bus access mode */
138 #define BUS_MODE_CPU 0 /* bus is owned by the cpu */
139 #define BUS_MODE_BLITTER 1 /* bus is owned by the blitter */
140
141
142 /* [NP] Notes on IACK :
143 * When an interrupt happens, it's possible a similar interrupt happens again
144 * between the start of the exception and the IACK sequence. In that case, we
145 * might have to set pending bit twice and change the interrupt vector.
146 *
147 * From the 68000's doc, IACK starts after 10 cycles (12 cycles on STF due to 2 cycle
148 * bus penalty) and is supposed to take 4 cycles if the interrupt takes a total of 44 cycles.
149 *
150 * On Atari STF, interrupts take 56 cycles instead of 44, which means it takes
151 * 12 extra cycles to fetch the vector number and to handle non-aligned memory accesses.
152 * From WinUAE's CE mode, we have 2 non-aligned memory accesses to wait for (ie 2+2 cycles),
153 * which leaves a total of 12 cycles to fetch the vector.
154 *
155 * As seen wth a custom program on STF that measures HBL's jitter, we get the same results with Hatari
156 * in CE mode if we use 10 cycles to fetch the vector (step 3), which will also add 2 cycle penalty (step 4b)
157 * This means we have at max 12+10=22 cycles after the start of the exception where some
158 * changes can happen (maybe it's a little less, depending on when the interrupt
159 * vector is written on the bus).
160 *
161 * Additionally, auto vectored interrupts (HBL and VBL) require to be in sync with E-clock,
162 * which can add 0 to 8 cycles (step 3a). In that case we have between 22+0 and 22+8 cycles
163 * to get another interrupt before vector is written on the bus.
164 *
165 * The values we use were not entirely measured on real ST hardware, they were guessed/adjusted
166 * to get the correct behaviour in some games/demos relying on this.
167 * These values are when running in CE mode (2 cycle precision) ; when CPU runs in prefetch
168 * mode, values need to be rounded to 4).
169 *
170 * Interrupt steps + WinUAE cycles (measured on real A500 HW) + ST specific values :
171 *
172 * 1 6 idle cycles
173 * 1b 2(*) ST bus access penalty (if necessary)
174 * 2 4 write PC low word
175 * 3a 0-8(*) wait for E-clock for auto vectored interrupt
176 * 3 10(*) read exception number
177 * 4 4 idle cycles
178 * 4b 2(*) ST bus access penalty
179 * 5 4 write SR
180 * 6 4 write PC high word
181 * 7 4 read exception address high word
182 * 8 4 read exception address low word
183 * 9 4 prefetch
184 * 10 2 idle cycles
185 * 10b 2(*) ST bus access penalty
186 * 11 4 prefetch
187 * TOTAL = 56
188 *
189 * (*) ST specific timings
190 */
191
192 /* Values for IACK sequence when running in cycle exact mode */
193 #define CPU_IACK_CYCLES_MFP_CE 12 /* vector sent by the MFP (TODO value not measured on real STF) */
194 #define CPU_IACK_CYCLES_VIDEO_CE 10 /* auto vectored for HBL/VBL (value measured on real STF) */
195
196 /* Values for IACK sequence when running in normal/prefetch mode or when using old UAE CPU */
197 #define CPU_IACK_CYCLES_START 12 /* number of cycles before starting the IACK when not using CE mode */
198 /* (this should be a multiple of 4, else it will be rounded by M68000_AddCycles) */
199 #define CPU_IACK_CYCLES_MFP 12 /* vector sent by the MFP */
200 #define CPU_IACK_CYCLES_VIDEO 12 /* auto vectored for HBL/VBL */
201
202 /* Informations about current CPU instruction */
203 typedef struct {
204 /* These are provided only by WinUAE CPU core */
205 int I_Cache_miss; /* Instruction cache for 68020/30/40/60 */
206 int I_Cache_hit;
207 int D_Cache_miss; /* Data cache for 68030/40/60 */
208 int D_Cache_hit;
209
210 /* TODO: move other instruction specific Hatari variables here */
211 } cpu_instruction_t;
212
213 extern cpu_instruction_t CpuInstruction;
214
215 extern Uint32 BusErrorAddress;
216 extern bool bBusErrorReadWrite;
217 extern int nCpuFreqShift;
218 extern int WaitStateCycles;
219 extern int BusMode;
220 extern bool CPU_IACK;
221
222 extern int LastOpcodeFamily;
223 extern int LastInstrCycles;
224 extern int Pairing;
225 extern char PairingArray[ MAX_OPCODE_FAMILY ][ MAX_OPCODE_FAMILY ];
226 extern const char *OpcodeName[];
227
228
229 /*-----------------------------------------------------------------------*/
230 /**
231 * Add CPU cycles.
232 * NOTE: All times are rounded up to nearest 4 cycles.
233 */
M68000_AddCycles(int cycles)234 static inline void M68000_AddCycles(int cycles)
235 {
236 cycles = (cycles + 3) & ~3;
237 PendingInterruptCount -= INT_CONVERT_TO_INTERNAL ( cycles , INT_CPU_CYCLE );
238 nCyclesMainCounter += cycles;
239 CyclesGlobalClockCounter += cycles;
240 }
241
242
243 /*-----------------------------------------------------------------------*/
244 /**
245 * Add CPU cycles, take cycles pairing into account. Pairing will make
246 * some specific instructions take 4 cycles less when run one after the other.
247 * Pairing happens when the 2 instructions are "aligned" on different bus accesses.
248 * Candidates are :
249 * - 2 instructions taking 4n+2 cycles
250 * - 1 instruction taking 4n+2 cycles, followed by 1 instruction using d8(an,ix)
251 *
252 * Not all the candidate instructions can pair, only the opcodes listed in PairingArray.
253 * On ST, when using d8(an,ix), we get an extra 2 cycle penalty for misaligned bus access.
254 * The only instruction that can generate BusCyclePenalty=4 is move d8(an,ix),d8(an,ix)
255 * and although it takes 4n cycles (24 for .b/.w or 32 for .l) it can pair with
256 * a previous 4n+2 instruction (but it will still have 1 misaligned bus access in the end).
257 *
258 * Verified pairing on an STF :
259 * - lsl.w #4,d1 + move.w 0(a4,d2.w),d1 motorola=14+14=28 stf=28
260 * - lsl.w #4,d1 + move.w 0(a4,d2.w),(a4) motorola=14+18=32 stf=32
261 * - lsl.w #4,d1 + move.w 0(a4,d2.w),0(a4,d2.w) motorola=14+24=38 stf=40
262 * - add.l (a5,d1.w),d0 + move.b 7(a5,d1.w),d5) motorola=20+14=34 stf=36
263 *
264 * d8(an,ix) timings without pairing (2 cycles penalty) :
265 * - add.l 0(a4,d2.w),a1 motorola=20 stf=24
266 * - move.w 0(a4,d2.w),d1 motorola=14 stf=16
267 * - move.w 0(a4,d2.w),(a4) motorola=18 stf=20
268 * - move.w 0(a4,d2.w),0(a4,d2.w) motorola=24 stf=28
269 *
270 * NOTE: All times are rounded up to nearest 4 cycles.
271 */
M68000_AddCyclesWithPairing(int cycles)272 static inline void M68000_AddCyclesWithPairing(int cycles)
273 {
274 Pairing = 0;
275 /* Check if number of cycles for current instr and for */
276 /* the previous one is of the form 4+2n */
277 /* If so, a pairing could be possible depending on the opcode */
278 /* A pairing is also possible if current instr is 4n but with BusCyclePenalty > 0 */
279 if ( ( PairingArray[ LastOpcodeFamily ][ OpcodeFamily ] == 1 )
280 && ( ( LastInstrCycles & 3 ) == 2 )
281 && ( ( ( cycles & 3 ) == 2 ) || ( BusCyclePenalty > 0 ) ) )
282 {
283 Pairing = 1;
284 LOG_TRACE(TRACE_CPU_PAIRING,
285 "cpu pairing detected pc=%x family %s/%s cycles %d/%d\n",
286 m68k_getpc(), OpcodeName[LastOpcodeFamily],
287 OpcodeName[OpcodeFamily], LastInstrCycles, cycles);
288 }
289
290 /* [NP] This part is only needed to track possible pairing instructions, */
291 /* we can keep it disabled most of the time */
292 #if 0
293 if ( (LastOpcodeFamily!=OpcodeFamily) && ( Pairing == 0 )
294 && ( ( cycles & 3 ) == 2 ) && ( ( LastInstrCycles & 3 ) == 2 ) )
295 {
296 LOG_TRACE(TRACE_CPU_PAIRING,
297 "cpu could pair pc=%x family %s/%s cycles %d/%d\n",
298 m68k_getpc(), OpcodeName[LastOpcodeFamily],
299 OpcodeName[OpcodeFamily], LastInstrCycles, cycles);
300 }
301 #endif
302
303 /* Store current instr (not rounded) to check next time */
304 LastInstrCycles = cycles + BusCyclePenalty;
305 LastOpcodeFamily = OpcodeFamily;
306
307 /* If pairing is true, we need to subtract 2 cycles for the */
308 /* previous instr which was rounded to 4 cycles while it wasn't */
309 /* needed (and we don't round the current one) */
310 /* -> both instr will take 4 cycles less on the ST than if ran */
311 /* separately. */
312 if (Pairing == 1)
313 {
314 if ( ( cycles & 3 ) == 2 ) /* pairing between 4n+2 and 4n+2 instructions */
315 cycles -= 2; /* if we have a pairing, we should not count the misaligned bus access */
316
317 else /* this is the case of move d8(an,ix),d8(an,ix) where BusCyclePenalty=4 */
318 /*do nothing */; /* we gain 2 cycles for the pairing with 1st d8(an,ix) */
319 /* and we have 1 remaining misaligned access for the 2nd d8(an,ix). So in the end, we keep */
320 /* cycles unmodified as 4n cycles (eg lsl.w #4,d1 + move.w 0(a4,d2.w),0(a4,d2.w) takes 40 cycles) */
321 }
322 else
323 {
324 cycles += BusCyclePenalty; /* >0 if d8(an,ix) was used */
325 cycles = (cycles + 3) & ~3; /* no pairing, round current instr to 4 cycles */
326 }
327
328 PendingInterruptCount -= INT_CONVERT_TO_INTERNAL ( cycles , INT_CPU_CYCLE );
329
330 nCyclesMainCounter += cycles;
331 CyclesGlobalClockCounter += cycles;
332 BusCyclePenalty = 0;
333 }
334
335
336 /*-----------------------------------------------------------------------*/
337 /**
338 * Add CPU cycles when using WinUAE CPU 'cycle exact' mode.
339 * In this mode, we should not round cycles to the next nearest 4 cycles
340 * because all memory accesses will already be aligned to 4 cycles when
341 * using CE mode.
342 * The CE mode will also give the correct 'instruction pairing' for all
343 * opcodes/addressing mode, without requiring tables/heuristics (in the
344 * same way that it's done in real hardware)
345 */
M68000_AddCycles_CE(int cycles)346 static inline void M68000_AddCycles_CE(int cycles)
347 {
348 PendingInterruptCount -= INT_CONVERT_TO_INTERNAL ( cycles , INT_CPU_CYCLE );
349
350 nCyclesMainCounter += cycles;
351 CyclesGlobalClockCounter += cycles;
352 }
353
354
355
356 extern void M68000_Init(void);
357 extern void M68000_Reset(bool bCold);
358 extern void M68000_SetDebugger(bool debug);
359 extern void M68000_RestoreDebugger(void);
360 extern void M68000_Start(void);
361 extern void M68000_CheckCpuSettings(void);
362 extern void M68000_MemorySnapShot_Capture(bool bSave);
363 extern bool M68000_IsVerboseBusError(uint32_t pc, uint32_t addr);
364 extern void M68000_BusError ( Uint32 addr , int ReadWrite , int Size , int AccessType );
365 extern void M68000_Exception(Uint32 ExceptionNr , int ExceptionSource);
366 extern void M68000_Update_intlev ( void );
367 extern void M68000_WaitState(int WaitCycles);
368 extern int M68000_WaitEClock ( void );
369 extern void M68000_SyncCpuBus_OnReadAccess ( void );
370 extern void M68000_SyncCpuBus_OnWriteAccess ( void );
371 extern void M68000_Flush_Instr_Cache ( uaecptr addr , int size );
372 extern void M68000_Flush_Data_Cache ( uaecptr addr , int size );
373 extern void M68000_Flush_All_Caches ( uaecptr addr , int size );
374 extern void M68000_SetBlitter_CE ( bool ce_mode );
375 extern int DMA_MaskAddressHigh ( void );
376 extern void M68000_ChangeCpuFreq ( void );
377 extern Uint16 M68000_GetSR ( void );
378 extern void M68000_SetSR ( Uint16 v );
379 extern void M68000_SetPC ( uaecptr v );
380
381 #endif
382