1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_ASIC_H__ 29 #define __RADEON_ASIC_H__ 30 31 /* 32 * common functions 33 */ 34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); 35 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 36 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); 37 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 38 39 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); 40 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 41 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); 42 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); 43 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 44 45 void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 46 u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); 47 void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 48 u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); 49 50 /* 51 * r100,rv100,rs100,rv200,rs200 52 */ 53 struct r100_mc_save { 54 u32 GENMO_WT; 55 u32 CRTC_EXT_CNTL; 56 u32 CRTC_GEN_CNTL; 57 u32 CRTC2_GEN_CNTL; 58 u32 CUR_OFFSET; 59 u32 CUR2_OFFSET; 60 }; 61 int r100_init(struct radeon_device *rdev); 62 void r100_fini(struct radeon_device *rdev); 63 int r100_suspend(struct radeon_device *rdev); 64 int r100_resume(struct radeon_device *rdev); 65 void r100_vga_set_state(struct radeon_device *rdev, bool state); 66 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 67 int r100_asic_reset(struct radeon_device *rdev, bool hard); 68 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); 69 void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 70 uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags); 71 void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i, 72 uint64_t entry); 73 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 74 int r100_irq_set(struct radeon_device *rdev); 75 irqreturn_t r100_irq_process(struct radeon_device *rdev); 76 void r100_fence_ring_emit(struct radeon_device *rdev, 77 struct radeon_fence *fence); 78 bool r100_semaphore_ring_emit(struct radeon_device *rdev, 79 struct radeon_ring *cp, 80 struct radeon_semaphore *semaphore, 81 bool emit_wait); 82 int r100_cs_parse(struct radeon_cs_parser *p); 83 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 84 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); 85 struct radeon_fence *r100_copy_blit(struct radeon_device *rdev, 86 uint64_t src_offset, 87 uint64_t dst_offset, 88 unsigned num_gpu_pages, 89 struct reservation_object *resv); 90 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 91 uint32_t tiling_flags, uint32_t pitch, 92 uint32_t offset, uint32_t obj_size); 93 void r100_clear_surface_reg(struct radeon_device *rdev, int reg); 94 void r100_bandwidth_update(struct radeon_device *rdev); 95 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 96 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 97 void r100_hpd_init(struct radeon_device *rdev); 98 void r100_hpd_fini(struct radeon_device *rdev); 99 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 100 void r100_hpd_set_polarity(struct radeon_device *rdev, 101 enum radeon_hpd_id hpd); 102 int r100_debugfs_rbbm_init(struct radeon_device *rdev); 103 int r100_debugfs_cp_init(struct radeon_device *rdev); 104 void r100_cp_disable(struct radeon_device *rdev); 105 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 106 void r100_cp_fini(struct radeon_device *rdev); 107 int r100_pci_gart_init(struct radeon_device *rdev); 108 void r100_pci_gart_fini(struct radeon_device *rdev); 109 int r100_pci_gart_enable(struct radeon_device *rdev); 110 void r100_pci_gart_disable(struct radeon_device *rdev); 111 int r100_debugfs_mc_info_init(struct radeon_device *rdev); 112 int r100_gui_wait_for_idle(struct radeon_device *rdev); 113 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 114 void r100_irq_disable(struct radeon_device *rdev); 115 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); 116 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); 117 void r100_vram_init_sizes(struct radeon_device *rdev); 118 int r100_cp_reset(struct radeon_device *rdev); 119 void r100_vga_render_disable(struct radeon_device *rdev); 120 void r100_restore_sanity(struct radeon_device *rdev); 121 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 122 struct radeon_cs_packet *pkt, 123 struct radeon_bo *robj); 124 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 125 struct radeon_cs_packet *pkt, 126 const unsigned *auth, unsigned n, 127 radeon_packet0_check_t check); 128 int r100_cs_packet_parse(struct radeon_cs_parser *p, 129 struct radeon_cs_packet *pkt, 130 unsigned idx); 131 void r100_enable_bm(struct radeon_device *rdev); 132 void r100_set_common_regs(struct radeon_device *rdev); 133 void r100_bm_disable(struct radeon_device *rdev); 134 extern bool r100_gui_idle(struct radeon_device *rdev); 135 extern void r100_pm_misc(struct radeon_device *rdev); 136 extern void r100_pm_prepare(struct radeon_device *rdev); 137 extern void r100_pm_finish(struct radeon_device *rdev); 138 extern void r100_pm_init_profile(struct radeon_device *rdev); 139 extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); 140 extern void r100_page_flip(struct radeon_device *rdev, int crtc, 141 u64 crtc_base, bool async); 142 extern bool r100_page_flip_pending(struct radeon_device *rdev, int crtc); 143 extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); 144 extern int r100_mc_wait_for_idle(struct radeon_device *rdev); 145 146 u32 r100_gfx_get_rptr(struct radeon_device *rdev, 147 struct radeon_ring *ring); 148 u32 r100_gfx_get_wptr(struct radeon_device *rdev, 149 struct radeon_ring *ring); 150 void r100_gfx_set_wptr(struct radeon_device *rdev, 151 struct radeon_ring *ring); 152 153 /* 154 * r200,rv250,rs300,rv280 155 */ 156 struct radeon_fence *r200_copy_dma(struct radeon_device *rdev, 157 uint64_t src_offset, 158 uint64_t dst_offset, 159 unsigned num_gpu_pages, 160 struct reservation_object *resv); 161 void r200_set_safe_registers(struct radeon_device *rdev); 162 163 /* 164 * r300,r350,rv350,rv380 165 */ 166 extern int r300_init(struct radeon_device *rdev); 167 extern void r300_fini(struct radeon_device *rdev); 168 extern int r300_suspend(struct radeon_device *rdev); 169 extern int r300_resume(struct radeon_device *rdev); 170 extern int r300_asic_reset(struct radeon_device *rdev, bool hard); 171 extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 172 extern void r300_fence_ring_emit(struct radeon_device *rdev, 173 struct radeon_fence *fence); 174 extern int r300_cs_parse(struct radeon_cs_parser *p); 175 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); 176 extern uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags); 177 extern void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i, 178 uint64_t entry); 179 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); 180 extern int rv370_get_pcie_lanes(struct radeon_device *rdev); 181 extern void r300_set_reg_safe(struct radeon_device *rdev); 182 extern void r300_mc_program(struct radeon_device *rdev); 183 extern void r300_mc_init(struct radeon_device *rdev); 184 extern void r300_clock_startup(struct radeon_device *rdev); 185 extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 186 extern int rv370_pcie_gart_init(struct radeon_device *rdev); 187 extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 188 extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 189 extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 190 191 /* 192 * r420,r423,rv410 193 */ 194 extern int r420_init(struct radeon_device *rdev); 195 extern void r420_fini(struct radeon_device *rdev); 196 extern int r420_suspend(struct radeon_device *rdev); 197 extern int r420_resume(struct radeon_device *rdev); 198 extern void r420_pm_init_profile(struct radeon_device *rdev); 199 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 200 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 201 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 202 extern void r420_pipes_init(struct radeon_device *rdev); 203 204 /* 205 * rs400,rs480 206 */ 207 extern int rs400_init(struct radeon_device *rdev); 208 extern void rs400_fini(struct radeon_device *rdev); 209 extern int rs400_suspend(struct radeon_device *rdev); 210 extern int rs400_resume(struct radeon_device *rdev); 211 void rs400_gart_tlb_flush(struct radeon_device *rdev); 212 uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags); 213 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, 214 uint64_t entry); 215 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); 216 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 217 int rs400_gart_init(struct radeon_device *rdev); 218 int rs400_gart_enable(struct radeon_device *rdev); 219 void rs400_gart_adjust_size(struct radeon_device *rdev); 220 void rs400_gart_disable(struct radeon_device *rdev); 221 void rs400_gart_fini(struct radeon_device *rdev); 222 extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); 223 224 /* 225 * rs600. 226 */ 227 extern int rs600_asic_reset(struct radeon_device *rdev, bool hard); 228 extern int rs600_init(struct radeon_device *rdev); 229 extern void rs600_fini(struct radeon_device *rdev); 230 extern int rs600_suspend(struct radeon_device *rdev); 231 extern int rs600_resume(struct radeon_device *rdev); 232 int rs600_irq_set(struct radeon_device *rdev); 233 irqreturn_t rs600_irq_process(struct radeon_device *rdev); 234 void rs600_irq_disable(struct radeon_device *rdev); 235 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); 236 void rs600_gart_tlb_flush(struct radeon_device *rdev); 237 uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags); 238 void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, 239 uint64_t entry); 240 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); 241 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 242 void rs600_bandwidth_update(struct radeon_device *rdev); 243 void rs600_hpd_init(struct radeon_device *rdev); 244 void rs600_hpd_fini(struct radeon_device *rdev); 245 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 246 void rs600_hpd_set_polarity(struct radeon_device *rdev, 247 enum radeon_hpd_id hpd); 248 extern void rs600_pm_misc(struct radeon_device *rdev); 249 extern void rs600_pm_prepare(struct radeon_device *rdev); 250 extern void rs600_pm_finish(struct radeon_device *rdev); 251 extern void rs600_page_flip(struct radeon_device *rdev, int crtc, 252 u64 crtc_base, bool async); 253 extern bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc); 254 void rs600_set_safe_registers(struct radeon_device *rdev); 255 extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); 256 extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); 257 258 /* 259 * rs690,rs740 260 */ 261 int rs690_init(struct radeon_device *rdev); 262 void rs690_fini(struct radeon_device *rdev); 263 int rs690_resume(struct radeon_device *rdev); 264 int rs690_suspend(struct radeon_device *rdev); 265 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); 266 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 267 void rs690_bandwidth_update(struct radeon_device *rdev); 268 void rs690_line_buffer_adjust(struct radeon_device *rdev, 269 struct drm_display_mode *mode1, 270 struct drm_display_mode *mode2); 271 extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); 272 273 /* 274 * rv515 275 */ 276 struct rv515_mc_save { 277 u32 vga_render_control; 278 u32 vga_hdp_control; 279 bool crtc_enabled[2]; 280 }; 281 282 int rv515_init(struct radeon_device *rdev); 283 void rv515_fini(struct radeon_device *rdev); 284 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); 285 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 286 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 287 void rv515_bandwidth_update(struct radeon_device *rdev); 288 int rv515_resume(struct radeon_device *rdev); 289 int rv515_suspend(struct radeon_device *rdev); 290 void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 291 void rv515_vga_render_disable(struct radeon_device *rdev); 292 void rv515_set_safe_registers(struct radeon_device *rdev); 293 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 294 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 295 void rv515_clock_startup(struct radeon_device *rdev); 296 void rv515_debugfs(struct radeon_device *rdev); 297 int rv515_mc_wait_for_idle(struct radeon_device *rdev); 298 299 /* 300 * r520,rv530,rv560,rv570,r580 301 */ 302 int r520_init(struct radeon_device *rdev); 303 int r520_resume(struct radeon_device *rdev); 304 int r520_mc_wait_for_idle(struct radeon_device *rdev); 305 306 /* 307 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 308 */ 309 int r600_init(struct radeon_device *rdev); 310 void r600_fini(struct radeon_device *rdev); 311 int r600_suspend(struct radeon_device *rdev); 312 int r600_resume(struct radeon_device *rdev); 313 void r600_vga_set_state(struct radeon_device *rdev, bool state); 314 int r600_wb_init(struct radeon_device *rdev); 315 void r600_wb_fini(struct radeon_device *rdev); 316 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 317 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 318 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 319 int r600_cs_parse(struct radeon_cs_parser *p); 320 int r600_dma_cs_parse(struct radeon_cs_parser *p); 321 int r600_dma_cs_next_reloc(struct radeon_cs_parser *p, 322 struct radeon_bo_list **cs_reloc); 323 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev); 324 void r600_fence_ring_emit(struct radeon_device *rdev, 325 struct radeon_fence *fence); 326 bool r600_semaphore_ring_emit(struct radeon_device *rdev, 327 struct radeon_ring *cp, 328 struct radeon_semaphore *semaphore, 329 bool emit_wait); 330 void r600_dma_fence_ring_emit(struct radeon_device *rdev, 331 struct radeon_fence *fence); 332 bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev, 333 struct radeon_ring *ring, 334 struct radeon_semaphore *semaphore, 335 bool emit_wait); 336 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 337 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 338 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 339 int r600_asic_reset(struct radeon_device *rdev, bool hard); 340 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 341 uint32_t tiling_flags, uint32_t pitch, 342 uint32_t offset, uint32_t obj_size); 343 void r600_clear_surface_reg(struct radeon_device *rdev, int reg); 344 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 345 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 346 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 347 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 348 int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 349 struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev, 350 uint64_t src_offset, uint64_t dst_offset, 351 unsigned num_gpu_pages, 352 struct reservation_object *resv); 353 struct radeon_fence *r600_copy_dma(struct radeon_device *rdev, 354 uint64_t src_offset, uint64_t dst_offset, 355 unsigned num_gpu_pages, 356 struct reservation_object *resv); 357 void r600_hpd_init(struct radeon_device *rdev); 358 void r600_hpd_fini(struct radeon_device *rdev); 359 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 360 void r600_hpd_set_polarity(struct radeon_device *rdev, 361 enum radeon_hpd_id hpd); 362 extern void r600_mmio_hdp_flush(struct radeon_device *rdev); 363 extern bool r600_gui_idle(struct radeon_device *rdev); 364 extern void r600_pm_misc(struct radeon_device *rdev); 365 extern void r600_pm_init_profile(struct radeon_device *rdev); 366 extern void rs780_pm_init_profile(struct radeon_device *rdev); 367 extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg); 368 extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 369 extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); 370 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); 371 extern int r600_get_pcie_lanes(struct radeon_device *rdev); 372 bool r600_card_posted(struct radeon_device *rdev); 373 void r600_cp_stop(struct radeon_device *rdev); 374 int r600_cp_start(struct radeon_device *rdev); 375 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); 376 int r600_cp_resume(struct radeon_device *rdev); 377 void r600_cp_fini(struct radeon_device *rdev); 378 int r600_count_pipe_bits(uint32_t val); 379 int r600_mc_wait_for_idle(struct radeon_device *rdev); 380 int r600_pcie_gart_init(struct radeon_device *rdev); 381 void r600_scratch_init(struct radeon_device *rdev); 382 int r600_init_microcode(struct radeon_device *rdev); 383 u32 r600_gfx_get_rptr(struct radeon_device *rdev, 384 struct radeon_ring *ring); 385 u32 r600_gfx_get_wptr(struct radeon_device *rdev, 386 struct radeon_ring *ring); 387 void r600_gfx_set_wptr(struct radeon_device *rdev, 388 struct radeon_ring *ring); 389 int r600_get_allowed_info_register(struct radeon_device *rdev, 390 u32 reg, u32 *val); 391 void r600_fini_microcode(struct radeon_device *rdev); 392 /* r600 irq */ 393 irqreturn_t r600_irq_process(struct radeon_device *rdev); 394 int r600_irq_init(struct radeon_device *rdev); 395 void r600_irq_fini(struct radeon_device *rdev); 396 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 397 int r600_irq_set(struct radeon_device *rdev); 398 void r600_irq_suspend(struct radeon_device *rdev); 399 void r600_disable_interrupts(struct radeon_device *rdev); 400 void r600_rlc_stop(struct radeon_device *rdev); 401 /* r600 audio */ 402 void r600_audio_fini(struct radeon_device *rdev); 403 void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock); 404 void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer, 405 size_t size); 406 void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock); 407 void r600_hdmi_audio_workaround(struct drm_encoder *encoder); 408 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 409 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); 410 u32 r600_get_xclk(struct radeon_device *rdev); 411 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev); 412 int rv6xx_get_temp(struct radeon_device *rdev); 413 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 414 int r600_dpm_pre_set_power_state(struct radeon_device *rdev); 415 void r600_dpm_post_set_power_state(struct radeon_device *rdev); 416 int r600_dpm_late_enable(struct radeon_device *rdev); 417 /* r600 dma */ 418 uint32_t r600_dma_get_rptr(struct radeon_device *rdev, 419 struct radeon_ring *ring); 420 uint32_t r600_dma_get_wptr(struct radeon_device *rdev, 421 struct radeon_ring *ring); 422 void r600_dma_set_wptr(struct radeon_device *rdev, 423 struct radeon_ring *ring); 424 /* rv6xx dpm */ 425 int rv6xx_dpm_init(struct radeon_device *rdev); 426 int rv6xx_dpm_enable(struct radeon_device *rdev); 427 void rv6xx_dpm_disable(struct radeon_device *rdev); 428 int rv6xx_dpm_set_power_state(struct radeon_device *rdev); 429 void rv6xx_setup_asic(struct radeon_device *rdev); 430 void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev); 431 void rv6xx_dpm_fini(struct radeon_device *rdev); 432 u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low); 433 u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low); 434 void rv6xx_dpm_print_power_state(struct radeon_device *rdev, 435 struct radeon_ps *ps); 436 void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 437 struct seq_file *m); 438 int rv6xx_dpm_force_performance_level(struct radeon_device *rdev, 439 enum radeon_dpm_forced_level level); 440 u32 rv6xx_dpm_get_current_sclk(struct radeon_device *rdev); 441 u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev); 442 /* rs780 dpm */ 443 int rs780_dpm_init(struct radeon_device *rdev); 444 int rs780_dpm_enable(struct radeon_device *rdev); 445 void rs780_dpm_disable(struct radeon_device *rdev); 446 int rs780_dpm_set_power_state(struct radeon_device *rdev); 447 void rs780_dpm_setup_asic(struct radeon_device *rdev); 448 void rs780_dpm_display_configuration_changed(struct radeon_device *rdev); 449 void rs780_dpm_fini(struct radeon_device *rdev); 450 u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low); 451 u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low); 452 void rs780_dpm_print_power_state(struct radeon_device *rdev, 453 struct radeon_ps *ps); 454 void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 455 struct seq_file *m); 456 int rs780_dpm_force_performance_level(struct radeon_device *rdev, 457 enum radeon_dpm_forced_level level); 458 u32 rs780_dpm_get_current_sclk(struct radeon_device *rdev); 459 u32 rs780_dpm_get_current_mclk(struct radeon_device *rdev); 460 461 /* 462 * rv770,rv730,rv710,rv740 463 */ 464 int rv770_init(struct radeon_device *rdev); 465 void rv770_fini(struct radeon_device *rdev); 466 int rv770_suspend(struct radeon_device *rdev); 467 int rv770_resume(struct radeon_device *rdev); 468 void rv770_pm_misc(struct radeon_device *rdev); 469 void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base, 470 bool async); 471 bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc); 472 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 473 void r700_cp_stop(struct radeon_device *rdev); 474 void r700_cp_fini(struct radeon_device *rdev); 475 struct radeon_fence *rv770_copy_dma(struct radeon_device *rdev, 476 uint64_t src_offset, uint64_t dst_offset, 477 unsigned num_gpu_pages, 478 struct reservation_object *resv); 479 u32 rv770_get_xclk(struct radeon_device *rdev); 480 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 481 int rv770_get_temp(struct radeon_device *rdev); 482 /* rv7xx pm */ 483 int rv770_dpm_init(struct radeon_device *rdev); 484 int rv770_dpm_enable(struct radeon_device *rdev); 485 int rv770_dpm_late_enable(struct radeon_device *rdev); 486 void rv770_dpm_disable(struct radeon_device *rdev); 487 int rv770_dpm_set_power_state(struct radeon_device *rdev); 488 void rv770_dpm_setup_asic(struct radeon_device *rdev); 489 void rv770_dpm_display_configuration_changed(struct radeon_device *rdev); 490 void rv770_dpm_fini(struct radeon_device *rdev); 491 u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low); 492 u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low); 493 void rv770_dpm_print_power_state(struct radeon_device *rdev, 494 struct radeon_ps *ps); 495 void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 496 struct seq_file *m); 497 bool rv770_dpm_vblank_too_short(struct radeon_device *rdev); 498 void rv770_set_clk_bypass_mode(struct radeon_device *rdev); 499 u32 rv770_dpm_get_current_sclk(struct radeon_device *rdev); 500 u32 rv770_dpm_get_current_mclk(struct radeon_device *rdev); 501 502 /* 503 * evergreen 504 */ 505 struct evergreen_mc_save { 506 u32 vga_render_control; 507 u32 vga_hdp_control; 508 bool crtc_enabled[RADEON_MAX_CRTCS]; 509 }; 510 511 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); 512 int evergreen_init(struct radeon_device *rdev); 513 void evergreen_fini(struct radeon_device *rdev); 514 int evergreen_suspend(struct radeon_device *rdev); 515 int evergreen_resume(struct radeon_device *rdev); 516 bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 517 bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 518 int evergreen_asic_reset(struct radeon_device *rdev, bool hard); 519 void evergreen_bandwidth_update(struct radeon_device *rdev); 520 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 521 void evergreen_hpd_init(struct radeon_device *rdev); 522 void evergreen_hpd_fini(struct radeon_device *rdev); 523 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 524 void evergreen_hpd_set_polarity(struct radeon_device *rdev, 525 enum radeon_hpd_id hpd); 526 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); 527 int evergreen_irq_set(struct radeon_device *rdev); 528 irqreturn_t evergreen_irq_process(struct radeon_device *rdev); 529 extern int evergreen_cs_parse(struct radeon_cs_parser *p); 530 extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p); 531 extern void evergreen_pm_misc(struct radeon_device *rdev); 532 extern void evergreen_pm_prepare(struct radeon_device *rdev); 533 extern void evergreen_pm_finish(struct radeon_device *rdev); 534 extern void sumo_pm_init_profile(struct radeon_device *rdev); 535 extern void btc_pm_init_profile(struct radeon_device *rdev); 536 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 537 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 538 extern void evergreen_page_flip(struct radeon_device *rdev, int crtc, 539 u64 crtc_base, bool async); 540 extern bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc); 541 extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); 542 void evergreen_disable_interrupt_state(struct radeon_device *rdev); 543 int evergreen_mc_wait_for_idle(struct radeon_device *rdev); 544 void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, 545 struct radeon_fence *fence); 546 void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, 547 struct radeon_ib *ib); 548 struct radeon_fence *evergreen_copy_dma(struct radeon_device *rdev, 549 uint64_t src_offset, uint64_t dst_offset, 550 unsigned num_gpu_pages, 551 struct reservation_object *resv); 552 u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev); 553 void evergreen_gpu_pci_config_reset(struct radeon_device *rdev); 554 void evergreen_pcie_gen2_enable(struct radeon_device *rdev); 555 void evergreen_print_gpu_status_regs(struct radeon_device *rdev); 556 void evergreen_program_aspm(struct radeon_device *rdev); 557 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); 558 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev); 559 void sumo_rlc_fini(struct radeon_device *rdev); 560 int sumo_rlc_init(struct radeon_device *rdev); 561 int evergreen_rlc_resume(struct radeon_device *rdev); 562 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); 563 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); 564 void evergreen_mc_program(struct radeon_device *rdev); 565 int evergreen_mc_init(struct radeon_device *rdev); 566 void evergreen_irq_suspend(struct radeon_device *rdev); 567 bool evergreen_is_display_hung(struct radeon_device *rdev); 568 int evergreen_get_temp(struct radeon_device *rdev); 569 int evergreen_get_allowed_info_register(struct radeon_device *rdev, 570 u32 reg, u32 *val); 571 int sumo_get_temp(struct radeon_device *rdev); 572 int tn_get_temp(struct radeon_device *rdev); 573 int cypress_dpm_init(struct radeon_device *rdev); 574 void cypress_dpm_setup_asic(struct radeon_device *rdev); 575 int cypress_dpm_enable(struct radeon_device *rdev); 576 void cypress_dpm_disable(struct radeon_device *rdev); 577 int cypress_dpm_set_power_state(struct radeon_device *rdev); 578 void cypress_dpm_display_configuration_changed(struct radeon_device *rdev); 579 void cypress_dpm_fini(struct radeon_device *rdev); 580 bool cypress_dpm_vblank_too_short(struct radeon_device *rdev); 581 int btc_dpm_init(struct radeon_device *rdev); 582 void btc_dpm_setup_asic(struct radeon_device *rdev); 583 int btc_dpm_enable(struct radeon_device *rdev); 584 void btc_dpm_disable(struct radeon_device *rdev); 585 int btc_dpm_pre_set_power_state(struct radeon_device *rdev); 586 int btc_dpm_set_power_state(struct radeon_device *rdev); 587 void btc_dpm_post_set_power_state(struct radeon_device *rdev); 588 void btc_dpm_fini(struct radeon_device *rdev); 589 u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low); 590 u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low); 591 bool btc_dpm_vblank_too_short(struct radeon_device *rdev); 592 void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 593 struct seq_file *m); 594 u32 btc_dpm_get_current_sclk(struct radeon_device *rdev); 595 u32 btc_dpm_get_current_mclk(struct radeon_device *rdev); 596 int sumo_dpm_init(struct radeon_device *rdev); 597 int sumo_dpm_enable(struct radeon_device *rdev); 598 int sumo_dpm_late_enable(struct radeon_device *rdev); 599 void sumo_dpm_disable(struct radeon_device *rdev); 600 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev); 601 int sumo_dpm_set_power_state(struct radeon_device *rdev); 602 void sumo_dpm_post_set_power_state(struct radeon_device *rdev); 603 void sumo_dpm_setup_asic(struct radeon_device *rdev); 604 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev); 605 void sumo_dpm_fini(struct radeon_device *rdev); 606 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low); 607 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low); 608 void sumo_dpm_print_power_state(struct radeon_device *rdev, 609 struct radeon_ps *ps); 610 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 611 struct seq_file *m); 612 int sumo_dpm_force_performance_level(struct radeon_device *rdev, 613 enum radeon_dpm_forced_level level); 614 u32 sumo_dpm_get_current_sclk(struct radeon_device *rdev); 615 u32 sumo_dpm_get_current_mclk(struct radeon_device *rdev); 616 617 /* 618 * cayman 619 */ 620 void cayman_fence_ring_emit(struct radeon_device *rdev, 621 struct radeon_fence *fence); 622 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); 623 int cayman_init(struct radeon_device *rdev); 624 void cayman_fini(struct radeon_device *rdev); 625 int cayman_suspend(struct radeon_device *rdev); 626 int cayman_resume(struct radeon_device *rdev); 627 int cayman_asic_reset(struct radeon_device *rdev, bool hard); 628 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 629 int cayman_vm_init(struct radeon_device *rdev); 630 void cayman_vm_fini(struct radeon_device *rdev); 631 void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 632 unsigned vm_id, uint64_t pd_addr); 633 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); 634 void cayman_vm_decode_fault(struct radeon_device *rdev, 635 u32 status, u32 addr); 636 u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev); 637 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 638 int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 639 void cayman_dma_ring_ib_execute(struct radeon_device *rdev, 640 struct radeon_ib *ib); 641 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 642 bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 643 644 void cayman_dma_vm_copy_pages(struct radeon_device *rdev, 645 struct radeon_ib *ib, 646 uint64_t pe, uint64_t src, 647 unsigned count); 648 void cayman_dma_vm_write_pages(struct radeon_device *rdev, 649 struct radeon_ib *ib, 650 uint64_t pe, 651 uint64_t addr, unsigned count, 652 uint32_t incr, uint32_t flags); 653 void cayman_dma_vm_set_pages(struct radeon_device *rdev, 654 struct radeon_ib *ib, 655 uint64_t pe, 656 uint64_t addr, unsigned count, 657 uint32_t incr, uint32_t flags); 658 void cayman_dma_vm_pad_ib(struct radeon_ib *ib); 659 660 void cayman_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 661 unsigned vm_id, uint64_t pd_addr); 662 663 u32 cayman_gfx_get_rptr(struct radeon_device *rdev, 664 struct radeon_ring *ring); 665 u32 cayman_gfx_get_wptr(struct radeon_device *rdev, 666 struct radeon_ring *ring); 667 void cayman_gfx_set_wptr(struct radeon_device *rdev, 668 struct radeon_ring *ring); 669 uint32_t cayman_dma_get_rptr(struct radeon_device *rdev, 670 struct radeon_ring *ring); 671 uint32_t cayman_dma_get_wptr(struct radeon_device *rdev, 672 struct radeon_ring *ring); 673 void cayman_dma_set_wptr(struct radeon_device *rdev, 674 struct radeon_ring *ring); 675 int cayman_get_allowed_info_register(struct radeon_device *rdev, 676 u32 reg, u32 *val); 677 void cayman_cp_int_cntl_setup(struct radeon_device *rdev, 678 int ring, u32 cp_int_cntl); 679 680 int ni_dpm_init(struct radeon_device *rdev); 681 void ni_dpm_setup_asic(struct radeon_device *rdev); 682 int ni_dpm_enable(struct radeon_device *rdev); 683 void ni_dpm_disable(struct radeon_device *rdev); 684 int ni_dpm_pre_set_power_state(struct radeon_device *rdev); 685 int ni_dpm_set_power_state(struct radeon_device *rdev); 686 void ni_dpm_post_set_power_state(struct radeon_device *rdev); 687 void ni_dpm_fini(struct radeon_device *rdev); 688 u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low); 689 u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low); 690 void ni_dpm_print_power_state(struct radeon_device *rdev, 691 struct radeon_ps *ps); 692 void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 693 struct seq_file *m); 694 int ni_dpm_force_performance_level(struct radeon_device *rdev, 695 enum radeon_dpm_forced_level level); 696 //bool ni_dpm_vblank_too_short(struct radeon_device *rdev); 697 u32 ni_dpm_get_current_sclk(struct radeon_device *rdev); 698 u32 ni_dpm_get_current_mclk(struct radeon_device *rdev); 699 int trinity_dpm_init(struct radeon_device *rdev); 700 int trinity_dpm_enable(struct radeon_device *rdev); 701 int trinity_dpm_late_enable(struct radeon_device *rdev); 702 void trinity_dpm_disable(struct radeon_device *rdev); 703 int trinity_dpm_pre_set_power_state(struct radeon_device *rdev); 704 int trinity_dpm_set_power_state(struct radeon_device *rdev); 705 void trinity_dpm_post_set_power_state(struct radeon_device *rdev); 706 void trinity_dpm_setup_asic(struct radeon_device *rdev); 707 void trinity_dpm_display_configuration_changed(struct radeon_device *rdev); 708 void trinity_dpm_fini(struct radeon_device *rdev); 709 u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low); 710 u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low); 711 void trinity_dpm_print_power_state(struct radeon_device *rdev, 712 struct radeon_ps *ps); 713 void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 714 struct seq_file *m); 715 int trinity_dpm_force_performance_level(struct radeon_device *rdev, 716 enum radeon_dpm_forced_level level); 717 void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable); 718 u32 trinity_dpm_get_current_sclk(struct radeon_device *rdev); 719 u32 trinity_dpm_get_current_mclk(struct radeon_device *rdev); 720 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); 721 722 /* DCE6 - SI */ 723 void dce6_bandwidth_update(struct radeon_device *rdev); 724 void dce6_audio_fini(struct radeon_device *rdev); 725 726 void dce6_afmt_write_sad_regs(struct drm_encoder *encoder); 727 728 /* 729 * si 730 */ 731 void si_fence_ring_emit(struct radeon_device *rdev, 732 struct radeon_fence *fence); 733 void si_pcie_gart_tlb_flush(struct radeon_device *rdev); 734 int si_init(struct radeon_device *rdev); 735 void si_fini(struct radeon_device *rdev); 736 int si_suspend(struct radeon_device *rdev); 737 int si_resume(struct radeon_device *rdev); 738 bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 739 bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 740 int si_asic_reset(struct radeon_device *rdev, bool hard); 741 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 742 int si_irq_set(struct radeon_device *rdev); 743 irqreturn_t si_irq_process(struct radeon_device *rdev); 744 int si_vm_init(struct radeon_device *rdev); 745 void si_vm_fini(struct radeon_device *rdev); 746 void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 747 unsigned vm_id, uint64_t pd_addr); 748 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 749 struct radeon_fence *si_copy_dma(struct radeon_device *rdev, 750 uint64_t src_offset, uint64_t dst_offset, 751 unsigned num_gpu_pages, 752 struct reservation_object *resv); 753 754 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode); 755 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock); 756 u32 si_get_csb_size(struct radeon_device *rdev); 757 void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer); 758 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 759 u32 max_voltage_steps, 760 struct atom_voltage_table *voltage_table); 761 u32 si_gpu_check_soft_reset(struct radeon_device *rdev); 762 763 void si_dma_vm_copy_pages(struct radeon_device *rdev, 764 struct radeon_ib *ib, 765 uint64_t pe, uint64_t src, 766 unsigned count); 767 void si_dma_vm_write_pages(struct radeon_device *rdev, 768 struct radeon_ib *ib, 769 uint64_t pe, 770 uint64_t addr, unsigned count, 771 uint32_t incr, uint32_t flags); 772 void si_dma_vm_set_pages(struct radeon_device *rdev, 773 struct radeon_ib *ib, 774 uint64_t pe, 775 uint64_t addr, unsigned count, 776 uint32_t incr, uint32_t flags); 777 778 void si_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 779 unsigned vm_id, uint64_t pd_addr); 780 u32 si_get_xclk(struct radeon_device *rdev); 781 uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev); 782 int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 783 int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); 784 int si_get_temp(struct radeon_device *rdev); 785 int si_get_allowed_info_register(struct radeon_device *rdev, 786 u32 reg, u32 *val); 787 void si_rlc_fini(struct radeon_device *rdev); 788 int si_rlc_init(struct radeon_device *rdev); 789 void si_rlc_reset(struct radeon_device *rdev); 790 int si_mc_load_microcode(struct radeon_device *rdev); 791 void si_vram_gtt_location(struct radeon_device *rdev, 792 struct radeon_mc *mc); 793 void si_init_uvd_internal_cg(struct radeon_device *rdev); 794 int si_dpm_init(struct radeon_device *rdev); 795 void si_dpm_setup_asic(struct radeon_device *rdev); 796 int si_dpm_enable(struct radeon_device *rdev); 797 int si_dpm_late_enable(struct radeon_device *rdev); 798 void si_dpm_disable(struct radeon_device *rdev); 799 int si_dpm_pre_set_power_state(struct radeon_device *rdev); 800 int si_dpm_set_power_state(struct radeon_device *rdev); 801 void si_dpm_post_set_power_state(struct radeon_device *rdev); 802 void si_dpm_fini(struct radeon_device *rdev); 803 void si_dpm_display_configuration_changed(struct radeon_device *rdev); 804 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 805 struct seq_file *m); 806 int si_dpm_force_performance_level(struct radeon_device *rdev, 807 enum radeon_dpm_forced_level level); 808 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 809 u32 *speed); 810 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 811 u32 speed); 812 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev); 813 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode); 814 u32 si_dpm_get_current_sclk(struct radeon_device *rdev); 815 u32 si_dpm_get_current_mclk(struct radeon_device *rdev); 816 817 /* DCE8 - CIK */ 818 void dce8_bandwidth_update(struct radeon_device *rdev); 819 820 /* 821 * cik 822 */ 823 u32 cik_get_csb_size(struct radeon_device *rdev); 824 void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer); 825 uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev); 826 u32 cik_get_xclk(struct radeon_device *rdev); 827 uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 828 void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 829 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); 830 int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); 831 void cik_init_cp_pg_table(struct radeon_device *rdev); 832 void cik_update_cg(struct radeon_device *rdev, 833 u32 block, bool enable); 834 void cik_enter_rlc_safe_mode(struct radeon_device *rdev); 835 void cik_exit_rlc_safe_mode(struct radeon_device *rdev); 836 int ci_mc_load_microcode(struct radeon_device *rdev); 837 void cik_sdma_fence_ring_emit(struct radeon_device *rdev, 838 struct radeon_fence *fence); 839 bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev, 840 struct radeon_ring *ring, 841 struct radeon_semaphore *semaphore, 842 bool emit_wait); 843 void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 844 struct radeon_fence *cik_copy_dma(struct radeon_device *rdev, 845 uint64_t src_offset, uint64_t dst_offset, 846 unsigned num_gpu_pages, 847 struct reservation_object *resv); 848 struct radeon_fence *cik_copy_cpdma(struct radeon_device *rdev, 849 uint64_t src_offset, uint64_t dst_offset, 850 unsigned num_gpu_pages, 851 struct reservation_object *resv); 852 int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 853 int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 854 bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 855 void cik_fence_gfx_ring_emit(struct radeon_device *rdev, 856 struct radeon_fence *fence); 857 void cik_fence_compute_ring_emit(struct radeon_device *rdev, 858 struct radeon_fence *fence); 859 bool cik_semaphore_ring_emit(struct radeon_device *rdev, 860 struct radeon_ring *cp, 861 struct radeon_semaphore *semaphore, 862 bool emit_wait); 863 void cik_pcie_gart_tlb_flush(struct radeon_device *rdev); 864 int cik_init(struct radeon_device *rdev); 865 void cik_fini(struct radeon_device *rdev); 866 int cik_suspend(struct radeon_device *rdev); 867 int cik_resume(struct radeon_device *rdev); 868 bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 869 int cik_asic_reset(struct radeon_device *rdev, bool hard); 870 void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 871 int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 872 int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 873 int cik_irq_set(struct radeon_device *rdev); 874 irqreturn_t cik_irq_process(struct radeon_device *rdev); 875 int cik_vm_init(struct radeon_device *rdev); 876 void cik_vm_fini(struct radeon_device *rdev); 877 void cik_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 878 unsigned vm_id, uint64_t pd_addr); 879 880 void cik_sdma_vm_copy_pages(struct radeon_device *rdev, 881 struct radeon_ib *ib, 882 uint64_t pe, uint64_t src, 883 unsigned count); 884 void cik_sdma_vm_write_pages(struct radeon_device *rdev, 885 struct radeon_ib *ib, 886 uint64_t pe, 887 uint64_t addr, unsigned count, 888 uint32_t incr, uint32_t flags); 889 void cik_sdma_vm_set_pages(struct radeon_device *rdev, 890 struct radeon_ib *ib, 891 uint64_t pe, 892 uint64_t addr, unsigned count, 893 uint32_t incr, uint32_t flags); 894 void cik_sdma_vm_pad_ib(struct radeon_ib *ib); 895 896 void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, 897 unsigned vm_id, uint64_t pd_addr); 898 int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 899 u32 cik_gfx_get_rptr(struct radeon_device *rdev, 900 struct radeon_ring *ring); 901 u32 cik_gfx_get_wptr(struct radeon_device *rdev, 902 struct radeon_ring *ring); 903 void cik_gfx_set_wptr(struct radeon_device *rdev, 904 struct radeon_ring *ring); 905 u32 cik_compute_get_rptr(struct radeon_device *rdev, 906 struct radeon_ring *ring); 907 u32 cik_compute_get_wptr(struct radeon_device *rdev, 908 struct radeon_ring *ring); 909 void cik_compute_set_wptr(struct radeon_device *rdev, 910 struct radeon_ring *ring); 911 u32 cik_sdma_get_rptr(struct radeon_device *rdev, 912 struct radeon_ring *ring); 913 u32 cik_sdma_get_wptr(struct radeon_device *rdev, 914 struct radeon_ring *ring); 915 void cik_sdma_set_wptr(struct radeon_device *rdev, 916 struct radeon_ring *ring); 917 bool cik_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 918 void cik_fence_ring_emit(struct radeon_device *rdev, 919 struct radeon_fence *fence); 920 u32 cik_gpu_check_soft_reset(struct radeon_device *rdev); 921 void cik_sdma_enable(struct radeon_device *rdev, bool enable); 922 int cik_sdma_resume(struct radeon_device *rdev); 923 void cik_sdma_fini(struct radeon_device *rdev); 924 int ci_get_temp(struct radeon_device *rdev); 925 int kv_get_temp(struct radeon_device *rdev); 926 int cik_get_allowed_info_register(struct radeon_device *rdev, 927 u32 reg, u32 *val); 928 929 int ci_dpm_init(struct radeon_device *rdev); 930 int ci_dpm_enable(struct radeon_device *rdev); 931 int ci_dpm_late_enable(struct radeon_device *rdev); 932 void ci_dpm_disable(struct radeon_device *rdev); 933 int ci_dpm_pre_set_power_state(struct radeon_device *rdev); 934 int ci_dpm_set_power_state(struct radeon_device *rdev); 935 void ci_dpm_post_set_power_state(struct radeon_device *rdev); 936 void ci_dpm_setup_asic(struct radeon_device *rdev); 937 void ci_dpm_display_configuration_changed(struct radeon_device *rdev); 938 void ci_dpm_fini(struct radeon_device *rdev); 939 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low); 940 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low); 941 void ci_dpm_print_power_state(struct radeon_device *rdev, 942 struct radeon_ps *ps); 943 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 944 struct seq_file *m); 945 int ci_dpm_force_performance_level(struct radeon_device *rdev, 946 enum radeon_dpm_forced_level level); 947 bool ci_dpm_vblank_too_short(struct radeon_device *rdev); 948 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); 949 u32 ci_dpm_get_current_sclk(struct radeon_device *rdev); 950 u32 ci_dpm_get_current_mclk(struct radeon_device *rdev); 951 952 int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 953 u32 *speed); 954 int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 955 u32 speed); 956 u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev); 957 void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode); 958 959 int kv_dpm_init(struct radeon_device *rdev); 960 int kv_dpm_enable(struct radeon_device *rdev); 961 int kv_dpm_late_enable(struct radeon_device *rdev); 962 void kv_dpm_disable(struct radeon_device *rdev); 963 int kv_dpm_pre_set_power_state(struct radeon_device *rdev); 964 int kv_dpm_set_power_state(struct radeon_device *rdev); 965 void kv_dpm_post_set_power_state(struct radeon_device *rdev); 966 void kv_dpm_setup_asic(struct radeon_device *rdev); 967 void kv_dpm_display_configuration_changed(struct radeon_device *rdev); 968 void kv_dpm_fini(struct radeon_device *rdev); 969 u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low); 970 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low); 971 void kv_dpm_print_power_state(struct radeon_device *rdev, 972 struct radeon_ps *ps); 973 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 974 struct seq_file *m); 975 int kv_dpm_force_performance_level(struct radeon_device *rdev, 976 enum radeon_dpm_forced_level level); 977 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate); 978 void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable); 979 u32 kv_dpm_get_current_sclk(struct radeon_device *rdev); 980 u32 kv_dpm_get_current_mclk(struct radeon_device *rdev); 981 982 /* uvd v1.0 */ 983 uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev, 984 struct radeon_ring *ring); 985 uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev, 986 struct radeon_ring *ring); 987 void uvd_v1_0_set_wptr(struct radeon_device *rdev, 988 struct radeon_ring *ring); 989 int uvd_v1_0_resume(struct radeon_device *rdev); 990 991 int uvd_v1_0_init(struct radeon_device *rdev); 992 void uvd_v1_0_fini(struct radeon_device *rdev); 993 int uvd_v1_0_start(struct radeon_device *rdev); 994 void uvd_v1_0_stop(struct radeon_device *rdev); 995 996 int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 997 void uvd_v1_0_fence_emit(struct radeon_device *rdev, 998 struct radeon_fence *fence); 999 int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1000 bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev, 1001 struct radeon_ring *ring, 1002 struct radeon_semaphore *semaphore, 1003 bool emit_wait); 1004 void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1005 1006 /* uvd v2.2 */ 1007 int uvd_v2_2_resume(struct radeon_device *rdev); 1008 void uvd_v2_2_fence_emit(struct radeon_device *rdev, 1009 struct radeon_fence *fence); 1010 bool uvd_v2_2_semaphore_emit(struct radeon_device *rdev, 1011 struct radeon_ring *ring, 1012 struct radeon_semaphore *semaphore, 1013 bool emit_wait); 1014 1015 /* uvd v3.1 */ 1016 bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev, 1017 struct radeon_ring *ring, 1018 struct radeon_semaphore *semaphore, 1019 bool emit_wait); 1020 1021 /* uvd v4.2 */ 1022 int uvd_v4_2_resume(struct radeon_device *rdev); 1023 1024 /* vce v1.0 */ 1025 uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev, 1026 struct radeon_ring *ring); 1027 uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev, 1028 struct radeon_ring *ring); 1029 void vce_v1_0_set_wptr(struct radeon_device *rdev, 1030 struct radeon_ring *ring); 1031 int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data); 1032 unsigned vce_v1_0_bo_size(struct radeon_device *rdev); 1033 int vce_v1_0_resume(struct radeon_device *rdev); 1034 int vce_v1_0_init(struct radeon_device *rdev); 1035 int vce_v1_0_start(struct radeon_device *rdev); 1036 1037 /* vce v2.0 */ 1038 unsigned vce_v2_0_bo_size(struct radeon_device *rdev); 1039 int vce_v2_0_resume(struct radeon_device *rdev); 1040 void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable); 1041 1042 #endif 1043