1 /* pdp11_cpumod.h: PDP-11 CPU model definitions 2 3 Copyright (c) 2004-2008, Robert M Supnik 4 5 Permission is hereby granted, free of charge, to any person obtaining a 6 copy of this software and associated documentation files (the "Software"), 7 to deal in the Software without restriction, including without limitation 8 the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 and/or sell copies of the Software, and to permit persons to whom the 10 Software is furnished to do so, subject to the following conditions: 11 12 The above copyright notice and this permission notice shall be included in 13 all copies or substantial portions of the Software. 14 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 22 Except as contained in this notice, the name of Robert M Supnik shall not be 23 used in advertising or otherwise to promote the sale, use or other dealings 24 in this Software without prior written authorization from Robert M Supnik. 25 26 22-Apr-08 RMS Added 11/70 MBRK register 27 30-Aug-05 RMS Added additional 11/60 registers 28 */ 29 30 #ifndef _PDP11_CPUMOD_H_ 31 #define _PDP11_CPUMOD_H_ 0 32 33 #define SOP_1103 (BUS_Q) 34 #define OPT_1103 (OPT_EIS|OPT_FIS) 35 #define PSW_1103 0000377 36 37 #define SOP_1104 (BUS_U) 38 #define OPT_1104 0 39 #define PSW_1104 0000377 40 41 #define SOP_1105 (BUS_U) 42 #define OPT_1105 0 43 #define PSW_1105 0000377 44 45 #define SOP_1120 (BUS_U) 46 #define OPT_1120 0 47 #define PSW_1120 0000377 48 49 #define SOP_1123 (BUS_Q|OPT_EIS|OPT_FPP|OPT_MMU) 50 #define OPT_1123 (OPT_FPP|OPT_CIS) 51 #define PSW_F 0170777 52 #define PAR_F 0177777 53 #define PDR_F 0077516 54 #define MM0_F 0160157 55 #define MM3_F 0000060 56 57 #define SOP_1123P (BUS_Q|OPT_EIS|OPT_FPP|OPT_MMU) 58 #define OPT_1123P (OPT_FPP|OPT_CIS) 59 60 #define SOP_1124 (BUS_U|OPT_EIS|OPT_FPP|OPT_MMU|OPT_UBM) 61 #define OPT_1124 (OPT_FPP|OPT_CIS) 62 63 #define SOP_1134 (BUS_U|OPT_EIS|OPT_MMU) 64 #define OPT_1134 (OPT_FPP) 65 #define PSW_1134 0170377 66 #define PAR_1134 0007777 67 #define PDR_1134 0077516 68 #define MM0_1134 0160557 69 70 #define SOP_1140 (BUS_U|OPT_EIS|OPT_MMU) 71 #define OPT_1140 (OPT_FIS) 72 #define PSW_1140 0170377 73 #define PAR_1140 0007777 74 #define PDR_1140 0077516 75 #define MM0_1140 0160557 76 77 #define SOP_1144 (BUS_U|OPT_EIS|OPT_FPP|OPT_MMU|OPT_UBM) 78 #define OPT_1144 (OPT_FPP|OPT_CIS) 79 #define PSW_1144 0170777 80 #define PAR_1144 0177777 81 #define PDR_1144 0177516 82 #define MM0_1144 0160557 83 #define MM3_1144 0000077 84 85 #define SOP_1145 (BUS_U|OPT_EIS|OPT_FPP|OPT_MMU|OPT_RH11) 86 #define OPT_1145 (OPT_FPP) 87 #define PSW_1145 0174377 88 #define PAR_1145 0007777 89 #define PDR_1145 0077717 90 #define MM0_1145 0171777 91 #define MM3_1145 0000007 92 93 #define SOP_1160 (BUS_U|OPT_EIS|OPT_FPP|OPT_MMU) 94 #define OPT_1160 0 95 #define PSW_1160 0170377 96 #define PAR_1160 0007777 97 #define PDR_1160 0077516 98 #define MM0_1160 0160557 99 100 #define SOP_1170 (BUS_U|OPT_EIS|OPT_FPP|OPT_MMU|OPT_UBM) 101 #define OPT_1170 (OPT_FPP|OPT_RH11) 102 #define PSW_1170 0174377 103 #define PAR_1170 0177777 104 #define PDR_1170 0077717 105 #define MM0_1170 0171777 106 #define MM3_1170 0000067 107 108 #define SOP_1173 (BUS_Q|OPT_EIS|OPT_FPP|OPT_MMU) 109 #define OPT_1173 (OPT_CIS) 110 #define PSW_J 0174777 111 #define PAR_J 0177777 112 #define PDR_J 0177516 113 #define MM0_J 0160177 114 #define MM3_J 0000077 115 116 #define SOP_1153 (BUS_Q|OPT_EIS|OPT_FPP|OPT_MMU) 117 #define OPT_1153 (OPT_CIS) 118 119 #define SOP_1173B (BUS_Q|OPT_EIS|OPT_FPP|OPT_MMU) 120 #define OPT_1173B (OPT_CIS) 121 122 #define SOP_1183 (BUS_Q|OPT_EIS|OPT_FPP|OPT_MMU) 123 #define OPT_1183 (OPT_CIS) 124 125 #define SOP_1184 (BUS_U|OPT_EIS|OPT_FPP|OPT_MMU|OPT_UBM|OPT_RH11) 126 #define OPT_1184 (OPT_CIS) 127 128 #define SOP_1193 (BUS_Q|OPT_EIS|OPT_FPP|OPT_MMU) 129 #define OPT_1193 (OPT_CIS) 130 131 #define SOP_1194 (BUS_U|OPT_EIS|OPT_FPP|OPT_MMU|OPT_UBM|OPT_RH11) 132 #define OPT_1194 (OPT_CIS) 133 134 #define MOD_MAX 20 135 136 /* MFPT codes */ 137 138 #define MFPT_44 1 139 #define MFPT_F 3 140 #define MFPT_T 4 141 #define MFPT_J 5 142 143 /* KDF11B specific register */ 144 145 #define PCRFB_RW 0037477 /* page ctrl reg */ 146 147 #define CDRFB_RD 0000377 /* config reg */ 148 #define CDRFB_WR 0000017 149 150 /* KT24 Unibus map specific registers */ 151 152 #define LMAL_RD 0177777 /* last mapped low */ 153 154 #define LMAH_RD 0000177 /* last mapped high */ 155 #define LMAH_WR 0000100 156 157 /* 11/44 specific registers */ 158 159 #define CCR44_RD 0033315 /* cache control */ 160 #define CCR44_WR 0003315 161 162 #define CMR44_RD 0177437 /* cache maint */ 163 #define CMR44_WR 0000037 164 165 #define CPUE44_BUSE 0004000 166 167 /* 11/60 specific registers */ 168 169 #define WCS60_RD 0161776 /* WCS control */ 170 #define WCS60_WR 0061676 171 172 #define MEME60_RD 0100340 /* memory error */ 173 174 #define CCR60_RD 0000315 /* cache control */ 175 #define CCR60_WR 0000115 176 177 #define MBRK60_WR 0007777 /* microbreak */ 178 179 #define CPUE60_RD (CPUE_ODD|CPUE_TMO|CPUE_RED) 180 181 /* 11/70 specific registers */ 182 183 #define MBRK70_WR 0000377 /* microbreak */ 184 185 /* J11 specific registers */ 186 187 /* Maintenance register */ 188 189 #define MAINT_V_UQ 9 /* Q/U flag */ 190 #define MAINT_Q (0 << MAINT_V_UQ) /* Qbus */ 191 #define MAINT_U (1 << MAINT_V_UQ) 192 #define MAINT_V_FPA 8 /* FPA flag */ 193 #define MAINT_NOFPA (0 << MAINT_V_FPA) 194 #define MAINT_FPA (1 << MAINT_V_FPA) 195 #define MAINT_V_TYP 4 /* system type */ 196 #define MAINT_KDJA (1 << MAINT_V_TYP) /* KDJ11A */ 197 #define MAINT_KDJB (2 << MAINT_V_TYP) /* KDJ11B */ 198 #define MAINT_KDJD (4 << MAINT_V_TYP) /* KDJ11D */ 199 #define MAINT_KDJE (5 << MAINT_V_TYP) /* KDJ11E */ 200 #define MAINT_V_HTRAP 3 /* trap 4 on HALT */ 201 #define MAINT_HTRAP (1 << MAINT_V_HTRAP) 202 #define MAINT_V_POM 1 /* power on option */ 203 #define MAINT_POODT (0 << MAINT_V_POM) /* power up ODT */ 204 #define MAINT_POROM (2 << MAINT_V_POM) /* power up ROM */ 205 #define MAINT_V_BPOK 0 /* power OK */ 206 #define MAINT_BPOK (1 << MAINT_V_BPOK) 207 208 /* KDJ11B control */ 209 210 #define CSRJB_RD 0177767 211 #define CSRJB_WR 0037767 212 #define CSRJ_LTCI 0020000 /* force LTC int */ 213 #define CSRJ_LTCD 0010000 /* disable LTC reg */ 214 #define CSRJ_V_LTCSEL 10 215 #define CSRJ_M_LTCSEL 03 216 #define CSRJ_LTCSEL(x) (((x) >> CSRJ_V_LTCSEL) & CSRJ_M_LTCSEL) 217 #define CSRJ_HBREAK 0001000 /* halt on break */ 218 219 #define PCRJB_RW 0077176 /* page ctrl reg */ 220 221 #define CDRJB_RD 0000377 /* config register */ 222 #define CDRJB_WR 0000377 223 224 /* KDJ11D control */ 225 226 #define CSRJD_RD 0157777 /* native register */ 227 #define CSRJD_WR 0000377 228 #define CSRJD_15M 0040000 /* 1.5M mem on board */ 229 230 /* KDJ11E control */ 231 232 #define CSRJE_RD 0137360 /* control reg */ 233 #define CSRJE_WR 0037370 234 235 #define PCRJE_RW 0177376 /* page ctrl reg */ 236 237 #define CDRJE_RD 0000377 /* config register */ 238 #define CDRJE_WR 0000077 239 240 #define ASRJE_RW 0030462 /* additional status */ 241 #define ASRJE_V_TOY 8 242 #define ASRJE_TOY (1u << ASRJE_V_TOY) /* TOY serial bit */ 243 #define ASRJE_TOYBIT(x) (((x) >> ASRJE_V_TOY) & 1) 244 245 /* KDJ11E TOY clock */ 246 247 #define TOY_HSEC 0 248 #define TOY_SEC 1 249 #define TOY_MIN 2 250 #define TOY_HR 3 251 #define TOY_DOW 4 252 #define TOY_DOM 5 253 #define TOY_MON 6 254 #define TOY_YR 7 255 #define TOY_LNT 8 256 257 /* KTJ11B Unibus map */ 258 259 #define DCRKTJ_RD 0100616 /* diag control */ 260 #define DCRKTJ_WR 0000416 261 262 #define DDRKTJ_RW 0177777 /* diag data */ 263 264 #define MCRKTJ_RD 0000377 /* control register */ 265 #define MCRKTJ_WR 0000177 266 267 /* Data tables */ 268 269 struct cpu_table { 270 char *name; /* model name */ 271 uint32 std; /* standard flags */ 272 uint32 opt; /* set/clear flags */ 273 uint32 maxm; /* max memory */ 274 uint32 psw; /* PSW mask */ 275 uint32 mfpt; /* MFPT code */ 276 uint32 par; /* PAR mask */ 277 uint32 pdr; /* PDR mask */ 278 uint32 mm0; /* MMR0 mask */ 279 uint32 mm3; /* MMR3 mask */ 280 }; 281 282 typedef struct cpu_table CPUTAB; 283 284 struct conf_table { 285 uint32 cpum; 286 uint32 optm; 287 DIB *dib; 288 }; 289 290 typedef struct conf_table CNFTAB; 291 292 /* Prototypes */ 293 294 t_stat cpu_set_model (UNIT *uptr, int32 val, char *cptr, void *desc); 295 t_stat cpu_show_model (FILE *st, UNIT *uptr, int32 val, void *desc); 296 t_stat cpu_set_opt (UNIT *uptr, int32 val, char *cptr, void *desc); 297 t_stat cpu_clr_opt (UNIT *uptr, int32 val, char *cptr, void *desc); 298 t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc); 299 t_stat cpu_set_bus (int32 opt); 300 301 #endif 302