1 /* $NetBSD: rpb.h,v 1.44 2020/10/03 17:33:23 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Keith Bostic, Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * From DEC 3000 300/400/500/600/700/800/900 System Programmer's Manual, 32 * EK-D3SYS-PM.B01. 33 */ 34 35 /* 36 * HWRPB (Hardware Restart Parameter Block). 37 */ 38 #define HWRPB_ADDR 0x10000000 /* virtual address, at boot */ 39 40 #ifndef ASSEMBLER 41 struct rpb { 42 uint64_t rpb_phys; /* 0: HWRPB phys. address. */ 43 char rpb_magic[8]; /* 8: "HWRPB" (in ASCII) */ 44 uint64_t rpb_version; /* 10 */ 45 uint64_t rpb_size; /* 18: HWRPB size in bytes */ 46 uint64_t rpb_primary_cpu_id; /* 20 */ 47 uint64_t rpb_page_size; /* 28: (8192) */ 48 uint32_t rpb_phys_addr_size; /* 30: physical address size */ 49 uint32_t rpb_extended_va_size; /* 34: extended VA size (4L) */ 50 uint64_t rpb_max_asn; /* 38: (16) */ 51 char rpb_ssn[16]; /* 40: only first 10 valid */ 52 53 #define ST_ADU 1 /* Alpha Demo. Unit (?) */ 54 #define ST_DEC_4000 2 /* "Cobra" */ 55 #define ST_DEC_7000 3 /* "Ruby" */ 56 #define ST_DEC_3000_500 4 /* "Flamingo" family (TC) */ 57 #define ST_DEC_2000_300 6 /* "Jensen" (EISA/ISA) */ 58 #define ST_DEC_3000_300 7 /* "Pelican" (TC) */ 59 #define ST_AVALON_A12 8 /* XXX Avalon Multicomputer */ 60 #define ST_DEC_2100_A500 9 /* "Sable" */ 61 #define ST_DEC_APXVME_64 10 /* "AXPvme" (VME) */ 62 #define ST_DEC_AXPPCI_33 11 /* "NoName" (PCI/ISA) */ 63 #define ST_DEC_21000 12 /* "TurboLaser" (PCI/EISA) */ 64 #define ST_DEC_2100_A50 13 /* "Avanti" (PCI/ISA) */ 65 #define ST_DEC_MUSTANG 14 /* "Mustang" */ 66 #define ST_DEC_KN20AA 15 /* kn20aa (PCI/EISA) */ 67 #define ST_DEC_1000 17 /* "Mikasa" (PCI/EISA) */ 68 #define ST_EB66 19 /* EB66 (PCI/ISA?) */ 69 #define ST_EB64P 20 /* EB64+ (PCI/ISA?) */ 70 #define ST_ALPHABOOK1 21 /* Alphabook1 */ 71 #define ST_DEC_4100 22 /* "Rawhide" (PCI/EISA) */ 72 #define ST_DEC_EV45_PBP 23 /* "Lego" K2 Passive SBC */ 73 #define ST_DEC_2100A_A500 24 /* "Lynx" */ 74 #define ST_DEC_XL 25 /* Alpha XL */ 75 #define ST_EB164 26 /* EB164 (PCI/ISA) */ 76 #define ST_DEC_1000A 27 /* "Noritake" (PCI/EISA)*/ 77 #define ST_DEC_ALPHAVME_224 28 /* "Cortex" */ 78 #define ST_DEC_550 30 /* "Miata" (PCI/ISA) */ 79 #define ST_DEC_XXM 31 /* XXM */ 80 #define ST_DEC_EV56_PBP 32 /* "Takara" */ 81 #define ST_DEC_ALPHAVME_320 33 /* "Yukon" (VME) */ 82 #define ST_DEC_6600 34 /* EV6-Tsunami based systems */ 83 #define ST_DEC_WILDFIRE 35 /* "Wildfire" */ 84 #define ST_DEC_CUSCO 36 /* "CUSCO" */ 85 #define ST_DEC_EIGER 37 /* "Eiger" */ 86 #define ST_DEC_TITAN 38 /* "Titan" */ 87 #define ST_DEC_MARVEL 39 /* "Marvel" */ 88 89 /* DTI systypes */ 90 #define ST_DTI_RUFFIAN 101 /* EV56-Pyxis + ARC? */ 91 92 /* Alpha Processor, Inc. systypes */ 93 #define ST_API_NAUTILUS 201 /* EV6-AMD 751 UP1000 */ 94 95 uint64_t rpb_type; /* 50: */ 96 97 #define SV_MPCAP 0x00000001 /* multiprocessor capable */ 98 99 #define SV_CONSOLE 0x0000001e /* console hardware mask */ 100 #define SV_CONSOLE_DETACHED 0x00000002 101 #define SV_CONSOLE_EMBEDDED 0x00000004 102 103 #define SV_POWERFAIL 0x000000e0 /* powerfail mask */ 104 #define SV_PF_UNITED 0x00000020 105 #define SV_PF_SEPARATE 0x00000040 106 #define SV_PF_BBACKUP 0x00000060 107 #define SV_PF_ACTION 0x00000100 /* powerfail restart */ 108 109 #define SV_GRAPHICS 0x00000200 /* graphic engine present */ 110 111 #define SV_ST_MASK 0x0000fc00 /* system type mask */ 112 #define SV_ST_RESERVED 0x00000000 /* RESERVED */ 113 114 /* 115 * System types for the DEC 3000/500 (Flamingo) Family 116 */ 117 #define SV_ST_SANDPIPER 0x00000400 /* Sandpiper; 3000/400 */ 118 #define SV_ST_FLAMINGO 0x00000800 /* Flamingo; 3000/500 */ 119 #define SV_ST_HOTPINK 0x00000c00 /* "Hot Pink"; 3000/500X */ 120 #define SV_ST_FLAMINGOPLUS 0x00001000 /* Flamingo+; 3000/800 */ 121 #define SV_ST_ULTRA 0x00001400 /* "Ultra", aka Flamingo+ */ 122 #define SV_ST_SANDPLUS 0x00001800 /* Sandpiper+; 3000/600 */ 123 #define SV_ST_SANDPIPER45 0x00001c00 /* Sandpiper45; 3000/700 */ 124 #define SV_ST_FLAMINGO45 0x00002000 /* Flamingo45; 3000/900 */ 125 126 /* 127 * System types for ??? 128 */ 129 #define SV_ST_SABLE 0x00000400 /* Sable (???) */ 130 131 /* 132 * System types for the DEC 3000/300 (Pelican) Family 133 */ 134 #define SV_ST_PELICAN 0x00000000 /* Pelican; 3000/300 */ 135 #define SV_ST_PELICA 0x00000400 /* Pelica; 3000/300L */ 136 #define SV_ST_PELICANPLUS 0x00000800 /* Pelican+; 3000/300X */ 137 #define SV_ST_PELICAPLUS 0x00000c00 /* Pelica+; 3000/300LX */ 138 139 /* 140 * System types for the AlphaStation Family 141 */ 142 #define SV_ST_AVANTI 0x00000000 /* Avanti; 400 4/233 */ 143 #define SV_ST_MUSTANG2_4_166 0x00000800 /* Mustang II; 200 4/166 */ 144 #define SV_ST_MUSTANG2_4_233 0x00001000 /* Mustang II; 200 4/233 */ 145 #define SV_ST_AVANTI_XXX 0x00001400 /* also Avanti; 400 4/233 */ 146 #define SV_ST_AVANTI_4_266 0x00002000 147 #define SV_ST_MUSTANG2_4_100 0x00002400 /* Mustang II; 200 4/100 */ 148 #define SV_ST_AVANTI_4_233 0x0000a800 /* AlphaStation 255/233 */ 149 150 #define SV_ST_KN20AA 0x00000400 /* AlphaStation 500/600 */ 151 152 /* 153 * System types for the AXPvme Family 154 */ 155 #define SV_ST_AXPVME_64 0x00000000 /* 21068, 64MHz */ 156 #define SV_ST_AXPVME_160 0x00000400 /* 21066, 160MHz */ 157 #define SV_ST_AXPVME_100 0x00000c00 /* 21066A, 99MHz */ 158 #define SV_ST_AXPVME_230 0x00001000 /* 21066A, 231MHz */ 159 #define SV_ST_AXPVME_66 0x00001400 /* 21066A, 66MHz */ 160 #define SV_ST_AXPVME_166 0x00001800 /* 21066A, 165MHz */ 161 #define SV_ST_AXPVME_264 0x00001c00 /* 21066A, 264MHz */ 162 163 /* 164 * System types for the EB164 Family 165 */ 166 #define SV_ST_EB164_266 0x00000400 /* EB164, 266MHz */ 167 #define SV_ST_EB164_300 0x00000800 /* EB164, 300MHz */ 168 #define SV_ST_ALPHAPC164_366 0x00000c00 /* AlphaPC164, 366MHz */ 169 #define SV_ST_ALPHAPC164_400 0x00001000 /* AlphaPC164, 400MHz */ 170 #define SV_ST_ALPHAPC164_433 0x00001400 /* AlphaPC164, 433MHz */ 171 #define SV_ST_ALPHAPC164_466 0x00001800 /* AlphaPC164, 466MHz */ 172 #define SV_ST_ALPHAPC164_500 0x00001c00 /* AlphaPC164, 500MHz */ 173 #define SV_ST_ALPHAPC164LX_400 0x00002000 /* AlphaPC164LX, 400MHz */ 174 #define SV_ST_ALPHAPC164LX_466 0x00002400 /* AlphaPC164LX, 466MHz */ 175 #define SV_ST_ALPHAPC164LX_533 0x00002800 /* AlphaPC164LX, 533MHz */ 176 #define SV_ST_ALPHAPC164LX_600 0x00002c00 /* AlphaPC164LX, 600MHz */ 177 #define SV_ST_ALPHAPC164SX_400 0x00003000 /* AlphaPC164SX, 400MHz */ 178 #define SV_ST_ALPHAPC164SX_466 0x00003400 /* AlphaPC164SX, 433MHz */ 179 #define SV_ST_ALPHAPC164SX_533 0x00003800 /* AlphaPC164SX, 533MHz */ 180 #define SV_ST_ALPHAPC164SX_600 0x00003c00 /* AlphaPC164SX, 600MHz */ 181 182 /* 183 * System types for the Digital Personal Workstation (Miata) Family 184 * XXX These are not very complete! 185 */ 186 #define SV_ST_MIATA_1_5 0x00004c00 /* Miata 1.5 */ 187 188 uint64_t rpb_variation; /* 58 */ 189 190 char rpb_revision[8]; /* 60; only first 4 valid */ 191 uint64_t rpb_intr_freq; /* 68; scaled by 4096 */ 192 uint64_t rpb_cc_freq; /* 70: cycle cntr frequency */ 193 u_long rpb_vptb; /* 78: virtual page tbl base */ 194 uint64_t rpb_reserved_arch; /* 80: */ 195 u_long rpb_tbhint_off; /* 88: */ 196 uint64_t rpb_pcs_cnt; /* 90: */ 197 uint64_t rpb_pcs_size; /* 98; pcs size in bytes */ 198 u_long rpb_pcs_off; /* A0: offset to pcs info */ 199 uint64_t rpb_ctb_cnt; /* A8: console terminal */ 200 uint64_t rpb_ctb_size; /* B0: ctb size in bytes */ 201 u_long rpb_ctb_off; /* B8: offset to ctb */ 202 u_long rpb_crb_off; /* C0: offset to crb */ 203 u_long rpb_memdat_off; /* C8: memory data offset */ 204 u_long rpb_condat_off; /* D0: config data offset */ 205 u_long rpb_fru_off; /* D8: FRU table offset */ 206 uint64_t rpb_save_term; /* E0: terminal save */ 207 uint64_t rpb_save_term_val; /* E8: */ 208 uint64_t rpb_rest_term; /* F0: terminal restore */ 209 uint64_t rpb_rest_term_val; /* F8: */ 210 uint64_t rpb_restart; /* 100: restart */ 211 uint64_t rpb_restart_val; /* 108: */ 212 uint64_t rpb_reserve_os; /* 110: */ 213 uint64_t rpb_reserve_hw; /* 118: */ 214 uint64_t rpb_checksum; /* 120: HWRPB checksum */ 215 uint64_t rpb_rxrdy; /* 128: receive ready */ 216 uint64_t rpb_txrdy; /* 130: transmit ready */ 217 u_long rpb_dsrdb_off; /* 138: HWRPB + DSRDB offset */ 218 uint64_t rpb_tbhint[8]; /* 149: TB hint block */ 219 }; 220 221 #define LOCATE_PCS(h,cpunumber) ((struct pcs *) \ 222 ((char *)(h) + (h)->rpb_pcs_off + ((cpunumber) * (h)->rpb_pcs_size))) 223 224 /* 225 * PCS: Per-CPU information. 226 */ 227 struct pcs { 228 uint8_t pcs_hwpcb[128]; /* 0: PAL dependent */ 229 230 #define PCS_BIP 0x000001 /* boot in progress */ 231 #define PCS_RC 0x000002 /* restart possible */ 232 #define PCS_PA 0x000004 /* processor available */ 233 #define PCS_PP 0x000008 /* processor present */ 234 #define PCS_OH 0x000010 /* user halted */ 235 #define PCS_CV 0x000020 /* context valid */ 236 #define PCS_PV 0x000040 /* PALcode valid */ 237 #define PCS_PMV 0x000080 /* PALcode memory valid */ 238 #define PCS_PL 0x000100 /* PALcode loaded */ 239 240 #define PCS_HALT_REQ 0xff0000 /* halt request mask */ 241 #define PCS_HALT_DEFAULT 0x000000 242 #define PCS_HALT_SAVE_EXIT 0x010000 243 #define PCS_HALT_COLD_BOOT 0x020000 244 #define PCS_HALT_WARM_BOOT 0x030000 245 #define PCS_HALT_STAY_HALTED 0x040000 246 #define PCS_mbz 0xffffffffff000000 /* 24:63 -- must be zero */ 247 uint64_t pcs_flags; /* 80: */ 248 249 uint64_t pcs_pal_memsize; /* 88: PAL memory size */ 250 uint64_t pcs_pal_scrsize; /* 90: PAL scratch size */ 251 u_long pcs_pal_memaddr; /* 98: PAL memory addr */ 252 u_long pcs_pal_scraddr; /* A0: PAL scratch addr */ 253 struct { 254 uint64_t 255 minorrev : 8, /* alphabetic char 'a' - 'z' */ 256 majorrev : 8, /* alphabetic char 'a' - 'z' */ 257 #define PAL_TYPE_STANDARD 0 258 #define PAL_TYPE_VMS 1 259 #define PAL_TYPE_OSF1 2 260 pal_type : 8, /* PALcode type: 261 * 0 == standard 262 * 1 == OpenVMS 263 * 2 == OSF/1 264 * 3-127 DIGITAL reserv. 265 * 128-255 non-DIGITAL reserv. 266 */ 267 sbz1 : 8, 268 compatibility : 16, /* Compatibility revision */ 269 proc_cnt : 16; /* Processor count */ 270 } pcs_pal_rev; /* A8: */ 271 #define pcs_minorrev pcs_pal_rev.minorrev 272 #define pcs_majorrev pcs_pal_rev.majorrev 273 #define pcs_pal_type pcs_pal_rev.pal_type 274 #define pcs_compatibility pcs_pal_rev.compatibility 275 #define pcs_proc_cnt pcs_pal_rev.proc_cnt 276 277 uint64_t pcs_proc_type; /* B0: processor type */ 278 279 #define PCS_PROC_EV3 1 /* EV3 */ 280 #define PCS_PROC_EV4 2 /* EV4: 21064 */ 281 #define PCS_PROC_SIMULATION 3 /* Simulation */ 282 #define PCS_PROC_LCA4 4 /* LCA4: 2106[68] */ 283 #define PCS_PROC_EV5 5 /* EV5: 21164 */ 284 #define PCS_PROC_EV45 6 /* EV45: 21064A */ 285 #define PCS_PROC_EV56 7 /* EV56: 21164A */ 286 #define PCS_PROC_EV6 8 /* EV6: 21264 */ 287 #define PCS_PROC_PCA56 9 /* PCA56: 21164PC */ 288 #define PCS_PROC_PCA57 10 /* PCA57: 21164?? */ 289 #define PCS_PROC_EV67 11 /* EV67: 21246A */ 290 #define PCS_PROC_EV68CB 12 /* EV68CB: 21264C */ 291 #define PCS_PROC_EV68AL 13 /* EV68AL: 21264B */ 292 #define PCS_PROC_EV68CX 14 /* EV68CX: 21264D */ 293 #define PCS_PROC_EV7 15 /* EV7: 21364 */ 294 #define PCS_PROC_EV79 16 /* EV79: 21364?? */ 295 #define PCS_PROC_EV69 17 /* EV69: 21264/EV69A */ 296 297 #define PCS_CPU_MAJORTYPE(p) ((p)->pcs_proc_type & 0xffffffff) 298 #define PCS_CPU_MINORTYPE(p) ((p)->pcs_proc_type >> 32) 299 300 /* Minor number interpretation is processor specific. See cpu.c. */ 301 302 uint64_t pcs_proc_var; /* B8: processor variation. */ 303 304 #define PCS_VAR_VAXFP 0x0000000000000001 /* VAX FP support */ 305 #define PCS_VAR_IEEEFP 0x0000000000000002 /* IEEE FP support */ 306 #define PCS_VAR_PE 0x0000000000000004 /* Primary Eligible */ 307 #define PCS_VAR_RESERVED 0xfffffffffffffff8 /* Reserved */ 308 309 char pcs_proc_revision[8]; /* C0: only first 4 valid */ 310 char pcs_proc_sn[16]; /* C8: only first 10 valid */ 311 u_long pcs_machcheck; /* D8: mach chk phys addr. */ 312 uint64_t pcs_machcheck_len; /* E0: length in bytes */ 313 u_long pcs_halt_pcbb; /* E8: phys addr of halt PCB */ 314 u_long pcs_halt_pc; /* F0: halt PC */ 315 uint64_t pcs_halt_ps; /* F8: halt PS */ 316 uint64_t pcs_halt_r25; /* 100: halt argument list */ 317 uint64_t pcs_halt_r26; /* 108: halt return addr list */ 318 uint64_t pcs_halt_r27; /* 110: halt procedure value */ 319 320 #define PCS_HALT_RESERVED 0 321 #define PCS_HALT_POWERUP 1 322 #define PCS_HALT_CONSOLE_HALT 2 323 #define PCS_HALT_CONSOLE_CRASH 3 324 #define PCS_HALT_KERNEL_MODE 4 325 #define PCS_HALT_KERNEL_STACK_INVALID 5 326 #define PCS_HALT_DOUBLE_ERROR_ABORT 6 327 #define PCS_HALT_SCBB 7 328 #define PCS_HALT_PTBR 8 /* 9-FF: reserved */ 329 uint64_t pcs_halt_reason; /* 118: */ 330 331 uint64_t pcs_reserved_soft; /* 120: preserved software */ 332 333 struct { /* 128: inter-console buffers */ 334 u_int iccb_rxlen; 335 u_int iccb_txlen; 336 char iccb_rxbuf[80]; 337 char iccb_txbuf[80]; 338 } pcs_iccb; 339 340 #define PALvar_reserved 0 341 #define PALvar_OpenVMS 1 342 #define PALvar_OSF1 2 343 uint64_t pcs_palrevisions[16]; /* 1D0: PALcode revisions */ 344 345 uint64_t pcs_reserved_arch[6]; /* 250: reserved arch */ 346 }; 347 348 /* 349 * CTB: Console Terminal Block 350 */ 351 struct ctb { 352 uint64_t ctb_type; /* 0: CTB type */ 353 uint64_t ctb_unit; /* 8: */ 354 uint64_t ctb_reserved; /* 16: */ 355 uint64_t ctb_len; /* 24: bytes of info */ 356 uint64_t ctb_ipl; /* 32: console ipl level */ 357 u_long ctb_tintr_vec; /* 40: transmit vec (0x800) */ 358 u_long ctb_rintr_vec; /* 48: receive vec (0x800) */ 359 360 #define CTB_NONE 0x00 /* no console present */ 361 #define CTB_SERVICE 0x01 /* service processor */ 362 #define CTB_PRINTERPORT 0x02 /* printer port on the SCC */ 363 #define CTB_GRAPHICS 0x03 /* graphics device */ 364 #define CTB_TYPE4 0x04 /* type 4 CTB */ 365 #define CTB_NETWORK 0xC0 /* network device */ 366 uint64_t ctb_term_type; /* 56: terminal type */ 367 368 uint64_t ctb_keybd_type; /* 64: keyboard nationality */ 369 u_long ctb_keybd_trans; /* 72: trans. table addr */ 370 u_long ctb_keybd_map; /* 80: map table addr */ 371 uint64_t ctb_keybd_state; /* 88: keyboard flags */ 372 uint64_t ctb_keybd_last; /* 96: last key entered */ 373 u_long ctb_font_us; /* 104: US font table addr */ 374 u_long ctb_font_mcs; /* 112: MCS font table addr */ 375 uint64_t ctb_font_width; /* 120: font width, height */ 376 uint64_t ctb_font_height; /* 128: in pixels */ 377 uint64_t ctb_mon_width; /* 136: monitor width, height */ 378 uint64_t ctb_mon_height; /* 144: in pixels */ 379 uint64_t ctb_dpi; /* 152: monitor dots per inch */ 380 uint64_t ctb_planes; /* 160: # of planes */ 381 uint64_t ctb_cur_width; /* 168: cursor width, height */ 382 uint64_t ctb_cur_height; /* 176: in pixels */ 383 uint64_t ctb_head_cnt; /* 184: # of heads */ 384 uint64_t ctb_opwindow; /* 192: opwindow on screen */ 385 u_long ctb_head_offset; /* 200: offset to head info */ 386 u_long ctb_putchar; /* 208: output char to TURBO */ 387 uint64_t ctb_io_state; /* 216: I/O flags */ 388 uint64_t ctb_listen_state; /* 224: listener flags */ 389 u_long ctb_xaddr; /* 232: extended info addr */ 390 uint64_t ctb_turboslot; /* 248: TURBOchannel slot # */ 391 uint64_t ctb_server_off; /* 256: offset to server info */ 392 uint64_t ctb_line_off; /* 264: line parameter offset */ 393 uint8_t ctb_csd; /* 272: console specific data */ 394 }; 395 396 struct ctb_tt { 397 uint64_t ctb_type; /* 0: CTB type */ 398 uint64_t ctb_unit; /* 8: console unit */ 399 uint64_t ctb_reserved; /* 16: reserved */ 400 uint64_t ctb_length; /* 24: length */ 401 uint64_t ctb_csr; /* 32: address */ 402 uint64_t ctb_tivec; /* 40: Tx intr vector */ 403 uint64_t ctb_rivec; /* 48: Rx intr vector */ 404 uint64_t ctb_baud; /* 56: baud rate */ 405 uint64_t ctb_put_sts; /* 64: PUTS status */ 406 uint64_t ctb_get_sts; /* 72: GETS status */ 407 uint64_t ctb_reserved0; /* 80: reserved */ 408 }; 409 410 /* 411 * Format of the Console Terminal Block Type 4 `turboslot' field: 412 * 413 * 63 40 39 32 31 24 23 16 15 8 7 0 414 * | reserved | channel | hose | bus type | bus | slot| 415 */ 416 #define CTB_TURBOSLOT_CHANNEL(x) (((x) >> 32) & 0xff) 417 #define CTB_TURBOSLOT_HOSE(x) (((x) >> 24) & 0xff) 418 #define CTB_TURBOSLOT_TYPE(x) (((x) >> 16) & 0xff) 419 #define CTB_TURBOSLOT_BUS(x) (((x) >> 8) & 0xff) 420 #define CTB_TURBOSLOT_SLOT(x) ((x) & 0xff) 421 422 #define CTB_TURBOSLOT_TYPE_TC 0 /* TURBOchannel */ 423 #define CTB_TURBOSLOT_TYPE_ISA 1 /* ISA */ 424 #define CTB_TURBOSLOT_TYPE_EISA 2 /* EISA */ 425 #define CTB_TURBOSLOT_TYPE_PCI 3 /* PCI */ 426 427 /* 428 * CRD: Console Routine Descriptor 429 */ 430 struct crd { 431 int64_t descriptor; 432 uint64_t entry_va; 433 }; 434 435 /* 436 * CRB: Console Routine Block 437 */ 438 struct crb { 439 struct crd *crb_v_dispatch; /* 0: virtual dispatch addr */ 440 u_long crb_p_dispatch; /* 8: phys dispatch addr */ 441 struct crd *crb_v_fixup; /* 10: virtual fixup addr */ 442 u_long crb_p_fixup; /* 18: phys fixup addr */ 443 uint64_t crb_map_cnt; /* 20: phys/virt map entries */ 444 uint64_t crb_page_cnt; /* 28: pages to be mapped */ 445 }; 446 447 /* 448 * MDDT: Memory Data Descriptor Table 449 */ 450 struct mddt { 451 int64_t mddt_cksum; /* 0: 7-N checksum */ 452 u_long mddt_physaddr; /* 8: bank config addr 453 * IMPLEMENTATION SPECIFIC 454 */ 455 uint64_t mddt_cluster_cnt; /* 10: memory cluster count */ 456 struct mddt_cluster { 457 u_long mddt_pfn; /* 0: starting PFN */ 458 uint64_t mddt_pg_cnt; /* 8: 8KB page count */ 459 uint64_t mddt_pg_test; /* 10: tested page count */ 460 u_long mddt_v_bitaddr; /* 18: bitmap virt addr */ 461 u_long mddt_p_bitaddr; /* 20: bitmap phys addr */ 462 int64_t mddt_bit_cksum; /* 28: bitmap checksum */ 463 464 #define MDDT_NONVOLATILE 0x10 /* cluster is non-volatile */ 465 #define MDDT_PALCODE 0x01 /* console and PAL only */ 466 #define MDDT_SYSTEM 0x00 /* system software only */ 467 #define MDDT_mbz 0xfffffffffffffffc /* 2:63 -- must be zero */ 468 int64_t mddt_usage; /* 30: bitmap permissions */ 469 } mddt_clusters[1]; /* variable length array */ 470 }; 471 472 /* 473 * DSR: Dynamic System Recognition. We're interested in the sysname 474 * offset. The data pointed to by sysname is: 475 * 476 * [8 bytes: length of system name][N bytes: system name string] 477 * 478 * The system name string is NUL-terminated. 479 */ 480 struct dsrdb { 481 int64_t dsr_smm; /* 0: SMM number */ 482 uint64_t dsr_lurt_off; /* 8: LURT table offset */ 483 uint64_t dsr_sysname_off; /* 16: offset to sysname */ 484 }; 485 486 /* 487 * The DSR appeared in version 5 of the HWRPB. 488 */ 489 #define HWRPB_DSRDB_MINVERS 5 490 491 #ifdef _KERNEL 492 extern int cputype; 493 extern struct rpb *hwrpb; 494 #endif 495 496 #endif /* ASSEMBLER */ 497