1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3  * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
4  */
5 
6 #define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
7 #include <linux/slab.h>
8 #include <linux/of_address.h>
9 #include <linux/platform_device.h>
10 #include "dpu_hw_mdss.h"
11 #include "dpu_hw_interrupts.h"
12 #include "dpu_hw_catalog.h"
13 #include "dpu_kms.h"
14 
15 #define VIG_BASE_MASK \
16 	(BIT(DPU_SSPP_QOS) |\
17 	BIT(DPU_SSPP_CDP) |\
18 	BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
19 
20 #define VIG_MASK \
21 	(VIG_BASE_MASK | \
22 	BIT(DPU_SSPP_CSC_10BIT))
23 
24 #define VIG_MSM8998_MASK \
25 	(VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE))
26 
27 #define VIG_SDM845_MASK \
28 	(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE))
29 
30 #define VIG_SDM845_MASK_SDMA \
31 	(VIG_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
32 
33 #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
34 
35 #define DMA_MSM8998_MASK \
36 	(BIT(DPU_SSPP_QOS) |\
37 	BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
38 	BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
39 
40 #define VIG_SC7280_MASK \
41 	(VIG_SDM845_MASK | BIT(DPU_SSPP_INLINE_ROTATION))
42 
43 #define VIG_SC7280_MASK_SDMA \
44 	(VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
45 
46 #define DMA_SDM845_MASK \
47 	(BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
48 	BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
49 	BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
50 
51 #define DMA_CURSOR_SDM845_MASK \
52 	(DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR))
53 
54 #define DMA_SDM845_MASK_SDMA \
55 	(DMA_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
56 
57 #define DMA_CURSOR_SDM845_MASK_SDMA \
58 	(DMA_CURSOR_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
59 
60 #define DMA_CURSOR_MSM8998_MASK \
61 	(DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR))
62 
63 #define MIXER_MSM8998_MASK \
64 	(BIT(DPU_MIXER_SOURCESPLIT))
65 
66 #define MIXER_SDM845_MASK \
67 	(BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
68 
69 #define MIXER_QCM2290_MASK \
70 	(BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
71 
72 #define PINGPONG_SDM845_MASK \
73 	(BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
74 
75 #define PINGPONG_SDM845_TE2_MASK \
76 	(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
77 
78 #define PINGPONG_SM8150_MASK \
79 	(BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
80 
81 #define CTL_SC7280_MASK \
82 	(BIT(DPU_CTL_ACTIVE_CFG) | \
83 	 BIT(DPU_CTL_FETCH_ACTIVE) | \
84 	 BIT(DPU_CTL_VM_CFG) | \
85 	 BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
86 
87 #define CTL_SM8550_MASK \
88 	(CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4))
89 
90 #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC)
91 
92 #define INTF_SC7180_MASK \
93 	(BIT(DPU_INTF_INPUT_CTRL) | \
94 	 BIT(DPU_INTF_STATUS_SUPPORTED) | \
95 	 BIT(DPU_DATA_HCTL_EN))
96 
97 #define INTF_SC7280_MASK (INTF_SC7180_MASK)
98 
99 #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \
100 			 BIT(DPU_WB_UBWC) | \
101 			 BIT(DPU_WB_YUV_CONFIG) | \
102 			 BIT(DPU_WB_PIPE_ALPHA) | \
103 			 BIT(DPU_WB_XY_ROI_OFFSET) | \
104 			 BIT(DPU_WB_QOS) | \
105 			 BIT(DPU_WB_QOS_8LVL) | \
106 			 BIT(DPU_WB_CDP))
107 
108 #define WB_SM8250_MASK (WB_SDM845_MASK | \
109 			 BIT(DPU_WB_INPUT_CTRL))
110 
111 #define DEFAULT_PIXEL_RAM_SIZE		(50 * 1024)
112 #define DEFAULT_DPU_LINE_WIDTH		2048
113 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH	2560
114 
115 #define MAX_HORZ_DECIMATION	4
116 #define MAX_VERT_DECIMATION	4
117 
118 #define MAX_UPSCALE_RATIO	20
119 #define MAX_DOWNSCALE_RATIO	4
120 #define SSPP_UNITY_SCALE	1
121 
122 #define STRCAT(X, Y) (X Y)
123 
124 static const uint32_t plane_formats[] = {
125 	DRM_FORMAT_ARGB8888,
126 	DRM_FORMAT_ABGR8888,
127 	DRM_FORMAT_RGBA8888,
128 	DRM_FORMAT_BGRA8888,
129 	DRM_FORMAT_XRGB8888,
130 	DRM_FORMAT_RGBX8888,
131 	DRM_FORMAT_BGRX8888,
132 	DRM_FORMAT_XBGR8888,
133 	DRM_FORMAT_ARGB2101010,
134 	DRM_FORMAT_XRGB2101010,
135 	DRM_FORMAT_RGB888,
136 	DRM_FORMAT_BGR888,
137 	DRM_FORMAT_RGB565,
138 	DRM_FORMAT_BGR565,
139 	DRM_FORMAT_ARGB1555,
140 	DRM_FORMAT_ABGR1555,
141 	DRM_FORMAT_RGBA5551,
142 	DRM_FORMAT_BGRA5551,
143 	DRM_FORMAT_XRGB1555,
144 	DRM_FORMAT_XBGR1555,
145 	DRM_FORMAT_RGBX5551,
146 	DRM_FORMAT_BGRX5551,
147 	DRM_FORMAT_ARGB4444,
148 	DRM_FORMAT_ABGR4444,
149 	DRM_FORMAT_RGBA4444,
150 	DRM_FORMAT_BGRA4444,
151 	DRM_FORMAT_XRGB4444,
152 	DRM_FORMAT_XBGR4444,
153 	DRM_FORMAT_RGBX4444,
154 	DRM_FORMAT_BGRX4444,
155 };
156 
157 static const uint32_t plane_formats_yuv[] = {
158 	DRM_FORMAT_ARGB8888,
159 	DRM_FORMAT_ABGR8888,
160 	DRM_FORMAT_RGBA8888,
161 	DRM_FORMAT_BGRX8888,
162 	DRM_FORMAT_BGRA8888,
163 	DRM_FORMAT_ARGB2101010,
164 	DRM_FORMAT_XRGB2101010,
165 	DRM_FORMAT_XRGB8888,
166 	DRM_FORMAT_XBGR8888,
167 	DRM_FORMAT_RGBX8888,
168 	DRM_FORMAT_RGB888,
169 	DRM_FORMAT_BGR888,
170 	DRM_FORMAT_RGB565,
171 	DRM_FORMAT_BGR565,
172 	DRM_FORMAT_ARGB1555,
173 	DRM_FORMAT_ABGR1555,
174 	DRM_FORMAT_RGBA5551,
175 	DRM_FORMAT_BGRA5551,
176 	DRM_FORMAT_XRGB1555,
177 	DRM_FORMAT_XBGR1555,
178 	DRM_FORMAT_RGBX5551,
179 	DRM_FORMAT_BGRX5551,
180 	DRM_FORMAT_ARGB4444,
181 	DRM_FORMAT_ABGR4444,
182 	DRM_FORMAT_RGBA4444,
183 	DRM_FORMAT_BGRA4444,
184 	DRM_FORMAT_XRGB4444,
185 	DRM_FORMAT_XBGR4444,
186 	DRM_FORMAT_RGBX4444,
187 	DRM_FORMAT_BGRX4444,
188 
189 	DRM_FORMAT_P010,
190 	DRM_FORMAT_NV12,
191 	DRM_FORMAT_NV21,
192 	DRM_FORMAT_NV16,
193 	DRM_FORMAT_NV61,
194 	DRM_FORMAT_VYUY,
195 	DRM_FORMAT_UYVY,
196 	DRM_FORMAT_YUYV,
197 	DRM_FORMAT_YVYU,
198 	DRM_FORMAT_YUV420,
199 	DRM_FORMAT_YVU420,
200 };
201 
202 static const u32 rotation_v2_formats[] = {
203 	DRM_FORMAT_NV12,
204 	/* TODO add formats after validation */
205 };
206 
207 static const u32 wb2_formats_rgb[] = {
208 	DRM_FORMAT_RGB565,
209 	DRM_FORMAT_BGR565,
210 	DRM_FORMAT_RGB888,
211 	DRM_FORMAT_ARGB8888,
212 	DRM_FORMAT_RGBA8888,
213 	DRM_FORMAT_ABGR8888,
214 	DRM_FORMAT_XRGB8888,
215 	DRM_FORMAT_RGBX8888,
216 	DRM_FORMAT_XBGR8888,
217 	DRM_FORMAT_ARGB1555,
218 	DRM_FORMAT_RGBA5551,
219 	DRM_FORMAT_XRGB1555,
220 	DRM_FORMAT_RGBX5551,
221 	DRM_FORMAT_ARGB4444,
222 	DRM_FORMAT_RGBA4444,
223 	DRM_FORMAT_RGBX4444,
224 	DRM_FORMAT_XRGB4444,
225 	DRM_FORMAT_BGR888,
226 	DRM_FORMAT_BGRA8888,
227 	DRM_FORMAT_BGRX8888,
228 	DRM_FORMAT_ABGR1555,
229 	DRM_FORMAT_BGRA5551,
230 	DRM_FORMAT_XBGR1555,
231 	DRM_FORMAT_BGRX5551,
232 	DRM_FORMAT_ABGR4444,
233 	DRM_FORMAT_BGRA4444,
234 	DRM_FORMAT_BGRX4444,
235 	DRM_FORMAT_XBGR4444,
236 };
237 
238 static const u32 wb2_formats_rgb_yuv[] = {
239 	DRM_FORMAT_RGB565,
240 	DRM_FORMAT_BGR565,
241 	DRM_FORMAT_RGB888,
242 	DRM_FORMAT_ARGB8888,
243 	DRM_FORMAT_RGBA8888,
244 	DRM_FORMAT_ABGR8888,
245 	DRM_FORMAT_XRGB8888,
246 	DRM_FORMAT_RGBX8888,
247 	DRM_FORMAT_XBGR8888,
248 	DRM_FORMAT_ARGB1555,
249 	DRM_FORMAT_RGBA5551,
250 	DRM_FORMAT_XRGB1555,
251 	DRM_FORMAT_RGBX5551,
252 	DRM_FORMAT_ARGB4444,
253 	DRM_FORMAT_RGBA4444,
254 	DRM_FORMAT_RGBX4444,
255 	DRM_FORMAT_XRGB4444,
256 	DRM_FORMAT_BGR888,
257 	DRM_FORMAT_BGRA8888,
258 	DRM_FORMAT_BGRX8888,
259 	DRM_FORMAT_ABGR1555,
260 	DRM_FORMAT_BGRA5551,
261 	DRM_FORMAT_XBGR1555,
262 	DRM_FORMAT_BGRX5551,
263 	DRM_FORMAT_ABGR4444,
264 	DRM_FORMAT_BGRA4444,
265 	DRM_FORMAT_BGRX4444,
266 	DRM_FORMAT_XBGR4444,
267 	DRM_FORMAT_NV12,
268 };
269 
270 /*************************************************************
271  * SSPP sub blocks config
272  *************************************************************/
273 
274 #define SSPP_SCALER_VER(maj, min) (((maj) << 16) | (min))
275 
276 /* SSPP common configuration */
277 #define _VIG_SBLK(scaler_ver) \
278 	{ \
279 	.maxdwnscale = MAX_DOWNSCALE_RATIO, \
280 	.maxupscale = MAX_UPSCALE_RATIO, \
281 	.scaler_blk = {.name = "scaler", \
282 		.version = scaler_ver, \
283 		.base = 0xa00, .len = 0xa0,}, \
284 	.csc_blk = {.name = "csc", \
285 		.base = 0x1a00, .len = 0x100,}, \
286 	.format_list = plane_formats_yuv, \
287 	.num_formats = ARRAY_SIZE(plane_formats_yuv), \
288 	.virt_format_list = plane_formats, \
289 	.virt_num_formats = ARRAY_SIZE(plane_formats), \
290 	.rotation_cfg = NULL, \
291 	}
292 
293 #define _VIG_SBLK_ROT(scaler_ver, rot_cfg) \
294 	{ \
295 	.maxdwnscale = MAX_DOWNSCALE_RATIO, \
296 	.maxupscale = MAX_UPSCALE_RATIO, \
297 	.scaler_blk = {.name = "scaler", \
298 		.version = scaler_ver, \
299 		.base = 0xa00, .len = 0xa0,}, \
300 	.csc_blk = {.name = "csc", \
301 		.base = 0x1a00, .len = 0x100,}, \
302 	.format_list = plane_formats_yuv, \
303 	.num_formats = ARRAY_SIZE(plane_formats_yuv), \
304 	.virt_format_list = plane_formats, \
305 	.virt_num_formats = ARRAY_SIZE(plane_formats), \
306 	.rotation_cfg = rot_cfg, \
307 	}
308 
309 #define _VIG_SBLK_NOSCALE() \
310 	{ \
311 	.maxdwnscale = SSPP_UNITY_SCALE, \
312 	.maxupscale = SSPP_UNITY_SCALE, \
313 	.format_list = plane_formats, \
314 	.num_formats = ARRAY_SIZE(plane_formats), \
315 	.virt_format_list = plane_formats, \
316 	.virt_num_formats = ARRAY_SIZE(plane_formats), \
317 	}
318 
319 #define _DMA_SBLK() \
320 	{ \
321 	.maxdwnscale = SSPP_UNITY_SCALE, \
322 	.maxupscale = SSPP_UNITY_SCALE, \
323 	.format_list = plane_formats, \
324 	.num_formats = ARRAY_SIZE(plane_formats), \
325 	.virt_format_list = plane_formats, \
326 	.virt_num_formats = ARRAY_SIZE(plane_formats), \
327 	}
328 
329 static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = {
330 	.rot_maxheight = 1088,
331 	.rot_num_formats = ARRAY_SIZE(rotation_v2_formats),
332 	.rot_format_list = rotation_v2_formats,
333 };
334 
335 static const struct dpu_sspp_sub_blks dpu_vig_sblk_noscale =
336 				_VIG_SBLK_NOSCALE();
337 
338 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_1_2 =
339 				_VIG_SBLK(SSPP_SCALER_VER(1, 2));
340 
341 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_1_3 =
342 				_VIG_SBLK(SSPP_SCALER_VER(1, 3));
343 
344 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_1_4 =
345 				_VIG_SBLK(SSPP_SCALER_VER(1, 4));
346 
347 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_2_4 =
348 				_VIG_SBLK(SSPP_SCALER_VER(2, 4));
349 
350 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_0 =
351 				_VIG_SBLK(SSPP_SCALER_VER(3, 0));
352 
353 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_0_rot_v2 =
354 			_VIG_SBLK_ROT(SSPP_SCALER_VER(3, 0),
355 				      &dpu_rot_sc7280_cfg_v2);
356 
357 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_1 =
358 				_VIG_SBLK(SSPP_SCALER_VER(3, 1));
359 
360 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_2 =
361 				_VIG_SBLK(SSPP_SCALER_VER(3, 2));
362 
363 static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_3 =
364 				_VIG_SBLK(SSPP_SCALER_VER(3, 3));
365 
366 static const struct dpu_sspp_sub_blks dpu_dma_sblk = _DMA_SBLK();
367 
368 /*************************************************************
369  * MIXER sub blocks config
370  *************************************************************/
371 
372 /* MSM8998 */
373 
374 static const struct dpu_lm_sub_blks msm8998_lm_sblk = {
375 	.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
376 	.maxblendstages = 7, /* excluding base layer */
377 	.blendstage_base = { /* offsets relative to mixer base */
378 		0x20, 0x50, 0x80, 0xb0, 0x230,
379 		0x260, 0x290
380 	},
381 };
382 
383 /* SDM845 */
384 
385 static const struct dpu_lm_sub_blks sdm845_lm_sblk = {
386 	.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
387 	.maxblendstages = 11, /* excluding base layer */
388 	.blendstage_base = { /* offsets relative to mixer base */
389 		0x20, 0x38, 0x50, 0x68, 0x80, 0x98,
390 		0xb0, 0xc8, 0xe0, 0xf8, 0x110
391 	},
392 };
393 
394 /* SC7180 */
395 
396 static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
397 	.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
398 	.maxblendstages = 7, /* excluding base layer */
399 	.blendstage_base = { /* offsets relative to mixer base */
400 		0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0
401 	},
402 };
403 
404 /* QCM2290 */
405 
406 static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
407 	.maxwidth = DEFAULT_DPU_LINE_WIDTH,
408 	.maxblendstages = 4, /* excluding base layer */
409 	.blendstage_base = { /* offsets relative to mixer base */
410 		0x20, 0x38, 0x50, 0x68
411 	},
412 };
413 
414 /*************************************************************
415  * DSPP sub blocks config
416  *************************************************************/
417 static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = {
418 	.pcc = {.name = "pcc", .base = 0x1700,
419 		.len = 0x90, .version = 0x10007},
420 };
421 
422 static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = {
423 	.pcc = {.name = "pcc", .base = 0x1700,
424 		.len = 0x90, .version = 0x40000},
425 };
426 
427 /*************************************************************
428  * PINGPONG sub blocks config
429  *************************************************************/
430 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = {
431 	.te2 = {.name = "te2", .base = 0x2000, .len = 0x0,
432 		.version = 0x1},
433 	.dither = {.name = "dither", .base = 0x30e0,
434 		.len = 0x20, .version = 0x10000},
435 };
436 
437 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = {
438 	.dither = {.name = "dither", .base = 0x30e0,
439 		.len = 0x20, .version = 0x10000},
440 };
441 
442 static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
443 	.dither = {.name = "dither", .base = 0xe0,
444 	.len = 0x20, .version = 0x20000},
445 };
446 
447 /*************************************************************
448  * DSC sub blocks config
449  *************************************************************/
450 static const struct dpu_dsc_sub_blks dsc_sblk_0 = {
451 	.enc = {.name = "enc", .base = 0x100, .len = 0x9c},
452 	.ctl = {.name = "ctl", .base = 0xF00, .len = 0x10},
453 };
454 
455 static const struct dpu_dsc_sub_blks dsc_sblk_1 = {
456 	.enc = {.name = "enc", .base = 0x200, .len = 0x9c},
457 	.ctl = {.name = "ctl", .base = 0xF80, .len = 0x10},
458 };
459 
460 /*************************************************************
461  * CDM block config
462  *************************************************************/
463 static const struct dpu_cdm_cfg sc7280_cdm = {
464 	.name = "cdm_0",
465 	.id = CDM_0,
466 	.len = 0x228,
467 	.base = 0x79200,
468 };
469 
470 /*************************************************************
471  * VBIF sub blocks config
472  *************************************************************/
473 /* VBIF QOS remap */
474 static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2};
475 static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1};
476 static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6};
477 static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3};
478 static const u32 sm8650_rt_pri_lvl[] = {4, 4, 5, 5, 5, 5, 5, 6};
479 
480 static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = {
481 	{
482 		.pps = 1920 * 1080 * 30,
483 		.ot_limit = 2,
484 	},
485 	{
486 		.pps = 1920 * 1080 * 60,
487 		.ot_limit = 4,
488 	},
489 	{
490 		.pps = 3840 * 2160 * 30,
491 		.ot_limit = 16,
492 	},
493 };
494 
495 static const struct dpu_vbif_cfg msm8998_vbif[] = {
496 	{
497 	.name = "vbif_rt", .id = VBIF_RT,
498 	.base = 0, .len = 0x1040,
499 	.default_ot_rd_limit = 32,
500 	.default_ot_wr_limit = 32,
501 	.features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM),
502 	.xin_halt_timeout = 0x4000,
503 	.qos_rp_remap_size = 0x20,
504 	.dynamic_ot_rd_tbl = {
505 		.count = ARRAY_SIZE(msm8998_ot_rdwr_cfg),
506 		.cfg = msm8998_ot_rdwr_cfg,
507 		},
508 	.dynamic_ot_wr_tbl = {
509 		.count = ARRAY_SIZE(msm8998_ot_rdwr_cfg),
510 		.cfg = msm8998_ot_rdwr_cfg,
511 		},
512 	.qos_rt_tbl = {
513 		.npriority_lvl = ARRAY_SIZE(msm8998_rt_pri_lvl),
514 		.priority_lvl = msm8998_rt_pri_lvl,
515 		},
516 	.qos_nrt_tbl = {
517 		.npriority_lvl = ARRAY_SIZE(msm8998_nrt_pri_lvl),
518 		.priority_lvl = msm8998_nrt_pri_lvl,
519 		},
520 	.memtype_count = 14,
521 	.memtype = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
522 	},
523 };
524 
525 static const struct dpu_vbif_cfg sdm845_vbif[] = {
526 	{
527 	.name = "vbif_rt", .id = VBIF_RT,
528 	.base = 0, .len = 0x1040,
529 	.features = BIT(DPU_VBIF_QOS_REMAP),
530 	.xin_halt_timeout = 0x4000,
531 	.qos_rp_remap_size = 0x40,
532 	.qos_rt_tbl = {
533 		.npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
534 		.priority_lvl = sdm845_rt_pri_lvl,
535 		},
536 	.qos_nrt_tbl = {
537 		.npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
538 		.priority_lvl = sdm845_nrt_pri_lvl,
539 		},
540 	.memtype_count = 14,
541 	.memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
542 	},
543 };
544 
545 static const struct dpu_vbif_cfg sm8550_vbif[] = {
546 	{
547 	.name = "vbif_rt", .id = VBIF_RT,
548 	.base = 0, .len = 0x1040,
549 	.features = BIT(DPU_VBIF_QOS_REMAP),
550 	.xin_halt_timeout = 0x4000,
551 	.qos_rp_remap_size = 0x40,
552 	.qos_rt_tbl = {
553 		.npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
554 		.priority_lvl = sdm845_rt_pri_lvl,
555 		},
556 	.qos_nrt_tbl = {
557 		.npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
558 		.priority_lvl = sdm845_nrt_pri_lvl,
559 		},
560 	.memtype_count = 16,
561 	.memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
562 	},
563 };
564 
565 static const struct dpu_vbif_cfg sm8650_vbif[] = {
566 	{
567 	.name = "vbif_rt", .id = VBIF_RT,
568 	.base = 0, .len = 0x1074,
569 	.features = BIT(DPU_VBIF_QOS_REMAP),
570 	.xin_halt_timeout = 0x4000,
571 	.qos_rp_remap_size = 0x40,
572 	.qos_rt_tbl = {
573 		.npriority_lvl = ARRAY_SIZE(sm8650_rt_pri_lvl),
574 		.priority_lvl = sm8650_rt_pri_lvl,
575 		},
576 	.qos_nrt_tbl = {
577 		.npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
578 		.priority_lvl = sdm845_nrt_pri_lvl,
579 		},
580 	.memtype_count = 16,
581 	.memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
582 	},
583 };
584 
585 /*************************************************************
586  * PERF data config
587  *************************************************************/
588 
589 /* SSPP QOS LUTs */
590 static const struct dpu_qos_lut_entry msm8998_qos_linear[] = {
591 	{.fl = 4,  .lut = 0x1b},
592 	{.fl = 5,  .lut = 0x5b},
593 	{.fl = 6,  .lut = 0x15b},
594 	{.fl = 7,  .lut = 0x55b},
595 	{.fl = 8,  .lut = 0x155b},
596 	{.fl = 9,  .lut = 0x555b},
597 	{.fl = 10, .lut = 0x1555b},
598 	{.fl = 11, .lut = 0x5555b},
599 	{.fl = 12, .lut = 0x15555b},
600 	{.fl = 0,  .lut = 0x55555b}
601 };
602 
603 static const struct dpu_qos_lut_entry sdm845_qos_linear[] = {
604 	{.fl = 4, .lut = 0x357},
605 	{.fl = 5, .lut = 0x3357},
606 	{.fl = 6, .lut = 0x23357},
607 	{.fl = 7, .lut = 0x223357},
608 	{.fl = 8, .lut = 0x2223357},
609 	{.fl = 9, .lut = 0x22223357},
610 	{.fl = 10, .lut = 0x222223357},
611 	{.fl = 11, .lut = 0x2222223357},
612 	{.fl = 12, .lut = 0x22222223357},
613 	{.fl = 13, .lut = 0x222222223357},
614 	{.fl = 14, .lut = 0x1222222223357},
615 	{.fl = 0, .lut = 0x11222222223357}
616 };
617 
618 static const struct dpu_qos_lut_entry msm8998_qos_macrotile[] = {
619 	{.fl = 10, .lut = 0x1aaff},
620 	{.fl = 11, .lut = 0x5aaff},
621 	{.fl = 12, .lut = 0x15aaff},
622 	{.fl = 0,  .lut = 0x55aaff},
623 };
624 
625 static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
626 	{.fl = 0, .lut = 0x0011222222335777},
627 };
628 
629 static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
630 	{.fl = 0, .lut = 0x0011223445566777 },
631 };
632 
633 static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
634 	{.fl = 0, .lut = 0x0011222222223357 },
635 };
636 
637 static const struct dpu_qos_lut_entry sc8180x_qos_linear[] = {
638 	{.fl = 4, .lut = 0x0000000000000357 },
639 };
640 
641 static const struct dpu_qos_lut_entry qcm2290_qos_linear[] = {
642 	{.fl = 0, .lut = 0x0011222222335777},
643 };
644 
645 static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = {
646 	{.fl = 10, .lut = 0x344556677},
647 	{.fl = 11, .lut = 0x3344556677},
648 	{.fl = 12, .lut = 0x23344556677},
649 	{.fl = 13, .lut = 0x223344556677},
650 	{.fl = 14, .lut = 0x1223344556677},
651 	{.fl = 0, .lut = 0x112233344556677},
652 };
653 
654 static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = {
655 	{.fl = 0, .lut = 0x0011223344556677},
656 };
657 
658 static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = {
659 	{.fl = 10, .lut = 0x0000000344556677},
660 };
661 
662 static const struct dpu_qos_lut_entry msm8998_qos_nrt[] = {
663 	{.fl = 0, .lut = 0x0},
664 };
665 
666 static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = {
667 	{.fl = 0, .lut = 0x0},
668 };
669 
670 static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
671 	{.fl = 0, .lut = 0x0},
672 };
673 
674 /*************************************************************
675  * Hardware catalog
676  *************************************************************/
677 
678 #include "catalog/dpu_3_0_msm8998.h"
679 #include "catalog/dpu_3_2_sdm660.h"
680 #include "catalog/dpu_3_3_sdm630.h"
681 
682 #include "catalog/dpu_4_0_sdm845.h"
683 #include "catalog/dpu_4_1_sdm670.h"
684 
685 #include "catalog/dpu_5_0_sm8150.h"
686 #include "catalog/dpu_5_1_sc8180x.h"
687 #include "catalog/dpu_5_2_sm7150.h"
688 #include "catalog/dpu_5_4_sm6125.h"
689 
690 #include "catalog/dpu_6_0_sm8250.h"
691 #include "catalog/dpu_6_2_sc7180.h"
692 #include "catalog/dpu_6_3_sm6115.h"
693 #include "catalog/dpu_6_4_sm6350.h"
694 #include "catalog/dpu_6_5_qcm2290.h"
695 #include "catalog/dpu_6_9_sm6375.h"
696 
697 #include "catalog/dpu_7_0_sm8350.h"
698 #include "catalog/dpu_7_2_sc7280.h"
699 
700 #include "catalog/dpu_8_0_sc8280xp.h"
701 #include "catalog/dpu_8_1_sm8450.h"
702 
703 #include "catalog/dpu_9_0_sm8550.h"
704 
705 #include "catalog/dpu_9_2_x1e80100.h"
706 
707 #include "catalog/dpu_10_0_sm8650.h"
708