xref: /dragonfly/sys/dev/netif/sn/if_snreg.h (revision 86d7f5d3)
1 /*
2  * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  * 3. All advertising materials mentioning features or use of this software
14  *    must display the following acknowledgement:
15  *      This product includes software developed by Gardner Buchanan.
16  * 4. The name of Gardner Buchanan may not be used to endorse or promote
17  *    products derived from this software without specific prior written
18  *    permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30  *
31  *   $FreeBSD: src/sys/dev/sn/if_snreg.h,v 1.2.2.1 2001/02/04 04:38:38 toshi Exp $
32  *   $DragonFly: src/sys/dev/netif/sn/if_snreg.h,v 1.2 2003/06/17 04:28:29 dillon Exp $
33  */
34 
35 /*
36  * This file contains register information and access macros for
37  * the SMC91xxx chipset.
38  *
39  * Information contained in this file was obtained from the SMC91C92
40  * and SMC91C94 manuals from SMC.  You will need one of these in order
41  * to make any meaningful changes to this driver.  Information about
42  * obtaining one can be found at http://www.smc.com in the components
43  * division.
44  *
45  * This FreeBSD driver is derived in part from the smc9194 Linux driver
46  * by Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman.
47  * It is also derived in part from the FreeBSD ep (3C509) driver which
48  * is Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights
49  * reserved.
50  *
51  */
52 #ifndef _IF_SNREG_H_
53 #define _IF_SNREG_H_
54 
55 /*
56  * Wait time for memory to be free.  This probably shouldn't be
57  * tuned that much, as waiting for this means nothing else happens
58  * in the system
59  */
60 #define	MEMORY_WAIT_TIME	1000
61 
62 
63 /* The SMC91xxx uses 16 I/O ports
64  */
65 #define SMC_IO_EXTENT   16
66 
67 
68 /*
69  * A description of the SMC registers is probably in order here,
70  * although for details, the SMC datasheet is invaluable.
71  * The data sheet I (GB) am using is "SMC91C92 Single Chip Ethernet
72  * Controller With RAM", Rev. 12/0/94.  Constant definitions I give
73  * here are loosely based on the mnemonic names given to them in the
74  * data sheet, but there are many exceptions.
75  *
76  * Basically, the chip has 4 banks of registers (0 to 3), which
77  * are accessed by writing a number into the BANK_SELECT register
78  * (I also use a SMC_SELECT_BANK macro for this).  Registers are
79  * either Byte or Word sized.  My constant definitions end in _B
80  * or _W as appropriate.
81  *
82  * The banks are arranged so that for most purposes, bank 2 is all
83  * that is needed for normal run time tasks.
84  */
85 
86 /*
87  * Bank Select Register.  This also doubles as
88  * a chip identification register.  This register
89  * is mapped at the same position in all banks.
90  */
91 #define BANK_SELECT_REG_W       0x0e
92 #define BSR_DETECT_MASK         0xff00
93 #define BSR_DETECT_VALUE        0x3300
94 
95 
96 /* BANK 0
97  */
98 
99 /* Transmit Control Register controls some aspects of the transmit
100  * behavior of the Ethernet Protocol Handler.
101  */
102 #define TXMIT_CONTROL_REG_W  0x00
103 
104 #define TCR_ENABLE      0x0001	/* if this is 1, we can transmit */
105 #define TCR_LOOP        0x0002	/* Enable internal analogue loopback */
106 #define TCR_FORCOL      0x0004	/* Force Collision on next TX */
107 #define TCR_PAD_ENABLE  0x0080	/* Pad short packets to 64 bytes */
108 #define TCR_NOCRC       0x0100	/* Do not append CRC */
109 #define TCR_MON_CSN     0x0400	/* monitors the carrier status */
110 #define TCR_FDUPLX      0x0800	/* receive packets sent out */
111 #define TCR_STP_SQET    0x1000	/* stop transmitting if Signal quality error */
112 #define TCR_EPH_LOOP    0x2000	/* Enable internal digital loopback */
113 
114 
115 /* Status of the last transmitted frame and instantaneous status of
116  * the Ethernet Protocol Handler jumbled together.  In auto-release
117  * mode this information is simply discarded after each TX.  This info
118  * is copied to the status word of in-memory packets after transmit
119  * where relevent statuses can be checked.
120  */
121 #define EPH_STATUS_REG_W 0x02
122 
123 #define EPHSR_TX_SUC    0x0001	/* Transmit was successful */
124 #define EPHSR_SNGLCOL   0x0002	/* Single collision occurred */
125 #define EPHSR_MULCOL    0x0004	/* Multiple Collisions occurred */
126 #define EPHSR_LTX_MULT  0x0008	/* Transmit was a multicast */
127 #define EPHSR_16COL     0x0010	/* 16 Collisions occurred, TX disabled */
128 #define EPHSR_SQET      0x0020	/* SQE Test failed, TX disabled */
129 #define EPHSR_LTX_BRD   0x0040	/* Transmit was a broadcast */
130 #define EPHSR_DEFR      0x0080	/* TX deferred due to carrier det. */
131 #define EPHSR_LATCOL    0x0200	/* Late collision detected, TX disabled */
132 #define EPHSR_LOST_CAR  0x0400	/* Lost carrier sense, TX disabled */
133 #define EPHSR_EXC_DEF   0x0800	/* Excessive deferrals in TX >2 MAXETHER
134 				 * times */
135 #define EPHSR_CTR_ROL   0x1000	/* Some ECR Counter(s) rolled over */
136 #define EPHSR_RX_OVRN   0x2000	/* Receiver overrun, packets dropped */
137 #define EPHSR_LINK_OK   0x4000	/* Link integrity is OK */
138 #define EPHSR_TXUNRN    0x8000	/* Transmit underrun */
139 
140 
141 /* Receiver Control Register controls some aspects of the receive
142  * behavior of the Ethernet Protocol Handler.
143  */
144 #define RECV_CONTROL_REG_W 0x04
145 
146 #define RCR_RX_ABORT    0x0001	/* Received huge packet */
147 #define RCR_PROMISC     0x0002	/* enable promiscuous mode */
148 #define RCR_ALMUL       0x0004	/* receive all multicast packets */
149 #define RCR_ENABLE      0x0100	/* IFF this is set, we can recieve packets */
150 #define RCR_STRIP_CRC   0x0200	/* strips CRC */
151 #define RCR_GAIN_BITS   0x0c00	/* PLL Gain control (for testing) */
152 #define RCR_FILT_CAR    0x4000	/* Enable 12 bit carrier filter */
153 #define RCR_SOFTRESET   0x8000	/* Resets the EPH logic */
154 
155 
156 /* TX Statistics counters
157  */
158 #define COUNTER_REG_W   0x06
159 
160 #define ECR_COLN_MASK   0x000f	/* Vanilla collisions */
161 #define ECR_MCOLN_MASK  0x00f0	/* Multiple collisions */
162 #define ECR_DTX_MASK    0x0f00	/* Deferred transmits */
163 #define ECR_EXDTX_MASK  0xf000	/* Excessively deferred transmits */
164 
165 /* Memory Information
166  */
167 #define MEM_INFO_REG_W  0x08
168 
169 #define MIR_FREE_MASK   0xff00	/* Free memory pages available */
170 #define MIR_TOTAL_MASK  0x00ff	/* Total memory pages available */
171 
172 /* Memory Configuration
173  */
174 #define MEM_CFG_REG_W   0x0a
175 
176 #define MCR_TXRSV_MASK  0x001f	/* Count of pages reserved for transmit */
177 
178 
179 /* Bank 0, Register 0x0c is unised in the SMC91C92
180  */
181 
182 
183 /* BANK 1
184  */
185 
186 /* Adapter configuration
187  */
188 #define CONFIG_REG_W    0x00
189 
190 #define CR_INT_SEL0     0x0002	/* Interrupt selector */
191 #define CR_INT_SEL1     0x0004	/* Interrupt selector */
192 #define CR_DIS_LINK     0x0040	/* Disable 10BaseT Link Test */
193 #define CR_16BIT        0x0080	/* Bus width */
194 #define CR_AUI_SELECT   0x0100	/* Use external (AUI) Transceiver */
195 #define CR_SET_SQLCH    0x0200	/* Squelch level */
196 #define CR_FULL_STEP    0x0400	/* AUI signalling mode */
197 #define CR_NOW_WAIT_ST  0x1000	/* Disable bus wait states */
198 
199 /* The contents of this port are used by the adapter
200  * to decode its I/O address.  We use it as a varification
201  * that the adapter is detected properly when probing.
202  */
203 #define BASE_ADDR_REG_W 0x02	/* The select IO Base addr. */
204 
205 /* These registers hold the Ethernet MAC address.
206  */
207 #define IAR_ADDR0_REG_W 0x04	/* My Ethernet address */
208 #define IAR_ADDR1_REG_W 0x06	/* My Ethernet address */
209 #define IAR_ADDR2_REG_W 0x08	/* My Ethernet address */
210 
211 /* General purpose register used for talking to the EEPROM.
212  */
213 #define GENERAL_REG_W   0x0a
214 
215 /* Control register used for talking to the EEPROM and
216  * setting some EPH functions.
217  */
218 #define CONTROL_REG_W    0x0c
219 #define CTR_STORE        0x0001	/* Store something to EEPROM */
220 #define CTR_RELOAD       0x0002	/* Read EEPROM into registers */
221 #define CTR_EEPROM_SEL   0x0004	/* Select registers for Reload/Store */
222 #define CTR_TE_ENABLE    0x0020	/* Enable TX Error detection via EPH_INT */
223 #define CTR_CR_ENABLE    0x0040	/* Enable Counter Rollover via EPH_INT */
224 #define CTR_LE_ENABLE    0x0080	/* Enable Link Error detection via EPH_INT */
225 #define CTR_AUTO_RELEASE 0x0800	/* Enable auto release mode for TX */
226 #define CTR_POWERDOWN    0x2000	/* Enter powerdown mode */
227 #define CTR_RCV_BAD      0x4000	/* Enable receipt of frames with bad CRC */
228 
229 
230 /* BANK 2
231  */
232 
233 /* Memory Management Unit Control Register
234  * Controls allocation of memory to receive and
235  * transmit functions.
236  */
237 #define MMU_CMD_REG_W   0x00
238 #define MMUCR_BUSY      0x0001	/* MMU busy performing a release */
239 
240 /* MMU Commands:
241  */
242 #define MMUCR_NOP       0x0000	/* Do nothing */
243 #define MMUCR_ALLOC     0x0020	/* Or with number of 256 byte packets - 1 */
244 #define MMUCR_RESET     0x0040	/* Reset MMU State */
245 #define MMUCR_REMOVE    0x0060	/* Dequeue (but not free) current RX packet */
246 #define MMUCR_RELEASE   0x0080	/* Dequeue and free the current RX packet */
247 #define MMUCR_FREEPKT   0x00a0	/* Release packet in PNR register */
248 #define MMUCR_ENQUEUE   0x00c0	/* Enqueue the packet for transmit */
249 #define MMUCR_RESETTX   0x00e0	/* Reset transmit queues */
250 
251 /* Packet Number at TX Area
252  */
253 #define PACKET_NUM_REG_B   0x02
254 
255 /* Packet number resulting from MMUCR_ALLOC
256  */
257 #define ALLOC_RESULT_REG_B 0x03
258 #define ARR_FAILED      0x80
259 
260 /* Transmit and receive queue heads
261  */
262 #define FIFO_PORTS_REG_W 0x04
263 #define FIFO_REMPTY     0x8000
264 #define FIFO_TEMPTY     0x0080
265 #define FIFO_RX_MASK    0x7f00
266 #define FIFO_TX_MASK    0x007f
267 
268 /* The address within the packet for reading/writing.  The
269  * PTR_RCV bit is tricky.  When PTR_RCV==1, the packet number
270  * to be read is found in the FIFO_PORTS_REG_W, FIFO_RX_MASK.
271  * When PTR_RCV==0, the packet number to be written is found
272  * in the PACKET_NUM_REG_B.
273  */
274 #define POINTER_REG_W   0x06
275 #define PTR_READ        0x2000	/* Intended access mode */
276 #define PTR_AUTOINC     0x4000	/* Do auto inc after read/write */
277 #define PTR_RCV         0x8000	/* FIFO_RX is packet, otherwise PNR is packet */
278 
279 /* Data I/O register to be used in conjunction with
280  * The pointer register to read and write data from the
281  * card.  The same register can be used for byte and word
282  * ops.
283  */
284 #define DATA_REG_W      0x08
285 #define DATA_REG_B      0x08
286 #define DATA_1_REG_B    0x08
287 #define DATA_2_REG_B    0x0a
288 
289 /* Sense interrupt status (READ)
290  */
291 #define INTR_STAT_REG_B 0x0c
292 
293 /* Acknowledge interrupt sources (WRITE)
294  */
295 #define INTR_ACK_REG_B  0x0c
296 
297 /* Interrupt mask.  Bit set indicates interrupt allowed.
298  */
299 #define INTR_MASK_REG_B 0x0d
300 
301 /* Interrupts
302  */
303 #define IM_RCV_INT      0x01	/* A packet has been received */
304 #define IM_TX_INT       0x02	/* Packet TX complete */
305 #define IM_TX_EMPTY_INT 0x04	/* No packets left to TX  */
306 #define IM_ALLOC_INT    0x08	/* Memory allocation completed */
307 #define IM_RX_OVRN_INT  0x10	/* Receiver was overrun */
308 #define IM_EPH_INT      0x20	/* Misc. EPH conditions (see CONTROL_REG_W) */
309 #define IM_ERCV_INT     0x40	/* not on SMC9192 */
310 
311 /* BANK 3
312  */
313 
314 /* Multicast subscriptions.
315  * The multicast handling in the SMC90Cxx is quite complicated.  A table
316  * of multicast address subscriptions is provided and a clever way of
317  * speeding the search of that table by hashing is implemented in the
318  * hardware.  I have ignored this and simply subscribed to all multicasts
319  * and let the kernel deal with the results.
320  */
321 #define MULTICAST1_REG_W 0x00
322 #define MULTICAST2_REG_W 0x02
323 #define MULTICAST3_REG_W 0x04
324 #define MULTICAST4_REG_W 0x06
325 
326 /* These registers do not exist on SMC9192, or at least
327  * are not documented in the SMC91C92 data sheet.
328  * The REVISION_REG_W register does however seem to work.
329  */
330 #define MGMT_REG_W      0x08
331 #define REVISION_REG_W  0x0a	/* (hi: chip id low: rev #) */
332 #define ERCV_REG_W      0x0c
333 
334 /* These are constants expected to be found in the
335  * chip id register.
336  */
337 #define CHIP_9190       3
338 #define CHIP_9194       4
339 #define CHIP_9195       5
340 #define CHIP_91100      7
341 #define CHIP_91100FD    8
342 
343 /* When packets are stuffed into the card or sucked out of the card
344  * they are set up more or less as follows:
345  *
346  * Addr msbyte   lsbyte
347  * 00   SSSSSSSS SSSSSSSS - STATUS-WORD 16 bit TX or RX status
348  * 02   RRRRR             - RESERVED (unused)
349  * 02        CCC CCCCCCCC - BYTE COUNT (RX: always even, TX: bit 0 ignored)
350  * 04   DDDDDDDD DDDDDDDD - DESTINATION ADDRESS
351  * 06   DDDDDDDD DDDDDDDD        (48 bit Ethernet MAC Address)
352  * 08   DDDDDDDD DDDDDDDD
353  * 0A   SSSSSSSS SSSSSSSS - SOURCE ADDRESS
354  * 0C   SSSSSSSS SSSSSSSS        (48 bit Ethernet MAC Address)
355  * 0E   SSSSSSSS SSSSSSSS
356  * 10   PPPPPPPP PPPPPPPP
357  * ..   PPPPPPPP PPPPPPPP
358  * C-2  CCCCCCCC          - CONTROL BYTE
359  * C-2           PPPPPPPP - Last data byte (If odd length)
360  *
361  * The STATUS_WORD is derived from the EPH_STATUS_REG_W register
362  * during transmit and is composed of another set of bits described
363  * below during receive.
364  */
365 
366 
367 /* Receive status bits.  These values are found in the status word
368  * field of a received packet.  For receive packets I use the RS_ODDFRAME
369  * to detect whether a frame has an extra byte on it.  The CTLB_ODD
370  * bit of the control byte tells the same thing.
371  */
372 #define RS_MULTICAST    0x0001	/* Packet is multicast */
373 #define RS_HASH_MASK    0x007e	/* Mask of multicast hash value */
374 #define RS_TOOSHORT     0x0400	/* Frame was a runt, <64 bytes */
375 #define RS_TOOLONG      0x0800	/* Frame was giant, >1518 */
376 #define RS_ODDFRAME     0x1000	/* Frame is odd lengthed */
377 #define RS_BADCRC       0x2000	/* Frame had CRC error */
378 #define RS_ALGNERR      0x8000	/* Frame had alignment error */
379 #define RS_ERRORS       (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
380 
381 #define RLEN_MASK       0x07ff	/* Significant length bits in RX length */
382 
383 /* The control byte has the following significant bits.
384  * For transmit, the CTLB_ODD bit specifies whether an extra byte
385  * is present in the frame.  Bit 0 of the byte count field is
386  * ignored.  I just pad every frame to even length and forget about
387  * it.
388  */
389 #define CTLB_CRC        0x10	/* Add CRC for this packet (TX only) */
390 #define CTLB_ODD        0x20	/* The packet length is ODD */
391 
392 
393 /*
394  * I define some macros to make it easier to do somewhat common
395  * or slightly complicated, repeated tasks.
396  */
397 
398 /* The base I/O address.
399  */
400 #define BASE    (sc->sn_io_addr)
401 
402 /* Select a register bank, 0 to 3
403  */
404 #define SMC_SELECT_BANK(x)  { outw( BASE + BANK_SELECT_REG_W, (x) ); }
405 
406 /* Define a small delay for the reset
407  */
408 #define SMC_DELAY() { inw( BASE + RECV_CONTROL_REG_W );\
409                       inw( BASE + RECV_CONTROL_REG_W );\
410                       inw( BASE + RECV_CONTROL_REG_W );  }
411 
412 /* Define flags
413  */
414 
415 #define SN_FLAGS_PCCARD		0x0001	/* PCMCIA (PC-card) */
416 #define	SN_FLAGS_XJBT10		0x0002	/* Megahertz XJ-BT10 (PCMCIA) */
417 
418 #endif	/* _IF_SNREG_H_ */
419