1 /*	$NetBSD: radeon_ucode.h,v 1.3 2021/12/18 23:45:43 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2012 Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  */
25 #ifndef __RADEON_UCODE_H__
26 #define __RADEON_UCODE_H__
27 
28 /* CP */
29 #define R600_PFP_UCODE_SIZE          576
30 #define R600_PM4_UCODE_SIZE          1792
31 #define R700_PFP_UCODE_SIZE          848
32 #define R700_PM4_UCODE_SIZE          1360
33 #define EVERGREEN_PFP_UCODE_SIZE     1120
34 #define EVERGREEN_PM4_UCODE_SIZE     1376
35 #define CAYMAN_PFP_UCODE_SIZE        2176
36 #define CAYMAN_PM4_UCODE_SIZE        2176
37 #define SI_PFP_UCODE_SIZE            2144
38 #define SI_PM4_UCODE_SIZE            2144
39 #define SI_CE_UCODE_SIZE             2144
40 #define CIK_PFP_UCODE_SIZE           2144
41 #define CIK_ME_UCODE_SIZE            2144
42 #define CIK_CE_UCODE_SIZE            2144
43 
44 /* MEC */
45 #define CIK_MEC_UCODE_SIZE           4192
46 
47 /* RLC */
48 #define R600_RLC_UCODE_SIZE          768
49 #define R700_RLC_UCODE_SIZE          1024
50 #define EVERGREEN_RLC_UCODE_SIZE     768
51 #define CAYMAN_RLC_UCODE_SIZE        1024
52 #define ARUBA_RLC_UCODE_SIZE         1536
53 #define SI_RLC_UCODE_SIZE            2048
54 #define BONAIRE_RLC_UCODE_SIZE       2048
55 #define KB_RLC_UCODE_SIZE            2560
56 #define KV_RLC_UCODE_SIZE            2560
57 #define ML_RLC_UCODE_SIZE            2560
58 
59 /* MC */
60 #define BTC_MC_UCODE_SIZE            6024
61 #define CAYMAN_MC_UCODE_SIZE         6037
62 #define SI_MC_UCODE_SIZE             7769
63 #define TAHITI_MC_UCODE_SIZE         7808
64 #define PITCAIRN_MC_UCODE_SIZE       7775
65 #define VERDE_MC_UCODE_SIZE          7875
66 #define OLAND_MC_UCODE_SIZE          7863
67 #define BONAIRE_MC_UCODE_SIZE        7866
68 #define BONAIRE_MC2_UCODE_SIZE       7948
69 #define HAWAII_MC_UCODE_SIZE         7933
70 #define HAWAII_MC2_UCODE_SIZE        8091
71 
72 /* SDMA */
73 #define CIK_SDMA_UCODE_SIZE          1050
74 #define CIK_SDMA_UCODE_VERSION       64
75 
76 /* SMC */
77 #define RV770_SMC_UCODE_START        0x0100
78 #define RV770_SMC_UCODE_SIZE         0x410d
79 #define RV770_SMC_INT_VECTOR_START   0xffc0
80 #define RV770_SMC_INT_VECTOR_SIZE    0x0040
81 
82 #define RV730_SMC_UCODE_START        0x0100
83 #define RV730_SMC_UCODE_SIZE         0x412c
84 #define RV730_SMC_INT_VECTOR_START   0xffc0
85 #define RV730_SMC_INT_VECTOR_SIZE    0x0040
86 
87 #define RV710_SMC_UCODE_START        0x0100
88 #define RV710_SMC_UCODE_SIZE         0x3f1f
89 #define RV710_SMC_INT_VECTOR_START   0xffc0
90 #define RV710_SMC_INT_VECTOR_SIZE    0x0040
91 
92 #define RV740_SMC_UCODE_START        0x0100
93 #define RV740_SMC_UCODE_SIZE         0x41c5
94 #define RV740_SMC_INT_VECTOR_START   0xffc0
95 #define RV740_SMC_INT_VECTOR_SIZE    0x0040
96 
97 #define CEDAR_SMC_UCODE_START        0x0100
98 #define CEDAR_SMC_UCODE_SIZE         0x5d50
99 #define CEDAR_SMC_INT_VECTOR_START   0xffc0
100 #define CEDAR_SMC_INT_VECTOR_SIZE    0x0040
101 
102 #define REDWOOD_SMC_UCODE_START      0x0100
103 #define REDWOOD_SMC_UCODE_SIZE       0x5f0a
104 #define REDWOOD_SMC_INT_VECTOR_START 0xffc0
105 #define REDWOOD_SMC_INT_VECTOR_SIZE  0x0040
106 
107 #define JUNIPER_SMC_UCODE_START      0x0100
108 #define JUNIPER_SMC_UCODE_SIZE       0x5f1f
109 #define JUNIPER_SMC_INT_VECTOR_START 0xffc0
110 #define JUNIPER_SMC_INT_VECTOR_SIZE  0x0040
111 
112 #define CYPRESS_SMC_UCODE_START      0x0100
113 #define CYPRESS_SMC_UCODE_SIZE       0x61f7
114 #define CYPRESS_SMC_INT_VECTOR_START 0xffc0
115 #define CYPRESS_SMC_INT_VECTOR_SIZE  0x0040
116 
117 #define BARTS_SMC_UCODE_START        0x0100
118 #define BARTS_SMC_UCODE_SIZE         0x6107
119 #define BARTS_SMC_INT_VECTOR_START   0xffc0
120 #define BARTS_SMC_INT_VECTOR_SIZE    0x0040
121 
122 #define TURKS_SMC_UCODE_START        0x0100
123 #define TURKS_SMC_UCODE_SIZE         0x605b
124 #define TURKS_SMC_INT_VECTOR_START   0xffc0
125 #define TURKS_SMC_INT_VECTOR_SIZE    0x0040
126 
127 #define CAICOS_SMC_UCODE_START       0x0100
128 #define CAICOS_SMC_UCODE_SIZE        0x5fbd
129 #define CAICOS_SMC_INT_VECTOR_START  0xffc0
130 #define CAICOS_SMC_INT_VECTOR_SIZE   0x0040
131 
132 #define CAYMAN_SMC_UCODE_START       0x0100
133 #define CAYMAN_SMC_UCODE_SIZE        0x79ec
134 #define CAYMAN_SMC_INT_VECTOR_START  0xffc0
135 #define CAYMAN_SMC_INT_VECTOR_SIZE   0x0040
136 
137 #define TAHITI_SMC_UCODE_START       0x10000
138 #define TAHITI_SMC_UCODE_SIZE        0xf458
139 
140 #define PITCAIRN_SMC_UCODE_START     0x10000
141 #define PITCAIRN_SMC_UCODE_SIZE      0xe9f4
142 
143 #define VERDE_SMC_UCODE_START        0x10000
144 #define VERDE_SMC_UCODE_SIZE         0xebe4
145 
146 #define OLAND_SMC_UCODE_START        0x10000
147 #define OLAND_SMC_UCODE_SIZE         0xe7b4
148 
149 #define HAINAN_SMC_UCODE_START       0x10000
150 #define HAINAN_SMC_UCODE_SIZE        0xe67C
151 
152 #define BONAIRE_SMC_UCODE_START      0x20000
153 #define BONAIRE_SMC_UCODE_SIZE       0x1FDEC
154 
155 #define HAWAII_SMC_UCODE_START       0x20000
156 #define HAWAII_SMC_UCODE_SIZE        0x1FDEC
157 
158 struct common_firmware_header {
159 	uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
160 	uint32_t header_size_bytes; /* size of just the header in bytes */
161 	uint16_t header_version_major; /* header version */
162 	uint16_t header_version_minor; /* header version */
163 	uint16_t ip_version_major; /* IP version */
164 	uint16_t ip_version_minor; /* IP version */
165 	uint32_t ucode_version;
166 	uint32_t ucode_size_bytes; /* size of ucode in bytes */
167 	uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
168 	uint32_t crc32;  /* crc32 checksum of the payload */
169 };
170 
171 /* version_major=1, version_minor=0 */
172 struct mc_firmware_header_v1_0 {
173 	struct common_firmware_header header;
174 	uint32_t io_debug_size_bytes; /* size of debug array in dwords */
175 	uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
176 };
177 
178 /* version_major=1, version_minor=0 */
179 struct smc_firmware_header_v1_0 {
180 	struct common_firmware_header header;
181 	uint32_t ucode_start_addr;
182 };
183 
184 /* version_major=1, version_minor=0 */
185 struct gfx_firmware_header_v1_0 {
186 	struct common_firmware_header header;
187 	uint32_t ucode_feature_version;
188 	uint32_t jt_offset; /* jt location */
189 	uint32_t jt_size;  /* size of jt */
190 };
191 
192 /* version_major=1, version_minor=0 */
193 struct rlc_firmware_header_v1_0 {
194 	struct common_firmware_header header;
195 	uint32_t ucode_feature_version;
196 	uint32_t save_and_restore_offset;
197 	uint32_t clear_state_descriptor_offset;
198 	uint32_t avail_scratch_ram_locations;
199 	uint32_t master_pkt_description_offset;
200 };
201 
202 /* version_major=1, version_minor=0 */
203 struct sdma_firmware_header_v1_0 {
204 	struct common_firmware_header header;
205 	uint32_t ucode_feature_version;
206 	uint32_t ucode_change_version;
207 	uint32_t jt_offset; /* jt location */
208 	uint32_t jt_size; /* size of jt */
209 };
210 
211 /* header is fixed size */
212 union radeon_firmware_header {
213 	struct common_firmware_header common;
214 	struct mc_firmware_header_v1_0 mc;
215 	struct smc_firmware_header_v1_0 smc;
216 	struct gfx_firmware_header_v1_0 gfx;
217 	struct rlc_firmware_header_v1_0 rlc;
218 	struct sdma_firmware_header_v1_0 sdma;
219 	uint8_t raw[0x100];
220 };
221 
222 void radeon_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
223 void radeon_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
224 void radeon_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
225 void radeon_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
226 void radeon_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
227 int radeon_ucode_validate(const struct firmware *fw);
228 
229 #endif
230