1 /* $OpenBSD: pciide_cy693_reg.h,v 1.9 2022/01/09 05:42:58 jsg Exp $ */ 2 /* $NetBSD: pciide_cy693_reg.h,v 1.4 2000/05/15 08:46:01 bouyer Exp $ */ 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef _DEV_PCI_PCIIDE_CY693_REG_H_ 30 #define _DEV_PCI_PCIIDE_CY693_REG_H_ 31 32 /* 33 * Registers definitions for Contaq/Cypress's CY82693U PCI IDE controller. 34 * Available from http://www.cypress.com/japan/prodgate/chip/cy82c693.html 35 * This chip has 2 PCI IDE functions, each of them has only one channel 36 * So there's no primary/secondary distinction in the registers defs. 37 */ 38 39 /* IDE control register */ 40 #define CY_CTRL 0x40 41 #define CY_CTRL_RETRY 0x00002000 42 #define CY_CTRL_SLAVE_PREFETCH 0x00000400 43 #define CY_CTRL_POSTWRITE 0x00000200 44 #define CY_CTRL_PREFETCH(drive) (0x00000100 << (2 * (drive))) 45 #define CY_CTRL_POSTWRITE_LENGTH_MASK 0x00000030 46 #define CY_CTRL_POSTWRITE_LENGTH_OFF 4 47 #define CY_CTRL_PREFETCH_LENGTH_MASK 0x00000003 48 #define CY_CTRL_PREFETCH_LENGTH_OFF 0 49 50 /* IDE addr setup control register */ 51 #define CY_ADDR_CTRL 0x48 52 #define CY_ADDR_CTRL_SETUP_OFF(drive) (4 * (drive)) 53 #define CY_ADDR_CTRL_SETUP_MASK(drive) \ 54 (0x00000007 << CY_ADDR_CTRL_SETUP_OFF(drive)) 55 56 /* command control register */ 57 #define CY_CMD_CTRL 0x4c 58 #define CY_CMD_CTRL_IOW_PULSE_OFF(drive) (12 + 16 * (drive)) 59 #define CY_CMD_CTRL_IOW_REC_OFF(drive) (8 + 16 * (drive)) 60 #define CY_CMD_CTRL_IOR_PULSE_OFF(drive) (4 + 16 * (drive)) 61 #define CY_CMD_CTRL_IOR_REC_OFF(drive) (0 + 16 * (drive)) 62 63 static int8_t cy_pio_pulse[] = {9, 4, 3, 2, 2}; 64 static int8_t cy_pio_rec[] = {9, 7, 4, 2, 0}; 65 #ifdef unused 66 static int8_t cy_dma_pulse[] = {7, 2, 2}; 67 static int8_t cy_dma_rec[] = {7, 1, 0}; 68 #endif 69 70 /* 71 * The cypress is quite weird: it uses 8-bit ISA registers to control 72 * DMA modes. 73 */ 74 75 #define CY_DMA_ADDR 0x22 76 #define CY_DMA_SIZE 0x2 77 78 #define CY_DMA_IDX 0x00 79 #define CY_DMA_IDX_PRIMARY 0x30 80 #define CY_DMA_IDX_SECONDARY 0x31 81 #define CY_DMA_IDX_TIMEOUT 0x32 82 83 #define CY_DMA_DATA 0x01 84 /* Multiword DMA transfer, for CY_DMA_IDX_PRIMARY or CY_DMA_IDX_SECONDARY */ 85 #define CY_DMA_DATA_MODE_MASK 0x03 86 #define CY_DMA_DATA_SINGLE 0x04 87 88 /* Private data */ 89 struct pciide_cy { 90 const struct cy82c693_handle *cy_handle; 91 int cy_compatchan; 92 }; 93 94 #endif /* !_DEV_PCI_PCIIDE_CY693_REG_H_ */ 95