1 //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// 9 /// \file 10 /// This file describes how to lower LLVM code to machine code. This has two 11 /// main components: 12 /// 13 /// 1. Which ValueTypes are natively supported by the target. 14 /// 2. Which operations are supported for supported ValueTypes. 15 /// 3. Cost thresholds for alternative implementations of certain operations. 16 /// 17 /// In addition it has a few other components, like information about FP 18 /// immediates. 19 /// 20 //===----------------------------------------------------------------------===// 21 22 #ifndef LLVM_CODEGEN_TARGETLOWERING_H 23 #define LLVM_CODEGEN_TARGETLOWERING_H 24 25 #include "llvm/ADT/APInt.h" 26 #include "llvm/ADT/ArrayRef.h" 27 #include "llvm/ADT/DenseMap.h" 28 #include "llvm/ADT/STLExtras.h" 29 #include "llvm/ADT/SmallVector.h" 30 #include "llvm/ADT/StringRef.h" 31 #include "llvm/CodeGen/DAGCombine.h" 32 #include "llvm/CodeGen/ISDOpcodes.h" 33 #include "llvm/CodeGen/RuntimeLibcalls.h" 34 #include "llvm/CodeGen/SelectionDAG.h" 35 #include "llvm/CodeGen/SelectionDAGNodes.h" 36 #include "llvm/CodeGen/TargetCallingConv.h" 37 #include "llvm/CodeGen/ValueTypes.h" 38 #include "llvm/IR/Attributes.h" 39 #include "llvm/IR/CallingConv.h" 40 #include "llvm/IR/DataLayout.h" 41 #include "llvm/IR/DerivedTypes.h" 42 #include "llvm/IR/Function.h" 43 #include "llvm/IR/IRBuilder.h" 44 #include "llvm/IR/InlineAsm.h" 45 #include "llvm/IR/Instruction.h" 46 #include "llvm/IR/Instructions.h" 47 #include "llvm/IR/Type.h" 48 #include "llvm/Support/Alignment.h" 49 #include "llvm/Support/AtomicOrdering.h" 50 #include "llvm/Support/Casting.h" 51 #include "llvm/Support/ErrorHandling.h" 52 #include "llvm/Support/InstructionCost.h" 53 #include "llvm/Support/MachineValueType.h" 54 #include <algorithm> 55 #include <cassert> 56 #include <climits> 57 #include <cstdint> 58 #include <iterator> 59 #include <map> 60 #include <string> 61 #include <utility> 62 #include <vector> 63 64 namespace llvm { 65 66 class BranchProbability; 67 class CCState; 68 class CCValAssign; 69 class Constant; 70 class FastISel; 71 class FunctionLoweringInfo; 72 class GlobalValue; 73 class GISelKnownBits; 74 class IntrinsicInst; 75 struct KnownBits; 76 class LegacyDivergenceAnalysis; 77 class LLVMContext; 78 class MachineBasicBlock; 79 class MachineFunction; 80 class MachineInstr; 81 class MachineJumpTableInfo; 82 class MachineLoop; 83 class MachineRegisterInfo; 84 class MCContext; 85 class MCExpr; 86 class Module; 87 class ProfileSummaryInfo; 88 class TargetLibraryInfo; 89 class TargetMachine; 90 class TargetRegisterClass; 91 class TargetRegisterInfo; 92 class TargetTransformInfo; 93 class Value; 94 95 namespace Sched { 96 97 enum Preference { 98 None, // No preference 99 Source, // Follow source order. 100 RegPressure, // Scheduling for lowest register pressure. 101 Hybrid, // Scheduling for both latency and register pressure. 102 ILP, // Scheduling for ILP in low register pressure mode. 103 VLIW, // Scheduling for VLIW targets. 104 Fast, // Fast suboptimal list scheduling 105 Linearize // Linearize DAG, no scheduling 106 }; 107 108 } // end namespace Sched 109 110 // MemOp models a memory operation, either memset or memcpy/memmove. 111 struct MemOp { 112 private: 113 // Shared 114 uint64_t Size; 115 bool DstAlignCanChange; // true if destination alignment can satisfy any 116 // constraint. 117 Align DstAlign; // Specified alignment of the memory operation. 118 119 bool AllowOverlap; 120 // memset only 121 bool IsMemset; // If setthis memory operation is a memset. 122 bool ZeroMemset; // If set clears out memory with zeros. 123 // memcpy only 124 bool MemcpyStrSrc; // Indicates whether the memcpy source is an in-register 125 // constant so it does not need to be loaded. 126 Align SrcAlign; // Inferred alignment of the source or default value if the 127 // memory operation does not need to load the value. 128 public: 129 static MemOp Copy(uint64_t Size, bool DstAlignCanChange, Align DstAlign, 130 Align SrcAlign, bool IsVolatile, 131 bool MemcpyStrSrc = false) { 132 MemOp Op; 133 Op.Size = Size; 134 Op.DstAlignCanChange = DstAlignCanChange; 135 Op.DstAlign = DstAlign; 136 Op.AllowOverlap = !IsVolatile; 137 Op.IsMemset = false; 138 Op.ZeroMemset = false; 139 Op.MemcpyStrSrc = MemcpyStrSrc; 140 Op.SrcAlign = SrcAlign; 141 return Op; 142 } 143 SetMemOp144 static MemOp Set(uint64_t Size, bool DstAlignCanChange, Align DstAlign, 145 bool IsZeroMemset, bool IsVolatile) { 146 MemOp Op; 147 Op.Size = Size; 148 Op.DstAlignCanChange = DstAlignCanChange; 149 Op.DstAlign = DstAlign; 150 Op.AllowOverlap = !IsVolatile; 151 Op.IsMemset = true; 152 Op.ZeroMemset = IsZeroMemset; 153 Op.MemcpyStrSrc = false; 154 return Op; 155 } 156 sizeMemOp157 uint64_t size() const { return Size; } getDstAlignMemOp158 Align getDstAlign() const { 159 assert(!DstAlignCanChange); 160 return DstAlign; 161 } isFixedDstAlignMemOp162 bool isFixedDstAlign() const { return !DstAlignCanChange; } allowOverlapMemOp163 bool allowOverlap() const { return AllowOverlap; } isMemsetMemOp164 bool isMemset() const { return IsMemset; } isMemcpyMemOp165 bool isMemcpy() const { return !IsMemset; } isMemcpyWithFixedDstAlignMemOp166 bool isMemcpyWithFixedDstAlign() const { 167 return isMemcpy() && !DstAlignCanChange; 168 } isZeroMemsetMemOp169 bool isZeroMemset() const { return isMemset() && ZeroMemset; } isMemcpyStrSrcMemOp170 bool isMemcpyStrSrc() const { 171 assert(isMemcpy() && "Must be a memcpy"); 172 return MemcpyStrSrc; 173 } getSrcAlignMemOp174 Align getSrcAlign() const { 175 assert(isMemcpy() && "Must be a memcpy"); 176 return SrcAlign; 177 } isSrcAlignedMemOp178 bool isSrcAligned(Align AlignCheck) const { 179 return isMemset() || llvm::isAligned(AlignCheck, SrcAlign.value()); 180 } isDstAlignedMemOp181 bool isDstAligned(Align AlignCheck) const { 182 return DstAlignCanChange || llvm::isAligned(AlignCheck, DstAlign.value()); 183 } isAlignedMemOp184 bool isAligned(Align AlignCheck) const { 185 return isSrcAligned(AlignCheck) && isDstAligned(AlignCheck); 186 } 187 }; 188 189 /// This base class for TargetLowering contains the SelectionDAG-independent 190 /// parts that can be used from the rest of CodeGen. 191 class TargetLoweringBase { 192 public: 193 /// This enum indicates whether operations are valid for a target, and if not, 194 /// what action should be used to make them valid. 195 enum LegalizeAction : uint8_t { 196 Legal, // The target natively supports this operation. 197 Promote, // This operation should be executed in a larger type. 198 Expand, // Try to expand this to other ops, otherwise use a libcall. 199 LibCall, // Don't try to expand this to other ops, always use a libcall. 200 Custom // Use the LowerOperation hook to implement custom lowering. 201 }; 202 203 /// This enum indicates whether a types are legal for a target, and if not, 204 /// what action should be used to make them valid. 205 enum LegalizeTypeAction : uint8_t { 206 TypeLegal, // The target natively supports this type. 207 TypePromoteInteger, // Replace this integer with a larger one. 208 TypeExpandInteger, // Split this integer into two of half the size. 209 TypeSoftenFloat, // Convert this float to a same size integer type. 210 TypeExpandFloat, // Split this float into two of half the size. 211 TypeScalarizeVector, // Replace this one-element vector with its element. 212 TypeSplitVector, // Split this vector into two of half the size. 213 TypeWidenVector, // This vector should be widened into a larger vector. 214 TypePromoteFloat, // Replace this float with a larger one. 215 TypeSoftPromoteHalf, // Soften half to i16 and use float to do arithmetic. 216 TypeScalarizeScalableVector, // This action is explicitly left unimplemented. 217 // While it is theoretically possible to 218 // legalize operations on scalable types with a 219 // loop that handles the vscale * #lanes of the 220 // vector, this is non-trivial at SelectionDAG 221 // level and these types are better to be 222 // widened or promoted. 223 }; 224 225 /// LegalizeKind holds the legalization kind that needs to happen to EVT 226 /// in order to type-legalize it. 227 using LegalizeKind = std::pair<LegalizeTypeAction, EVT>; 228 229 /// Enum that describes how the target represents true/false values. 230 enum BooleanContent { 231 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage. 232 ZeroOrOneBooleanContent, // All bits zero except for bit 0. 233 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0. 234 }; 235 236 /// Enum that describes what type of support for selects the target has. 237 enum SelectSupportKind { 238 ScalarValSelect, // The target supports scalar selects (ex: cmov). 239 ScalarCondVectorVal, // The target supports selects with a scalar condition 240 // and vector values (ex: cmov). 241 VectorMaskSelect // The target supports vector selects with a vector 242 // mask (ex: x86 blends). 243 }; 244 245 /// Enum that specifies what an atomic load/AtomicRMWInst is expanded 246 /// to, if at all. Exists because different targets have different levels of 247 /// support for these atomic instructions, and also have different options 248 /// w.r.t. what they should expand to. 249 enum class AtomicExpansionKind { 250 None, // Don't expand the instruction. 251 LLSC, // Expand the instruction into loadlinked/storeconditional; used 252 // by ARM/AArch64. 253 LLOnly, // Expand the (load) instruction into just a load-linked, which has 254 // greater atomic guarantees than a normal load. 255 CmpXChg, // Expand the instruction into cmpxchg; used by at least X86. 256 MaskedIntrinsic, // Use a target-specific intrinsic for the LL/SC loop. 257 }; 258 259 /// Enum that specifies when a multiplication should be expanded. 260 enum class MulExpansionKind { 261 Always, // Always expand the instruction. 262 OnlyLegalOrCustom, // Only expand when the resulting instructions are legal 263 // or custom. 264 }; 265 266 /// Enum that specifies when a float negation is beneficial. 267 enum class NegatibleCost { 268 Cheaper = 0, // Negated expression is cheaper. 269 Neutral = 1, // Negated expression has the same cost. 270 Expensive = 2 // Negated expression is more expensive. 271 }; 272 273 class ArgListEntry { 274 public: 275 Value *Val = nullptr; 276 SDValue Node = SDValue(); 277 Type *Ty = nullptr; 278 bool IsSExt : 1; 279 bool IsZExt : 1; 280 bool IsInReg : 1; 281 bool IsSRet : 1; 282 bool IsNest : 1; 283 bool IsByVal : 1; 284 bool IsByRef : 1; 285 bool IsInAlloca : 1; 286 bool IsPreallocated : 1; 287 bool IsReturned : 1; 288 bool IsSwiftSelf : 1; 289 bool IsSwiftAsync : 1; 290 bool IsSwiftError : 1; 291 bool IsCFGuardTarget : 1; 292 MaybeAlign Alignment = None; 293 // Type for byval, inalloca, or preallocated. 294 Type *IndirectType = nullptr; 295 ArgListEntry()296 ArgListEntry() 297 : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false), 298 IsNest(false), IsByVal(false), IsByRef(false), IsInAlloca(false), 299 IsPreallocated(false), IsReturned(false), IsSwiftSelf(false), 300 IsSwiftAsync(false), IsSwiftError(false), IsCFGuardTarget(false) {} 301 302 void setAttributes(const CallBase *Call, unsigned ArgIdx); 303 }; 304 using ArgListTy = std::vector<ArgListEntry>; 305 markLibCallAttributes(MachineFunction * MF,unsigned CC,ArgListTy & Args)306 virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC, 307 ArgListTy &Args) const {}; 308 getExtendForContent(BooleanContent Content)309 static ISD::NodeType getExtendForContent(BooleanContent Content) { 310 switch (Content) { 311 case UndefinedBooleanContent: 312 // Extend by adding rubbish bits. 313 return ISD::ANY_EXTEND; 314 case ZeroOrOneBooleanContent: 315 // Extend by adding zero bits. 316 return ISD::ZERO_EXTEND; 317 case ZeroOrNegativeOneBooleanContent: 318 // Extend by copying the sign bit. 319 return ISD::SIGN_EXTEND; 320 } 321 llvm_unreachable("Invalid content kind"); 322 } 323 324 explicit TargetLoweringBase(const TargetMachine &TM); 325 TargetLoweringBase(const TargetLoweringBase &) = delete; 326 TargetLoweringBase &operator=(const TargetLoweringBase &) = delete; 327 virtual ~TargetLoweringBase() = default; 328 329 /// Return true if the target support strict float operation isStrictFPEnabled()330 bool isStrictFPEnabled() const { 331 return IsStrictFPEnabled; 332 } 333 334 protected: 335 /// Initialize all of the actions to default values. 336 void initActions(); 337 338 public: getTargetMachine()339 const TargetMachine &getTargetMachine() const { return TM; } 340 useSoftFloat()341 virtual bool useSoftFloat() const { return false; } 342 343 /// Return the pointer type for the given address space, defaults to 344 /// the pointer type from the data layout. 345 /// FIXME: The default needs to be removed once all the code is updated. 346 virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const { 347 return MVT::getIntegerVT(DL.getPointerSizeInBits(AS)); 348 } 349 350 /// Return the in-memory pointer type for the given address space, defaults to 351 /// the pointer type from the data layout. FIXME: The default needs to be 352 /// removed once all the code is updated. 353 MVT getPointerMemTy(const DataLayout &DL, uint32_t AS = 0) const { 354 return MVT::getIntegerVT(DL.getPointerSizeInBits(AS)); 355 } 356 357 /// Return the type for frame index, which is determined by 358 /// the alloca address space specified through the data layout. getFrameIndexTy(const DataLayout & DL)359 MVT getFrameIndexTy(const DataLayout &DL) const { 360 return getPointerTy(DL, DL.getAllocaAddrSpace()); 361 } 362 363 /// Return the type for code pointers, which is determined by the program 364 /// address space specified through the data layout. getProgramPointerTy(const DataLayout & DL)365 MVT getProgramPointerTy(const DataLayout &DL) const { 366 return getPointerTy(DL, DL.getProgramAddressSpace()); 367 } 368 369 /// Return the type for operands of fence. 370 /// TODO: Let fence operands be of i32 type and remove this. getFenceOperandTy(const DataLayout & DL)371 virtual MVT getFenceOperandTy(const DataLayout &DL) const { 372 return getPointerTy(DL); 373 } 374 375 /// EVT is not used in-tree, but is used by out-of-tree target. 376 /// A documentation for this function would be nice... 377 virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const; 378 379 EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, 380 bool LegalTypes = true) const; 381 382 /// Return the preferred type to use for a shift opcode, given the shifted 383 /// amount type is \p ShiftValueTy. 384 LLVM_READONLY getPreferredShiftAmountTy(LLT ShiftValueTy)385 virtual LLT getPreferredShiftAmountTy(LLT ShiftValueTy) const { 386 return ShiftValueTy; 387 } 388 389 /// Returns the type to be used for the index operand of: 390 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, 391 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR getVectorIdxTy(const DataLayout & DL)392 virtual MVT getVectorIdxTy(const DataLayout &DL) const { 393 return getPointerTy(DL); 394 } 395 396 /// This callback is used to inspect load/store instructions and add 397 /// target-specific MachineMemOperand flags to them. The default 398 /// implementation does nothing. getTargetMMOFlags(const Instruction & I)399 virtual MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const { 400 return MachineMemOperand::MONone; 401 } 402 403 MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI, 404 const DataLayout &DL) const; 405 MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, 406 const DataLayout &DL) const; 407 MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, 408 const DataLayout &DL) const; 409 isSelectSupported(SelectSupportKind)410 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const { 411 return true; 412 } 413 414 /// Return true if it is profitable to convert a select of FP constants into 415 /// a constant pool load whose address depends on the select condition. The 416 /// parameter may be used to differentiate a select with FP compare from 417 /// integer compare. reduceSelectOfFPConstantLoads(EVT CmpOpVT)418 virtual bool reduceSelectOfFPConstantLoads(EVT CmpOpVT) const { 419 return true; 420 } 421 422 /// Return true if multiple condition registers are available. hasMultipleConditionRegisters()423 bool hasMultipleConditionRegisters() const { 424 return HasMultipleConditionRegisters; 425 } 426 427 /// Return true if the target has BitExtract instructions. hasExtractBitsInsn()428 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; } 429 430 /// Return the preferred vector type legalization action. 431 virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)432 getPreferredVectorAction(MVT VT) const { 433 // The default action for one element vectors is to scalarize 434 if (VT.getVectorElementCount().isScalar()) 435 return TypeScalarizeVector; 436 // The default action for an odd-width vector is to widen. 437 if (!VT.isPow2VectorType()) 438 return TypeWidenVector; 439 // The default action for other vectors is to promote 440 return TypePromoteInteger; 441 } 442 443 // Return true if the half type should be passed around as i16, but promoted 444 // to float around arithmetic. The default behavior is to pass around as 445 // float and convert around loads/stores/bitcasts and other places where 446 // the size matters. softPromoteHalfType()447 virtual bool softPromoteHalfType() const { return false; } 448 449 // There are two general methods for expanding a BUILD_VECTOR node: 450 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle 451 // them together. 452 // 2. Build the vector on the stack and then load it. 453 // If this function returns true, then method (1) will be used, subject to 454 // the constraint that all of the necessary shuffles are legal (as determined 455 // by isShuffleMaskLegal). If this function returns false, then method (2) is 456 // always used. The vector type, and the number of defined values, are 457 // provided. 458 virtual bool shouldExpandBuildVectorWithShuffles(EVT,unsigned DefinedValues)459 shouldExpandBuildVectorWithShuffles(EVT /* VT */, 460 unsigned DefinedValues) const { 461 return DefinedValues < 3; 462 } 463 464 /// Return true if integer divide is usually cheaper than a sequence of 465 /// several shifts, adds, and multiplies for this target. 466 /// The definition of "cheaper" may depend on whether we're optimizing 467 /// for speed or for size. isIntDivCheap(EVT VT,AttributeList Attr)468 virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; } 469 470 /// Return true if the target can handle a standalone remainder operation. hasStandaloneRem(EVT VT)471 virtual bool hasStandaloneRem(EVT VT) const { 472 return true; 473 } 474 475 /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X). isFsqrtCheap(SDValue X,SelectionDAG & DAG)476 virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const { 477 // Default behavior is to replace SQRT(X) with X*RSQRT(X). 478 return false; 479 } 480 481 /// Reciprocal estimate status values used by the functions below. 482 enum ReciprocalEstimate : int { 483 Unspecified = -1, 484 Disabled = 0, 485 Enabled = 1 486 }; 487 488 /// Return a ReciprocalEstimate enum value for a square root of the given type 489 /// based on the function's attributes. If the operation is not overridden by 490 /// the function's attributes, "Unspecified" is returned and target defaults 491 /// are expected to be used for instruction selection. 492 int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const; 493 494 /// Return a ReciprocalEstimate enum value for a division of the given type 495 /// based on the function's attributes. If the operation is not overridden by 496 /// the function's attributes, "Unspecified" is returned and target defaults 497 /// are expected to be used for instruction selection. 498 int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const; 499 500 /// Return the refinement step count for a square root of the given type based 501 /// on the function's attributes. If the operation is not overridden by 502 /// the function's attributes, "Unspecified" is returned and target defaults 503 /// are expected to be used for instruction selection. 504 int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const; 505 506 /// Return the refinement step count for a division of the given type based 507 /// on the function's attributes. If the operation is not overridden by 508 /// the function's attributes, "Unspecified" is returned and target defaults 509 /// are expected to be used for instruction selection. 510 int getDivRefinementSteps(EVT VT, MachineFunction &MF) const; 511 512 /// Returns true if target has indicated at least one type should be bypassed. isSlowDivBypassed()513 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); } 514 515 /// Returns map of slow types for division or remainder with corresponding 516 /// fast types getBypassSlowDivWidths()517 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const { 518 return BypassSlowDivWidths; 519 } 520 521 /// Return true if Flow Control is an expensive operation that should be 522 /// avoided. isJumpExpensive()523 bool isJumpExpensive() const { return JumpIsExpensive; } 524 525 /// Return true if selects are only cheaper than branches if the branch is 526 /// unlikely to be predicted right. isPredictableSelectExpensive()527 bool isPredictableSelectExpensive() const { 528 return PredictableSelectIsExpensive; 529 } 530 fallBackToDAGISel(const Instruction & Inst)531 virtual bool fallBackToDAGISel(const Instruction &Inst) const { 532 return false; 533 } 534 535 /// Return true if the following transform is beneficial: 536 /// fold (conv (load x)) -> (load (conv*)x) 537 /// On architectures that don't natively support some vector loads 538 /// efficiently, casting the load to a smaller vector of larger types and 539 /// loading is more efficient, however, this can be undone by optimizations in 540 /// dag combiner. isLoadBitCastBeneficial(EVT LoadVT,EVT BitcastVT,const SelectionDAG & DAG,const MachineMemOperand & MMO)541 virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, 542 const SelectionDAG &DAG, 543 const MachineMemOperand &MMO) const { 544 // Don't do if we could do an indexed load on the original type, but not on 545 // the new one. 546 if (!LoadVT.isSimple() || !BitcastVT.isSimple()) 547 return true; 548 549 MVT LoadMVT = LoadVT.getSimpleVT(); 550 551 // Don't bother doing this if it's just going to be promoted again later, as 552 // doing so might interfere with other combines. 553 if (getOperationAction(ISD::LOAD, LoadMVT) == Promote && 554 getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT()) 555 return false; 556 557 bool Fast = false; 558 return allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), BitcastVT, 559 MMO, &Fast) && Fast; 560 } 561 562 /// Return true if the following transform is beneficial: 563 /// (store (y (conv x)), y*)) -> (store x, (x*)) isStoreBitCastBeneficial(EVT StoreVT,EVT BitcastVT,const SelectionDAG & DAG,const MachineMemOperand & MMO)564 virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT, 565 const SelectionDAG &DAG, 566 const MachineMemOperand &MMO) const { 567 // Default to the same logic as loads. 568 return isLoadBitCastBeneficial(StoreVT, BitcastVT, DAG, MMO); 569 } 570 571 /// Return true if it is expected to be cheaper to do a store of a non-zero 572 /// vector constant with the given size and type for the address space than to 573 /// store the individual scalar element constants. storeOfVectorConstantIsCheap(EVT MemVT,unsigned NumElem,unsigned AddrSpace)574 virtual bool storeOfVectorConstantIsCheap(EVT MemVT, 575 unsigned NumElem, 576 unsigned AddrSpace) const { 577 return false; 578 } 579 580 /// Allow store merging for the specified type after legalization in addition 581 /// to before legalization. This may transform stores that do not exist 582 /// earlier (for example, stores created from intrinsics). mergeStoresAfterLegalization(EVT MemVT)583 virtual bool mergeStoresAfterLegalization(EVT MemVT) const { 584 return true; 585 } 586 587 /// Returns if it's reasonable to merge stores to MemVT size. canMergeStoresTo(unsigned AS,EVT MemVT,const SelectionDAG & DAG)588 virtual bool canMergeStoresTo(unsigned AS, EVT MemVT, 589 const SelectionDAG &DAG) const { 590 return true; 591 } 592 593 /// Return true if it is cheap to speculate a call to intrinsic cttz. isCheapToSpeculateCttz()594 virtual bool isCheapToSpeculateCttz() const { 595 return false; 596 } 597 598 /// Return true if it is cheap to speculate a call to intrinsic ctlz. isCheapToSpeculateCtlz()599 virtual bool isCheapToSpeculateCtlz() const { 600 return false; 601 } 602 603 /// Return true if ctlz instruction is fast. isCtlzFast()604 virtual bool isCtlzFast() const { 605 return false; 606 } 607 608 /// Return the maximum number of "x & (x - 1)" operations that can be done 609 /// instead of deferring to a custom CTPOP. getCustomCtpopCost(EVT VT,ISD::CondCode Cond)610 virtual unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const { 611 return 1; 612 } 613 614 /// Return true if instruction generated for equality comparison is folded 615 /// with instruction generated for signed comparison. isEqualityCmpFoldedWithSignedCmp()616 virtual bool isEqualityCmpFoldedWithSignedCmp() const { return true; } 617 618 /// Return true if the heuristic to prefer icmp eq zero should be used in code 619 /// gen prepare. preferZeroCompareBranch()620 virtual bool preferZeroCompareBranch() const { return false; } 621 622 /// Return true if it is safe to transform an integer-domain bitwise operation 623 /// into the equivalent floating-point operation. This should be set to true 624 /// if the target has IEEE-754-compliant fabs/fneg operations for the input 625 /// type. hasBitPreservingFPLogic(EVT VT)626 virtual bool hasBitPreservingFPLogic(EVT VT) const { 627 return false; 628 } 629 630 /// Return true if it is cheaper to split the store of a merged int val 631 /// from a pair of smaller values into multiple stores. isMultiStoresCheaperThanBitsMerge(EVT LTy,EVT HTy)632 virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const { 633 return false; 634 } 635 636 /// Return if the target supports combining a 637 /// chain like: 638 /// \code 639 /// %andResult = and %val1, #mask 640 /// %icmpResult = icmp %andResult, 0 641 /// \endcode 642 /// into a single machine instruction of a form like: 643 /// \code 644 /// cc = test %register, #mask 645 /// \endcode isMaskAndCmp0FoldingBeneficial(const Instruction & AndI)646 virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const { 647 return false; 648 } 649 650 /// Use bitwise logic to make pairs of compares more efficient. For example: 651 /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0 652 /// This should be true when it takes more than one instruction to lower 653 /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on 654 /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win. convertSetCCLogicToBitwiseLogic(EVT VT)655 virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const { 656 return false; 657 } 658 659 /// Return the preferred operand type if the target has a quick way to compare 660 /// integer values of the given size. Assume that any legal integer type can 661 /// be compared efficiently. Targets may override this to allow illegal wide 662 /// types to return a vector type if there is support to compare that type. hasFastEqualityCompare(unsigned NumBits)663 virtual MVT hasFastEqualityCompare(unsigned NumBits) const { 664 MVT VT = MVT::getIntegerVT(NumBits); 665 return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE; 666 } 667 668 /// Return true if the target should transform: 669 /// (X & Y) == Y ---> (~X & Y) == 0 670 /// (X & Y) != Y ---> (~X & Y) != 0 671 /// 672 /// This may be profitable if the target has a bitwise and-not operation that 673 /// sets comparison flags. A target may want to limit the transformation based 674 /// on the type of Y or if Y is a constant. 675 /// 676 /// Note that the transform will not occur if Y is known to be a power-of-2 677 /// because a mask and compare of a single bit can be handled by inverting the 678 /// predicate, for example: 679 /// (X & 8) == 8 ---> (X & 8) != 0 hasAndNotCompare(SDValue Y)680 virtual bool hasAndNotCompare(SDValue Y) const { 681 return false; 682 } 683 684 /// Return true if the target has a bitwise and-not operation: 685 /// X = ~A & B 686 /// This can be used to simplify select or other instructions. hasAndNot(SDValue X)687 virtual bool hasAndNot(SDValue X) const { 688 // If the target has the more complex version of this operation, assume that 689 // it has this operation too. 690 return hasAndNotCompare(X); 691 } 692 693 /// Return true if the target has a bit-test instruction: 694 /// (X & (1 << Y)) ==/!= 0 695 /// This knowledge can be used to prevent breaking the pattern, 696 /// or creating it if it could be recognized. hasBitTest(SDValue X,SDValue Y)697 virtual bool hasBitTest(SDValue X, SDValue Y) const { return false; } 698 699 /// There are two ways to clear extreme bits (either low or high): 700 /// Mask: x & (-1 << y) (the instcombine canonical form) 701 /// Shifts: x >> y << y 702 /// Return true if the variant with 2 variable shifts is preferred. 703 /// Return false if there is no preference. shouldFoldMaskToVariableShiftPair(SDValue X)704 virtual bool shouldFoldMaskToVariableShiftPair(SDValue X) const { 705 // By default, let's assume that no one prefers shifts. 706 return false; 707 } 708 709 /// Return true if it is profitable to fold a pair of shifts into a mask. 710 /// This is usually true on most targets. But some targets, like Thumb1, 711 /// have immediate shift instructions, but no immediate "and" instruction; 712 /// this makes the fold unprofitable. shouldFoldConstantShiftPairToMask(const SDNode * N,CombineLevel Level)713 virtual bool shouldFoldConstantShiftPairToMask(const SDNode *N, 714 CombineLevel Level) const { 715 return true; 716 } 717 718 /// Should we tranform the IR-optimal check for whether given truncation 719 /// down into KeptBits would be truncating or not: 720 /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits) 721 /// Into it's more traditional form: 722 /// ((%x << C) a>> C) dstcond %x 723 /// Return true if we should transform. 724 /// Return false if there is no preference. shouldTransformSignedTruncationCheck(EVT XVT,unsigned KeptBits)725 virtual bool shouldTransformSignedTruncationCheck(EVT XVT, 726 unsigned KeptBits) const { 727 // By default, let's assume that no one prefers shifts. 728 return false; 729 } 730 731 /// Given the pattern 732 /// (X & (C l>>/<< Y)) ==/!= 0 733 /// return true if it should be transformed into: 734 /// ((X <</l>> Y) & C) ==/!= 0 735 /// WARNING: if 'X' is a constant, the fold may deadlock! 736 /// FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat() 737 /// here because it can end up being not linked in. shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X,ConstantSDNode * XC,ConstantSDNode * CC,SDValue Y,unsigned OldShiftOpcode,unsigned NewShiftOpcode,SelectionDAG & DAG)738 virtual bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd( 739 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, 740 unsigned OldShiftOpcode, unsigned NewShiftOpcode, 741 SelectionDAG &DAG) const { 742 if (hasBitTest(X, Y)) { 743 // One interesting pattern that we'd want to form is 'bit test': 744 // ((1 << Y) & C) ==/!= 0 745 // But we also need to be careful not to try to reverse that fold. 746 747 // Is this '1 << Y' ? 748 if (OldShiftOpcode == ISD::SHL && CC->isOne()) 749 return false; // Keep the 'bit test' pattern. 750 751 // Will it be '1 << Y' after the transform ? 752 if (XC && NewShiftOpcode == ISD::SHL && XC->isOne()) 753 return true; // Do form the 'bit test' pattern. 754 } 755 756 // If 'X' is a constant, and we transform, then we will immediately 757 // try to undo the fold, thus causing endless combine loop. 758 // So by default, let's assume everyone prefers the fold 759 // iff 'X' is not a constant. 760 return !XC; 761 } 762 763 /// These two forms are equivalent: 764 /// sub %y, (xor %x, -1) 765 /// add (add %x, 1), %y 766 /// The variant with two add's is IR-canonical. 767 /// Some targets may prefer one to the other. preferIncOfAddToSubOfNot(EVT VT)768 virtual bool preferIncOfAddToSubOfNot(EVT VT) const { 769 // By default, let's assume that everyone prefers the form with two add's. 770 return true; 771 } 772 773 /// Return true if the target wants to use the optimization that 774 /// turns ext(promotableInst1(...(promotableInstN(load)))) into 775 /// promotedInst1(...(promotedInstN(ext(load)))). enableExtLdPromotion()776 bool enableExtLdPromotion() const { return EnableExtLdPromotion; } 777 778 /// Return true if the target can combine store(extractelement VectorTy, 779 /// Idx). 780 /// \p Cost[out] gives the cost of that transformation when this is true. canCombineStoreAndExtract(Type * VectorTy,Value * Idx,unsigned & Cost)781 virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, 782 unsigned &Cost) const { 783 return false; 784 } 785 786 /// Return true if inserting a scalar into a variable element of an undef 787 /// vector is more efficiently handled by splatting the scalar instead. shouldSplatInsEltVarIndex(EVT)788 virtual bool shouldSplatInsEltVarIndex(EVT) const { 789 return false; 790 } 791 792 /// Return true if target always benefits from combining into FMA for a 793 /// given value type. This must typically return false on targets where FMA 794 /// takes more cycles to execute than FADD. enableAggressiveFMAFusion(EVT VT)795 virtual bool enableAggressiveFMAFusion(EVT VT) const { 796 return false; 797 } 798 799 /// Return the ValueType of the result of SETCC operations. 800 virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 801 EVT VT) const; 802 803 /// Return the ValueType for comparison libcalls. Comparions libcalls include 804 /// floating point comparion calls, and Ordered/Unordered check calls on 805 /// floating point numbers. 806 virtual 807 MVT::SimpleValueType getCmpLibcallReturnType() const; 808 809 /// For targets without i1 registers, this gives the nature of the high-bits 810 /// of boolean values held in types wider than i1. 811 /// 812 /// "Boolean values" are special true/false values produced by nodes like 813 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. 814 /// Not to be confused with general values promoted from i1. Some cpus 815 /// distinguish between vectors of boolean and scalars; the isVec parameter 816 /// selects between the two kinds. For example on X86 a scalar boolean should 817 /// be zero extended from i1, while the elements of a vector of booleans 818 /// should be sign extended from i1. 819 /// 820 /// Some cpus also treat floating point types the same way as they treat 821 /// vectors instead of the way they treat scalars. getBooleanContents(bool isVec,bool isFloat)822 BooleanContent getBooleanContents(bool isVec, bool isFloat) const { 823 if (isVec) 824 return BooleanVectorContents; 825 return isFloat ? BooleanFloatContents : BooleanContents; 826 } 827 getBooleanContents(EVT Type)828 BooleanContent getBooleanContents(EVT Type) const { 829 return getBooleanContents(Type.isVector(), Type.isFloatingPoint()); 830 } 831 832 /// Return target scheduling preference. getSchedulingPreference()833 Sched::Preference getSchedulingPreference() const { 834 return SchedPreferenceInfo; 835 } 836 837 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics 838 /// for different nodes. This function returns the preference (or none) for 839 /// the given node. getSchedulingPreference(SDNode *)840 virtual Sched::Preference getSchedulingPreference(SDNode *) const { 841 return Sched::None; 842 } 843 844 /// Return the register class that should be used for the specified value 845 /// type. 846 virtual const TargetRegisterClass *getRegClassFor(MVT VT, bool isDivergent = false) const { 847 (void)isDivergent; 848 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 849 assert(RC && "This value type is not natively supported!"); 850 return RC; 851 } 852 853 /// Allows target to decide about the register class of the 854 /// specific value that is live outside the defining block. 855 /// Returns true if the value needs uniform register class. requiresUniformRegister(MachineFunction & MF,const Value *)856 virtual bool requiresUniformRegister(MachineFunction &MF, 857 const Value *) const { 858 return false; 859 } 860 861 /// Return the 'representative' register class for the specified value 862 /// type. 863 /// 864 /// The 'representative' register class is the largest legal super-reg 865 /// register class for the register class of the value type. For example, on 866 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep 867 /// register class is GR64 on x86_64. getRepRegClassFor(MVT VT)868 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { 869 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy]; 870 return RC; 871 } 872 873 /// Return the cost of the 'representative' register class for the specified 874 /// value type. getRepRegClassCostFor(MVT VT)875 virtual uint8_t getRepRegClassCostFor(MVT VT) const { 876 return RepRegClassCostForVT[VT.SimpleTy]; 877 } 878 879 /// Return true if SHIFT instructions should be expanded to SHIFT_PARTS 880 /// instructions, and false if a library call is preferred (e.g for code-size 881 /// reasons). shouldExpandShift(SelectionDAG & DAG,SDNode * N)882 virtual bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const { 883 return true; 884 } 885 886 /// Return true if the target has native support for the specified value type. 887 /// This means that it has a register that directly holds it without 888 /// promotions or expansions. isTypeLegal(EVT VT)889 bool isTypeLegal(EVT VT) const { 890 assert(!VT.isSimple() || 891 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); 892 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr; 893 } 894 895 class ValueTypeActionImpl { 896 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum 897 /// that indicates how instruction selection should deal with the type. 898 LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE]; 899 900 public: ValueTypeActionImpl()901 ValueTypeActionImpl() { 902 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions), 903 TypeLegal); 904 } 905 getTypeAction(MVT VT)906 LegalizeTypeAction getTypeAction(MVT VT) const { 907 return ValueTypeActions[VT.SimpleTy]; 908 } 909 setTypeAction(MVT VT,LegalizeTypeAction Action)910 void setTypeAction(MVT VT, LegalizeTypeAction Action) { 911 ValueTypeActions[VT.SimpleTy] = Action; 912 } 913 }; 914 getValueTypeActions()915 const ValueTypeActionImpl &getValueTypeActions() const { 916 return ValueTypeActions; 917 } 918 919 /// Return how we should legalize values of this type, either it is already 920 /// legal (return 'Legal') or we need to promote it to a larger type (return 921 /// 'Promote'), or we need to expand it into multiple registers of smaller 922 /// integer type (return 'Expand'). 'Custom' is not an option. getTypeAction(LLVMContext & Context,EVT VT)923 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const { 924 return getTypeConversion(Context, VT).first; 925 } getTypeAction(MVT VT)926 LegalizeTypeAction getTypeAction(MVT VT) const { 927 return ValueTypeActions.getTypeAction(VT); 928 } 929 930 /// For types supported by the target, this is an identity function. For 931 /// types that must be promoted to larger types, this returns the larger type 932 /// to promote to. For integer types that are larger than the largest integer 933 /// register, this contains one step in the expansion to get to the smaller 934 /// register. For illegal floating point types, this returns the integer type 935 /// to transform to. getTypeToTransformTo(LLVMContext & Context,EVT VT)936 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { 937 return getTypeConversion(Context, VT).second; 938 } 939 940 /// For types supported by the target, this is an identity function. For 941 /// types that must be expanded (i.e. integer types that are larger than the 942 /// largest integer register or illegal floating point types), this returns 943 /// the largest legal type it will be expanded to. getTypeToExpandTo(LLVMContext & Context,EVT VT)944 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { 945 assert(!VT.isVector()); 946 while (true) { 947 switch (getTypeAction(Context, VT)) { 948 case TypeLegal: 949 return VT; 950 case TypeExpandInteger: 951 VT = getTypeToTransformTo(Context, VT); 952 break; 953 default: 954 llvm_unreachable("Type is not legal nor is it to be expanded!"); 955 } 956 } 957 } 958 959 /// Vector types are broken down into some number of legal first class types. 960 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8 961 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64 962 /// turns into 4 EVT::i32 values with both PPC and X86. 963 /// 964 /// This method returns the number of registers needed, and the VT for each 965 /// register. It also returns the VT and quantity of the intermediate values 966 /// before they are promoted/expanded. 967 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 968 EVT &IntermediateVT, 969 unsigned &NumIntermediates, 970 MVT &RegisterVT) const; 971 972 /// Certain targets such as MIPS require that some types such as vectors are 973 /// always broken down into scalars in some contexts. This occurs even if the 974 /// vector type is legal. getVectorTypeBreakdownForCallingConv(LLVMContext & Context,CallingConv::ID CC,EVT VT,EVT & IntermediateVT,unsigned & NumIntermediates,MVT & RegisterVT)975 virtual unsigned getVectorTypeBreakdownForCallingConv( 976 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 977 unsigned &NumIntermediates, MVT &RegisterVT) const { 978 return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates, 979 RegisterVT); 980 } 981 982 struct IntrinsicInfo { 983 unsigned opc = 0; // target opcode 984 EVT memVT; // memory VT 985 986 // value representing memory location 987 PointerUnion<const Value *, const PseudoSourceValue *> ptrVal; 988 989 int offset = 0; // offset off of ptrVal 990 uint64_t size = 0; // the size of the memory location 991 // (taken from memVT if zero) 992 MaybeAlign align = Align(1); // alignment 993 994 MachineMemOperand::Flags flags = MachineMemOperand::MONone; 995 IntrinsicInfo() = default; 996 }; 997 998 /// Given an intrinsic, checks if on the target the intrinsic will need to map 999 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns 1000 /// true and store the intrinsic information into the IntrinsicInfo that was 1001 /// passed to the function. getTgtMemIntrinsic(IntrinsicInfo &,const CallInst &,MachineFunction &,unsigned)1002 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 1003 MachineFunction &, 1004 unsigned /*Intrinsic*/) const { 1005 return false; 1006 } 1007 1008 /// Returns true if the target can instruction select the specified FP 1009 /// immediate natively. If false, the legalizer will materialize the FP 1010 /// immediate as a load from a constant pool. 1011 virtual bool isFPImmLegal(const APFloat & /*Imm*/, EVT /*VT*/, 1012 bool ForCodeSize = false) const { 1013 return false; 1014 } 1015 1016 /// Targets can use this to indicate that they only support *some* 1017 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a 1018 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be 1019 /// legal. isShuffleMaskLegal(ArrayRef<int>,EVT)1020 virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const { 1021 return true; 1022 } 1023 1024 /// Returns true if the operation can trap for the value type. 1025 /// 1026 /// VT must be a legal type. By default, we optimistically assume most 1027 /// operations don't trap except for integer divide and remainder. 1028 virtual bool canOpTrap(unsigned Op, EVT VT) const; 1029 1030 /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there 1031 /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a 1032 /// constant pool entry. isVectorClearMaskLegal(ArrayRef<int>,EVT)1033 virtual bool isVectorClearMaskLegal(ArrayRef<int> /*Mask*/, 1034 EVT /*VT*/) const { 1035 return false; 1036 } 1037 1038 /// Return how this operation should be treated: either it is legal, needs to 1039 /// be promoted to a larger size, needs to be expanded to some other code 1040 /// sequence, or the target has a custom expander for it. getOperationAction(unsigned Op,EVT VT)1041 LegalizeAction getOperationAction(unsigned Op, EVT VT) const { 1042 if (VT.isExtended()) return Expand; 1043 // If a target-specific SDNode requires legalization, require the target 1044 // to provide custom legalization for it. 1045 if (Op >= array_lengthof(OpActions[0])) return Custom; 1046 return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op]; 1047 } 1048 1049 /// Custom method defined by each target to indicate if an operation which 1050 /// may require a scale is supported natively by the target. 1051 /// If not, the operation is illegal. isSupportedFixedPointOperation(unsigned Op,EVT VT,unsigned Scale)1052 virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT, 1053 unsigned Scale) const { 1054 return false; 1055 } 1056 1057 /// Some fixed point operations may be natively supported by the target but 1058 /// only for specific scales. This method allows for checking 1059 /// if the width is supported by the target for a given operation that may 1060 /// depend on scale. getFixedPointOperationAction(unsigned Op,EVT VT,unsigned Scale)1061 LegalizeAction getFixedPointOperationAction(unsigned Op, EVT VT, 1062 unsigned Scale) const { 1063 auto Action = getOperationAction(Op, VT); 1064 if (Action != Legal) 1065 return Action; 1066 1067 // This operation is supported in this type but may only work on specific 1068 // scales. 1069 bool Supported; 1070 switch (Op) { 1071 default: 1072 llvm_unreachable("Unexpected fixed point operation."); 1073 case ISD::SMULFIX: 1074 case ISD::SMULFIXSAT: 1075 case ISD::UMULFIX: 1076 case ISD::UMULFIXSAT: 1077 case ISD::SDIVFIX: 1078 case ISD::SDIVFIXSAT: 1079 case ISD::UDIVFIX: 1080 case ISD::UDIVFIXSAT: 1081 Supported = isSupportedFixedPointOperation(Op, VT, Scale); 1082 break; 1083 } 1084 1085 return Supported ? Action : Expand; 1086 } 1087 1088 // If Op is a strict floating-point operation, return the result 1089 // of getOperationAction for the equivalent non-strict operation. getStrictFPOperationAction(unsigned Op,EVT VT)1090 LegalizeAction getStrictFPOperationAction(unsigned Op, EVT VT) const { 1091 unsigned EqOpc; 1092 switch (Op) { 1093 default: llvm_unreachable("Unexpected FP pseudo-opcode"); 1094 #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \ 1095 case ISD::STRICT_##DAGN: EqOpc = ISD::DAGN; break; 1096 #define CMP_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \ 1097 case ISD::STRICT_##DAGN: EqOpc = ISD::SETCC; break; 1098 #include "llvm/IR/ConstrainedOps.def" 1099 } 1100 1101 return getOperationAction(EqOpc, VT); 1102 } 1103 1104 /// Return true if the specified operation is legal on this target or can be 1105 /// made legal with custom lowering. This is used to help guide high-level 1106 /// lowering decisions. LegalOnly is an optional convenience for code paths 1107 /// traversed pre and post legalisation. 1108 bool isOperationLegalOrCustom(unsigned Op, EVT VT, 1109 bool LegalOnly = false) const { 1110 if (LegalOnly) 1111 return isOperationLegal(Op, VT); 1112 1113 return (VT == MVT::Other || isTypeLegal(VT)) && 1114 (getOperationAction(Op, VT) == Legal || 1115 getOperationAction(Op, VT) == Custom); 1116 } 1117 1118 /// Return true if the specified operation is legal on this target or can be 1119 /// made legal using promotion. This is used to help guide high-level lowering 1120 /// decisions. LegalOnly is an optional convenience for code paths traversed 1121 /// pre and post legalisation. 1122 bool isOperationLegalOrPromote(unsigned Op, EVT VT, 1123 bool LegalOnly = false) const { 1124 if (LegalOnly) 1125 return isOperationLegal(Op, VT); 1126 1127 return (VT == MVT::Other || isTypeLegal(VT)) && 1128 (getOperationAction(Op, VT) == Legal || 1129 getOperationAction(Op, VT) == Promote); 1130 } 1131 1132 /// Return true if the specified operation is legal on this target or can be 1133 /// made legal with custom lowering or using promotion. This is used to help 1134 /// guide high-level lowering decisions. LegalOnly is an optional convenience 1135 /// for code paths traversed pre and post legalisation. 1136 bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT, 1137 bool LegalOnly = false) const { 1138 if (LegalOnly) 1139 return isOperationLegal(Op, VT); 1140 1141 return (VT == MVT::Other || isTypeLegal(VT)) && 1142 (getOperationAction(Op, VT) == Legal || 1143 getOperationAction(Op, VT) == Custom || 1144 getOperationAction(Op, VT) == Promote); 1145 } 1146 1147 /// Return true if the operation uses custom lowering, regardless of whether 1148 /// the type is legal or not. isOperationCustom(unsigned Op,EVT VT)1149 bool isOperationCustom(unsigned Op, EVT VT) const { 1150 return getOperationAction(Op, VT) == Custom; 1151 } 1152 1153 /// Return true if lowering to a jump table is allowed. areJTsAllowed(const Function * Fn)1154 virtual bool areJTsAllowed(const Function *Fn) const { 1155 if (Fn->getFnAttribute("no-jump-tables").getValueAsBool()) 1156 return false; 1157 1158 return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 1159 isOperationLegalOrCustom(ISD::BRIND, MVT::Other); 1160 } 1161 1162 /// Check whether the range [Low,High] fits in a machine word. rangeFitsInWord(const APInt & Low,const APInt & High,const DataLayout & DL)1163 bool rangeFitsInWord(const APInt &Low, const APInt &High, 1164 const DataLayout &DL) const { 1165 // FIXME: Using the pointer type doesn't seem ideal. 1166 uint64_t BW = DL.getIndexSizeInBits(0u); 1167 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1; 1168 return Range <= BW; 1169 } 1170 1171 /// Return true if lowering to a jump table is suitable for a set of case 1172 /// clusters which may contain \p NumCases cases, \p Range range of values. 1173 virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, 1174 uint64_t Range, ProfileSummaryInfo *PSI, 1175 BlockFrequencyInfo *BFI) const; 1176 1177 /// Return true if lowering to a bit test is suitable for a set of case 1178 /// clusters which contains \p NumDests unique destinations, \p Low and 1179 /// \p High as its lowest and highest case values, and expects \p NumCmps 1180 /// case value comparisons. Check if the number of destinations, comparison 1181 /// metric, and range are all suitable. isSuitableForBitTests(unsigned NumDests,unsigned NumCmps,const APInt & Low,const APInt & High,const DataLayout & DL)1182 bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, 1183 const APInt &Low, const APInt &High, 1184 const DataLayout &DL) const { 1185 // FIXME: I don't think NumCmps is the correct metric: a single case and a 1186 // range of cases both require only one branch to lower. Just looking at the 1187 // number of clusters and destinations should be enough to decide whether to 1188 // build bit tests. 1189 1190 // To lower a range with bit tests, the range must fit the bitwidth of a 1191 // machine word. 1192 if (!rangeFitsInWord(Low, High, DL)) 1193 return false; 1194 1195 // Decide whether it's profitable to lower this range with bit tests. Each 1196 // destination requires a bit test and branch, and there is an overall range 1197 // check branch. For a small number of clusters, separate comparisons might 1198 // be cheaper, and for many destinations, splitting the range might be 1199 // better. 1200 return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) || 1201 (NumDests == 3 && NumCmps >= 6); 1202 } 1203 1204 /// Return true if the specified operation is illegal on this target or 1205 /// unlikely to be made legal with custom lowering. This is used to help guide 1206 /// high-level lowering decisions. isOperationExpand(unsigned Op,EVT VT)1207 bool isOperationExpand(unsigned Op, EVT VT) const { 1208 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand); 1209 } 1210 1211 /// Return true if the specified operation is legal on this target. isOperationLegal(unsigned Op,EVT VT)1212 bool isOperationLegal(unsigned Op, EVT VT) const { 1213 return (VT == MVT::Other || isTypeLegal(VT)) && 1214 getOperationAction(Op, VT) == Legal; 1215 } 1216 1217 /// Return how this load with extension should be treated: either it is legal, 1218 /// needs to be promoted to a larger size, needs to be expanded to some other 1219 /// code sequence, or the target has a custom expander for it. getLoadExtAction(unsigned ExtType,EVT ValVT,EVT MemVT)1220 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, 1221 EVT MemVT) const { 1222 if (ValVT.isExtended() || MemVT.isExtended()) return Expand; 1223 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy; 1224 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy; 1225 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE && 1226 MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!"); 1227 unsigned Shift = 4 * ExtType; 1228 return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf); 1229 } 1230 1231 /// Return true if the specified load with extension is legal on this target. isLoadExtLegal(unsigned ExtType,EVT ValVT,EVT MemVT)1232 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const { 1233 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal; 1234 } 1235 1236 /// Return true if the specified load with extension is legal or custom 1237 /// on this target. isLoadExtLegalOrCustom(unsigned ExtType,EVT ValVT,EVT MemVT)1238 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const { 1239 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal || 1240 getLoadExtAction(ExtType, ValVT, MemVT) == Custom; 1241 } 1242 1243 /// Return how this store with truncation should be treated: either it is 1244 /// legal, needs to be promoted to a larger size, needs to be expanded to some 1245 /// other code sequence, or the target has a custom expander for it. getTruncStoreAction(EVT ValVT,EVT MemVT)1246 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const { 1247 if (ValVT.isExtended() || MemVT.isExtended()) return Expand; 1248 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy; 1249 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy; 1250 assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE && 1251 "Table isn't big enough!"); 1252 return TruncStoreActions[ValI][MemI]; 1253 } 1254 1255 /// Return true if the specified store with truncation is legal on this 1256 /// target. isTruncStoreLegal(EVT ValVT,EVT MemVT)1257 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const { 1258 return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal; 1259 } 1260 1261 /// Return true if the specified store with truncation has solution on this 1262 /// target. isTruncStoreLegalOrCustom(EVT ValVT,EVT MemVT)1263 bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const { 1264 return isTypeLegal(ValVT) && 1265 (getTruncStoreAction(ValVT, MemVT) == Legal || 1266 getTruncStoreAction(ValVT, MemVT) == Custom); 1267 } 1268 1269 /// Return how the indexed load should be treated: either it is legal, needs 1270 /// to be promoted to a larger size, needs to be expanded to some other code 1271 /// sequence, or the target has a custom expander for it. getIndexedLoadAction(unsigned IdxMode,MVT VT)1272 LegalizeAction getIndexedLoadAction(unsigned IdxMode, MVT VT) const { 1273 return getIndexedModeAction(IdxMode, VT, IMAB_Load); 1274 } 1275 1276 /// Return true if the specified indexed load is legal on this target. isIndexedLoadLegal(unsigned IdxMode,EVT VT)1277 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const { 1278 return VT.isSimple() && 1279 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal || 1280 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom); 1281 } 1282 1283 /// Return how the indexed store should be treated: either it is legal, needs 1284 /// to be promoted to a larger size, needs to be expanded to some other code 1285 /// sequence, or the target has a custom expander for it. getIndexedStoreAction(unsigned IdxMode,MVT VT)1286 LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const { 1287 return getIndexedModeAction(IdxMode, VT, IMAB_Store); 1288 } 1289 1290 /// Return true if the specified indexed load is legal on this target. isIndexedStoreLegal(unsigned IdxMode,EVT VT)1291 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const { 1292 return VT.isSimple() && 1293 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal || 1294 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom); 1295 } 1296 1297 /// Return how the indexed load should be treated: either it is legal, needs 1298 /// to be promoted to a larger size, needs to be expanded to some other code 1299 /// sequence, or the target has a custom expander for it. getIndexedMaskedLoadAction(unsigned IdxMode,MVT VT)1300 LegalizeAction getIndexedMaskedLoadAction(unsigned IdxMode, MVT VT) const { 1301 return getIndexedModeAction(IdxMode, VT, IMAB_MaskedLoad); 1302 } 1303 1304 /// Return true if the specified indexed load is legal on this target. isIndexedMaskedLoadLegal(unsigned IdxMode,EVT VT)1305 bool isIndexedMaskedLoadLegal(unsigned IdxMode, EVT VT) const { 1306 return VT.isSimple() && 1307 (getIndexedMaskedLoadAction(IdxMode, VT.getSimpleVT()) == Legal || 1308 getIndexedMaskedLoadAction(IdxMode, VT.getSimpleVT()) == Custom); 1309 } 1310 1311 /// Return how the indexed store should be treated: either it is legal, needs 1312 /// to be promoted to a larger size, needs to be expanded to some other code 1313 /// sequence, or the target has a custom expander for it. getIndexedMaskedStoreAction(unsigned IdxMode,MVT VT)1314 LegalizeAction getIndexedMaskedStoreAction(unsigned IdxMode, MVT VT) const { 1315 return getIndexedModeAction(IdxMode, VT, IMAB_MaskedStore); 1316 } 1317 1318 /// Return true if the specified indexed load is legal on this target. isIndexedMaskedStoreLegal(unsigned IdxMode,EVT VT)1319 bool isIndexedMaskedStoreLegal(unsigned IdxMode, EVT VT) const { 1320 return VT.isSimple() && 1321 (getIndexedMaskedStoreAction(IdxMode, VT.getSimpleVT()) == Legal || 1322 getIndexedMaskedStoreAction(IdxMode, VT.getSimpleVT()) == Custom); 1323 } 1324 1325 /// Returns true if the index type for a masked gather/scatter requires 1326 /// extending shouldExtendGSIndex(EVT VT,EVT & EltTy)1327 virtual bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const { return false; } 1328 1329 // Returns true if VT is a legal index type for masked gathers/scatters 1330 // on this target shouldRemoveExtendFromGSIndex(EVT VT)1331 virtual bool shouldRemoveExtendFromGSIndex(EVT VT) const { return false; } 1332 1333 /// Return how the condition code should be treated: either it is legal, needs 1334 /// to be expanded to some other code sequence, or the target has a custom 1335 /// expander for it. 1336 LegalizeAction getCondCodeAction(ISD::CondCode CC,MVT VT)1337 getCondCodeAction(ISD::CondCode CC, MVT VT) const { 1338 assert((unsigned)CC < array_lengthof(CondCodeActions) && 1339 ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) && 1340 "Table isn't big enough!"); 1341 // See setCondCodeAction for how this is encoded. 1342 uint32_t Shift = 4 * (VT.SimpleTy & 0x7); 1343 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3]; 1344 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF); 1345 assert(Action != Promote && "Can't promote condition code!"); 1346 return Action; 1347 } 1348 1349 /// Return true if the specified condition code is legal on this target. isCondCodeLegal(ISD::CondCode CC,MVT VT)1350 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { 1351 return getCondCodeAction(CC, VT) == Legal; 1352 } 1353 1354 /// Return true if the specified condition code is legal or custom on this 1355 /// target. isCondCodeLegalOrCustom(ISD::CondCode CC,MVT VT)1356 bool isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) const { 1357 return getCondCodeAction(CC, VT) == Legal || 1358 getCondCodeAction(CC, VT) == Custom; 1359 } 1360 1361 /// If the action for this operation is to promote, this method returns the 1362 /// ValueType to promote to. getTypeToPromoteTo(unsigned Op,MVT VT)1363 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const { 1364 assert(getOperationAction(Op, VT) == Promote && 1365 "This operation isn't promoted!"); 1366 1367 // See if this has an explicit type specified. 1368 std::map<std::pair<unsigned, MVT::SimpleValueType>, 1369 MVT::SimpleValueType>::const_iterator PTTI = 1370 PromoteToType.find(std::make_pair(Op, VT.SimpleTy)); 1371 if (PTTI != PromoteToType.end()) return PTTI->second; 1372 1373 assert((VT.isInteger() || VT.isFloatingPoint()) && 1374 "Cannot autopromote this type, add it with AddPromotedToType."); 1375 1376 MVT NVT = VT; 1377 do { 1378 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1); 1379 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && 1380 "Didn't find type to promote to!"); 1381 } while (!isTypeLegal(NVT) || 1382 getOperationAction(Op, NVT) == Promote); 1383 return NVT; 1384 } 1385 1386 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM 1387 /// operations except for the pointer size. If AllowUnknown is true, this 1388 /// will return MVT::Other for types with no EVT counterpart (e.g. structs), 1389 /// otherwise it will assert. 1390 EVT getValueType(const DataLayout &DL, Type *Ty, 1391 bool AllowUnknown = false) const { 1392 // Lower scalar pointers to native pointer types. 1393 if (auto *PTy = dyn_cast<PointerType>(Ty)) 1394 return getPointerTy(DL, PTy->getAddressSpace()); 1395 1396 if (auto *VTy = dyn_cast<VectorType>(Ty)) { 1397 Type *EltTy = VTy->getElementType(); 1398 // Lower vectors of pointers to native pointer types. 1399 if (auto *PTy = dyn_cast<PointerType>(EltTy)) { 1400 EVT PointerTy(getPointerTy(DL, PTy->getAddressSpace())); 1401 EltTy = PointerTy.getTypeForEVT(Ty->getContext()); 1402 } 1403 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(EltTy, false), 1404 VTy->getElementCount()); 1405 } 1406 1407 return EVT::getEVT(Ty, AllowUnknown); 1408 } 1409 1410 EVT getMemValueType(const DataLayout &DL, Type *Ty, 1411 bool AllowUnknown = false) const { 1412 // Lower scalar pointers to native pointer types. 1413 if (PointerType *PTy = dyn_cast<PointerType>(Ty)) 1414 return getPointerMemTy(DL, PTy->getAddressSpace()); 1415 else if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1416 Type *Elm = VTy->getElementType(); 1417 if (PointerType *PT = dyn_cast<PointerType>(Elm)) { 1418 EVT PointerTy(getPointerMemTy(DL, PT->getAddressSpace())); 1419 Elm = PointerTy.getTypeForEVT(Ty->getContext()); 1420 } 1421 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false), 1422 VTy->getElementCount()); 1423 } 1424 1425 return getValueType(DL, Ty, AllowUnknown); 1426 } 1427 1428 1429 /// Return the MVT corresponding to this LLVM type. See getValueType. 1430 MVT getSimpleValueType(const DataLayout &DL, Type *Ty, 1431 bool AllowUnknown = false) const { 1432 return getValueType(DL, Ty, AllowUnknown).getSimpleVT(); 1433 } 1434 1435 /// Return the desired alignment for ByVal or InAlloca aggregate function 1436 /// arguments in the caller parameter area. This is the actual alignment, not 1437 /// its logarithm. 1438 virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const; 1439 1440 /// Return the type of registers that this ValueType will eventually require. getRegisterType(MVT VT)1441 MVT getRegisterType(MVT VT) const { 1442 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)); 1443 return RegisterTypeForVT[VT.SimpleTy]; 1444 } 1445 1446 /// Return the type of registers that this ValueType will eventually require. getRegisterType(LLVMContext & Context,EVT VT)1447 MVT getRegisterType(LLVMContext &Context, EVT VT) const { 1448 if (VT.isSimple()) { 1449 assert((unsigned)VT.getSimpleVT().SimpleTy < 1450 array_lengthof(RegisterTypeForVT)); 1451 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy]; 1452 } 1453 if (VT.isVector()) { 1454 EVT VT1; 1455 MVT RegisterVT; 1456 unsigned NumIntermediates; 1457 (void)getVectorTypeBreakdown(Context, VT, VT1, 1458 NumIntermediates, RegisterVT); 1459 return RegisterVT; 1460 } 1461 if (VT.isInteger()) { 1462 return getRegisterType(Context, getTypeToTransformTo(Context, VT)); 1463 } 1464 llvm_unreachable("Unsupported extended type!"); 1465 } 1466 1467 /// Return the number of registers that this ValueType will eventually 1468 /// require. 1469 /// 1470 /// This is one for any types promoted to live in larger registers, but may be 1471 /// more than one for types (like i64) that are split into pieces. For types 1472 /// like i140, which are first promoted then expanded, it is the number of 1473 /// registers needed to hold all the bits of the original type. For an i140 1474 /// on a 32 bit machine this means 5 registers. getNumRegisters(LLVMContext & Context,EVT VT)1475 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const { 1476 if (VT.isSimple()) { 1477 assert((unsigned)VT.getSimpleVT().SimpleTy < 1478 array_lengthof(NumRegistersForVT)); 1479 return NumRegistersForVT[VT.getSimpleVT().SimpleTy]; 1480 } 1481 if (VT.isVector()) { 1482 EVT VT1; 1483 MVT VT2; 1484 unsigned NumIntermediates; 1485 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2); 1486 } 1487 if (VT.isInteger()) { 1488 unsigned BitWidth = VT.getSizeInBits(); 1489 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); 1490 return (BitWidth + RegWidth - 1) / RegWidth; 1491 } 1492 llvm_unreachable("Unsupported extended type!"); 1493 } 1494 1495 /// Certain combinations of ABIs, Targets and features require that types 1496 /// are legal for some operations and not for other operations. 1497 /// For MIPS all vector types must be passed through the integer register set. getRegisterTypeForCallingConv(LLVMContext & Context,CallingConv::ID CC,EVT VT)1498 virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, 1499 CallingConv::ID CC, EVT VT) const { 1500 return getRegisterType(Context, VT); 1501 } 1502 1503 /// Certain targets require unusual breakdowns of certain types. For MIPS, 1504 /// this occurs when a vector type is used, as vector are passed through the 1505 /// integer register set. getNumRegistersForCallingConv(LLVMContext & Context,CallingConv::ID CC,EVT VT)1506 virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, 1507 CallingConv::ID CC, 1508 EVT VT) const { 1509 return getNumRegisters(Context, VT); 1510 } 1511 1512 /// Certain targets have context senstive alignment requirements, where one 1513 /// type has the alignment requirement of another type. getABIAlignmentForCallingConv(Type * ArgTy,DataLayout DL)1514 virtual Align getABIAlignmentForCallingConv(Type *ArgTy, 1515 DataLayout DL) const { 1516 return DL.getABITypeAlign(ArgTy); 1517 } 1518 1519 /// If true, then instruction selection should seek to shrink the FP constant 1520 /// of the specified type to a smaller type in order to save space and / or 1521 /// reduce runtime. ShouldShrinkFPConstant(EVT)1522 virtual bool ShouldShrinkFPConstant(EVT) const { return true; } 1523 1524 /// Return true if it is profitable to reduce a load to a smaller type. 1525 /// Example: (i16 (trunc (i32 (load x))) -> i16 load x shouldReduceLoadWidth(SDNode * Load,ISD::LoadExtType ExtTy,EVT NewVT)1526 virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, 1527 EVT NewVT) const { 1528 // By default, assume that it is cheaper to extract a subvector from a wide 1529 // vector load rather than creating multiple narrow vector loads. 1530 if (NewVT.isVector() && !Load->hasOneUse()) 1531 return false; 1532 1533 return true; 1534 } 1535 1536 /// When splitting a value of the specified type into parts, does the Lo 1537 /// or Hi part come first? This usually follows the endianness, except 1538 /// for ppcf128, where the Hi part always comes first. hasBigEndianPartOrdering(EVT VT,const DataLayout & DL)1539 bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const { 1540 return DL.isBigEndian() || VT == MVT::ppcf128; 1541 } 1542 1543 /// If true, the target has custom DAG combine transformations that it can 1544 /// perform for the specified node. hasTargetDAGCombine(ISD::NodeType NT)1545 bool hasTargetDAGCombine(ISD::NodeType NT) const { 1546 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 1547 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7)); 1548 } 1549 getGatherAllAliasesMaxDepth()1550 unsigned getGatherAllAliasesMaxDepth() const { 1551 return GatherAllAliasesMaxDepth; 1552 } 1553 1554 /// Returns the size of the platform's va_list object. getVaListSizeInBits(const DataLayout & DL)1555 virtual unsigned getVaListSizeInBits(const DataLayout &DL) const { 1556 return getPointerTy(DL).getSizeInBits(); 1557 } 1558 1559 /// Get maximum # of store operations permitted for llvm.memset 1560 /// 1561 /// This function returns the maximum number of store operations permitted 1562 /// to replace a call to llvm.memset. The value is set by the target at the 1563 /// performance threshold for such a replacement. If OptSize is true, 1564 /// return the limit for functions that have OptSize attribute. getMaxStoresPerMemset(bool OptSize)1565 unsigned getMaxStoresPerMemset(bool OptSize) const { 1566 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset; 1567 } 1568 1569 /// Get maximum # of store operations permitted for llvm.memcpy 1570 /// 1571 /// This function returns the maximum number of store operations permitted 1572 /// to replace a call to llvm.memcpy. The value is set by the target at the 1573 /// performance threshold for such a replacement. If OptSize is true, 1574 /// return the limit for functions that have OptSize attribute. getMaxStoresPerMemcpy(bool OptSize)1575 unsigned getMaxStoresPerMemcpy(bool OptSize) const { 1576 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy; 1577 } 1578 1579 /// \brief Get maximum # of store operations to be glued together 1580 /// 1581 /// This function returns the maximum number of store operations permitted 1582 /// to glue together during lowering of llvm.memcpy. The value is set by 1583 // the target at the performance threshold for such a replacement. getMaxGluedStoresPerMemcpy()1584 virtual unsigned getMaxGluedStoresPerMemcpy() const { 1585 return MaxGluedStoresPerMemcpy; 1586 } 1587 1588 /// Get maximum # of load operations permitted for memcmp 1589 /// 1590 /// This function returns the maximum number of load operations permitted 1591 /// to replace a call to memcmp. The value is set by the target at the 1592 /// performance threshold for such a replacement. If OptSize is true, 1593 /// return the limit for functions that have OptSize attribute. getMaxExpandSizeMemcmp(bool OptSize)1594 unsigned getMaxExpandSizeMemcmp(bool OptSize) const { 1595 return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp; 1596 } 1597 1598 /// Get maximum # of store operations permitted for llvm.memmove 1599 /// 1600 /// This function returns the maximum number of store operations permitted 1601 /// to replace a call to llvm.memmove. The value is set by the target at the 1602 /// performance threshold for such a replacement. If OptSize is true, 1603 /// return the limit for functions that have OptSize attribute. getMaxStoresPerMemmove(bool OptSize)1604 unsigned getMaxStoresPerMemmove(bool OptSize) const { 1605 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove; 1606 } 1607 1608 /// Determine if the target supports unaligned memory accesses. 1609 /// 1610 /// This function returns true if the target allows unaligned memory accesses 1611 /// of the specified type in the given address space. If true, it also returns 1612 /// whether the unaligned memory access is "fast" in the last argument by 1613 /// reference. This is used, for example, in situations where an array 1614 /// copy/move/set is converted to a sequence of store operations. Its use 1615 /// helps to ensure that such replacements don't generate code that causes an 1616 /// alignment error (trap) on the target machine. 1617 virtual bool allowsMisalignedMemoryAccesses( 1618 EVT, unsigned AddrSpace = 0, Align Alignment = Align(1), 1619 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 1620 bool * /*Fast*/ = nullptr) const { 1621 return false; 1622 } 1623 1624 /// LLT handling variant. 1625 virtual bool allowsMisalignedMemoryAccesses( 1626 LLT, unsigned AddrSpace = 0, Align Alignment = Align(1), 1627 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 1628 bool * /*Fast*/ = nullptr) const { 1629 return false; 1630 } 1631 1632 /// This function returns true if the memory access is aligned or if the 1633 /// target allows this specific unaligned memory access. If the access is 1634 /// allowed, the optional final parameter returns if the access is also fast 1635 /// (as defined by the target). 1636 bool allowsMemoryAccessForAlignment( 1637 LLVMContext &Context, const DataLayout &DL, EVT VT, 1638 unsigned AddrSpace = 0, Align Alignment = Align(1), 1639 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 1640 bool *Fast = nullptr) const; 1641 1642 /// Return true if the memory access of this type is aligned or if the target 1643 /// allows this specific unaligned access for the given MachineMemOperand. 1644 /// If the access is allowed, the optional final parameter returns if the 1645 /// access is also fast (as defined by the target). 1646 bool allowsMemoryAccessForAlignment(LLVMContext &Context, 1647 const DataLayout &DL, EVT VT, 1648 const MachineMemOperand &MMO, 1649 bool *Fast = nullptr) const; 1650 1651 /// Return true if the target supports a memory access of this type for the 1652 /// given address space and alignment. If the access is allowed, the optional 1653 /// final parameter returns if the access is also fast (as defined by the 1654 /// target). 1655 virtual bool 1656 allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, 1657 unsigned AddrSpace = 0, Align Alignment = Align(1), 1658 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 1659 bool *Fast = nullptr) const; 1660 1661 /// Return true if the target supports a memory access of this type for the 1662 /// given MachineMemOperand. If the access is allowed, the optional 1663 /// final parameter returns if the access is also fast (as defined by the 1664 /// target). 1665 bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, 1666 const MachineMemOperand &MMO, 1667 bool *Fast = nullptr) const; 1668 1669 /// LLT handling variant. 1670 bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, LLT Ty, 1671 const MachineMemOperand &MMO, 1672 bool *Fast = nullptr) const; 1673 1674 /// Returns the target specific optimal type for load and store operations as 1675 /// a result of memset, memcpy, and memmove lowering. 1676 /// It returns EVT::Other if the type should be determined using generic 1677 /// target-independent logic. 1678 virtual EVT getOptimalMemOpType(const MemOp & Op,const AttributeList &)1679 getOptimalMemOpType(const MemOp &Op, 1680 const AttributeList & /*FuncAttributes*/) const { 1681 return MVT::Other; 1682 } 1683 1684 /// LLT returning variant. 1685 virtual LLT getOptimalMemOpLLT(const MemOp & Op,const AttributeList &)1686 getOptimalMemOpLLT(const MemOp &Op, 1687 const AttributeList & /*FuncAttributes*/) const { 1688 return LLT(); 1689 } 1690 1691 /// Returns true if it's safe to use load / store of the specified type to 1692 /// expand memcpy / memset inline. 1693 /// 1694 /// This is mostly true for all types except for some special cases. For 1695 /// example, on X86 targets without SSE2 f64 load / store are done with fldl / 1696 /// fstpl which also does type conversion. Note the specified type doesn't 1697 /// have to be legal as the hook is used before type legalization. isSafeMemOpType(MVT)1698 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; } 1699 1700 /// Return lower limit for number of blocks in a jump table. 1701 virtual unsigned getMinimumJumpTableEntries() const; 1702 1703 /// Return lower limit of the density in a jump table. 1704 unsigned getMinimumJumpTableDensity(bool OptForSize) const; 1705 1706 /// Return upper limit for number of entries in a jump table. 1707 /// Zero if no limit. 1708 unsigned getMaximumJumpTableSize() const; 1709 1710 virtual bool isJumpTableRelative() const; 1711 1712 /// If a physical register, this specifies the register that 1713 /// llvm.savestack/llvm.restorestack should save and restore. getStackPointerRegisterToSaveRestore()1714 Register getStackPointerRegisterToSaveRestore() const { 1715 return StackPointerRegisterToSaveRestore; 1716 } 1717 1718 /// If a physical register, this returns the register that receives the 1719 /// exception address on entry to an EH pad. 1720 virtual Register getExceptionPointerRegister(const Constant * PersonalityFn)1721 getExceptionPointerRegister(const Constant *PersonalityFn) const { 1722 return Register(); 1723 } 1724 1725 /// If a physical register, this returns the register that receives the 1726 /// exception typeid on entry to a landing pad. 1727 virtual Register getExceptionSelectorRegister(const Constant * PersonalityFn)1728 getExceptionSelectorRegister(const Constant *PersonalityFn) const { 1729 return Register(); 1730 } 1731 needsFixedCatchObjects()1732 virtual bool needsFixedCatchObjects() const { 1733 report_fatal_error("Funclet EH is not implemented for this target"); 1734 } 1735 1736 /// Return the minimum stack alignment of an argument. getMinStackArgumentAlignment()1737 Align getMinStackArgumentAlignment() const { 1738 return MinStackArgumentAlignment; 1739 } 1740 1741 /// Return the minimum function alignment. getMinFunctionAlignment()1742 Align getMinFunctionAlignment() const { return MinFunctionAlignment; } 1743 1744 /// Return the preferred function alignment. getPrefFunctionAlignment()1745 Align getPrefFunctionAlignment() const { return PrefFunctionAlignment; } 1746 1747 /// Return the preferred loop alignment. 1748 virtual Align getPrefLoopAlignment(MachineLoop *ML = nullptr) const { 1749 return PrefLoopAlignment; 1750 } 1751 1752 /// Should loops be aligned even when the function is marked OptSize (but not 1753 /// MinSize). alignLoopsWithOptSize()1754 virtual bool alignLoopsWithOptSize() const { 1755 return false; 1756 } 1757 1758 /// If the target has a standard location for the stack protector guard, 1759 /// returns the address of that location. Otherwise, returns nullptr. 1760 /// DEPRECATED: please override useLoadStackGuardNode and customize 1761 /// LOAD_STACK_GUARD, or customize \@llvm.stackguard(). 1762 virtual Value *getIRStackGuard(IRBuilder<> &IRB) const; 1763 1764 /// Inserts necessary declarations for SSP (stack protection) purpose. 1765 /// Should be used only when getIRStackGuard returns nullptr. 1766 virtual void insertSSPDeclarations(Module &M) const; 1767 1768 /// Return the variable that's previously inserted by insertSSPDeclarations, 1769 /// if any, otherwise return nullptr. Should be used only when 1770 /// getIRStackGuard returns nullptr. 1771 virtual Value *getSDagStackGuard(const Module &M) const; 1772 1773 /// If this function returns true, stack protection checks should XOR the 1774 /// frame pointer (or whichever pointer is used to address locals) into the 1775 /// stack guard value before checking it. getIRStackGuard must return nullptr 1776 /// if this returns true. useStackGuardXorFP()1777 virtual bool useStackGuardXorFP() const { return false; } 1778 1779 /// If the target has a standard stack protection check function that 1780 /// performs validation and error handling, returns the function. Otherwise, 1781 /// returns nullptr. Must be previously inserted by insertSSPDeclarations. 1782 /// Should be used only when getIRStackGuard returns nullptr. 1783 virtual Function *getSSPStackGuardCheck(const Module &M) const; 1784 1785 protected: 1786 Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, 1787 bool UseTLS) const; 1788 1789 public: 1790 /// Returns the target-specific address of the unsafe stack pointer. 1791 virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const; 1792 1793 /// Returns the name of the symbol used to emit stack probes or the empty 1794 /// string if not applicable. hasStackProbeSymbol(MachineFunction & MF)1795 virtual bool hasStackProbeSymbol(MachineFunction &MF) const { return false; } 1796 hasInlineStackProbe(MachineFunction & MF)1797 virtual bool hasInlineStackProbe(MachineFunction &MF) const { return false; } 1798 getStackProbeSymbolName(MachineFunction & MF)1799 virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const { 1800 return ""; 1801 } 1802 1803 /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we 1804 /// are happy to sink it into basic blocks. A cast may be free, but not 1805 /// necessarily a no-op. e.g. a free truncate from a 64-bit to 32-bit pointer. 1806 virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const; 1807 1808 /// Return true if the pointer arguments to CI should be aligned by aligning 1809 /// the object whose address is being passed. If so then MinSize is set to the 1810 /// minimum size the object must be to be aligned and PrefAlign is set to the 1811 /// preferred alignment. shouldAlignPointerArgs(CallInst *,unsigned &,unsigned &)1812 virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/, 1813 unsigned & /*PrefAlign*/) const { 1814 return false; 1815 } 1816 1817 //===--------------------------------------------------------------------===// 1818 /// \name Helpers for TargetTransformInfo implementations 1819 /// @{ 1820 1821 /// Get the ISD node that corresponds to the Instruction class opcode. 1822 int InstructionOpcodeToISD(unsigned Opcode) const; 1823 1824 /// Estimate the cost of type-legalization and the legalized type. 1825 std::pair<InstructionCost, MVT> getTypeLegalizationCost(const DataLayout &DL, 1826 Type *Ty) const; 1827 1828 /// @} 1829 1830 //===--------------------------------------------------------------------===// 1831 /// \name Helpers for atomic expansion. 1832 /// @{ 1833 1834 /// Returns the maximum atomic operation size (in bits) supported by 1835 /// the backend. Atomic operations greater than this size (as well 1836 /// as ones that are not naturally aligned), will be expanded by 1837 /// AtomicExpandPass into an __atomic_* library call. getMaxAtomicSizeInBitsSupported()1838 unsigned getMaxAtomicSizeInBitsSupported() const { 1839 return MaxAtomicSizeInBitsSupported; 1840 } 1841 1842 /// Returns the size of the smallest cmpxchg or ll/sc instruction 1843 /// the backend supports. Any smaller operations are widened in 1844 /// AtomicExpandPass. 1845 /// 1846 /// Note that *unlike* operations above the maximum size, atomic ops 1847 /// are still natively supported below the minimum; they just 1848 /// require a more complex expansion. getMinCmpXchgSizeInBits()1849 unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; } 1850 1851 /// Whether the target supports unaligned atomic operations. supportsUnalignedAtomics()1852 bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; } 1853 1854 /// Whether AtomicExpandPass should automatically insert fences and reduce 1855 /// ordering for this atomic. This should be true for most architectures with 1856 /// weak memory ordering. Defaults to false. shouldInsertFencesForAtomic(const Instruction * I)1857 virtual bool shouldInsertFencesForAtomic(const Instruction *I) const { 1858 return false; 1859 } 1860 1861 /// Perform a load-linked operation on Addr, returning a "Value *" with the 1862 /// corresponding pointee type. This may entail some non-trivial operations to 1863 /// truncate or reconstruct types that will be illegal in the backend. See 1864 /// ARMISelLowering for an example implementation. emitLoadLinked(IRBuilder<> & Builder,Value * Addr,AtomicOrdering Ord)1865 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr, 1866 AtomicOrdering Ord) const { 1867 llvm_unreachable("Load linked unimplemented on this target"); 1868 } 1869 1870 /// Perform a store-conditional operation to Addr. Return the status of the 1871 /// store. This should be 0 if the store succeeded, non-zero otherwise. emitStoreConditional(IRBuilder<> & Builder,Value * Val,Value * Addr,AtomicOrdering Ord)1872 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val, 1873 Value *Addr, AtomicOrdering Ord) const { 1874 llvm_unreachable("Store conditional unimplemented on this target"); 1875 } 1876 1877 /// Perform a masked atomicrmw using a target-specific intrinsic. This 1878 /// represents the core LL/SC loop which will be lowered at a late stage by 1879 /// the backend. emitMaskedAtomicRMWIntrinsic(IRBuilder<> & Builder,AtomicRMWInst * AI,Value * AlignedAddr,Value * Incr,Value * Mask,Value * ShiftAmt,AtomicOrdering Ord)1880 virtual Value *emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, 1881 AtomicRMWInst *AI, 1882 Value *AlignedAddr, Value *Incr, 1883 Value *Mask, Value *ShiftAmt, 1884 AtomicOrdering Ord) const { 1885 llvm_unreachable("Masked atomicrmw expansion unimplemented on this target"); 1886 } 1887 1888 /// Perform a masked cmpxchg using a target-specific intrinsic. This 1889 /// represents the core LL/SC loop which will be lowered at a late stage by 1890 /// the backend. emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> & Builder,AtomicCmpXchgInst * CI,Value * AlignedAddr,Value * CmpVal,Value * NewVal,Value * Mask,AtomicOrdering Ord)1891 virtual Value *emitMaskedAtomicCmpXchgIntrinsic( 1892 IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, 1893 Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const { 1894 llvm_unreachable("Masked cmpxchg expansion unimplemented on this target"); 1895 } 1896 1897 /// Inserts in the IR a target-specific intrinsic specifying a fence. 1898 /// It is called by AtomicExpandPass before expanding an 1899 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad 1900 /// if shouldInsertFencesForAtomic returns true. 1901 /// 1902 /// Inst is the original atomic instruction, prior to other expansions that 1903 /// may be performed. 1904 /// 1905 /// This function should either return a nullptr, or a pointer to an IR-level 1906 /// Instruction*. Even complex fence sequences can be represented by a 1907 /// single Instruction* through an intrinsic to be lowered later. 1908 /// Backends should override this method to produce target-specific intrinsic 1909 /// for their fences. 1910 /// FIXME: Please note that the default implementation here in terms of 1911 /// IR-level fences exists for historical/compatibility reasons and is 1912 /// *unsound* ! Fences cannot, in general, be used to restore sequential 1913 /// consistency. For example, consider the following example: 1914 /// atomic<int> x = y = 0; 1915 /// int r1, r2, r3, r4; 1916 /// Thread 0: 1917 /// x.store(1); 1918 /// Thread 1: 1919 /// y.store(1); 1920 /// Thread 2: 1921 /// r1 = x.load(); 1922 /// r2 = y.load(); 1923 /// Thread 3: 1924 /// r3 = y.load(); 1925 /// r4 = x.load(); 1926 /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all 1927 /// seq_cst. But if they are lowered to monotonic accesses, no amount of 1928 /// IR-level fences can prevent it. 1929 /// @{ emitLeadingFence(IRBuilder<> & Builder,Instruction * Inst,AtomicOrdering Ord)1930 virtual Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, 1931 AtomicOrdering Ord) const { 1932 if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore()) 1933 return Builder.CreateFence(Ord); 1934 else 1935 return nullptr; 1936 } 1937 emitTrailingFence(IRBuilder<> & Builder,Instruction * Inst,AtomicOrdering Ord)1938 virtual Instruction *emitTrailingFence(IRBuilder<> &Builder, 1939 Instruction *Inst, 1940 AtomicOrdering Ord) const { 1941 if (isAcquireOrStronger(Ord)) 1942 return Builder.CreateFence(Ord); 1943 else 1944 return nullptr; 1945 } 1946 /// @} 1947 1948 // Emits code that executes when the comparison result in the ll/sc 1949 // expansion of a cmpxchg instruction is such that the store-conditional will 1950 // not execute. This makes it possible to balance out the load-linked with 1951 // a dedicated instruction, if desired. 1952 // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would 1953 // be unnecessarily held, except if clrex, inserted by this hook, is executed. emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> & Builder)1954 virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {} 1955 1956 /// Returns true if the given (atomic) store should be expanded by the 1957 /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input. shouldExpandAtomicStoreInIR(StoreInst * SI)1958 virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const { 1959 return false; 1960 } 1961 1962 /// Returns true if arguments should be sign-extended in lib calls. shouldSignExtendTypeInLibCall(EVT Type,bool IsSigned)1963 virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const { 1964 return IsSigned; 1965 } 1966 1967 /// Returns true if arguments should be extended in lib calls. shouldExtendTypeInLibCall(EVT Type)1968 virtual bool shouldExtendTypeInLibCall(EVT Type) const { 1969 return true; 1970 } 1971 1972 /// Returns how the given (atomic) load should be expanded by the 1973 /// IR-level AtomicExpand pass. shouldExpandAtomicLoadInIR(LoadInst * LI)1974 virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const { 1975 return AtomicExpansionKind::None; 1976 } 1977 1978 /// Returns how the given atomic cmpxchg should be expanded by the IR-level 1979 /// AtomicExpand pass. 1980 virtual AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst * AI)1981 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const { 1982 return AtomicExpansionKind::None; 1983 } 1984 1985 /// Returns how the IR-level AtomicExpand pass should expand the given 1986 /// AtomicRMW, if at all. Default is to never expand. shouldExpandAtomicRMWInIR(AtomicRMWInst * RMW)1987 virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const { 1988 return RMW->isFloatingPointOperation() ? 1989 AtomicExpansionKind::CmpXChg : AtomicExpansionKind::None; 1990 } 1991 1992 /// On some platforms, an AtomicRMW that never actually modifies the value 1993 /// (such as fetch_add of 0) can be turned into a fence followed by an 1994 /// atomic load. This may sound useless, but it makes it possible for the 1995 /// processor to keep the cacheline shared, dramatically improving 1996 /// performance. And such idempotent RMWs are useful for implementing some 1997 /// kinds of locks, see for example (justification + benchmarks): 1998 /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf 1999 /// This method tries doing that transformation, returning the atomic load if 2000 /// it succeeds, and nullptr otherwise. 2001 /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo 2002 /// another round of expansion. 2003 virtual LoadInst * lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst * RMWI)2004 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const { 2005 return nullptr; 2006 } 2007 2008 /// Returns how the platform's atomic operations are extended (ZERO_EXTEND, 2009 /// SIGN_EXTEND, or ANY_EXTEND). getExtendForAtomicOps()2010 virtual ISD::NodeType getExtendForAtomicOps() const { 2011 return ISD::ZERO_EXTEND; 2012 } 2013 2014 /// Returns how the platform's atomic compare and swap expects its comparison 2015 /// value to be extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND). This is 2016 /// separate from getExtendForAtomicOps, which is concerned with the 2017 /// sign-extension of the instruction's output, whereas here we are concerned 2018 /// with the sign-extension of the input. For targets with compare-and-swap 2019 /// instructions (or sub-word comparisons in their LL/SC loop expansions), 2020 /// the input can be ANY_EXTEND, but the output will still have a specific 2021 /// extension. getExtendForAtomicCmpSwapArg()2022 virtual ISD::NodeType getExtendForAtomicCmpSwapArg() const { 2023 return ISD::ANY_EXTEND; 2024 } 2025 2026 /// @} 2027 2028 /// Returns true if we should normalize 2029 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and 2030 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely 2031 /// that it saves us from materializing N0 and N1 in an integer register. 2032 /// Targets that are able to perform and/or on flags should return false here. shouldNormalizeToSelectSequence(LLVMContext & Context,EVT VT)2033 virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context, 2034 EVT VT) const { 2035 // If a target has multiple condition registers, then it likely has logical 2036 // operations on those registers. 2037 if (hasMultipleConditionRegisters()) 2038 return false; 2039 // Only do the transform if the value won't be split into multiple 2040 // registers. 2041 LegalizeTypeAction Action = getTypeAction(Context, VT); 2042 return Action != TypeExpandInteger && Action != TypeExpandFloat && 2043 Action != TypeSplitVector; 2044 } 2045 isProfitableToCombineMinNumMaxNum(EVT VT)2046 virtual bool isProfitableToCombineMinNumMaxNum(EVT VT) const { return true; } 2047 2048 /// Return true if a select of constants (select Cond, C1, C2) should be 2049 /// transformed into simple math ops with the condition value. For example: 2050 /// select Cond, C1, C1-1 --> add (zext Cond), C1-1 convertSelectOfConstantsToMath(EVT VT)2051 virtual bool convertSelectOfConstantsToMath(EVT VT) const { 2052 return false; 2053 } 2054 2055 /// Return true if it is profitable to transform an integer 2056 /// multiplication-by-constant into simpler operations like shifts and adds. 2057 /// This may be true if the target does not directly support the 2058 /// multiplication operation for the specified type or the sequence of simpler 2059 /// ops is faster than the multiply. decomposeMulByConstant(LLVMContext & Context,EVT VT,SDValue C)2060 virtual bool decomposeMulByConstant(LLVMContext &Context, 2061 EVT VT, SDValue C) const { 2062 return false; 2063 } 2064 2065 /// Return true if it is more correct/profitable to use strict FP_TO_INT 2066 /// conversion operations - canonicalizing the FP source value instead of 2067 /// converting all cases and then selecting based on value. 2068 /// This may be true if the target throws exceptions for out of bounds 2069 /// conversions or has fast FP CMOV. shouldUseStrictFP_TO_INT(EVT FpVT,EVT IntVT,bool IsSigned)2070 virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, 2071 bool IsSigned) const { 2072 return false; 2073 } 2074 2075 //===--------------------------------------------------------------------===// 2076 // TargetLowering Configuration Methods - These methods should be invoked by 2077 // the derived class constructor to configure this object for the target. 2078 // 2079 protected: 2080 /// Specify how the target extends the result of integer and floating point 2081 /// boolean values from i1 to a wider type. See getBooleanContents. setBooleanContents(BooleanContent Ty)2082 void setBooleanContents(BooleanContent Ty) { 2083 BooleanContents = Ty; 2084 BooleanFloatContents = Ty; 2085 } 2086 2087 /// Specify how the target extends the result of integer and floating point 2088 /// boolean values from i1 to a wider type. See getBooleanContents. setBooleanContents(BooleanContent IntTy,BooleanContent FloatTy)2089 void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) { 2090 BooleanContents = IntTy; 2091 BooleanFloatContents = FloatTy; 2092 } 2093 2094 /// Specify how the target extends the result of a vector boolean value from a 2095 /// vector of i1 to a wider type. See getBooleanContents. setBooleanVectorContents(BooleanContent Ty)2096 void setBooleanVectorContents(BooleanContent Ty) { 2097 BooleanVectorContents = Ty; 2098 } 2099 2100 /// Specify the target scheduling preference. setSchedulingPreference(Sched::Preference Pref)2101 void setSchedulingPreference(Sched::Preference Pref) { 2102 SchedPreferenceInfo = Pref; 2103 } 2104 2105 /// Indicate the minimum number of blocks to generate jump tables. 2106 void setMinimumJumpTableEntries(unsigned Val); 2107 2108 /// Indicate the maximum number of entries in jump tables. 2109 /// Set to zero to generate unlimited jump tables. 2110 void setMaximumJumpTableSize(unsigned); 2111 2112 /// If set to a physical register, this specifies the register that 2113 /// llvm.savestack/llvm.restorestack should save and restore. setStackPointerRegisterToSaveRestore(Register R)2114 void setStackPointerRegisterToSaveRestore(Register R) { 2115 StackPointerRegisterToSaveRestore = R; 2116 } 2117 2118 /// Tells the code generator that the target has multiple (allocatable) 2119 /// condition registers that can be used to store the results of comparisons 2120 /// for use by selects and conditional branches. With multiple condition 2121 /// registers, the code generator will not aggressively sink comparisons into 2122 /// the blocks of their users. 2123 void setHasMultipleConditionRegisters(bool hasManyRegs = true) { 2124 HasMultipleConditionRegisters = hasManyRegs; 2125 } 2126 2127 /// Tells the code generator that the target has BitExtract instructions. 2128 /// The code generator will aggressively sink "shift"s into the blocks of 2129 /// their users if the users will generate "and" instructions which can be 2130 /// combined with "shift" to BitExtract instructions. 2131 void setHasExtractBitsInsn(bool hasExtractInsn = true) { 2132 HasExtractBitsInsn = hasExtractInsn; 2133 } 2134 2135 /// Tells the code generator not to expand logic operations on comparison 2136 /// predicates into separate sequences that increase the amount of flow 2137 /// control. 2138 void setJumpIsExpensive(bool isExpensive = true); 2139 2140 /// Tells the code generator which bitwidths to bypass. addBypassSlowDiv(unsigned int SlowBitWidth,unsigned int FastBitWidth)2141 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) { 2142 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth; 2143 } 2144 2145 /// Add the specified register class as an available regclass for the 2146 /// specified value type. This indicates the selector can handle values of 2147 /// that class natively. addRegisterClass(MVT VT,const TargetRegisterClass * RC)2148 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) { 2149 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT)); 2150 RegClassForVT[VT.SimpleTy] = RC; 2151 } 2152 2153 /// Return the largest legal super-reg register class of the register class 2154 /// for the specified type and its associated "cost". 2155 virtual std::pair<const TargetRegisterClass *, uint8_t> 2156 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const; 2157 2158 /// Once all of the register classes are added, this allows us to compute 2159 /// derived properties we expose. 2160 void computeRegisterProperties(const TargetRegisterInfo *TRI); 2161 2162 /// Indicate that the specified operation does not work with the specified 2163 /// type and indicate what to do about it. Note that VT may refer to either 2164 /// the type of a result or that of an operand of Op. setOperationAction(unsigned Op,MVT VT,LegalizeAction Action)2165 void setOperationAction(unsigned Op, MVT VT, 2166 LegalizeAction Action) { 2167 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"); 2168 OpActions[(unsigned)VT.SimpleTy][Op] = Action; 2169 } 2170 2171 /// Indicate that the specified load with extension does not work with the 2172 /// specified type and indicate what to do about it. setLoadExtAction(unsigned ExtType,MVT ValVT,MVT MemVT,LegalizeAction Action)2173 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, 2174 LegalizeAction Action) { 2175 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() && 2176 MemVT.isValid() && "Table isn't big enough!"); 2177 assert((unsigned)Action < 0x10 && "too many bits for bitfield array"); 2178 unsigned Shift = 4 * ExtType; 2179 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift); 2180 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift; 2181 } 2182 2183 /// Indicate that the specified truncating store does not work with the 2184 /// specified type and indicate what to do about it. setTruncStoreAction(MVT ValVT,MVT MemVT,LegalizeAction Action)2185 void setTruncStoreAction(MVT ValVT, MVT MemVT, 2186 LegalizeAction Action) { 2187 assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!"); 2188 TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action; 2189 } 2190 2191 /// Indicate that the specified indexed load does or does not work with the 2192 /// specified type and indicate what to do abort it. 2193 /// 2194 /// NOTE: All indexed mode loads are initialized to Expand in 2195 /// TargetLowering.cpp setIndexedLoadAction(unsigned IdxMode,MVT VT,LegalizeAction Action)2196 void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action) { 2197 setIndexedModeAction(IdxMode, VT, IMAB_Load, Action); 2198 } 2199 2200 /// Indicate that the specified indexed store does or does not work with the 2201 /// specified type and indicate what to do about it. 2202 /// 2203 /// NOTE: All indexed mode stores are initialized to Expand in 2204 /// TargetLowering.cpp setIndexedStoreAction(unsigned IdxMode,MVT VT,LegalizeAction Action)2205 void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action) { 2206 setIndexedModeAction(IdxMode, VT, IMAB_Store, Action); 2207 } 2208 2209 /// Indicate that the specified indexed masked load does or does not work with 2210 /// the specified type and indicate what to do about it. 2211 /// 2212 /// NOTE: All indexed mode masked loads are initialized to Expand in 2213 /// TargetLowering.cpp setIndexedMaskedLoadAction(unsigned IdxMode,MVT VT,LegalizeAction Action)2214 void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, 2215 LegalizeAction Action) { 2216 setIndexedModeAction(IdxMode, VT, IMAB_MaskedLoad, Action); 2217 } 2218 2219 /// Indicate that the specified indexed masked store does or does not work 2220 /// with the specified type and indicate what to do about it. 2221 /// 2222 /// NOTE: All indexed mode masked stores are initialized to Expand in 2223 /// TargetLowering.cpp setIndexedMaskedStoreAction(unsigned IdxMode,MVT VT,LegalizeAction Action)2224 void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, 2225 LegalizeAction Action) { 2226 setIndexedModeAction(IdxMode, VT, IMAB_MaskedStore, Action); 2227 } 2228 2229 /// Indicate that the specified condition code is or isn't supported on the 2230 /// target and indicate what to do about it. setCondCodeAction(ISD::CondCode CC,MVT VT,LegalizeAction Action)2231 void setCondCodeAction(ISD::CondCode CC, MVT VT, 2232 LegalizeAction Action) { 2233 assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) && 2234 "Table isn't big enough!"); 2235 assert((unsigned)Action < 0x10 && "too many bits for bitfield array"); 2236 /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit 2237 /// value and the upper 29 bits index into the second dimension of the array 2238 /// to select what 32-bit value to use. 2239 uint32_t Shift = 4 * (VT.SimpleTy & 0x7); 2240 CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift); 2241 CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift; 2242 } 2243 2244 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults 2245 /// to trying a larger integer/fp until it can find one that works. If that 2246 /// default is insufficient, this method can be used by the target to override 2247 /// the default. AddPromotedToType(unsigned Opc,MVT OrigVT,MVT DestVT)2248 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 2249 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; 2250 } 2251 2252 /// Convenience method to set an operation to Promote and specify the type 2253 /// in a single call. setOperationPromotedToType(unsigned Opc,MVT OrigVT,MVT DestVT)2254 void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { 2255 setOperationAction(Opc, OrigVT, Promote); 2256 AddPromotedToType(Opc, OrigVT, DestVT); 2257 } 2258 2259 /// Targets should invoke this method for each target independent node that 2260 /// they want to provide a custom DAG combiner for by implementing the 2261 /// PerformDAGCombine virtual method. setTargetDAGCombine(ISD::NodeType NT)2262 void setTargetDAGCombine(ISD::NodeType NT) { 2263 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)); 2264 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7); 2265 } 2266 2267 /// Set the target's minimum function alignment. setMinFunctionAlignment(Align Alignment)2268 void setMinFunctionAlignment(Align Alignment) { 2269 MinFunctionAlignment = Alignment; 2270 } 2271 2272 /// Set the target's preferred function alignment. This should be set if 2273 /// there is a performance benefit to higher-than-minimum alignment setPrefFunctionAlignment(Align Alignment)2274 void setPrefFunctionAlignment(Align Alignment) { 2275 PrefFunctionAlignment = Alignment; 2276 } 2277 2278 /// Set the target's preferred loop alignment. Default alignment is one, it 2279 /// means the target does not care about loop alignment. The target may also 2280 /// override getPrefLoopAlignment to provide per-loop values. setPrefLoopAlignment(Align Alignment)2281 void setPrefLoopAlignment(Align Alignment) { PrefLoopAlignment = Alignment; } 2282 2283 /// Set the minimum stack alignment of an argument. setMinStackArgumentAlignment(Align Alignment)2284 void setMinStackArgumentAlignment(Align Alignment) { 2285 MinStackArgumentAlignment = Alignment; 2286 } 2287 2288 /// Set the maximum atomic operation size supported by the 2289 /// backend. Atomic operations greater than this size (as well as 2290 /// ones that are not naturally aligned), will be expanded by 2291 /// AtomicExpandPass into an __atomic_* library call. setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)2292 void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) { 2293 MaxAtomicSizeInBitsSupported = SizeInBits; 2294 } 2295 2296 /// Sets the minimum cmpxchg or ll/sc size supported by the backend. setMinCmpXchgSizeInBits(unsigned SizeInBits)2297 void setMinCmpXchgSizeInBits(unsigned SizeInBits) { 2298 MinCmpXchgSizeInBits = SizeInBits; 2299 } 2300 2301 /// Sets whether unaligned atomic operations are supported. setSupportsUnalignedAtomics(bool UnalignedSupported)2302 void setSupportsUnalignedAtomics(bool UnalignedSupported) { 2303 SupportsUnalignedAtomics = UnalignedSupported; 2304 } 2305 2306 public: 2307 //===--------------------------------------------------------------------===// 2308 // Addressing mode description hooks (used by LSR etc). 2309 // 2310 2311 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store 2312 /// instructions reading the address. This allows as much computation as 2313 /// possible to be done in the address mode for that operand. This hook lets 2314 /// targets also pass back when this should be done on intrinsics which 2315 /// load/store. getAddrModeArguments(IntrinsicInst *,SmallVectorImpl<Value * > &,Type * &)2316 virtual bool getAddrModeArguments(IntrinsicInst * /*I*/, 2317 SmallVectorImpl<Value*> &/*Ops*/, 2318 Type *&/*AccessTy*/) const { 2319 return false; 2320 } 2321 2322 /// This represents an addressing mode of: 2323 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg 2324 /// If BaseGV is null, there is no BaseGV. 2325 /// If BaseOffs is zero, there is no base offset. 2326 /// If HasBaseReg is false, there is no base register. 2327 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with 2328 /// no scale. 2329 struct AddrMode { 2330 GlobalValue *BaseGV = nullptr; 2331 int64_t BaseOffs = 0; 2332 bool HasBaseReg = false; 2333 int64_t Scale = 0; 2334 AddrMode() = default; 2335 }; 2336 2337 /// Return true if the addressing mode represented by AM is legal for this 2338 /// target, for a load/store of the specified type. 2339 /// 2340 /// The type may be VoidTy, in which case only return true if the addressing 2341 /// mode is legal for a load/store of any legal type. TODO: Handle 2342 /// pre/postinc as well. 2343 /// 2344 /// If the address space cannot be determined, it will be -1. 2345 /// 2346 /// TODO: Remove default argument 2347 virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 2348 Type *Ty, unsigned AddrSpace, 2349 Instruction *I = nullptr) const; 2350 2351 /// Return the cost of the scaling factor used in the addressing mode 2352 /// represented by AM for this target, for a load/store of the specified type. 2353 /// 2354 /// If the AM is supported, the return value must be >= 0. 2355 /// If the AM is not supported, it returns a negative value. 2356 /// TODO: Handle pre/postinc as well. 2357 /// TODO: Remove default argument 2358 virtual InstructionCost getScalingFactorCost(const DataLayout &DL, 2359 const AddrMode &AM, Type *Ty, 2360 unsigned AS = 0) const { 2361 // Default: assume that any scaling factor used in a legal AM is free. 2362 if (isLegalAddressingMode(DL, AM, Ty, AS)) 2363 return 0; 2364 return -1; 2365 } 2366 2367 /// Return true if the specified immediate is legal icmp immediate, that is 2368 /// the target has icmp instructions which can compare a register against the 2369 /// immediate without having to materialize the immediate into a register. isLegalICmpImmediate(int64_t)2370 virtual bool isLegalICmpImmediate(int64_t) const { 2371 return true; 2372 } 2373 2374 /// Return true if the specified immediate is legal add immediate, that is the 2375 /// target has add instructions which can add a register with the immediate 2376 /// without having to materialize the immediate into a register. isLegalAddImmediate(int64_t)2377 virtual bool isLegalAddImmediate(int64_t) const { 2378 return true; 2379 } 2380 2381 /// Return true if the specified immediate is legal for the value input of a 2382 /// store instruction. isLegalStoreImmediate(int64_t Value)2383 virtual bool isLegalStoreImmediate(int64_t Value) const { 2384 // Default implementation assumes that at least 0 works since it is likely 2385 // that a zero register exists or a zero immediate is allowed. 2386 return Value == 0; 2387 } 2388 2389 /// Return true if it's significantly cheaper to shift a vector by a uniform 2390 /// scalar than by an amount which will vary across each lane. On x86 before 2391 /// AVX2 for example, there is a "psllw" instruction for the former case, but 2392 /// no simple instruction for a general "a << b" operation on vectors. 2393 /// This should also apply to lowering for vector funnel shifts (rotates). isVectorShiftByScalarCheap(Type * Ty)2394 virtual bool isVectorShiftByScalarCheap(Type *Ty) const { 2395 return false; 2396 } 2397 2398 /// Given a shuffle vector SVI representing a vector splat, return a new 2399 /// scalar type of size equal to SVI's scalar type if the new type is more 2400 /// profitable. Returns nullptr otherwise. For example under MVE float splats 2401 /// are converted to integer to prevent the need to move from SPR to GPR 2402 /// registers. shouldConvertSplatType(ShuffleVectorInst * SVI)2403 virtual Type* shouldConvertSplatType(ShuffleVectorInst* SVI) const { 2404 return nullptr; 2405 } 2406 2407 /// Given a set in interconnected phis of type 'From' that are loaded/stored 2408 /// or bitcast to type 'To', return true if the set should be converted to 2409 /// 'To'. shouldConvertPhiType(Type * From,Type * To)2410 virtual bool shouldConvertPhiType(Type *From, Type *To) const { 2411 return (From->isIntegerTy() || From->isFloatingPointTy()) && 2412 (To->isIntegerTy() || To->isFloatingPointTy()); 2413 } 2414 2415 /// Returns true if the opcode is a commutative binary operation. isCommutativeBinOp(unsigned Opcode)2416 virtual bool isCommutativeBinOp(unsigned Opcode) const { 2417 // FIXME: This should get its info from the td file. 2418 switch (Opcode) { 2419 case ISD::ADD: 2420 case ISD::SMIN: 2421 case ISD::SMAX: 2422 case ISD::UMIN: 2423 case ISD::UMAX: 2424 case ISD::MUL: 2425 case ISD::MULHU: 2426 case ISD::MULHS: 2427 case ISD::SMUL_LOHI: 2428 case ISD::UMUL_LOHI: 2429 case ISD::FADD: 2430 case ISD::FMUL: 2431 case ISD::AND: 2432 case ISD::OR: 2433 case ISD::XOR: 2434 case ISD::SADDO: 2435 case ISD::UADDO: 2436 case ISD::ADDC: 2437 case ISD::ADDE: 2438 case ISD::SADDSAT: 2439 case ISD::UADDSAT: 2440 case ISD::FMINNUM: 2441 case ISD::FMAXNUM: 2442 case ISD::FMINNUM_IEEE: 2443 case ISD::FMAXNUM_IEEE: 2444 case ISD::FMINIMUM: 2445 case ISD::FMAXIMUM: 2446 return true; 2447 default: return false; 2448 } 2449 } 2450 2451 /// Return true if the node is a math/logic binary operator. isBinOp(unsigned Opcode)2452 virtual bool isBinOp(unsigned Opcode) const { 2453 // A commutative binop must be a binop. 2454 if (isCommutativeBinOp(Opcode)) 2455 return true; 2456 // These are non-commutative binops. 2457 switch (Opcode) { 2458 case ISD::SUB: 2459 case ISD::SHL: 2460 case ISD::SRL: 2461 case ISD::SRA: 2462 case ISD::SDIV: 2463 case ISD::UDIV: 2464 case ISD::SREM: 2465 case ISD::UREM: 2466 case ISD::SSUBSAT: 2467 case ISD::USUBSAT: 2468 case ISD::FSUB: 2469 case ISD::FDIV: 2470 case ISD::FREM: 2471 return true; 2472 default: 2473 return false; 2474 } 2475 } 2476 2477 /// Return true if it's free to truncate a value of type FromTy to type 2478 /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16 2479 /// by referencing its sub-register AX. 2480 /// Targets must return false when FromTy <= ToTy. isTruncateFree(Type * FromTy,Type * ToTy)2481 virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const { 2482 return false; 2483 } 2484 2485 /// Return true if a truncation from FromTy to ToTy is permitted when deciding 2486 /// whether a call is in tail position. Typically this means that both results 2487 /// would be assigned to the same register or stack slot, but it could mean 2488 /// the target performs adequate checks of its own before proceeding with the 2489 /// tail call. Targets must return false when FromTy <= ToTy. allowTruncateForTailCall(Type * FromTy,Type * ToTy)2490 virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const { 2491 return false; 2492 } 2493 isTruncateFree(EVT FromVT,EVT ToVT)2494 virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const { 2495 return false; 2496 } 2497 isProfitableToHoist(Instruction * I)2498 virtual bool isProfitableToHoist(Instruction *I) const { return true; } 2499 2500 /// Return true if the extension represented by \p I is free. 2501 /// Unlikely the is[Z|FP]ExtFree family which is based on types, 2502 /// this method can use the context provided by \p I to decide 2503 /// whether or not \p I is free. 2504 /// This method extends the behavior of the is[Z|FP]ExtFree family. 2505 /// In other words, if is[Z|FP]Free returns true, then this method 2506 /// returns true as well. The converse is not true. 2507 /// The target can perform the adequate checks by overriding isExtFreeImpl. 2508 /// \pre \p I must be a sign, zero, or fp extension. isExtFree(const Instruction * I)2509 bool isExtFree(const Instruction *I) const { 2510 switch (I->getOpcode()) { 2511 case Instruction::FPExt: 2512 if (isFPExtFree(EVT::getEVT(I->getType()), 2513 EVT::getEVT(I->getOperand(0)->getType()))) 2514 return true; 2515 break; 2516 case Instruction::ZExt: 2517 if (isZExtFree(I->getOperand(0)->getType(), I->getType())) 2518 return true; 2519 break; 2520 case Instruction::SExt: 2521 break; 2522 default: 2523 llvm_unreachable("Instruction is not an extension"); 2524 } 2525 return isExtFreeImpl(I); 2526 } 2527 2528 /// Return true if \p Load and \p Ext can form an ExtLoad. 2529 /// For example, in AArch64 2530 /// %L = load i8, i8* %ptr 2531 /// %E = zext i8 %L to i32 2532 /// can be lowered into one load instruction 2533 /// ldrb w0, [x0] isExtLoad(const LoadInst * Load,const Instruction * Ext,const DataLayout & DL)2534 bool isExtLoad(const LoadInst *Load, const Instruction *Ext, 2535 const DataLayout &DL) const { 2536 EVT VT = getValueType(DL, Ext->getType()); 2537 EVT LoadVT = getValueType(DL, Load->getType()); 2538 2539 // If the load has other users and the truncate is not free, the ext 2540 // probably isn't free. 2541 if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) && 2542 !isTruncateFree(Ext->getType(), Load->getType())) 2543 return false; 2544 2545 // Check whether the target supports casts folded into loads. 2546 unsigned LType; 2547 if (isa<ZExtInst>(Ext)) 2548 LType = ISD::ZEXTLOAD; 2549 else { 2550 assert(isa<SExtInst>(Ext) && "Unexpected ext type!"); 2551 LType = ISD::SEXTLOAD; 2552 } 2553 2554 return isLoadExtLegal(LType, VT, LoadVT); 2555 } 2556 2557 /// Return true if any actual instruction that defines a value of type FromTy 2558 /// implicitly zero-extends the value to ToTy in the result register. 2559 /// 2560 /// The function should return true when it is likely that the truncate can 2561 /// be freely folded with an instruction defining a value of FromTy. If 2562 /// the defining instruction is unknown (because you're looking at a 2563 /// function argument, PHI, etc.) then the target may require an 2564 /// explicit truncate, which is not necessarily free, but this function 2565 /// does not deal with those cases. 2566 /// Targets must return false when FromTy >= ToTy. isZExtFree(Type * FromTy,Type * ToTy)2567 virtual bool isZExtFree(Type *FromTy, Type *ToTy) const { 2568 return false; 2569 } 2570 isZExtFree(EVT FromTy,EVT ToTy)2571 virtual bool isZExtFree(EVT FromTy, EVT ToTy) const { 2572 return false; 2573 } 2574 2575 /// Return true if sign-extension from FromTy to ToTy is cheaper than 2576 /// zero-extension. isSExtCheaperThanZExt(EVT FromTy,EVT ToTy)2577 virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const { 2578 return false; 2579 } 2580 2581 /// Return true if sinking I's operands to the same basic block as I is 2582 /// profitable, e.g. because the operands can be folded into a target 2583 /// instruction during instruction selection. After calling the function 2584 /// \p Ops contains the Uses to sink ordered by dominance (dominating users 2585 /// come first). shouldSinkOperands(Instruction * I,SmallVectorImpl<Use * > & Ops)2586 virtual bool shouldSinkOperands(Instruction *I, 2587 SmallVectorImpl<Use *> &Ops) const { 2588 return false; 2589 } 2590 2591 /// Return true if the target supplies and combines to a paired load 2592 /// two loaded values of type LoadedType next to each other in memory. 2593 /// RequiredAlignment gives the minimal alignment constraints that must be met 2594 /// to be able to select this paired load. 2595 /// 2596 /// This information is *not* used to generate actual paired loads, but it is 2597 /// used to generate a sequence of loads that is easier to combine into a 2598 /// paired load. 2599 /// For instance, something like this: 2600 /// a = load i64* addr 2601 /// b = trunc i64 a to i32 2602 /// c = lshr i64 a, 32 2603 /// d = trunc i64 c to i32 2604 /// will be optimized into: 2605 /// b = load i32* addr1 2606 /// d = load i32* addr2 2607 /// Where addr1 = addr2 +/- sizeof(i32). 2608 /// 2609 /// In other words, unless the target performs a post-isel load combining, 2610 /// this information should not be provided because it will generate more 2611 /// loads. hasPairedLoad(EVT,Align &)2612 virtual bool hasPairedLoad(EVT /*LoadedType*/, 2613 Align & /*RequiredAlignment*/) const { 2614 return false; 2615 } 2616 2617 /// Return true if the target has a vector blend instruction. hasVectorBlend()2618 virtual bool hasVectorBlend() const { return false; } 2619 2620 /// Get the maximum supported factor for interleaved memory accesses. 2621 /// Default to be the minimum interleave factor: 2. getMaxSupportedInterleaveFactor()2622 virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; } 2623 2624 /// Lower an interleaved load to target specific intrinsics. Return 2625 /// true on success. 2626 /// 2627 /// \p LI is the vector load instruction. 2628 /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector. 2629 /// \p Indices is the corresponding indices for each shufflevector. 2630 /// \p Factor is the interleave factor. lowerInterleavedLoad(LoadInst * LI,ArrayRef<ShuffleVectorInst * > Shuffles,ArrayRef<unsigned> Indices,unsigned Factor)2631 virtual bool lowerInterleavedLoad(LoadInst *LI, 2632 ArrayRef<ShuffleVectorInst *> Shuffles, 2633 ArrayRef<unsigned> Indices, 2634 unsigned Factor) const { 2635 return false; 2636 } 2637 2638 /// Lower an interleaved store to target specific intrinsics. Return 2639 /// true on success. 2640 /// 2641 /// \p SI is the vector store instruction. 2642 /// \p SVI is the shufflevector to RE-interleave the stored vector. 2643 /// \p Factor is the interleave factor. lowerInterleavedStore(StoreInst * SI,ShuffleVectorInst * SVI,unsigned Factor)2644 virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, 2645 unsigned Factor) const { 2646 return false; 2647 } 2648 2649 /// Return true if zero-extending the specific node Val to type VT2 is free 2650 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or 2651 /// because it's folded such as X86 zero-extending loads). isZExtFree(SDValue Val,EVT VT2)2652 virtual bool isZExtFree(SDValue Val, EVT VT2) const { 2653 return isZExtFree(Val.getValueType(), VT2); 2654 } 2655 2656 /// Return true if an fpext operation is free (for instance, because 2657 /// single-precision floating-point numbers are implicitly extended to 2658 /// double-precision). isFPExtFree(EVT DestVT,EVT SrcVT)2659 virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const { 2660 assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() && 2661 "invalid fpext types"); 2662 return false; 2663 } 2664 2665 /// Return true if an fpext operation input to an \p Opcode operation is free 2666 /// (for instance, because half-precision floating-point numbers are 2667 /// implicitly extended to float-precision) for an FMA instruction. isFPExtFoldable(const SelectionDAG & DAG,unsigned Opcode,EVT DestVT,EVT SrcVT)2668 virtual bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, 2669 EVT DestVT, EVT SrcVT) const { 2670 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && 2671 "invalid fpext types"); 2672 return isFPExtFree(DestVT, SrcVT); 2673 } 2674 2675 /// Return true if folding a vector load into ExtVal (a sign, zero, or any 2676 /// extend node) is profitable. isVectorLoadExtDesirable(SDValue ExtVal)2677 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; } 2678 2679 /// Return true if an fneg operation is free to the point where it is never 2680 /// worthwhile to replace it with a bitwise operation. isFNegFree(EVT VT)2681 virtual bool isFNegFree(EVT VT) const { 2682 assert(VT.isFloatingPoint()); 2683 return false; 2684 } 2685 2686 /// Return true if an fabs operation is free to the point where it is never 2687 /// worthwhile to replace it with a bitwise operation. isFAbsFree(EVT VT)2688 virtual bool isFAbsFree(EVT VT) const { 2689 assert(VT.isFloatingPoint()); 2690 return false; 2691 } 2692 2693 /// Return true if an FMA operation is faster than a pair of fmul and fadd 2694 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method 2695 /// returns true, otherwise fmuladd is expanded to fmul + fadd. 2696 /// 2697 /// NOTE: This may be called before legalization on types for which FMAs are 2698 /// not legal, but should return true if those types will eventually legalize 2699 /// to types that support FMAs. After legalization, it will only be called on 2700 /// types that support FMAs (via Legal or Custom actions) isFMAFasterThanFMulAndFAdd(const MachineFunction & MF,EVT)2701 virtual bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 2702 EVT) const { 2703 return false; 2704 } 2705 2706 /// IR version isFMAFasterThanFMulAndFAdd(const Function & F,Type *)2707 virtual bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *) const { 2708 return false; 2709 } 2710 2711 /// Returns true if be combined with to form an ISD::FMAD. \p N may be an 2712 /// ISD::FADD, ISD::FSUB, or an ISD::FMUL which will be distributed into an 2713 /// fadd/fsub. isFMADLegal(const SelectionDAG & DAG,const SDNode * N)2714 virtual bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const { 2715 assert((N->getOpcode() == ISD::FADD || N->getOpcode() == ISD::FSUB || 2716 N->getOpcode() == ISD::FMUL) && 2717 "unexpected node in FMAD forming combine"); 2718 return isOperationLegal(ISD::FMAD, N->getValueType(0)); 2719 } 2720 2721 // Return true when the decision to generate FMA's (or FMS, FMLA etc) rather 2722 // than FMUL and ADD is delegated to the machine combiner. generateFMAsInMachineCombiner(EVT VT,CodeGenOpt::Level OptLevel)2723 virtual bool generateFMAsInMachineCombiner(EVT VT, 2724 CodeGenOpt::Level OptLevel) const { 2725 return false; 2726 } 2727 2728 /// Return true if it's profitable to narrow operations of type VT1 to 2729 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from 2730 /// i32 to i16. isNarrowingProfitable(EVT,EVT)2731 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const { 2732 return false; 2733 } 2734 2735 /// Return true if it is beneficial to convert a load of a constant to 2736 /// just the constant itself. 2737 /// On some targets it might be more efficient to use a combination of 2738 /// arithmetic instructions to materialize the constant instead of loading it 2739 /// from a constant pool. shouldConvertConstantLoadToIntImm(const APInt & Imm,Type * Ty)2740 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 2741 Type *Ty) const { 2742 return false; 2743 } 2744 2745 /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type 2746 /// from this source type with this index. This is needed because 2747 /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of 2748 /// the first element, and only the target knows which lowering is cheap. isExtractSubvectorCheap(EVT ResVT,EVT SrcVT,unsigned Index)2749 virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 2750 unsigned Index) const { 2751 return false; 2752 } 2753 2754 /// Try to convert an extract element of a vector binary operation into an 2755 /// extract element followed by a scalar operation. shouldScalarizeBinop(SDValue VecOp)2756 virtual bool shouldScalarizeBinop(SDValue VecOp) const { 2757 return false; 2758 } 2759 2760 /// Return true if extraction of a scalar element from the given vector type 2761 /// at the given index is cheap. For example, if scalar operations occur on 2762 /// the same register file as vector operations, then an extract element may 2763 /// be a sub-register rename rather than an actual instruction. isExtractVecEltCheap(EVT VT,unsigned Index)2764 virtual bool isExtractVecEltCheap(EVT VT, unsigned Index) const { 2765 return false; 2766 } 2767 2768 /// Try to convert math with an overflow comparison into the corresponding DAG 2769 /// node operation. Targets may want to override this independently of whether 2770 /// the operation is legal/custom for the given type because it may obscure 2771 /// matching of other patterns. shouldFormOverflowOp(unsigned Opcode,EVT VT,bool MathUsed)2772 virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, 2773 bool MathUsed) const { 2774 // TODO: The default logic is inherited from code in CodeGenPrepare. 2775 // The opcode should not make a difference by default? 2776 if (Opcode != ISD::UADDO) 2777 return false; 2778 2779 // Allow the transform as long as we have an integer type that is not 2780 // obviously illegal and unsupported and if the math result is used 2781 // besides the overflow check. On some targets (e.g. SPARC), it is 2782 // not profitable to form on overflow op if the math result has no 2783 // concrete users. 2784 if (VT.isVector()) 2785 return false; 2786 return MathUsed && (VT.isSimple() || !isOperationExpand(Opcode, VT)); 2787 } 2788 2789 // Return true if it is profitable to use a scalar input to a BUILD_VECTOR 2790 // even if the vector itself has multiple uses. aggressivelyPreferBuildVectorSources(EVT VecVT)2791 virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const { 2792 return false; 2793 } 2794 2795 // Return true if CodeGenPrepare should consider splitting large offset of a 2796 // GEP to make the GEP fit into the addressing mode and can be sunk into the 2797 // same blocks of its users. shouldConsiderGEPOffsetSplit()2798 virtual bool shouldConsiderGEPOffsetSplit() const { return false; } 2799 2800 /// Return true if creating a shift of the type by the given 2801 /// amount is not profitable. shouldAvoidTransformToShift(EVT VT,unsigned Amount)2802 virtual bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const { 2803 return false; 2804 } 2805 2806 /// Does this target require the clearing of high-order bits in a register 2807 /// passed to the fp16 to fp conversion library function. shouldKeepZExtForFP16Conv()2808 virtual bool shouldKeepZExtForFP16Conv() const { return false; } 2809 2810 //===--------------------------------------------------------------------===// 2811 // Runtime Library hooks 2812 // 2813 2814 /// Rename the default libcall routine name for the specified libcall. setLibcallName(RTLIB::Libcall Call,const char * Name)2815 void setLibcallName(RTLIB::Libcall Call, const char *Name) { 2816 LibcallRoutineNames[Call] = Name; 2817 } 2818 2819 /// Get the libcall routine name for the specified libcall. getLibcallName(RTLIB::Libcall Call)2820 const char *getLibcallName(RTLIB::Libcall Call) const { 2821 return LibcallRoutineNames[Call]; 2822 } 2823 2824 /// Override the default CondCode to be used to test the result of the 2825 /// comparison libcall against zero. setCmpLibcallCC(RTLIB::Libcall Call,ISD::CondCode CC)2826 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { 2827 CmpLibcallCCs[Call] = CC; 2828 } 2829 2830 /// Get the CondCode that's to be used to test the result of the comparison 2831 /// libcall against zero. getCmpLibcallCC(RTLIB::Libcall Call)2832 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { 2833 return CmpLibcallCCs[Call]; 2834 } 2835 2836 /// Set the CallingConv that should be used for the specified libcall. setLibcallCallingConv(RTLIB::Libcall Call,CallingConv::ID CC)2837 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) { 2838 LibcallCallingConvs[Call] = CC; 2839 } 2840 2841 /// Get the CallingConv that should be used for the specified libcall. getLibcallCallingConv(RTLIB::Libcall Call)2842 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const { 2843 return LibcallCallingConvs[Call]; 2844 } 2845 2846 /// Execute target specific actions to finalize target lowering. 2847 /// This is used to set extra flags in MachineFrameInformation and freezing 2848 /// the set of reserved registers. 2849 /// The default implementation just freezes the set of reserved registers. 2850 virtual void finalizeLowering(MachineFunction &MF) const; 2851 2852 //===----------------------------------------------------------------------===// 2853 // GlobalISel Hooks 2854 //===----------------------------------------------------------------------===// 2855 /// Check whether or not \p MI needs to be moved close to its uses. 2856 virtual bool shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) const; 2857 2858 2859 private: 2860 const TargetMachine &TM; 2861 2862 /// Tells the code generator that the target has multiple (allocatable) 2863 /// condition registers that can be used to store the results of comparisons 2864 /// for use by selects and conditional branches. With multiple condition 2865 /// registers, the code generator will not aggressively sink comparisons into 2866 /// the blocks of their users. 2867 bool HasMultipleConditionRegisters; 2868 2869 /// Tells the code generator that the target has BitExtract instructions. 2870 /// The code generator will aggressively sink "shift"s into the blocks of 2871 /// their users if the users will generate "and" instructions which can be 2872 /// combined with "shift" to BitExtract instructions. 2873 bool HasExtractBitsInsn; 2874 2875 /// Tells the code generator to bypass slow divide or remainder 2876 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code 2877 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer 2878 /// div/rem when the operands are positive and less than 256. 2879 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths; 2880 2881 /// Tells the code generator that it shouldn't generate extra flow control 2882 /// instructions and should attempt to combine flow control instructions via 2883 /// predication. 2884 bool JumpIsExpensive; 2885 2886 /// Information about the contents of the high-bits in boolean values held in 2887 /// a type wider than i1. See getBooleanContents. 2888 BooleanContent BooleanContents; 2889 2890 /// Information about the contents of the high-bits in boolean values held in 2891 /// a type wider than i1. See getBooleanContents. 2892 BooleanContent BooleanFloatContents; 2893 2894 /// Information about the contents of the high-bits in boolean vector values 2895 /// when the element type is wider than i1. See getBooleanContents. 2896 BooleanContent BooleanVectorContents; 2897 2898 /// The target scheduling preference: shortest possible total cycles or lowest 2899 /// register usage. 2900 Sched::Preference SchedPreferenceInfo; 2901 2902 /// The minimum alignment that any argument on the stack needs to have. 2903 Align MinStackArgumentAlignment; 2904 2905 /// The minimum function alignment (used when optimizing for size, and to 2906 /// prevent explicitly provided alignment from leading to incorrect code). 2907 Align MinFunctionAlignment; 2908 2909 /// The preferred function alignment (used when alignment unspecified and 2910 /// optimizing for speed). 2911 Align PrefFunctionAlignment; 2912 2913 /// The preferred loop alignment (in log2 bot in bytes). 2914 Align PrefLoopAlignment; 2915 2916 /// Size in bits of the maximum atomics size the backend supports. 2917 /// Accesses larger than this will be expanded by AtomicExpandPass. 2918 unsigned MaxAtomicSizeInBitsSupported; 2919 2920 /// Size in bits of the minimum cmpxchg or ll/sc operation the 2921 /// backend supports. 2922 unsigned MinCmpXchgSizeInBits; 2923 2924 /// This indicates if the target supports unaligned atomic operations. 2925 bool SupportsUnalignedAtomics; 2926 2927 /// If set to a physical register, this specifies the register that 2928 /// llvm.savestack/llvm.restorestack should save and restore. 2929 Register StackPointerRegisterToSaveRestore; 2930 2931 /// This indicates the default register class to use for each ValueType the 2932 /// target supports natively. 2933 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE]; 2934 uint16_t NumRegistersForVT[MVT::LAST_VALUETYPE]; 2935 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]; 2936 2937 /// This indicates the "representative" register class to use for each 2938 /// ValueType the target supports natively. This information is used by the 2939 /// scheduler to track register pressure. By default, the representative 2940 /// register class is the largest legal super-reg register class of the 2941 /// register class of the specified type. e.g. On x86, i8, i16, and i32's 2942 /// representative class would be GR32. 2943 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE]; 2944 2945 /// This indicates the "cost" of the "representative" register class for each 2946 /// ValueType. The cost is used by the scheduler to approximate register 2947 /// pressure. 2948 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE]; 2949 2950 /// For any value types we are promoting or expanding, this contains the value 2951 /// type that we are changing to. For Expanded types, this contains one step 2952 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required 2953 /// (e.g. i64 -> i16). For types natively supported by the system, this holds 2954 /// the same type (e.g. i32 -> i32). 2955 MVT TransformToType[MVT::LAST_VALUETYPE]; 2956 2957 /// For each operation and each value type, keep a LegalizeAction that 2958 /// indicates how instruction selection should deal with the operation. Most 2959 /// operations are Legal (aka, supported natively by the target), but 2960 /// operations that are not should be described. Note that operations on 2961 /// non-legal value types are not described here. 2962 LegalizeAction OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]; 2963 2964 /// For each load extension type and each value type, keep a LegalizeAction 2965 /// that indicates how instruction selection should deal with a load of a 2966 /// specific value type and extension type. Uses 4-bits to store the action 2967 /// for each of the 4 load ext types. 2968 uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]; 2969 2970 /// For each value type pair keep a LegalizeAction that indicates whether a 2971 /// truncating store of a specific value type and truncating type is legal. 2972 LegalizeAction TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]; 2973 2974 /// For each indexed mode and each value type, keep a quad of LegalizeAction 2975 /// that indicates how instruction selection should deal with the load / 2976 /// store / maskedload / maskedstore. 2977 /// 2978 /// The first dimension is the value_type for the reference. The second 2979 /// dimension represents the various modes for load store. 2980 uint16_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]; 2981 2982 /// For each condition code (ISD::CondCode) keep a LegalizeAction that 2983 /// indicates how instruction selection should deal with the condition code. 2984 /// 2985 /// Because each CC action takes up 4 bits, we need to have the array size be 2986 /// large enough to fit all of the value types. This can be done by rounding 2987 /// up the MVT::LAST_VALUETYPE value to the next multiple of 8. 2988 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8]; 2989 2990 ValueTypeActionImpl ValueTypeActions; 2991 2992 private: 2993 LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const; 2994 2995 /// Targets can specify ISD nodes that they would like PerformDAGCombine 2996 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this 2997 /// array. 2998 unsigned char 2999 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]; 3000 3001 /// For operations that must be promoted to a specific type, this holds the 3002 /// destination type. This map should be sparse, so don't hold it as an 3003 /// array. 3004 /// 3005 /// Targets add entries to this map with AddPromotedToType(..), clients access 3006 /// this with getTypeToPromoteTo(..). 3007 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType> 3008 PromoteToType; 3009 3010 /// Stores the name each libcall. 3011 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1]; 3012 3013 /// The ISD::CondCode that should be used to test the result of each of the 3014 /// comparison libcall against zero. 3015 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]; 3016 3017 /// Stores the CallingConv that should be used for each libcall. 3018 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]; 3019 3020 /// Set default libcall names and calling conventions. 3021 void InitLibcalls(const Triple &TT); 3022 3023 /// The bits of IndexedModeActions used to store the legalisation actions 3024 /// We store the data as | ML | MS | L | S | each taking 4 bits. 3025 enum IndexedModeActionsBits { 3026 IMAB_Store = 0, 3027 IMAB_Load = 4, 3028 IMAB_MaskedStore = 8, 3029 IMAB_MaskedLoad = 12 3030 }; 3031 setIndexedModeAction(unsigned IdxMode,MVT VT,unsigned Shift,LegalizeAction Action)3032 void setIndexedModeAction(unsigned IdxMode, MVT VT, unsigned Shift, 3033 LegalizeAction Action) { 3034 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE && 3035 (unsigned)Action < 0xf && "Table isn't big enough!"); 3036 unsigned Ty = (unsigned)VT.SimpleTy; 3037 IndexedModeActions[Ty][IdxMode] &= ~(0xf << Shift); 3038 IndexedModeActions[Ty][IdxMode] |= ((uint16_t)Action) << Shift; 3039 } 3040 getIndexedModeAction(unsigned IdxMode,MVT VT,unsigned Shift)3041 LegalizeAction getIndexedModeAction(unsigned IdxMode, MVT VT, 3042 unsigned Shift) const { 3043 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() && 3044 "Table isn't big enough!"); 3045 unsigned Ty = (unsigned)VT.SimpleTy; 3046 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] >> Shift) & 0xf); 3047 } 3048 3049 protected: 3050 /// Return true if the extension represented by \p I is free. 3051 /// \pre \p I is a sign, zero, or fp extension and 3052 /// is[Z|FP]ExtFree of the related types is not true. isExtFreeImpl(const Instruction * I)3053 virtual bool isExtFreeImpl(const Instruction *I) const { return false; } 3054 3055 /// Depth that GatherAllAliases should should continue looking for chain 3056 /// dependencies when trying to find a more preferable chain. As an 3057 /// approximation, this should be more than the number of consecutive stores 3058 /// expected to be merged. 3059 unsigned GatherAllAliasesMaxDepth; 3060 3061 /// \brief Specify maximum number of store instructions per memset call. 3062 /// 3063 /// When lowering \@llvm.memset this field specifies the maximum number of 3064 /// store operations that may be substituted for the call to memset. Targets 3065 /// must set this value based on the cost threshold for that target. Targets 3066 /// should assume that the memset will be done using as many of the largest 3067 /// store operations first, followed by smaller ones, if necessary, per 3068 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine 3069 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte 3070 /// store. This only applies to setting a constant array of a constant size. 3071 unsigned MaxStoresPerMemset; 3072 /// Likewise for functions with the OptSize attribute. 3073 unsigned MaxStoresPerMemsetOptSize; 3074 3075 /// \brief Specify maximum number of store instructions per memcpy call. 3076 /// 3077 /// When lowering \@llvm.memcpy this field specifies the maximum number of 3078 /// store operations that may be substituted for a call to memcpy. Targets 3079 /// must set this value based on the cost threshold for that target. Targets 3080 /// should assume that the memcpy will be done using as many of the largest 3081 /// store operations first, followed by smaller ones, if necessary, per 3082 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine 3083 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store 3084 /// and one 1-byte store. This only applies to copying a constant array of 3085 /// constant size. 3086 unsigned MaxStoresPerMemcpy; 3087 /// Likewise for functions with the OptSize attribute. 3088 unsigned MaxStoresPerMemcpyOptSize; 3089 /// \brief Specify max number of store instructions to glue in inlined memcpy. 3090 /// 3091 /// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number 3092 /// of store instructions to keep together. This helps in pairing and 3093 // vectorization later on. 3094 unsigned MaxGluedStoresPerMemcpy = 0; 3095 3096 /// \brief Specify maximum number of load instructions per memcmp call. 3097 /// 3098 /// When lowering \@llvm.memcmp this field specifies the maximum number of 3099 /// pairs of load operations that may be substituted for a call to memcmp. 3100 /// Targets must set this value based on the cost threshold for that target. 3101 /// Targets should assume that the memcmp will be done using as many of the 3102 /// largest load operations first, followed by smaller ones, if necessary, per 3103 /// alignment restrictions. For example, loading 7 bytes on a 32-bit machine 3104 /// with 32-bit alignment would result in one 4-byte load, a one 2-byte load 3105 /// and one 1-byte load. This only applies to copying a constant array of 3106 /// constant size. 3107 unsigned MaxLoadsPerMemcmp; 3108 /// Likewise for functions with the OptSize attribute. 3109 unsigned MaxLoadsPerMemcmpOptSize; 3110 3111 /// \brief Specify maximum number of store instructions per memmove call. 3112 /// 3113 /// When lowering \@llvm.memmove this field specifies the maximum number of 3114 /// store instructions that may be substituted for a call to memmove. Targets 3115 /// must set this value based on the cost threshold for that target. Targets 3116 /// should assume that the memmove will be done using as many of the largest 3117 /// store operations first, followed by smaller ones, if necessary, per 3118 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine 3119 /// with 8-bit alignment would result in nine 1-byte stores. This only 3120 /// applies to copying a constant array of constant size. 3121 unsigned MaxStoresPerMemmove; 3122 /// Likewise for functions with the OptSize attribute. 3123 unsigned MaxStoresPerMemmoveOptSize; 3124 3125 /// Tells the code generator that select is more expensive than a branch if 3126 /// the branch is usually predicted right. 3127 bool PredictableSelectIsExpensive; 3128 3129 /// \see enableExtLdPromotion. 3130 bool EnableExtLdPromotion; 3131 3132 /// Return true if the value types that can be represented by the specified 3133 /// register class are all legal. 3134 bool isLegalRC(const TargetRegisterInfo &TRI, 3135 const TargetRegisterClass &RC) const; 3136 3137 /// Replace/modify any TargetFrameIndex operands with a targte-dependent 3138 /// sequence of memory operands that is recognized by PrologEpilogInserter. 3139 MachineBasicBlock *emitPatchPoint(MachineInstr &MI, 3140 MachineBasicBlock *MBB) const; 3141 3142 bool IsStrictFPEnabled; 3143 }; 3144 3145 /// This class defines information used to lower LLVM code to legal SelectionDAG 3146 /// operators that the target instruction selector can accept natively. 3147 /// 3148 /// This class also defines callbacks that targets must implement to lower 3149 /// target-specific constructs to SelectionDAG operators. 3150 class TargetLowering : public TargetLoweringBase { 3151 public: 3152 struct DAGCombinerInfo; 3153 struct MakeLibCallOptions; 3154 3155 TargetLowering(const TargetLowering &) = delete; 3156 TargetLowering &operator=(const TargetLowering &) = delete; 3157 3158 explicit TargetLowering(const TargetMachine &TM); 3159 3160 bool isPositionIndependent() const; 3161 isSDNodeSourceOfDivergence(const SDNode * N,FunctionLoweringInfo * FLI,LegacyDivergenceAnalysis * DA)3162 virtual bool isSDNodeSourceOfDivergence(const SDNode *N, 3163 FunctionLoweringInfo *FLI, 3164 LegacyDivergenceAnalysis *DA) const { 3165 return false; 3166 } 3167 isSDNodeAlwaysUniform(const SDNode * N)3168 virtual bool isSDNodeAlwaysUniform(const SDNode * N) const { 3169 return false; 3170 } 3171 3172 /// Returns true by value, base pointer and offset pointer and addressing mode 3173 /// by reference if the node's address can be legally represented as 3174 /// pre-indexed load / store address. getPreIndexedAddressParts(SDNode *,SDValue &,SDValue &,ISD::MemIndexedMode &,SelectionDAG &)3175 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/, 3176 SDValue &/*Offset*/, 3177 ISD::MemIndexedMode &/*AM*/, 3178 SelectionDAG &/*DAG*/) const { 3179 return false; 3180 } 3181 3182 /// Returns true by value, base pointer and offset pointer and addressing mode 3183 /// by reference if this node can be combined with a load / store to form a 3184 /// post-indexed load / store. getPostIndexedAddressParts(SDNode *,SDNode *,SDValue &,SDValue &,ISD::MemIndexedMode &,SelectionDAG &)3185 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/, 3186 SDValue &/*Base*/, 3187 SDValue &/*Offset*/, 3188 ISD::MemIndexedMode &/*AM*/, 3189 SelectionDAG &/*DAG*/) const { 3190 return false; 3191 } 3192 3193 /// Returns true if the specified base+offset is a legal indexed addressing 3194 /// mode for this target. \p MI is the load or store instruction that is being 3195 /// considered for transformation. isIndexingLegal(MachineInstr & MI,Register Base,Register Offset,bool IsPre,MachineRegisterInfo & MRI)3196 virtual bool isIndexingLegal(MachineInstr &MI, Register Base, Register Offset, 3197 bool IsPre, MachineRegisterInfo &MRI) const { 3198 return false; 3199 } 3200 3201 /// Return the entry encoding for a jump table in the current function. The 3202 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum. 3203 virtual unsigned getJumpTableEncoding() const; 3204 3205 virtual const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *,const MachineBasicBlock *,unsigned,MCContext &)3206 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/, 3207 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/, 3208 MCContext &/*Ctx*/) const { 3209 llvm_unreachable("Need to implement this hook if target has custom JTIs"); 3210 } 3211 3212 /// Returns relocation base for the given PIC jumptable. 3213 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 3214 SelectionDAG &DAG) const; 3215 3216 /// This returns the relocation base for the given PIC jumptable, the same as 3217 /// getPICJumpTableRelocBase, but as an MCExpr. 3218 virtual const MCExpr * 3219 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 3220 unsigned JTI, MCContext &Ctx) const; 3221 3222 /// Return true if folding a constant offset with the given GlobalAddress is 3223 /// legal. It is frequently not legal in PIC relocation models. 3224 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 3225 3226 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, 3227 SDValue &Chain) const; 3228 3229 void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, 3230 SDValue &NewRHS, ISD::CondCode &CCCode, 3231 const SDLoc &DL, const SDValue OldLHS, 3232 const SDValue OldRHS) const; 3233 3234 void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, 3235 SDValue &NewRHS, ISD::CondCode &CCCode, 3236 const SDLoc &DL, const SDValue OldLHS, 3237 const SDValue OldRHS, SDValue &Chain, 3238 bool IsSignaling = false) const; 3239 3240 /// Returns a pair of (return value, chain). 3241 /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC. 3242 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, 3243 EVT RetVT, ArrayRef<SDValue> Ops, 3244 MakeLibCallOptions CallOptions, 3245 const SDLoc &dl, 3246 SDValue Chain = SDValue()) const; 3247 3248 /// Check whether parameters to a call that are passed in callee saved 3249 /// registers are the same as from the calling function. This needs to be 3250 /// checked for tail call eligibility. 3251 bool parametersInCSRMatch(const MachineRegisterInfo &MRI, 3252 const uint32_t *CallerPreservedMask, 3253 const SmallVectorImpl<CCValAssign> &ArgLocs, 3254 const SmallVectorImpl<SDValue> &OutVals) const; 3255 3256 //===--------------------------------------------------------------------===// 3257 // TargetLowering Optimization Methods 3258 // 3259 3260 /// A convenience struct that encapsulates a DAG, and two SDValues for 3261 /// returning information from TargetLowering to its clients that want to 3262 /// combine. 3263 struct TargetLoweringOpt { 3264 SelectionDAG &DAG; 3265 bool LegalTys; 3266 bool LegalOps; 3267 SDValue Old; 3268 SDValue New; 3269 TargetLoweringOptTargetLoweringOpt3270 explicit TargetLoweringOpt(SelectionDAG &InDAG, 3271 bool LT, bool LO) : 3272 DAG(InDAG), LegalTys(LT), LegalOps(LO) {} 3273 LegalTypesTargetLoweringOpt3274 bool LegalTypes() const { return LegalTys; } LegalOperationsTargetLoweringOpt3275 bool LegalOperations() const { return LegalOps; } 3276 CombineToTargetLoweringOpt3277 bool CombineTo(SDValue O, SDValue N) { 3278 Old = O; 3279 New = N; 3280 return true; 3281 } 3282 }; 3283 3284 /// Determines the optimal series of memory ops to replace the memset / memcpy. 3285 /// Return true if the number of memory ops is below the threshold (Limit). 3286 /// It returns the types of the sequence of memory ops to perform 3287 /// memset / memcpy by reference. 3288 bool findOptimalMemOpLowering(std::vector<EVT> &MemOps, unsigned Limit, 3289 const MemOp &Op, unsigned DstAS, unsigned SrcAS, 3290 const AttributeList &FuncAttributes) const; 3291 3292 /// Check to see if the specified operand of the specified instruction is a 3293 /// constant integer. If so, check to see if there are any bits set in the 3294 /// constant that are not demanded. If so, shrink the constant and return 3295 /// true. 3296 bool ShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, 3297 const APInt &DemandedElts, 3298 TargetLoweringOpt &TLO) const; 3299 3300 /// Helper wrapper around ShrinkDemandedConstant, demanding all elements. 3301 bool ShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, 3302 TargetLoweringOpt &TLO) const; 3303 3304 // Target hook to do target-specific const optimization, which is called by 3305 // ShrinkDemandedConstant. This function should return true if the target 3306 // doesn't want ShrinkDemandedConstant to further optimize the constant. targetShrinkDemandedConstant(SDValue Op,const APInt & DemandedBits,const APInt & DemandedElts,TargetLoweringOpt & TLO)3307 virtual bool targetShrinkDemandedConstant(SDValue Op, 3308 const APInt &DemandedBits, 3309 const APInt &DemandedElts, 3310 TargetLoweringOpt &TLO) const { 3311 return false; 3312 } 3313 3314 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This 3315 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be 3316 /// generalized for targets with other types of implicit widening casts. 3317 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded, 3318 TargetLoweringOpt &TLO) const; 3319 3320 /// Look at Op. At this point, we know that only the DemandedBits bits of the 3321 /// result of Op are ever used downstream. If we can use this information to 3322 /// simplify Op, create a new simplified DAG node and return true, returning 3323 /// the original and new nodes in Old and New. Otherwise, analyze the 3324 /// expression and return a mask of KnownOne and KnownZero bits for the 3325 /// expression (used to simplify the caller). The KnownZero/One bits may only 3326 /// be accurate for those bits in the Demanded masks. 3327 /// \p AssumeSingleUse When this parameter is true, this function will 3328 /// attempt to simplify \p Op even if there are multiple uses. 3329 /// Callers are responsible for correctly updating the DAG based on the 3330 /// results of this function, because simply replacing replacing TLO.Old 3331 /// with TLO.New will be incorrect when this parameter is true and TLO.Old 3332 /// has multiple uses. 3333 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, 3334 const APInt &DemandedElts, KnownBits &Known, 3335 TargetLoweringOpt &TLO, unsigned Depth = 0, 3336 bool AssumeSingleUse = false) const; 3337 3338 /// Helper wrapper around SimplifyDemandedBits, demanding all elements. 3339 /// Adds Op back to the worklist upon success. 3340 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, 3341 KnownBits &Known, TargetLoweringOpt &TLO, 3342 unsigned Depth = 0, 3343 bool AssumeSingleUse = false) const; 3344 3345 /// Helper wrapper around SimplifyDemandedBits. 3346 /// Adds Op back to the worklist upon success. 3347 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, 3348 DAGCombinerInfo &DCI) const; 3349 3350 /// More limited version of SimplifyDemandedBits that can be used to "look 3351 /// through" ops that don't contribute to the DemandedBits/DemandedElts - 3352 /// bitwise ops etc. 3353 SDValue SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits, 3354 const APInt &DemandedElts, 3355 SelectionDAG &DAG, 3356 unsigned Depth) const; 3357 3358 /// Helper wrapper around SimplifyMultipleUseDemandedBits, demanding all 3359 /// elements. 3360 SDValue SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits, 3361 SelectionDAG &DAG, 3362 unsigned Depth = 0) const; 3363 3364 /// Helper wrapper around SimplifyMultipleUseDemandedBits, demanding all 3365 /// bits from only some vector elements. 3366 SDValue SimplifyMultipleUseDemandedVectorElts(SDValue Op, 3367 const APInt &DemandedElts, 3368 SelectionDAG &DAG, 3369 unsigned Depth = 0) const; 3370 3371 /// Look at Vector Op. At this point, we know that only the DemandedElts 3372 /// elements of the result of Op are ever used downstream. If we can use 3373 /// this information to simplify Op, create a new simplified DAG node and 3374 /// return true, storing the original and new nodes in TLO. 3375 /// Otherwise, analyze the expression and return a mask of KnownUndef and 3376 /// KnownZero elements for the expression (used to simplify the caller). 3377 /// The KnownUndef/Zero elements may only be accurate for those bits 3378 /// in the DemandedMask. 3379 /// \p AssumeSingleUse When this parameter is true, this function will 3380 /// attempt to simplify \p Op even if there are multiple uses. 3381 /// Callers are responsible for correctly updating the DAG based on the 3382 /// results of this function, because simply replacing replacing TLO.Old 3383 /// with TLO.New will be incorrect when this parameter is true and TLO.Old 3384 /// has multiple uses. 3385 bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask, 3386 APInt &KnownUndef, APInt &KnownZero, 3387 TargetLoweringOpt &TLO, unsigned Depth = 0, 3388 bool AssumeSingleUse = false) const; 3389 3390 /// Helper wrapper around SimplifyDemandedVectorElts. 3391 /// Adds Op back to the worklist upon success. 3392 bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts, 3393 APInt &KnownUndef, APInt &KnownZero, 3394 DAGCombinerInfo &DCI) const; 3395 3396 /// Determine which of the bits specified in Mask are known to be either zero 3397 /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts 3398 /// argument allows us to only collect the known bits that are shared by the 3399 /// requested vector elements. 3400 virtual void computeKnownBitsForTargetNode(const SDValue Op, 3401 KnownBits &Known, 3402 const APInt &DemandedElts, 3403 const SelectionDAG &DAG, 3404 unsigned Depth = 0) const; 3405 3406 /// Determine which of the bits specified in Mask are known to be either zero 3407 /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts 3408 /// argument allows us to only collect the known bits that are shared by the 3409 /// requested vector elements. This is for GISel. 3410 virtual void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, 3411 Register R, KnownBits &Known, 3412 const APInt &DemandedElts, 3413 const MachineRegisterInfo &MRI, 3414 unsigned Depth = 0) const; 3415 3416 /// Determine the known alignment for the pointer value \p R. This is can 3417 /// typically be inferred from the number of low known 0 bits. However, for a 3418 /// pointer with a non-integral address space, the alignment value may be 3419 /// independent from the known low bits. 3420 virtual Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, 3421 Register R, 3422 const MachineRegisterInfo &MRI, 3423 unsigned Depth = 0) const; 3424 3425 /// Determine which of the bits of FrameIndex \p FIOp are known to be 0. 3426 /// Default implementation computes low bits based on alignment 3427 /// information. This should preserve known bits passed into it. 3428 virtual void computeKnownBitsForFrameIndex(int FIOp, 3429 KnownBits &Known, 3430 const MachineFunction &MF) const; 3431 3432 /// This method can be implemented by targets that want to expose additional 3433 /// information about sign bits to the DAG Combiner. The DemandedElts 3434 /// argument allows us to only collect the minimum sign bits that are shared 3435 /// by the requested vector elements. 3436 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 3437 const APInt &DemandedElts, 3438 const SelectionDAG &DAG, 3439 unsigned Depth = 0) const; 3440 3441 /// This method can be implemented by targets that want to expose additional 3442 /// information about sign bits to GlobalISel combiners. The DemandedElts 3443 /// argument allows us to only collect the minimum sign bits that are shared 3444 /// by the requested vector elements. 3445 virtual unsigned computeNumSignBitsForTargetInstr(GISelKnownBits &Analysis, 3446 Register R, 3447 const APInt &DemandedElts, 3448 const MachineRegisterInfo &MRI, 3449 unsigned Depth = 0) const; 3450 3451 /// Attempt to simplify any target nodes based on the demanded vector 3452 /// elements, returning true on success. Otherwise, analyze the expression and 3453 /// return a mask of KnownUndef and KnownZero elements for the expression 3454 /// (used to simplify the caller). The KnownUndef/Zero elements may only be 3455 /// accurate for those bits in the DemandedMask. 3456 virtual bool SimplifyDemandedVectorEltsForTargetNode( 3457 SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, 3458 APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const; 3459 3460 /// Attempt to simplify any target nodes based on the demanded bits/elts, 3461 /// returning true on success. Otherwise, analyze the 3462 /// expression and return a mask of KnownOne and KnownZero bits for the 3463 /// expression (used to simplify the caller). The KnownZero/One bits may only 3464 /// be accurate for those bits in the Demanded masks. 3465 virtual bool SimplifyDemandedBitsForTargetNode(SDValue Op, 3466 const APInt &DemandedBits, 3467 const APInt &DemandedElts, 3468 KnownBits &Known, 3469 TargetLoweringOpt &TLO, 3470 unsigned Depth = 0) const; 3471 3472 /// More limited version of SimplifyDemandedBits that can be used to "look 3473 /// through" ops that don't contribute to the DemandedBits/DemandedElts - 3474 /// bitwise ops etc. 3475 virtual SDValue SimplifyMultipleUseDemandedBitsForTargetNode( 3476 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, 3477 SelectionDAG &DAG, unsigned Depth) const; 3478 3479 /// Tries to build a legal vector shuffle using the provided parameters 3480 /// or equivalent variations. The Mask argument maybe be modified as the 3481 /// function tries different variations. 3482 /// Returns an empty SDValue if the operation fails. 3483 SDValue buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0, 3484 SDValue N1, MutableArrayRef<int> Mask, 3485 SelectionDAG &DAG) const; 3486 3487 /// This method returns the constant pool value that will be loaded by LD. 3488 /// NOTE: You must check for implicit extensions of the constant by LD. 3489 virtual const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const; 3490 3491 /// If \p SNaN is false, \returns true if \p Op is known to never be any 3492 /// NaN. If \p sNaN is true, returns if \p Op is known to never be a signaling 3493 /// NaN. 3494 virtual bool isKnownNeverNaNForTargetNode(SDValue Op, 3495 const SelectionDAG &DAG, 3496 bool SNaN = false, 3497 unsigned Depth = 0) const; 3498 struct DAGCombinerInfo { 3499 void *DC; // The DAG Combiner object. 3500 CombineLevel Level; 3501 bool CalledByLegalizer; 3502 3503 public: 3504 SelectionDAG &DAG; 3505 DAGCombinerInfoDAGCombinerInfo3506 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc) 3507 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {} 3508 isBeforeLegalizeDAGCombinerInfo3509 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; } isBeforeLegalizeOpsDAGCombinerInfo3510 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; } isAfterLegalizeDAGDAGCombinerInfo3511 bool isAfterLegalizeDAG() const { return Level >= AfterLegalizeDAG; } getDAGCombineLevelDAGCombinerInfo3512 CombineLevel getDAGCombineLevel() { return Level; } isCalledByLegalizerDAGCombinerInfo3513 bool isCalledByLegalizer() const { return CalledByLegalizer; } 3514 3515 void AddToWorklist(SDNode *N); 3516 SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true); 3517 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true); 3518 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true); 3519 3520 bool recursivelyDeleteUnusedNodes(SDNode *N); 3521 3522 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO); 3523 }; 3524 3525 /// Return if the N is a constant or constant vector equal to the true value 3526 /// from getBooleanContents(). 3527 bool isConstTrueVal(const SDNode *N) const; 3528 3529 /// Return if the N is a constant or constant vector equal to the false value 3530 /// from getBooleanContents(). 3531 bool isConstFalseVal(const SDNode *N) const; 3532 3533 /// Return if \p N is a True value when extended to \p VT. 3534 bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const; 3535 3536 /// Try to simplify a setcc built with the specified operands and cc. If it is 3537 /// unable to simplify it, return a null SDValue. 3538 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 3539 bool foldBooleans, DAGCombinerInfo &DCI, 3540 const SDLoc &dl) const; 3541 3542 // For targets which wrap address, unwrap for analysis. unwrapAddress(SDValue N)3543 virtual SDValue unwrapAddress(SDValue N) const { return N; } 3544 3545 /// Returns true (and the GlobalValue and the offset) if the node is a 3546 /// GlobalAddress + offset. 3547 virtual bool 3548 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 3549 3550 /// This method will be invoked for all target nodes and for any 3551 /// target-independent nodes that the target has registered with invoke it 3552 /// for. 3553 /// 3554 /// The semantics are as follows: 3555 /// Return Value: 3556 /// SDValue.Val == 0 - No change was made 3557 /// SDValue.Val == N - N was replaced, is dead, and is already handled. 3558 /// otherwise - N should be replaced by the returned Operand. 3559 /// 3560 /// In addition, methods provided by DAGCombinerInfo may be used to perform 3561 /// more complex transformations. 3562 /// 3563 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 3564 3565 /// Return true if it is profitable to move this shift by a constant amount 3566 /// though its operand, adjusting any immediate operands as necessary to 3567 /// preserve semantics. This transformation may not be desirable if it 3568 /// disrupts a particularly auspicious target-specific tree (e.g. bitfield 3569 /// extraction in AArch64). By default, it returns true. 3570 /// 3571 /// @param N the shift node 3572 /// @param Level the current DAGCombine legalization level. isDesirableToCommuteWithShift(const SDNode * N,CombineLevel Level)3573 virtual bool isDesirableToCommuteWithShift(const SDNode *N, 3574 CombineLevel Level) const { 3575 return true; 3576 } 3577 3578 /// Return true if the target has native support for the specified value type 3579 /// and it is 'desirable' to use the type for the given node type. e.g. On x86 3580 /// i16 is legal, but undesirable since i16 instruction encodings are longer 3581 /// and some i16 instructions are slow. isTypeDesirableForOp(unsigned,EVT VT)3582 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const { 3583 // By default, assume all legal types are desirable. 3584 return isTypeLegal(VT); 3585 } 3586 3587 /// Return true if it is profitable for dag combiner to transform a floating 3588 /// point op of specified opcode to a equivalent op of an integer 3589 /// type. e.g. f32 load -> i32 load can be profitable on ARM. isDesirableToTransformToIntegerOp(unsigned,EVT)3590 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/, 3591 EVT /*VT*/) const { 3592 return false; 3593 } 3594 3595 /// This method query the target whether it is beneficial for dag combiner to 3596 /// promote the specified node. If true, it should return the desired 3597 /// promotion type by reference. IsDesirableToPromoteOp(SDValue,EVT &)3598 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const { 3599 return false; 3600 } 3601 3602 /// Return true if the target supports swifterror attribute. It optimizes 3603 /// loads and stores to reading and writing a specific register. supportSwiftError()3604 virtual bool supportSwiftError() const { 3605 return false; 3606 } 3607 3608 /// Return true if the target supports that a subset of CSRs for the given 3609 /// machine function is handled explicitly via copies. supportSplitCSR(MachineFunction * MF)3610 virtual bool supportSplitCSR(MachineFunction *MF) const { 3611 return false; 3612 } 3613 3614 /// Perform necessary initialization to handle a subset of CSRs explicitly 3615 /// via copies. This function is called at the beginning of instruction 3616 /// selection. initializeSplitCSR(MachineBasicBlock * Entry)3617 virtual void initializeSplitCSR(MachineBasicBlock *Entry) const { 3618 llvm_unreachable("Not Implemented"); 3619 } 3620 3621 /// Insert explicit copies in entry and exit blocks. We copy a subset of 3622 /// CSRs to virtual registers in the entry block, and copy them back to 3623 /// physical registers in the exit blocks. This function is called at the end 3624 /// of instruction selection. insertCopiesSplitCSR(MachineBasicBlock * Entry,const SmallVectorImpl<MachineBasicBlock * > & Exits)3625 virtual void insertCopiesSplitCSR( 3626 MachineBasicBlock *Entry, 3627 const SmallVectorImpl<MachineBasicBlock *> &Exits) const { 3628 llvm_unreachable("Not Implemented"); 3629 } 3630 3631 /// Return the newly negated expression if the cost is not expensive and 3632 /// set the cost in \p Cost to indicate that if it is cheaper or neutral to 3633 /// do the negation. 3634 virtual SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, 3635 bool LegalOps, bool OptForSize, 3636 NegatibleCost &Cost, 3637 unsigned Depth = 0) const; 3638 3639 /// This is the helper function to return the newly negated expression only 3640 /// when the cost is cheaper. 3641 SDValue getCheaperNegatedExpression(SDValue Op, SelectionDAG &DAG, 3642 bool LegalOps, bool OptForSize, 3643 unsigned Depth = 0) const { 3644 NegatibleCost Cost = NegatibleCost::Expensive; 3645 SDValue Neg = 3646 getNegatedExpression(Op, DAG, LegalOps, OptForSize, Cost, Depth); 3647 if (Neg && Cost == NegatibleCost::Cheaper) 3648 return Neg; 3649 // Remove the new created node to avoid the side effect to the DAG. 3650 if (Neg && Neg.getNode()->use_empty()) 3651 DAG.RemoveDeadNode(Neg.getNode()); 3652 return SDValue(); 3653 } 3654 3655 /// This is the helper function to return the newly negated expression if 3656 /// the cost is not expensive. 3657 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, 3658 bool OptForSize, unsigned Depth = 0) const { 3659 NegatibleCost Cost = NegatibleCost::Expensive; 3660 return getNegatedExpression(Op, DAG, LegalOps, OptForSize, Cost, Depth); 3661 } 3662 3663 //===--------------------------------------------------------------------===// 3664 // Lowering methods - These methods must be implemented by targets so that 3665 // the SelectionDAGBuilder code knows how to lower these. 3666 // 3667 3668 /// Target-specific splitting of values into parts that fit a register 3669 /// storing a legal type splitValueIntoRegisterParts(SelectionDAG & DAG,const SDLoc & DL,SDValue Val,SDValue * Parts,unsigned NumParts,MVT PartVT,Optional<CallingConv::ID> CC)3670 virtual bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, 3671 SDValue Val, SDValue *Parts, 3672 unsigned NumParts, MVT PartVT, 3673 Optional<CallingConv::ID> CC) const { 3674 return false; 3675 } 3676 3677 /// Target-specific combining of register parts into its original value 3678 virtual SDValue joinRegisterPartsIntoValue(SelectionDAG & DAG,const SDLoc & DL,const SDValue * Parts,unsigned NumParts,MVT PartVT,EVT ValueVT,Optional<CallingConv::ID> CC)3679 joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, 3680 const SDValue *Parts, unsigned NumParts, 3681 MVT PartVT, EVT ValueVT, 3682 Optional<CallingConv::ID> CC) const { 3683 return SDValue(); 3684 } 3685 3686 /// This hook must be implemented to lower the incoming (formal) arguments, 3687 /// described by the Ins array, into the specified DAG. The implementation 3688 /// should fill in the InVals array with legal-type argument values, and 3689 /// return the resulting token chain value. LowerFormalArguments(SDValue,CallingConv::ID,bool,const SmallVectorImpl<ISD::InputArg> &,const SDLoc &,SelectionDAG &,SmallVectorImpl<SDValue> &)3690 virtual SDValue LowerFormalArguments( 3691 SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/, 3692 const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/, 3693 SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const { 3694 llvm_unreachable("Not Implemented"); 3695 } 3696 3697 /// This structure contains all information that is necessary for lowering 3698 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder 3699 /// needs to lower a call, and targets will see this struct in their LowerCall 3700 /// implementation. 3701 struct CallLoweringInfo { 3702 SDValue Chain; 3703 Type *RetTy = nullptr; 3704 bool RetSExt : 1; 3705 bool RetZExt : 1; 3706 bool IsVarArg : 1; 3707 bool IsInReg : 1; 3708 bool DoesNotReturn : 1; 3709 bool IsReturnValueUsed : 1; 3710 bool IsConvergent : 1; 3711 bool IsPatchPoint : 1; 3712 bool IsPreallocated : 1; 3713 bool NoMerge : 1; 3714 3715 // IsTailCall should be modified by implementations of 3716 // TargetLowering::LowerCall that perform tail call conversions. 3717 bool IsTailCall = false; 3718 3719 // Is Call lowering done post SelectionDAG type legalization. 3720 bool IsPostTypeLegalization = false; 3721 3722 unsigned NumFixedArgs = -1; 3723 CallingConv::ID CallConv = CallingConv::C; 3724 SDValue Callee; 3725 ArgListTy Args; 3726 SelectionDAG &DAG; 3727 SDLoc DL; 3728 const CallBase *CB = nullptr; 3729 SmallVector<ISD::OutputArg, 32> Outs; 3730 SmallVector<SDValue, 32> OutVals; 3731 SmallVector<ISD::InputArg, 32> Ins; 3732 SmallVector<SDValue, 4> InVals; 3733 CallLoweringInfoCallLoweringInfo3734 CallLoweringInfo(SelectionDAG &DAG) 3735 : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false), 3736 DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false), 3737 IsPatchPoint(false), IsPreallocated(false), NoMerge(false), 3738 DAG(DAG) {} 3739 setDebugLocCallLoweringInfo3740 CallLoweringInfo &setDebugLoc(const SDLoc &dl) { 3741 DL = dl; 3742 return *this; 3743 } 3744 setChainCallLoweringInfo3745 CallLoweringInfo &setChain(SDValue InChain) { 3746 Chain = InChain; 3747 return *this; 3748 } 3749 3750 // setCallee with target/module-specific attributes setLibCalleeCallLoweringInfo3751 CallLoweringInfo &setLibCallee(CallingConv::ID CC, Type *ResultType, 3752 SDValue Target, ArgListTy &&ArgsList) { 3753 RetTy = ResultType; 3754 Callee = Target; 3755 CallConv = CC; 3756 NumFixedArgs = ArgsList.size(); 3757 Args = std::move(ArgsList); 3758 3759 DAG.getTargetLoweringInfo().markLibCallAttributes( 3760 &(DAG.getMachineFunction()), CC, Args); 3761 return *this; 3762 } 3763 setCalleeCallLoweringInfo3764 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType, 3765 SDValue Target, ArgListTy &&ArgsList) { 3766 RetTy = ResultType; 3767 Callee = Target; 3768 CallConv = CC; 3769 NumFixedArgs = ArgsList.size(); 3770 Args = std::move(ArgsList); 3771 return *this; 3772 } 3773 setCalleeCallLoweringInfo3774 CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy, 3775 SDValue Target, ArgListTy &&ArgsList, 3776 const CallBase &Call) { 3777 RetTy = ResultType; 3778 3779 IsInReg = Call.hasRetAttr(Attribute::InReg); 3780 DoesNotReturn = 3781 Call.doesNotReturn() || 3782 (!isa<InvokeInst>(Call) && isa<UnreachableInst>(Call.getNextNode())); 3783 IsVarArg = FTy->isVarArg(); 3784 IsReturnValueUsed = !Call.use_empty(); 3785 RetSExt = Call.hasRetAttr(Attribute::SExt); 3786 RetZExt = Call.hasRetAttr(Attribute::ZExt); 3787 NoMerge = Call.hasFnAttr(Attribute::NoMerge); 3788 3789 Callee = Target; 3790 3791 CallConv = Call.getCallingConv(); 3792 NumFixedArgs = FTy->getNumParams(); 3793 Args = std::move(ArgsList); 3794 3795 CB = &Call; 3796 3797 return *this; 3798 } 3799 3800 CallLoweringInfo &setInRegister(bool Value = true) { 3801 IsInReg = Value; 3802 return *this; 3803 } 3804 3805 CallLoweringInfo &setNoReturn(bool Value = true) { 3806 DoesNotReturn = Value; 3807 return *this; 3808 } 3809 3810 CallLoweringInfo &setVarArg(bool Value = true) { 3811 IsVarArg = Value; 3812 return *this; 3813 } 3814 3815 CallLoweringInfo &setTailCall(bool Value = true) { 3816 IsTailCall = Value; 3817 return *this; 3818 } 3819 3820 CallLoweringInfo &setDiscardResult(bool Value = true) { 3821 IsReturnValueUsed = !Value; 3822 return *this; 3823 } 3824 3825 CallLoweringInfo &setConvergent(bool Value = true) { 3826 IsConvergent = Value; 3827 return *this; 3828 } 3829 3830 CallLoweringInfo &setSExtResult(bool Value = true) { 3831 RetSExt = Value; 3832 return *this; 3833 } 3834 3835 CallLoweringInfo &setZExtResult(bool Value = true) { 3836 RetZExt = Value; 3837 return *this; 3838 } 3839 3840 CallLoweringInfo &setIsPatchPoint(bool Value = true) { 3841 IsPatchPoint = Value; 3842 return *this; 3843 } 3844 3845 CallLoweringInfo &setIsPreallocated(bool Value = true) { 3846 IsPreallocated = Value; 3847 return *this; 3848 } 3849 3850 CallLoweringInfo &setIsPostTypeLegalization(bool Value=true) { 3851 IsPostTypeLegalization = Value; 3852 return *this; 3853 } 3854 getArgsCallLoweringInfo3855 ArgListTy &getArgs() { 3856 return Args; 3857 } 3858 }; 3859 3860 /// This structure is used to pass arguments to makeLibCall function. 3861 struct MakeLibCallOptions { 3862 // By passing type list before soften to makeLibCall, the target hook 3863 // shouldExtendTypeInLibCall can get the original type before soften. 3864 ArrayRef<EVT> OpsVTBeforeSoften; 3865 EVT RetVTBeforeSoften; 3866 bool IsSExt : 1; 3867 bool DoesNotReturn : 1; 3868 bool IsReturnValueUsed : 1; 3869 bool IsPostTypeLegalization : 1; 3870 bool IsSoften : 1; 3871 MakeLibCallOptionsMakeLibCallOptions3872 MakeLibCallOptions() 3873 : IsSExt(false), DoesNotReturn(false), IsReturnValueUsed(true), 3874 IsPostTypeLegalization(false), IsSoften(false) {} 3875 3876 MakeLibCallOptions &setSExt(bool Value = true) { 3877 IsSExt = Value; 3878 return *this; 3879 } 3880 3881 MakeLibCallOptions &setNoReturn(bool Value = true) { 3882 DoesNotReturn = Value; 3883 return *this; 3884 } 3885 3886 MakeLibCallOptions &setDiscardResult(bool Value = true) { 3887 IsReturnValueUsed = !Value; 3888 return *this; 3889 } 3890 3891 MakeLibCallOptions &setIsPostTypeLegalization(bool Value = true) { 3892 IsPostTypeLegalization = Value; 3893 return *this; 3894 } 3895 3896 MakeLibCallOptions &setTypeListBeforeSoften(ArrayRef<EVT> OpsVT, EVT RetVT, 3897 bool Value = true) { 3898 OpsVTBeforeSoften = OpsVT; 3899 RetVTBeforeSoften = RetVT; 3900 IsSoften = Value; 3901 return *this; 3902 } 3903 }; 3904 3905 /// This function lowers an abstract call to a function into an actual call. 3906 /// This returns a pair of operands. The first element is the return value 3907 /// for the function (if RetTy is not VoidTy). The second element is the 3908 /// outgoing token chain. It calls LowerCall to do the actual lowering. 3909 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const; 3910 3911 /// This hook must be implemented to lower calls into the specified 3912 /// DAG. The outgoing arguments to the call are described by the Outs array, 3913 /// and the values to be returned by the call are described by the Ins 3914 /// array. The implementation should fill in the InVals array with legal-type 3915 /// return values from the call, and return the resulting token chain value. 3916 virtual SDValue LowerCall(CallLoweringInfo &,SmallVectorImpl<SDValue> &)3917 LowerCall(CallLoweringInfo &/*CLI*/, 3918 SmallVectorImpl<SDValue> &/*InVals*/) const { 3919 llvm_unreachable("Not Implemented"); 3920 } 3921 3922 /// Target-specific cleanup for formal ByVal parameters. HandleByVal(CCState *,unsigned &,Align)3923 virtual void HandleByVal(CCState *, unsigned &, Align) const {} 3924 3925 /// This hook should be implemented to check whether the return values 3926 /// described by the Outs array can fit into the return registers. If false 3927 /// is returned, an sret-demotion is performed. CanLowerReturn(CallingConv::ID,MachineFunction &,bool,const SmallVectorImpl<ISD::OutputArg> &,LLVMContext &)3928 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/, 3929 MachineFunction &/*MF*/, bool /*isVarArg*/, 3930 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, 3931 LLVMContext &/*Context*/) const 3932 { 3933 // Return true by default to get preexisting behavior. 3934 return true; 3935 } 3936 3937 /// This hook must be implemented to lower outgoing return values, described 3938 /// by the Outs array, into the specified DAG. The implementation should 3939 /// return the resulting token chain value. LowerReturn(SDValue,CallingConv::ID,bool,const SmallVectorImpl<ISD::OutputArg> &,const SmallVectorImpl<SDValue> &,const SDLoc &,SelectionDAG &)3940 virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/, 3941 bool /*isVarArg*/, 3942 const SmallVectorImpl<ISD::OutputArg> & /*Outs*/, 3943 const SmallVectorImpl<SDValue> & /*OutVals*/, 3944 const SDLoc & /*dl*/, 3945 SelectionDAG & /*DAG*/) const { 3946 llvm_unreachable("Not Implemented"); 3947 } 3948 3949 /// Return true if result of the specified node is used by a return node 3950 /// only. It also compute and return the input chain for the tail call. 3951 /// 3952 /// This is used to determine whether it is possible to codegen a libcall as 3953 /// tail call at legalization time. isUsedByReturnOnly(SDNode *,SDValue &)3954 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const { 3955 return false; 3956 } 3957 3958 /// Return true if the target may be able emit the call instruction as a tail 3959 /// call. This is used by optimization passes to determine if it's profitable 3960 /// to duplicate return instructions to enable tailcall optimization. mayBeEmittedAsTailCall(const CallInst *)3961 virtual bool mayBeEmittedAsTailCall(const CallInst *) const { 3962 return false; 3963 } 3964 3965 /// Return the builtin name for the __builtin___clear_cache intrinsic 3966 /// Default is to invoke the clear cache library call getClearCacheBuiltinName()3967 virtual const char * getClearCacheBuiltinName() const { 3968 return "__clear_cache"; 3969 } 3970 3971 /// Return the register ID of the name passed in. Used by named register 3972 /// global variables extension. There is no target-independent behaviour 3973 /// so the default action is to bail. getRegisterByName(const char * RegName,LLT Ty,const MachineFunction & MF)3974 virtual Register getRegisterByName(const char* RegName, LLT Ty, 3975 const MachineFunction &MF) const { 3976 report_fatal_error("Named registers not implemented for this target"); 3977 } 3978 3979 /// Return the type that should be used to zero or sign extend a 3980 /// zeroext/signext integer return value. FIXME: Some C calling conventions 3981 /// require the return type to be promoted, but this is not true all the time, 3982 /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling 3983 /// conventions. The frontend should handle this and include all of the 3984 /// necessary information. getTypeForExtReturn(LLVMContext & Context,EVT VT,ISD::NodeType)3985 virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, 3986 ISD::NodeType /*ExtendKind*/) const { 3987 EVT MinVT = getRegisterType(Context, MVT::i32); 3988 return VT.bitsLT(MinVT) ? MinVT : VT; 3989 } 3990 3991 /// For some targets, an LLVM struct type must be broken down into multiple 3992 /// simple types, but the calling convention specifies that the entire struct 3993 /// must be passed in a block of consecutive registers. 3994 virtual bool functionArgumentNeedsConsecutiveRegisters(Type * Ty,CallingConv::ID CallConv,bool isVarArg)3995 functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, 3996 bool isVarArg) const { 3997 return false; 3998 } 3999 4000 /// For most targets, an LLVM type must be broken down into multiple 4001 /// smaller types. Usually the halves are ordered according to the endianness 4002 /// but for some platform that would break. So this method will default to 4003 /// matching the endianness but can be overridden. 4004 virtual bool shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout & DL)4005 shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) const { 4006 return DL.isLittleEndian(); 4007 } 4008 4009 /// Returns a 0 terminated array of registers that can be safely used as 4010 /// scratch registers. getScratchRegisters(CallingConv::ID CC)4011 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const { 4012 return nullptr; 4013 } 4014 4015 /// This callback is used to prepare for a volatile or atomic load. 4016 /// It takes a chain node as input and returns the chain for the load itself. 4017 /// 4018 /// Having a callback like this is necessary for targets like SystemZ, 4019 /// which allows a CPU to reuse the result of a previous load indefinitely, 4020 /// even if a cache-coherent store is performed by another CPU. The default 4021 /// implementation does nothing. prepareVolatileOrAtomicLoad(SDValue Chain,const SDLoc & DL,SelectionDAG & DAG)4022 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, 4023 SelectionDAG &DAG) const { 4024 return Chain; 4025 } 4026 4027 /// Should SelectionDAG lower an atomic store of the given kind as a normal 4028 /// StoreSDNode (as opposed to an AtomicSDNode)? NOTE: The intention is to 4029 /// eventually migrate all targets to the using StoreSDNodes, but porting is 4030 /// being done target at a time. lowerAtomicStoreAsStoreSDNode(const StoreInst & SI)4031 virtual bool lowerAtomicStoreAsStoreSDNode(const StoreInst &SI) const { 4032 assert(SI.isAtomic() && "violated precondition"); 4033 return false; 4034 } 4035 4036 /// Should SelectionDAG lower an atomic load of the given kind as a normal 4037 /// LoadSDNode (as opposed to an AtomicSDNode)? NOTE: The intention is to 4038 /// eventually migrate all targets to the using LoadSDNodes, but porting is 4039 /// being done target at a time. lowerAtomicLoadAsLoadSDNode(const LoadInst & LI)4040 virtual bool lowerAtomicLoadAsLoadSDNode(const LoadInst &LI) const { 4041 assert(LI.isAtomic() && "violated precondition"); 4042 return false; 4043 } 4044 4045 4046 /// This callback is invoked by the type legalizer to legalize nodes with an 4047 /// illegal operand type but legal result types. It replaces the 4048 /// LowerOperation callback in the type Legalizer. The reason we can not do 4049 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to 4050 /// use this callback. 4051 /// 4052 /// TODO: Consider merging with ReplaceNodeResults. 4053 /// 4054 /// The target places new result values for the node in Results (their number 4055 /// and types must exactly match those of the original return values of 4056 /// the node), or leaves Results empty, which indicates that the node is not 4057 /// to be custom lowered after all. 4058 /// The default implementation calls LowerOperation. 4059 virtual void LowerOperationWrapper(SDNode *N, 4060 SmallVectorImpl<SDValue> &Results, 4061 SelectionDAG &DAG) const; 4062 4063 /// This callback is invoked for operations that are unsupported by the 4064 /// target, which are registered to use 'custom' lowering, and whose defined 4065 /// values are all legal. If the target has no operations that require custom 4066 /// lowering, it need not implement this. The default implementation of this 4067 /// aborts. 4068 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 4069 4070 /// This callback is invoked when a node result type is illegal for the 4071 /// target, and the operation was registered to use 'custom' lowering for that 4072 /// result type. The target places new result values for the node in Results 4073 /// (their number and types must exactly match those of the original return 4074 /// values of the node), or leaves Results empty, which indicates that the 4075 /// node is not to be custom lowered after all. 4076 /// 4077 /// If the target has no operations that require custom lowering, it need not 4078 /// implement this. The default implementation aborts. ReplaceNodeResults(SDNode *,SmallVectorImpl<SDValue> &,SelectionDAG &)4079 virtual void ReplaceNodeResults(SDNode * /*N*/, 4080 SmallVectorImpl<SDValue> &/*Results*/, 4081 SelectionDAG &/*DAG*/) const { 4082 llvm_unreachable("ReplaceNodeResults not implemented for this target!"); 4083 } 4084 4085 /// This method returns the name of a target specific DAG node. 4086 virtual const char *getTargetNodeName(unsigned Opcode) const; 4087 4088 /// This method returns a target specific FastISel object, or null if the 4089 /// target does not support "fast" ISel. createFastISel(FunctionLoweringInfo &,const TargetLibraryInfo *)4090 virtual FastISel *createFastISel(FunctionLoweringInfo &, 4091 const TargetLibraryInfo *) const { 4092 return nullptr; 4093 } 4094 4095 bool verifyReturnAddressArgumentIsConstant(SDValue Op, 4096 SelectionDAG &DAG) const; 4097 4098 //===--------------------------------------------------------------------===// 4099 // Inline Asm Support hooks 4100 // 4101 4102 /// This hook allows the target to expand an inline asm call to be explicit 4103 /// llvm code if it wants to. This is useful for turning simple inline asms 4104 /// into LLVM intrinsics, which gives the compiler more information about the 4105 /// behavior of the code. ExpandInlineAsm(CallInst *)4106 virtual bool ExpandInlineAsm(CallInst *) const { 4107 return false; 4108 } 4109 4110 enum ConstraintType { 4111 C_Register, // Constraint represents specific register(s). 4112 C_RegisterClass, // Constraint represents any of register(s) in class. 4113 C_Memory, // Memory constraint. 4114 C_Immediate, // Requires an immediate. 4115 C_Other, // Something else. 4116 C_Unknown // Unsupported constraint. 4117 }; 4118 4119 enum ConstraintWeight { 4120 // Generic weights. 4121 CW_Invalid = -1, // No match. 4122 CW_Okay = 0, // Acceptable. 4123 CW_Good = 1, // Good weight. 4124 CW_Better = 2, // Better weight. 4125 CW_Best = 3, // Best weight. 4126 4127 // Well-known weights. 4128 CW_SpecificReg = CW_Okay, // Specific register operands. 4129 CW_Register = CW_Good, // Register operands. 4130 CW_Memory = CW_Better, // Memory operands. 4131 CW_Constant = CW_Best, // Constant operand. 4132 CW_Default = CW_Okay // Default or don't know type. 4133 }; 4134 4135 /// This contains information for each constraint that we are lowering. 4136 struct AsmOperandInfo : public InlineAsm::ConstraintInfo { 4137 /// This contains the actual string for the code, like "m". TargetLowering 4138 /// picks the 'best' code from ConstraintInfo::Codes that most closely 4139 /// matches the operand. 4140 std::string ConstraintCode; 4141 4142 /// Information about the constraint code, e.g. Register, RegisterClass, 4143 /// Memory, Other, Unknown. 4144 TargetLowering::ConstraintType ConstraintType = TargetLowering::C_Unknown; 4145 4146 /// If this is the result output operand or a clobber, this is null, 4147 /// otherwise it is the incoming operand to the CallInst. This gets 4148 /// modified as the asm is processed. 4149 Value *CallOperandVal = nullptr; 4150 4151 /// The ValueType for the operand value. 4152 MVT ConstraintVT = MVT::Other; 4153 4154 /// Copy constructor for copying from a ConstraintInfo. AsmOperandInfoAsmOperandInfo4155 AsmOperandInfo(InlineAsm::ConstraintInfo Info) 4156 : InlineAsm::ConstraintInfo(std::move(Info)) {} 4157 4158 /// Return true of this is an input operand that is a matching constraint 4159 /// like "4". 4160 bool isMatchingInputConstraint() const; 4161 4162 /// If this is an input matching constraint, this method returns the output 4163 /// operand it matches. 4164 unsigned getMatchedOperand() const; 4165 }; 4166 4167 using AsmOperandInfoVector = std::vector<AsmOperandInfo>; 4168 4169 /// Split up the constraint string from the inline assembly value into the 4170 /// specific constraints and their prefixes, and also tie in the associated 4171 /// operand values. If this returns an empty vector, and if the constraint 4172 /// string itself isn't empty, there was an error parsing. 4173 virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL, 4174 const TargetRegisterInfo *TRI, 4175 const CallBase &Call) const; 4176 4177 /// Examine constraint type and operand type and determine a weight value. 4178 /// The operand object must already have been set up with the operand type. 4179 virtual ConstraintWeight getMultipleConstraintMatchWeight( 4180 AsmOperandInfo &info, int maIndex) const; 4181 4182 /// Examine constraint string and operand type and determine a weight value. 4183 /// The operand object must already have been set up with the operand type. 4184 virtual ConstraintWeight getSingleConstraintMatchWeight( 4185 AsmOperandInfo &info, const char *constraint) const; 4186 4187 /// Determines the constraint code and constraint type to use for the specific 4188 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. 4189 /// If the actual operand being passed in is available, it can be passed in as 4190 /// Op, otherwise an empty SDValue can be passed. 4191 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, 4192 SDValue Op, 4193 SelectionDAG *DAG = nullptr) const; 4194 4195 /// Given a constraint, return the type of constraint it is for this target. 4196 virtual ConstraintType getConstraintType(StringRef Constraint) const; 4197 4198 /// Given a physical register constraint (e.g. {edx}), return the register 4199 /// number and the register class for the register. 4200 /// 4201 /// Given a register class constraint, like 'r', if this corresponds directly 4202 /// to an LLVM register class, return a register of 0 and the register class 4203 /// pointer. 4204 /// 4205 /// This should only be used for C_Register constraints. On error, this 4206 /// returns a register number of 0 and a null register class pointer. 4207 virtual std::pair<unsigned, const TargetRegisterClass *> 4208 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 4209 StringRef Constraint, MVT VT) const; 4210 getInlineAsmMemConstraint(StringRef ConstraintCode)4211 virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const { 4212 if (ConstraintCode == "m") 4213 return InlineAsm::Constraint_m; 4214 if (ConstraintCode == "o") 4215 return InlineAsm::Constraint_o; 4216 if (ConstraintCode == "X") 4217 return InlineAsm::Constraint_X; 4218 return InlineAsm::Constraint_Unknown; 4219 } 4220 4221 /// Try to replace an X constraint, which matches anything, with another that 4222 /// has more specific requirements based on the type of the corresponding 4223 /// operand. This returns null if there is no replacement to make. 4224 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 4225 4226 /// Lower the specified operand into the Ops vector. If it is invalid, don't 4227 /// add anything to Ops. 4228 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 4229 std::vector<SDValue> &Ops, 4230 SelectionDAG &DAG) const; 4231 4232 // Lower custom output constraints. If invalid, return SDValue(). 4233 virtual SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag, 4234 const SDLoc &DL, 4235 const AsmOperandInfo &OpInfo, 4236 SelectionDAG &DAG) const; 4237 4238 //===--------------------------------------------------------------------===// 4239 // Div utility functions 4240 // 4241 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 4242 SmallVectorImpl<SDNode *> &Created) const; 4243 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, 4244 SmallVectorImpl<SDNode *> &Created) const; 4245 4246 /// Targets may override this function to provide custom SDIV lowering for 4247 /// power-of-2 denominators. If the target returns an empty SDValue, LLVM 4248 /// assumes SDIV is expensive and replaces it with a series of other integer 4249 /// operations. 4250 virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, 4251 SelectionDAG &DAG, 4252 SmallVectorImpl<SDNode *> &Created) const; 4253 4254 /// Indicate whether this target prefers to combine FDIVs with the same 4255 /// divisor. If the transform should never be done, return zero. If the 4256 /// transform should be done, return the minimum number of divisor uses 4257 /// that must exist. combineRepeatedFPDivisors()4258 virtual unsigned combineRepeatedFPDivisors() const { 4259 return 0; 4260 } 4261 4262 /// Hooks for building estimates in place of slower divisions and square 4263 /// roots. 4264 4265 /// Return either a square root or its reciprocal estimate value for the input 4266 /// operand. 4267 /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or 4268 /// 'Enabled' as set by a potential default override attribute. 4269 /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson 4270 /// refinement iterations required to generate a sufficient (though not 4271 /// necessarily IEEE-754 compliant) estimate is returned in that parameter. 4272 /// The boolean UseOneConstNR output is used to select a Newton-Raphson 4273 /// algorithm implementation that uses either one or two constants. 4274 /// The boolean Reciprocal is used to select whether the estimate is for the 4275 /// square root of the input operand or the reciprocal of its square root. 4276 /// A target may choose to implement its own refinement within this function. 4277 /// If that's true, then return '0' as the number of RefinementSteps to avoid 4278 /// any further refinement of the estimate. 4279 /// An empty SDValue return means no estimate sequence can be created. getSqrtEstimate(SDValue Operand,SelectionDAG & DAG,int Enabled,int & RefinementSteps,bool & UseOneConstNR,bool Reciprocal)4280 virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, 4281 int Enabled, int &RefinementSteps, 4282 bool &UseOneConstNR, bool Reciprocal) const { 4283 return SDValue(); 4284 } 4285 4286 /// Return a reciprocal estimate value for the input operand. 4287 /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or 4288 /// 'Enabled' as set by a potential default override attribute. 4289 /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson 4290 /// refinement iterations required to generate a sufficient (though not 4291 /// necessarily IEEE-754 compliant) estimate is returned in that parameter. 4292 /// A target may choose to implement its own refinement within this function. 4293 /// If that's true, then return '0' as the number of RefinementSteps to avoid 4294 /// any further refinement of the estimate. 4295 /// An empty SDValue return means no estimate sequence can be created. getRecipEstimate(SDValue Operand,SelectionDAG & DAG,int Enabled,int & RefinementSteps)4296 virtual SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, 4297 int Enabled, int &RefinementSteps) const { 4298 return SDValue(); 4299 } 4300 4301 /// Return a target-dependent comparison result if the input operand is 4302 /// suitable for use with a square root estimate calculation. For example, the 4303 /// comparison may check if the operand is NAN, INF, zero, normal, etc. The 4304 /// result should be used as the condition operand for a select or branch. 4305 virtual SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG, 4306 const DenormalMode &Mode) const; 4307 4308 /// Return a target-dependent result if the input operand is not suitable for 4309 /// use with a square root estimate calculation. getSqrtResultForDenormInput(SDValue Operand,SelectionDAG & DAG)4310 virtual SDValue getSqrtResultForDenormInput(SDValue Operand, 4311 SelectionDAG &DAG) const { 4312 return DAG.getConstantFP(0.0, SDLoc(Operand), Operand.getValueType()); 4313 } 4314 4315 //===--------------------------------------------------------------------===// 4316 // Legalization utility functions 4317 // 4318 4319 /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes, 4320 /// respectively, each computing an n/2-bit part of the result. 4321 /// \param Result A vector that will be filled with the parts of the result 4322 /// in little-endian order. 4323 /// \param LL Low bits of the LHS of the MUL. You can use this parameter 4324 /// if you want to control how low bits are extracted from the LHS. 4325 /// \param LH High bits of the LHS of the MUL. See LL for meaning. 4326 /// \param RL Low bits of the RHS of the MUL. See LL for meaning 4327 /// \param RH High bits of the RHS of the MUL. See LL for meaning. 4328 /// \returns true if the node has been expanded, false if it has not 4329 bool expandMUL_LOHI(unsigned Opcode, EVT VT, const SDLoc &dl, SDValue LHS, 4330 SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT, 4331 SelectionDAG &DAG, MulExpansionKind Kind, 4332 SDValue LL = SDValue(), SDValue LH = SDValue(), 4333 SDValue RL = SDValue(), SDValue RH = SDValue()) const; 4334 4335 /// Expand a MUL into two nodes. One that computes the high bits of 4336 /// the result and one that computes the low bits. 4337 /// \param HiLoVT The value type to use for the Lo and Hi nodes. 4338 /// \param LL Low bits of the LHS of the MUL. You can use this parameter 4339 /// if you want to control how low bits are extracted from the LHS. 4340 /// \param LH High bits of the LHS of the MUL. See LL for meaning. 4341 /// \param RL Low bits of the RHS of the MUL. See LL for meaning 4342 /// \param RH High bits of the RHS of the MUL. See LL for meaning. 4343 /// \returns true if the node has been expanded. false if it has not 4344 bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, 4345 SelectionDAG &DAG, MulExpansionKind Kind, 4346 SDValue LL = SDValue(), SDValue LH = SDValue(), 4347 SDValue RL = SDValue(), SDValue RH = SDValue()) const; 4348 4349 /// Expand funnel shift. 4350 /// \param N Node to expand 4351 /// \param Result output after conversion 4352 /// \returns True, if the expansion was successful, false otherwise 4353 bool expandFunnelShift(SDNode *N, SDValue &Result, SelectionDAG &DAG) const; 4354 4355 /// Expand rotations. 4356 /// \param N Node to expand 4357 /// \param AllowVectorOps expand vector rotate, this should only be performed 4358 /// if the legalization is happening outside of LegalizeVectorOps 4359 /// \param Result output after conversion 4360 /// \returns True, if the expansion was successful, false otherwise 4361 bool expandROT(SDNode *N, bool AllowVectorOps, SDValue &Result, 4362 SelectionDAG &DAG) const; 4363 4364 /// Expand shift-by-parts. 4365 /// \param N Node to expand 4366 /// \param Lo lower-output-part after conversion 4367 /// \param Hi upper-output-part after conversion 4368 void expandShiftParts(SDNode *N, SDValue &Lo, SDValue &Hi, 4369 SelectionDAG &DAG) const; 4370 4371 /// Expand float(f32) to SINT(i64) conversion 4372 /// \param N Node to expand 4373 /// \param Result output after conversion 4374 /// \returns True, if the expansion was successful, false otherwise 4375 bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const; 4376 4377 /// Expand float to UINT conversion 4378 /// \param N Node to expand 4379 /// \param Result output after conversion 4380 /// \param Chain output chain after conversion 4381 /// \returns True, if the expansion was successful, false otherwise 4382 bool expandFP_TO_UINT(SDNode *N, SDValue &Result, SDValue &Chain, 4383 SelectionDAG &DAG) const; 4384 4385 /// Expand UINT(i64) to double(f64) conversion 4386 /// \param N Node to expand 4387 /// \param Result output after conversion 4388 /// \param Chain output chain after conversion 4389 /// \returns True, if the expansion was successful, false otherwise 4390 bool expandUINT_TO_FP(SDNode *N, SDValue &Result, SDValue &Chain, 4391 SelectionDAG &DAG) const; 4392 4393 /// Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs. 4394 SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const; 4395 4396 /// Expand FP_TO_[US]INT_SAT into FP_TO_[US]INT and selects or min/max. 4397 /// \param N Node to expand 4398 /// \returns The expansion result 4399 SDValue expandFP_TO_INT_SAT(SDNode *N, SelectionDAG &DAG) const; 4400 4401 /// Expand CTPOP nodes. Expands vector/scalar CTPOP nodes, 4402 /// vector nodes can only succeed if all operations are legal/custom. 4403 /// \param N Node to expand 4404 /// \param Result output after conversion 4405 /// \returns True, if the expansion was successful, false otherwise 4406 bool expandCTPOP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const; 4407 4408 /// Expand CTLZ/CTLZ_ZERO_UNDEF nodes. Expands vector/scalar CTLZ nodes, 4409 /// vector nodes can only succeed if all operations are legal/custom. 4410 /// \param N Node to expand 4411 /// \param Result output after conversion 4412 /// \returns True, if the expansion was successful, false otherwise 4413 bool expandCTLZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const; 4414 4415 /// Expand CTTZ/CTTZ_ZERO_UNDEF nodes. Expands vector/scalar CTTZ nodes, 4416 /// vector nodes can only succeed if all operations are legal/custom. 4417 /// \param N Node to expand 4418 /// \param Result output after conversion 4419 /// \returns True, if the expansion was successful, false otherwise 4420 bool expandCTTZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const; 4421 4422 /// Expand ABS nodes. Expands vector/scalar ABS nodes, 4423 /// vector nodes can only succeed if all operations are legal/custom. 4424 /// (ABS x) -> (XOR (ADD x, (SRA x, type_size)), (SRA x, type_size)) 4425 /// \param N Node to expand 4426 /// \param Result output after conversion 4427 /// \param IsNegative indicate negated abs 4428 /// \returns True, if the expansion was successful, false otherwise 4429 bool expandABS(SDNode *N, SDValue &Result, SelectionDAG &DAG, 4430 bool IsNegative = false) const; 4431 4432 /// Expand BSWAP nodes. Expands scalar/vector BSWAP nodes with i16/i32/i64 4433 /// scalar types. Returns SDValue() if expand fails. 4434 /// \param N Node to expand 4435 /// \returns The expansion result or SDValue() if it fails. 4436 SDValue expandBSWAP(SDNode *N, SelectionDAG &DAG) const; 4437 4438 /// Expand BITREVERSE nodes. Expands scalar/vector BITREVERSE nodes. 4439 /// Returns SDValue() if expand fails. 4440 /// \param N Node to expand 4441 /// \returns The expansion result or SDValue() if it fails. 4442 SDValue expandBITREVERSE(SDNode *N, SelectionDAG &DAG) const; 4443 4444 /// Turn load of vector type into a load of the individual elements. 4445 /// \param LD load to expand 4446 /// \returns BUILD_VECTOR and TokenFactor nodes. 4447 std::pair<SDValue, SDValue> scalarizeVectorLoad(LoadSDNode *LD, 4448 SelectionDAG &DAG) const; 4449 4450 // Turn a store of a vector type into stores of the individual elements. 4451 /// \param ST Store with a vector value type 4452 /// \returns TokenFactor of the individual store chains. 4453 SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const; 4454 4455 /// Expands an unaligned load to 2 half-size loads for an integer, and 4456 /// possibly more for vectors. 4457 std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD, 4458 SelectionDAG &DAG) const; 4459 4460 /// Expands an unaligned store to 2 half-size stores for integer values, and 4461 /// possibly more for vectors. 4462 SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const; 4463 4464 /// Increments memory address \p Addr according to the type of the value 4465 /// \p DataVT that should be stored. If the data is stored in compressed 4466 /// form, the memory address should be incremented according to the number of 4467 /// the stored elements. This number is equal to the number of '1's bits 4468 /// in the \p Mask. 4469 /// \p DataVT is a vector type. \p Mask is a vector value. 4470 /// \p DataVT and \p Mask have the same number of vector elements. 4471 SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL, 4472 EVT DataVT, SelectionDAG &DAG, 4473 bool IsCompressedMemory) const; 4474 4475 /// Get a pointer to vector element \p Idx located in memory for a vector of 4476 /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of 4477 /// bounds the returned pointer is unspecified, but will be within the vector 4478 /// bounds. 4479 SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, 4480 SDValue Index) const; 4481 4482 /// Method for building the DAG expansion of ISD::[US][MIN|MAX]. This 4483 /// method accepts integers as its arguments. 4484 SDValue expandIntMINMAX(SDNode *Node, SelectionDAG &DAG) const; 4485 4486 /// Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. This 4487 /// method accepts integers as its arguments. 4488 SDValue expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const; 4489 4490 /// Method for building the DAG expansion of ISD::[US]SHLSAT. This 4491 /// method accepts integers as its arguments. 4492 SDValue expandShlSat(SDNode *Node, SelectionDAG &DAG) const; 4493 4494 /// Method for building the DAG expansion of ISD::[U|S]MULFIX[SAT]. This 4495 /// method accepts integers as its arguments. 4496 SDValue expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const; 4497 4498 /// Method for building the DAG expansion of ISD::[US]DIVFIX[SAT]. This 4499 /// method accepts integers as its arguments. 4500 /// Note: This method may fail if the division could not be performed 4501 /// within the type. Clients must retry with a wider type if this happens. 4502 SDValue expandFixedPointDiv(unsigned Opcode, const SDLoc &dl, 4503 SDValue LHS, SDValue RHS, 4504 unsigned Scale, SelectionDAG &DAG) const; 4505 4506 /// Method for building the DAG expansion of ISD::U(ADD|SUB)O. Expansion 4507 /// always suceeds and populates the Result and Overflow arguments. 4508 void expandUADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, 4509 SelectionDAG &DAG) const; 4510 4511 /// Method for building the DAG expansion of ISD::S(ADD|SUB)O. Expansion 4512 /// always suceeds and populates the Result and Overflow arguments. 4513 void expandSADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, 4514 SelectionDAG &DAG) const; 4515 4516 /// Method for building the DAG expansion of ISD::[US]MULO. Returns whether 4517 /// expansion was successful and populates the Result and Overflow arguments. 4518 bool expandMULO(SDNode *Node, SDValue &Result, SDValue &Overflow, 4519 SelectionDAG &DAG) const; 4520 4521 /// Expand a VECREDUCE_* into an explicit calculation. If Count is specified, 4522 /// only the first Count elements of the vector are used. 4523 SDValue expandVecReduce(SDNode *Node, SelectionDAG &DAG) const; 4524 4525 /// Expand a VECREDUCE_SEQ_* into an explicit ordered calculation. 4526 SDValue expandVecReduceSeq(SDNode *Node, SelectionDAG &DAG) const; 4527 4528 /// Expand an SREM or UREM using SDIV/UDIV or SDIVREM/UDIVREM, if legal. 4529 /// Returns true if the expansion was successful. 4530 bool expandREM(SDNode *Node, SDValue &Result, SelectionDAG &DAG) const; 4531 4532 /// Method for building the DAG expansion of ISD::VECTOR_SPLICE. This 4533 /// method accepts vectors as its arguments. 4534 SDValue expandVectorSplice(SDNode *Node, SelectionDAG &DAG) const; 4535 4536 /// Legalize a SETCC with given LHS and RHS and condition code CC on the 4537 /// current target. 4538 /// 4539 /// If the SETCC has been legalized using AND / OR, then the legalized node 4540 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert 4541 /// will be set to false. 4542 /// 4543 /// If the SETCC has been legalized by using getSetCCSwappedOperands(), 4544 /// then the values of LHS and RHS will be swapped, CC will be set to the 4545 /// new condition, and NeedInvert will be set to false. 4546 /// 4547 /// If the SETCC has been legalized using the inverse condcode, then LHS and 4548 /// RHS will be unchanged, CC will set to the inverted condcode, and 4549 /// NeedInvert will be set to true. The caller must invert the result of the 4550 /// SETCC with SelectionDAG::getLogicalNOT() or take equivalent action to swap 4551 /// the effect of a true/false result. 4552 /// 4553 /// \returns true if the SetCC has been legalized, false if it hasn't. 4554 bool LegalizeSetCCCondCode(SelectionDAG &DAG, EVT VT, SDValue &LHS, 4555 SDValue &RHS, SDValue &CC, bool &NeedInvert, 4556 const SDLoc &dl, SDValue &Chain, 4557 bool IsSignaling = false) const; 4558 4559 //===--------------------------------------------------------------------===// 4560 // Instruction Emitting Hooks 4561 // 4562 4563 /// This method should be implemented by targets that mark instructions with 4564 /// the 'usesCustomInserter' flag. These instructions are special in various 4565 /// ways, which require special support to insert. The specified MachineInstr 4566 /// is created but not inserted into any basic blocks, and this method is 4567 /// called to expand it into a sequence of instructions, potentially also 4568 /// creating new basic blocks and control flow. 4569 /// As long as the returned basic block is different (i.e., we created a new 4570 /// one), the custom inserter is free to modify the rest of \p MBB. 4571 virtual MachineBasicBlock * 4572 EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const; 4573 4574 /// This method should be implemented by targets that mark instructions with 4575 /// the 'hasPostISelHook' flag. These instructions must be adjusted after 4576 /// instruction selection by target hooks. e.g. To fill in optional defs for 4577 /// ARM 's' setting instructions. 4578 virtual void AdjustInstrPostInstrSelection(MachineInstr &MI, 4579 SDNode *Node) const; 4580 4581 /// If this function returns true, SelectionDAGBuilder emits a 4582 /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector. useLoadStackGuardNode()4583 virtual bool useLoadStackGuardNode() const { 4584 return false; 4585 } 4586 emitStackGuardXorFP(SelectionDAG & DAG,SDValue Val,const SDLoc & DL)4587 virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, 4588 const SDLoc &DL) const { 4589 llvm_unreachable("not implemented for this target"); 4590 } 4591 4592 /// Lower TLS global address SDNode for target independent emulated TLS model. 4593 virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, 4594 SelectionDAG &DAG) const; 4595 4596 /// Expands target specific indirect branch for the case of JumpTable 4597 /// expanasion. expandIndirectJTBranch(const SDLoc & dl,SDValue Value,SDValue Addr,SelectionDAG & DAG)4598 virtual SDValue expandIndirectJTBranch(const SDLoc& dl, SDValue Value, SDValue Addr, 4599 SelectionDAG &DAG) const { 4600 return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr); 4601 } 4602 4603 // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits))) 4604 // If we're comparing for equality to zero and isCtlzFast is true, expose the 4605 // fact that this can be implemented as a ctlz/srl pair, so that the dag 4606 // combiner can fold the new nodes. 4607 SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const; 4608 4609 /// Give targets the chance to reduce the number of distinct addresing modes. 4610 ISD::MemIndexType getCanonicalIndexType(ISD::MemIndexType IndexType, 4611 EVT MemVT, SDValue Offsets) const; 4612 4613 private: 4614 SDValue foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 4615 const SDLoc &DL, DAGCombinerInfo &DCI) const; 4616 SDValue foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 4617 const SDLoc &DL, DAGCombinerInfo &DCI) const; 4618 4619 SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0, 4620 SDValue N1, ISD::CondCode Cond, 4621 DAGCombinerInfo &DCI, 4622 const SDLoc &DL) const; 4623 4624 // (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 4625 SDValue optimizeSetCCByHoistingAndByConstFromLogicalShift( 4626 EVT SCCVT, SDValue N0, SDValue N1C, ISD::CondCode Cond, 4627 DAGCombinerInfo &DCI, const SDLoc &DL) const; 4628 4629 SDValue prepareUREMEqFold(EVT SETCCVT, SDValue REMNode, 4630 SDValue CompTargetNode, ISD::CondCode Cond, 4631 DAGCombinerInfo &DCI, const SDLoc &DL, 4632 SmallVectorImpl<SDNode *> &Created) const; 4633 SDValue buildUREMEqFold(EVT SETCCVT, SDValue REMNode, SDValue CompTargetNode, 4634 ISD::CondCode Cond, DAGCombinerInfo &DCI, 4635 const SDLoc &DL) const; 4636 4637 SDValue prepareSREMEqFold(EVT SETCCVT, SDValue REMNode, 4638 SDValue CompTargetNode, ISD::CondCode Cond, 4639 DAGCombinerInfo &DCI, const SDLoc &DL, 4640 SmallVectorImpl<SDNode *> &Created) const; 4641 SDValue buildSREMEqFold(EVT SETCCVT, SDValue REMNode, SDValue CompTargetNode, 4642 ISD::CondCode Cond, DAGCombinerInfo &DCI, 4643 const SDLoc &DL) const; 4644 }; 4645 4646 /// Given an LLVM IR type and return type attributes, compute the return value 4647 /// EVTs and flags, and optionally also the offsets, if the return value is 4648 /// being lowered to memory. 4649 void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, 4650 SmallVectorImpl<ISD::OutputArg> &Outs, 4651 const TargetLowering &TLI, const DataLayout &DL); 4652 4653 } // end namespace llvm 4654 4655 #endif // LLVM_CODEGEN_TARGETLOWERING_H 4656