| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/common/sync/ |
| H A D | Pulser.vhd | 48 Clk : in std_logic; port
180 signal Clk: std_logic := '0'; signal
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/simple_gemac/miim/ |
| H A D | eth_clockgen.v | 85 input Clk; // Input clock (Host clock) port
|
| H A D | eth_miim.v | 121 input Clk; // Host Clock port
|
| H A D | eth_shiftreg.v | 91 input Clk; // Input clock (Host clock) port
|
| H A D | eth_outputcontrol.v | 86 input Clk; // Host Clock port
|
| /dports/cad/verilator/verilator-4.216/test_regress/t/ |
| H A D | t_mem_slot.v | 11 input Clk; port
|
| /dports/cad/yosys/yosys-yosys-0.12/tests/asicworld/ |
| H A D | code_hdl_models_GrayCounter.v | 15 input wire Clk); port
|
| /dports/devel/universal-ctags/ctags-p5.9.20211128.0/Units/review-needed.r/test.vhd.t/ |
| H A D | input.vhd | 182 Clk: in std_logic; port
194 Clk: in std_logic; port in BidirCnt.behavioral.LoadCnt
2409 D, Clk: in std_logic; port
2880 A, B, Clk: in std_logic; port
4083 Clk: in std_logic; port
4803 Clk : in bit; port in PowerPkg.Power
4814 Clk : in bit; port
6304 port (D, Clk: in std_logic; port in simPrimitives.SimDFF
6342 port (D, Clk: in std_logic; port
|
| /dports/devel/geany/geany-1.38/tests/ctags/ |
| H A D | test.vhd | 182 Clk: in std_logic; port
194 Clk: in std_logic; port in BidirCnt.behavioral.LoadCnt
2409 D, Clk: in std_logic; port
2880 A, B, Clk: in std_logic; port
4083 Clk: in std_logic; port
4803 Clk : in bit; port in PowerPkg.Power
4814 Clk : in bit; port
6304 port (D, Clk: in std_logic; port in simPrimitives.SimDFF
6342 port (D, Clk: in std_logic; port
|
| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/video/fbdev/via/ |
| H A D | vt1636.c | 140 static int get_clk_range_index(u32 Clk) in get_clk_range_index()
|
| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/video/fbdev/via/ |
| H A D | vt1636.c | 140 static int get_clk_range_index(u32 Clk) in get_clk_range_index()
|
| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/ethernet/apple/ |
| H A D | bmac.c | 1077 #define Clk 0x0002 macro
|
| H A D | bmac.h | 45 # define Clk 0x0002 macro
|
| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/ethernet/apple/ |
| H A D | bmac.h | 45 # define Clk 0x0002 macro
|
| H A D | bmac.c | 1077 #define Clk 0x0002 macro
|
| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/ethernet/apple/ |
| H A D | bmac.h | 45 # define Clk 0x0002 macro
|
| H A D | bmac.c | 1077 #define Clk 0x0002 macro
|
| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/video/fbdev/via/ |
| H A D | vt1636.c | 140 static int get_clk_range_index(u32 Clk) in get_clk_range_index()
|
| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Marvell/Drivers/SdMmc/XenonDxe/ |
| H A D | XenonSdhci.c | 136 UINT32 Clk; in XenonSetClk() local
|
| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Scs/ |
| H A D | ScsConfig.h | 69 MUX_GPIO_PARAM Clk; member
77 MUX_GPIO_PARAM Clk; member
|
| /dports/sysutils/edk2/edk2-platforms-89f6170d/Silicon/Intel/TigerlakeSiliconPkg/Include/ |
| H A D | SerialIoDevices.h | 41 } SERIAL_IO_SPI_MODE;
|
| /dports/games/chessx/chessx-1.5.6/src/dialogs/ |
| H A D | commentdialog.h | 14 enum TimeMode { Egt, Emt, Clk}; enumerator
|
| /dports/games/libretro-bluemsx/blueMSX-libretro-faf470e/Src/IoDevice/ |
| H A D | Microwire93Cx6.c | 53 int Clk; member
|
| /dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue1051/ |
| H A D | psi_common_i2c_master_tb.vhd | 62 signal Clk : std_logic := '1'; signal
|
| /dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue17/ |
| H A D | cond_assign_proc.vhdl | 8 signal Clk : std_logic := '0' ; signal
|