1 /* $OpenBSD: omdisplay.c,v 1.11 2024/05/13 01:15:50 jsg Exp $ */
2 /*
3 * Copyright (c) 2007 Dale Rahn <drahn@openbsd.org>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #include <sys/param.h>
19 #include <sys/systm.h>
20 #include <sys/queue.h>
21 #include <sys/malloc.h>
22 #include <sys/device.h>
23 #include <sys/evcount.h>
24 #include <sys/conf.h>
25 #include <sys/uio.h>
26 #include <machine/bus.h>
27 #include <armv7/omap/omgpiovar.h>
28
29 #include <dev/cons.h>
30 #include <dev/wscons/wsconsio.h>
31 #include <dev/wscons/wsdisplayvar.h>
32 #include <dev/wscons/wscons_callbacks.h>
33
34 #include <dev/rasops/rasops.h>
35
36 #include "splash16.h"
37
38 #define OMDISPLAY_SIZE 0x1000
39 /* registers */
40 /* DSS */
41 #define DSS_REVISIONNUMBER 0x00
42 #define DSS_CONTROL 0x40
43 #define DSS_PSA_LCD_REG_1 0x50
44 #define DSS_PSA_LCD_REG_2 0x54
45 #define DSS_PSA_VIDEO_REG 0x58
46 #define DSS_STATUS 0x5C
47
48 /* DCR */
49 #define DISPC_REVISION 0x0000
50 #define DISPC_SYSCONFIG 0x0010
51 #define DISPC_SYSCONFIG_AUTOIDLE 0x00000001
52 #define DISPC_SYSCONFIG_SOFTRESET 0x00000002
53 #define DISPC_SYSCONFIG_SIDLEMODE_FORCE 0x00000000
54 #define DISPC_SYSCONFIG_SIDLEMODE_NONE 0x00000008
55 #define DISPC_SYSCONFIG_SIDLEMODE_SMART 0x00000010
56 #define DISPC_SYSCONFIG_MIDLEMODE_FORCE 0x00000000
57 #define DISPC_SYSCONFIG_MIDLEMODE_NONE 0x00001000
58 #define DISPC_SYSCONFIG_MIDLEMODE_SMART 0x00002000
59 #define DISPC_SYSSTATUS 0x0014
60 #define DISPC_SYSTATUS_RESETDONE 0x00000001
61 #define DISPC_IRQSTATUS 0x0018
62 #define DISPC_IRQSTATUS_FRAMEDONE 0x00000001
63 #define DISPC_IRQSTATUS_VSYNC 0x00000002
64 #define DISPC_IRQSTATUS_EVSYNCEVEN 0x00000004
65 #define DISPC_IRQSTATUS_EVSYNCODD 0x00000008
66 #define DISPC_IRQSTATUS_ACBIASCOUNT 0x00000010
67 #define DISPC_IRQSTATUS_PROGLINENUM 0x00000020
68 #define DISPC_IRQSTATUS_GFXFIFOUNDER 0x00000040
69 #define DISPC_IRQSTATUS_GFXENDWINDOW 0x00000080
70 #define DISPC_IRQSTATUS_PALGAMMA 0x00000100
71 #define DISPC_IRQSTATUS_OCPERROR 0x00000200
72 #define DISPC_IRQSTATUS_VID1FIFOUNDER 0x00000400
73 #define DISPC_IRQSTATUS_VID1ENDWIND 0x00000800
74 #define DISPC_IRQSTATUS_VID2FIFOUNDER 0x00001000
75 #define DISPC_IRQSTATUS_VID2ENDWIND 0x00002000
76 #define DISPC_IRQSTATUS_SYNCLOST 0x00004000
77 #define DISPC_IRQENABLE 0x001C
78 #define DISPC_IRQENABLE_FRAMEDONE 0x00000001
79 #define DISPC_IRQENABLE_VSYNC 0x00000002
80 #define DISPC_IRQENABLE_EVSYNCEVEN 0x00000004
81 #define DISPC_IRQENABLE_EVSYNCODD 0x00000008
82 #define DISPC_IRQENABLE_ACBIASCOUNT 0x00000010
83 #define DISPC_IRQENABLE_PROGLINENUM 0x00000020
84 #define DISPC_IRQENABLE_GFXFIFOUNDER 0x00000040
85 #define DISPC_IRQENABLE_GFXENDWINDOW 0x00000080
86 #define DISPC_IRQENABLE_PALGAMMA 0x00000100
87 #define DISPC_IRQENABLE_OCPERROR 0x00000200
88 #define DISPC_IRQENABLE_VID1FIFOUNDER 0x00000400
89 #define DISPC_IRQENABLE_VID1ENDWIND 0x00000800
90 #define DISPC_IRQENABLE_VID2FIFOUNDER 0x00001000
91 #define DISPC_IRQENABLE_VID2ENDWIND 0x00002000
92 #define DISPC_IRQENABLE_SYNCLOST 0x00004000
93 #define DISPC_CONTROL 0x0040
94 #define DISPC_CONTROL_LCDENABLE 0x00000001
95 #define DISPC_CONTROL_DIGITALENABLE 0x00000002
96 #define DISPC_CONTROL_MONOCOLOR 0x00000004
97 #define DISPC_CONTROL_STNTFT 0x00000008
98 #define DISPC_CONTROL_M8B 0x00000010
99 #define DISPC_CONTROL_GOLCD 0x00000020
100 #define DISPC_CONTROL_GODIGITAL 0x00000040
101 #define DISPC_CONTROL_TFTDITHEREN 0x00000080
102 #define DISPC_CONTROL_TFTDATALINES_12 0x00000000
103 #define DISPC_CONTROL_TFTDATALINES_16 0x00000100
104 #define DISPC_CONTROL_TFTDATALINES_18 0x00000200
105 #define DISPC_CONTROL_TFTDATALINES_24 0x00000300
106 #define DISPC_CONTROL_SECURE 0x00000400
107 #define DISPC_CONTROL_RFBIMODE 0x00000800
108 #define DISPC_CONTROL_OVERLAYOPT 0x00001000
109 #define DISPC_CONTROL_GPIN0 0x00002000
110 #define DISPC_CONTROL_GPIN1 0x00004000
111 #define DISPC_CONTROL_GPOUT0 0x00008000
112 #define DISPC_CONTROL_GPOUT1 0x00010000
113 #define DISPC_CONTROL_HT 0x00070000
114 #define DISPC_CONTROL_HT_s(x) ((x) << 17)
115 #define DISPC_CONTROL_TDMENABLE 0x00100000
116 #define DISPC_CONTROL_TDMPARALLEL_8 0x00000000
117 #define DISPC_CONTROL_TDMPARALLEL_9 0x00200000
118 #define DISPC_CONTROL_TDMPARALLEL_12 0x00400000
119 #define DISPC_CONTROL_TDMPARALLEL_16 0x00600000
120 #define DISPC_CONTROL_TDMCYCLE_1 0x00000000
121 #define DISPC_CONTROL_TDMCYCLE_2 0x00800000
122 #define DISPC_CONTROL_TDMCYCLE_3 0x00000000
123 #define DISPC_CONTROL_TDMCYCLE_3_2 0x01800000
124 #define DISPC_CONTROL_TDMUNUSED_0 0x00000000
125 #define DISPC_CONTROL_TDMUNUSED_1 0x02000000
126 #define DISPC_CONTROL_TDMUNUSED_M 0x04000000
127 #define DISPC_CONFIG 0x0044
128 #define DISPC_CONFIG_PIXELGATED 0x00000001
129 #define DISPC_CONFIG_LOADMODE_PGE 0x00000000
130 #define DISPC_CONFIG_LOADMODE_PG 0x00000002
131 #define DISPC_CONFIG_LOADMODE_DATA 0x00000004
132 #define DISPC_CONFIG_LOADMODE_DATA_PG 0x00000006
133 #define DISPC_CONFIG_PALETTEGAMMA 0x00000008
134 #define DISPC_CONFIG_PIXELDATAGATED 0x00000010
135 #define DISPC_CONFIG_PIXELCLOCKGATED 0x00000020
136 #define DISPC_CONFIG_HSYNCGATED 0x00000040
137 #define DISPC_CONFIG_VSYNCGATED 0x00000080
138 #define DISPC_CONFIG_ACBIAGATED 0x00000100
139 #define DISPC_CONFIG_FUNCGATED 0x00000200
140 #define DISPC_CONFIG_TCKLCDEN 0x00000400
141 #define DISPC_CONFIG_TCKLCDSEL 0x00000800
142 #define DISPC_CONFIG_TCKDIGEN 0x00001000
143 #define DISPC_CONFIG_TCKDIGSEL 0x00002000
144 #define DISPC_CAPABLE 0x0048
145 #define DISPC_DEFAULT_COLOR0 0x004C
146 #define DISPC_DEFAULT_COLOR1 0x0050
147 #define DISPC_TRANS_COLOR0 0x0054
148 #define DISPC_TRANS_COLOR1 0x0058
149 #define DISPC_LINE_STATUS 0x005C
150 #define DISPC_LINE_NUMBER 0x0060
151 #define DISPC_TIMING_H 0x0064
152 #define DISPC_TIMING_H_HSW_s(x) ((x) << 0)
153 #define DISPC_TIMING_H_HFP_s(x) ((x) << 8)
154 #define DISPC_TIMING_H_HBP_s(x) ((x) << 20)
155 #define DISPC_TIMING_V 0x0068
156 #define DISPC_TIMING_V_VSW_s(x) ((x) << 0)
157 #define DISPC_TIMING_V_VFP_s(x) ((x) << 8)
158 #define DISPC_TIMING_V_VBP_s(x) ((x) << 20)
159 #define DISPC_POL_FREQ 0x006C
160 #define DISPC_POL_FREQ_ACB_s(x) ((x) << 0)
161 #define DISPC_POL_FREQ_ACBI_s(x) ((x) << 8)
162 #define DISPC_POL_FREQ_IVS 0x00001000
163 #define DISPC_POL_FREQ_IHS 0x00002000
164 #define DISPC_POL_FREQ_IPC 0x00004000
165 #define DISPC_POL_FREQ_IEO 0x00008000
166 #define DISPC_POL_FREQ_RF 0x00010000
167 #define DISPC_POL_FREQ_ONOFF 0x00020000
168 #define DISPC_DIVISOR 0x0070
169 #define DISPC_DIVISOR_PCD_s(x) ((x) << 0)
170 #define DISPC_DIVISOR_LCD_s(x) ((x) << 16)
171 #define DISPC_SIZE_DIG 0x0078
172 #define DISPC_SIZE_DIG_PPL_s(x) ((x) << 0)
173 #define DISPC_SIZE_DIG_LPP_s(x) ((x) << 16)
174 #define DISPC_SIZE_LCD 0x007C
175 #define DISPC_SIZE_LCD_PPL_s(x) ((x) << 0)
176 #define DISPC_SIZE_LCD_LPP_s(x) ((x) << 16)
177 #define DISPC_GFX_BA0 0x0080
178 #define DISPC_GFX_BA1 0x0084
179 #define DISPC_GFX_POSITION 0x0088
180 #define DISPC_GFX_SIZE 0x008C
181 #define DISPC_GFX_SIZE_X_s(x) ((x) << 0)
182 #define DISPC_GFX_SIZE_Y_s(x) ((x) << 16)
183 #define DISPC_GFX_ATTRIBUTES 0x00A0
184 #define DISPC_GFX_ATTRIBUTES_GFXENABLE 0x001
185 #define DISPC_GFX_ATTRIBUTES_GFXFMT_1 0x000
186 #define DISPC_GFX_ATTRIBUTES_GFXFMT_2 0x002
187 #define DISPC_GFX_ATTRIBUTES_GFXFMT_4 0x004
188 #define DISPC_GFX_ATTRIBUTES_GFXFMT_8 0x006
189 #define DISPC_GFX_ATTRIBUTES_GFXFMT_12 0x008
190 #define DISPC_GFX_ATTRIBUTES_GFXFMT_16 0x00c
191 #define DISPC_GFX_ATTRIBUTES_GFXFMT_24 0x010
192 #define DISPC_GFX_ATTRIBUTES_GFXREPLICATE 0x020
193 #define DISPC_GFX_ATTRIBUTES_BURST_4 0x000
194 #define DISPC_GFX_ATTRIBUTES_BURST_8 0x040
195 #define DISPC_GFX_ATTRIBUTES_BURST_16 0x080
196 #define DISPC_GFX_ATTRIBUTES_GFXCHANNELOUT 0x100
197 #define DISPC_GFX_ATTRIBUTES_NIBBLEMODE 0x200
198 #define DISPC_GFX_ATTRIBUTES_ENDIAN 0x400
199 #define DISPC_GFX_FIFO_THRESHOLD 0x00A4
200 #define DISPC_GFX_FIFO_THRESHOLD_HIGH_SHIFT 16
201 #define DISPC_GFX_FIFO_THRESHOLD_LOW_SHIFT 0
202 #define DISPC_GFX_FIFO_SIZE_STATUS 0x00A8
203 #define DISPC_GFX_ROW_INC 0x00AC
204 #define DISPC_GFX_PIXEL_INC 0x00B0
205 #define DISPC_GFX_WINDOW_SKIP 0x00B4
206 #define DISPC_GFX_TABLE_BA 0x00B8
207 #define DISPC_VID1_BA0 0x00BC
208 #define DISPC_VID1_BA1 0x00C0
209 #define DISPC_VID1_POSITION 0x00C4
210 #define DISPC_VID1_SIZE 0x00C8
211 #define DISPC_VID1_ATTRIBUTES 0x00CC
212 #define DISPC_VID1_FIFO_THRESHOLD 0x00D0
213 #define DISPC_VID1_FIFO_SIZE_STATUS 0x00D4
214 #define DISPC_VID1_ROW_INC 0x00D8
215 #define DISPC_VID1_PIXEL_INC 0x00DC
216 #define DISPC_VID1_FIR 0x00E0
217 #define DISPC_VID1_PICTURE_SIZE 0x00E4
218 #define DISPC_VID1_ACCU0 0x00E8
219 #define DISPC_VID1_ACCU1 0x00EC
220 #define DISPC_VID1_FIR_COEF_H0 0x00F0
221 #define DISPC_VID1_FIR_COEF_H1 0x00F8
222 #define DISPC_VID1_FIR_COEF_H2 0x0100
223 #define DISPC_VID1_FIR_COEF_H3 0x0108
224 #define DISPC_VID1_FIR_COEF_H4 0x0110
225 #define DISPC_VID1_FIR_COEF_H5 0x0118
226 #define DISPC_VID1_FIR_COEF_H6 0x0120
227 #define DISPC_VID1_FIR_COEF_H7 0x0128
228 #define DISPC_VID1_FIR_COEF_HV0 0x00F4
229 #define DISPC_VID1_FIR_COEF_HV1 0x00FC
230 #define DISPC_VID1_FIR_COEF_HV2 0x0104
231 #define DISPC_VID1_FIR_COEF_HV3 0x010C
232 #define DISPC_VID1_FIR_COEF_HV4 0x0114
233 #define DISPC_VID1_FIR_COEF_HV5 0x011C
234 #define DISPC_VID1_FIR_COEF_HV6 0x0124
235 #define DISPC_VID1_FIR_COEF_HV7 0x012C
236 #define DISPC_VID1_CONV_COEF0 0x0130
237 #define DISPC_VID1_CONV_COEF1 0x0134
238 #define DISPC_VID1_CONV_COEF2 0x0138
239 #define DISPC_VID1_CONV_COEF3 0x013C
240 #define DISPC_VID1_CONV_COEF4 0x0140
241 #define DISPC_VID2_BA0 0x014C
242 #define DISPC_VID2_BA1 0x0150
243 #define DISPC_VID2_POSITION 0x0154
244 #define DISPC_VID2_SIZE 0x0158
245 #define DISPC_VID2_ATTRIBUTES 0x015C
246 #define DISPC_VID2_FIFO_THRESHOLD 0x0160
247 #define DISPC_VID2_FIFO_SIZE_STATUS 0x0164
248 #define DISPC_VID2_ROW_INC 0x0168
249 #define DISPC_VID2_PIXEL_INC 0x016C
250 #define DISPC_VID2_FIR 0x0170
251 #define DISPC_VID2_PICTURE_SIZE 0x0174
252 #define DISPC_VID2_ACCU0 0x0178
253 #define DISPC_VID2_ACCU1 0x017C
254 #define DISPC_VID2_FIR_COEF_H0 0x0180
255 #define DISPC_VID2_FIR_COEF_H1 0x0188
256 #define DISPC_VID2_FIR_COEF_H2 0x0190
257 #define DISPC_VID2_FIR_COEF_H3 0x0198
258 #define DISPC_VID2_FIR_COEF_H4 0x01A0
259 #define DISPC_VID2_FIR_COEF_H5 0x01A8
260 #define DISPC_VID2_FIR_COEF_H6 0x01B0
261 #define DISPC_VID2_FIR_COEF_H7 0x01B8
262 #define DISPC_VID2_FIR_COEF_HV0 0x0184
263 #define DISPC_VID2_FIR_COEF_HV1 0x018C
264 #define DISPC_VID2_FIR_COEF_HV2 0x0194
265 #define DISPC_VID2_FIR_COEF_HV3 0x019C
266 #define DISPC_VID2_FIR_COEF_HV4 0x01A4
267 #define DISPC_VID2_FIR_COEF_HV5 0x01AC
268 #define DISPC_VID2_FIR_COEF_HV6 0x01B4
269 #define DISPC_VID2_FIR_COEF_HV7 0x01BC
270 #define DISPC_VID2_CONV_COEF0 0x01C0
271 #define DISPC_VID2_CONV_COEF1 0x01C4
272 #define DISPC_VID2_CONV_COEF2 0x01C8
273 #define DISPC_VID2_CONV_COEF3 0x01CC
274 #define DISPC_VID2_CONV_COEF4 0x01D0
275 #define DISPC_DATA_CYCLE1 0x01D4
276 #define DISPC_DATA_CYCLE2 0x01D8
277 #define DISPC_DATA_CYCLE3 0x01DC
278 #define DISPC_SIZE 0x0200
279
280 /* RFBI */
281 #define RFBI_REVISION 0x0000
282 #define RFBI_SYSCONFIG 0x0010
283 #define RFBI_SYSSTATUS 0x0014
284 #define RFBI_CONTROL 0x0040
285 #define RFBI_PIXEL_CNT 0x0044
286 #define RFBI_LINE_NUMBER 0x0048
287 #define RFBI_CMD 0x004C
288 #define RFBI_PARAM 0x0050
289 #define RFBI_DATA 0x0054
290 #define RFBI_READ 0x0058
291 #define RFBI_STATUS 0x005C
292 #define RFBI_CONFIG0 0x0060
293 #define RFBI_CONFIG1 0x0078
294 #define RFBI_ONOFF_TIME0 0x0064
295 #define RFBI_ONOFF_TIME1 0x007C
296 #define RFBI_CYCLE_TIME0 0x0068
297 #define RFBI_CYCLE_TIME1 0x0080
298 #define RFBI_DATA_CYCLE1_0 0x006C
299 #define RFBI_DATA_CYCLE1_1 0x0084
300 #define RFBI_DATA_CYCLE2_0 0x0070
301 #define RFBI_DATA_CYCLE2_1 0x0088
302 #define RFBI_DATA_CYCLE3_0 0x0074
303 #define RFBI_DATA_CYCLE3_1 0x008C
304 #define RFBI_VSYNC_WIDTH 0x0090
305 #define RFBI_HSYNC_WIDTH 0x0094
306
307 /* VENC1 */
308 #define REV_ID 0x0000
309 #define STATUS 0x0004
310 #define F_CONTROL 0x0008
311 #define VIDOUT_CTRL 0x0010
312 #define SYNC_CTRL 0x0014
313 #define LLEN 0x001C
314 #define FLENS 0x0020
315 #define HFLTR_CTRL 0x0024
316 #define CC_CARR_WSS_CARR 0x0028
317 #define C_PHASE 0x002C
318 #define GAIN_U 0x0030
319 #define GAIN_V 0x0034
320 #define GAIN_Y 0x0038
321 #define BLACK_LEVEL 0x003C
322 #define BLANK_LEVEL 0x0040
323 #define X_COLOR 0x0044
324 #define M_CONTROL 0x0048
325 #define BSTAMP_WSS_DATA 0x004C
326 #define S_CARR 0x0050
327 #define LINE21 0x0054
328 #define LN_SEL 0x0058
329 #define L21_WC_CTL 0x005C
330 #define HTRIGGER_VTRIGGER 0x0060
331 #define SAVID_EAVID 0x0064
332 #define FLEN_FAL 0x0068
333 #define LAL_PHASE_RESET 0x006C
334 #define HS_INT_START_STOP_X 0x0070
335 #define HS_EXT_START_STOP_X 0x0074
336 #define VS_INT_START_X 0x0078
337 #define VS_INT_STOP_X_VS_INT_START_Y 0x007C
338 #define VS_INT_STOP_Y_VS_EXT_START_X 0x0080
339 #define VS_EXT_STOP_X_VS_EXT_START_Y 0x0084
340 #define VS_EXT_STOP_Y 0x0088
341 #define AVID_START_STOP_X 0x0090
342 #define AVID_START_STOP_Y 0x0094
343 #define FID_INT_START_X_FID_INT_START_Y 0x00A0
344 #define FID_INT_OFFSET_Y_FID_EXT_START_X 0x00A4
345 #define FID_EXT_START_Y_FID_EXT_OFFSET_Y 0x00A8
346 #define TVDETGP_INT_START_STOP_X 0x00B0
347 #define TVDETGP_INT_START_STOP_Y 0x00B4
348 #define GEN_CTRL 0x00B8
349 #define DAC_TST_DAC_A 0x00C4
350 #define DAC_B_DAC_C 0x00C8
351
352
353 /* NO CONSOLE SUPPORT */
354
355
356 /* assumes 565 panel. */
357 struct omdisplay_panel_data {
358 int width;
359 int height;
360 int horiz_sync_width;
361 int horiz_front_porch;
362 int horiz_back_porch;
363 int vert_sync_width;
364 int vert_front_porch;
365 int vert_back_porch;
366 int panel_flags;
367 int sync;
368 int depth;
369 #define PANEL_SYNC_H_ACTIVE_HIGH 1
370 #define PANEL_SYNC_V_ACTIVE_HIGH 2
371 int linebytes;
372 };
373
374 #define PIXELDEPTH 16
375 #define PIXELWIDTH 2
376
377 struct omdisplay_panel_data default_panel = {
378 240, /* Width */
379 322, /* Height */
380 9, 9, 19, /* horiz sync, fp, bp */
381 1, 2, 2, /* vert sync, fp, bp */
382 0, /* flags */
383 0, /* sync */
384 PIXELDEPTH,
385 240*PIXELWIDTH
386 };
387
388 struct omdisplay_screen {
389 LIST_ENTRY(omdisplay_screen) link;
390
391 /* Frame buffer */
392 bus_dmamap_t dma;
393 bus_dma_segment_t segs[1];
394 int nsegs;
395 size_t buf_size;
396 size_t map_size;
397 void *buf_va;
398 int depth;
399
400 /* rasterop */
401 struct rasops_info rinfo;
402 };
403
404 struct omdisplay_softc {
405 struct device sc_dev;
406 bus_space_tag_t sc_iot;
407 bus_space_handle_t sc_dsioh;
408 bus_space_handle_t sc_dcioh;
409 bus_space_handle_t sc_rfbioh;
410 bus_space_handle_t sc_venioh;
411 bus_dma_tag_t sc_dma_tag;
412
413 void *sc_ih;
414
415 int sc_nscreens;
416 LIST_HEAD(,omdisplay_screen) sc_screens;
417
418 struct omdisplay_panel_data *sc_geometry;
419 struct omdisplay_screen *sc_active;
420 };
421
422 int omdisplay_match(struct device *parent, void *v, void *aux);
423 void omdisplay_attach(struct device *parent, struct device *self, void *args);
424 int omdisplay_activate(struct device *, int);
425 int omdisplay_ioctl(void *v, u_long cmd, caddr_t data, int flag,
426 struct proc *p);
427 void omdisplay_burner(void *v, u_int on, u_int flags);
428 int omdisplay_show_screen(void *v, void *cookie, int waitok,
429 void (*cb)(void *, int, int), void *cbarg);
430 int omdisplay_param(struct omdisplay_softc *sc, ulong cmd,
431 struct wsdisplay_param *dp);
432 int omdisplay_max_brightness(void);
433 int omdisplay_get_brightness(void);
434 void omdisplay_set_brightness(int newval);
435 void omdisplay_set_brightness_internal(int newval);
436 int omdisplay_get_backlight(void);
437 void omdisplay_set_backlight(int on);
438 void omdisplay_blank(int blank);
439 void omdisplay_suspend(struct omdisplay_softc *sc);
440 void omdisplay_resume(struct omdisplay_softc *sc);
441 void omdisplay_initialize(struct omdisplay_softc *sc,
442 struct omdisplay_panel_data *geom);
443 void omdisplay_setup_rasops(struct omdisplay_softc *sc,
444 struct rasops_info *rinfo);
445 int omdisplay_alloc_screen(void *v, const struct wsscreen_descr *_type,
446 void **cookiep, int *curxp, int *curyp, uint32_t *attrp);
447 int omdisplay_new_screen(struct omdisplay_softc *sc,
448 struct omdisplay_screen *scr, int depth);
449 paddr_t omdisplay_mmap(void *v, off_t offset, int prot);
450 int omdisplay_load_font(void *, void *, struct wsdisplay_font *);
451 int omdisplay_list_font(void *, struct wsdisplay_font *);
452 void omdisplay_free_screen(void *v, void *cookie);
453 void omdisplay_start(struct omdisplay_softc *sc);
454 void omdisplay_stop(struct omdisplay_softc *sc);
455 int omdisplay_intr(void *v);
456
457 const struct cfattach omdisplay_ca = {
458 sizeof (struct omdisplay_softc), omdisplay_match, omdisplay_attach,
459 NULL, omdisplay_activate
460 };
461
462 struct cfdriver omdisplay_cd = {
463 NULL, "omdisplay", DV_DULL
464 };
465
466 struct wsdisplay_accessops omdisplay_accessops = {
467 .ioctl = omdisplay_ioctl,
468 .mmap = omdisplay_mmap,
469 .alloc_screen = omdisplay_alloc_screen,
470 .free_screen = omdisplay_free_screen,
471 .show_screen = omdisplay_show_screen,
472 .load_font = omdisplay_load_font,
473 .list_font = omdisplay_list_font,
474 .burn_screen = omdisplay_burner
475
476 };
477
478 struct omdisplay_wsscreen_descr {
479 struct wsscreen_descr c; /* standard descriptor */
480 int depth; /* bits per pixel */
481 int flags; /* rasops flags */
482 };
483
484 struct omdisplay_wsscreen_descr omdisplay_screen = {
485 {
486 "std"
487 },
488 16, /* bits per pixel */
489 0 /* rotate */
490 };
491
492 const struct wsscreen_descr *omdisplay_scr_descr[] = {
493 &omdisplay_screen.c
494 };
495
496 /* XXX - what about flip phones with CLI */
497 const struct wsscreen_list omdisplay_screen_list = {
498 sizeof omdisplay_scr_descr / sizeof omdisplay_scr_descr[0],
499 omdisplay_scr_descr
500 };
501
502
503 int
omdisplay_match(struct device * parent,void * v,void * aux)504 omdisplay_match(struct device *parent, void *v, void *aux)
505 {
506 /* XXX */
507 return (1);
508 }
509
510 void
omdisplay_attach(struct device * parent,struct device * self,void * args)511 omdisplay_attach(struct device *parent, struct device *self, void *args)
512 {
513 struct ahb_attach_args *aa = args;
514 struct omdisplay_softc *sc = (struct omdisplay_softc *) self;
515 struct wsemuldisplaydev_attach_args wsaa;
516
517
518 sc->sc_iot = aa->aa_iot;
519
520 if (bus_space_map(sc->sc_iot, aa->aa_addr, OMDISPLAY_SIZE, 0,
521 &sc->sc_dsioh))
522 panic("omdisplay_attach: bus_space_map failed!");
523
524 if (bus_space_subregion(sc->sc_iot, sc->sc_dsioh, 0x400, 1024,
525 &sc->sc_dcioh))
526 panic("omdisplay_attach: bus_space_submap failed!");
527
528 if (bus_space_subregion(sc->sc_iot, sc->sc_dsioh, 0x800, 1024,
529 &sc->sc_rfbioh))
530 panic("omdisplay_attach: bus_space_submap failed!");
531
532 if (bus_space_subregion(sc->sc_iot, sc->sc_dsioh, 0xc00, 1024,
533 &sc->sc_venioh))
534 panic("omdisplay_attach: bus_space_submap failed!");
535
536
537 sc->sc_nscreens = 0;
538 LIST_INIT(&sc->sc_screens);
539
540 sc->sc_dma_tag = aa->aa_dmat;
541
542 sc->sc_ih = arm_intr_establish(aa->aa_intr, IPL_BIO /* XXX */,
543 omdisplay_intr, sc, sc->sc_dev.dv_xname);
544
545 printf ("\n");
546
547 sc->sc_geometry = &default_panel;
548
549 {
550 /* XXX - dummy? */
551 struct rasops_info dummy;
552
553 omdisplay_initialize(sc, sc->sc_geometry);
554
555 /*
556 * Initialize a dummy rasops_info to compute fontsize and
557 * the screen size in chars.
558 */
559 bzero(&dummy, sizeof(dummy));
560 omdisplay_setup_rasops(sc, &dummy);
561 }
562
563 wsaa.console = 0;
564 wsaa.scrdata = &omdisplay_screen_list;
565 wsaa.accessops = &omdisplay_accessops;
566 wsaa.accesscookie = sc;
567 wsaa.defaultscreens = 0;
568
569 (void)config_found(self, &wsaa, wsemuldisplaydevprint);
570
571 /* backlight? */
572 }
573
574
575 int
omdisplay_ioctl(void * v,u_long cmd,caddr_t data,int flag,struct proc * p)576 omdisplay_ioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p)
577 {
578 struct omdisplay_softc *sc = v;
579 struct wsdisplay_fbinfo *wsdisp_info;
580 struct omdisplay_screen *scr = sc->sc_active;
581 int res = EINVAL;
582
583 switch (cmd) {
584 case WSDISPLAYIO_GETPARAM:
585 case WSDISPLAYIO_SETPARAM:
586 res = omdisplay_param(sc, cmd, (struct wsdisplay_param *)data);
587 break;
588 case WSDISPLAYIO_GTYPE:
589 *(u_int *)data = WSDISPLAY_TYPE_PXALCD; /* XXX */
590 break;
591
592 case WSDISPLAYIO_GINFO:
593 wsdisp_info = (struct wsdisplay_fbinfo *)data;
594
595 wsdisp_info->height = sc->sc_geometry->height;
596 wsdisp_info->width = sc->sc_geometry->width;
597 wsdisp_info->depth = 16; /* XXX */
598 if (scr != NULL)
599 wsdisp_info->stride = scr->rinfo.r_stride;
600 else
601 wsdisp_info->stride = 0;
602 wsdisp_info->offset = 0;
603 wsdisp_info->cmsize = 0;
604 break;
605
606 case WSDISPLAYIO_GETCMAP:
607 case WSDISPLAYIO_PUTCMAP:
608 return EINVAL; /* XXX Colormap */
609
610 case WSDISPLAYIO_SVIDEO:
611 case WSDISPLAYIO_GVIDEO:
612 break;
613
614 case WSDISPLAYIO_GCURPOS:
615 case WSDISPLAYIO_SCURPOS:
616 case WSDISPLAYIO_GCURMAX:
617 case WSDISPLAYIO_GCURSOR:
618 case WSDISPLAYIO_SCURSOR:
619 default:
620 return -1; /* not implemented */
621
622 case WSDISPLAYIO_LINEBYTES:
623 if (scr != NULL)
624 *(u_int *)data = scr->rinfo.ri_stride;
625 else
626 *(u_int *)data = 0;
627 break;
628
629 }
630
631 if (res == EINVAL)
632 res = omdisplay_ioctl(v, cmd, data, flag, p);
633
634 return res;
635 }
636
637 void
omdisplay_burner(void * v,u_int on,u_int flags)638 omdisplay_burner(void *v, u_int on, u_int flags)
639 {
640
641 omdisplay_set_brightness(on ? omdisplay_get_brightness() : 0);
642
643 /* GPIO controls for appsliver */
644 if (on) {
645 omgpio_set_bit(93); /* 1 enable backlight */
646 omgpio_set_dir(93, OMGPIO_DIR_OUT);
647 omgpio_clear_bit(26); /* 0 enable LCD */
648 omgpio_set_dir(26, OMGPIO_DIR_OUT);
649 } else {
650 omgpio_clear_bit(93); /* 0 disable backlt */
651 omgpio_set_dir(93, OMGPIO_DIR_OUT);
652 omgpio_set_bit(26); /* 1 disable LCD */
653 omgpio_set_dir(26, OMGPIO_DIR_OUT);
654 }
655 }
656
657 int
omdisplay_show_screen(void * v,void * cookie,int waitok,void (* cb)(void *,int,int),void * cbarg)658 omdisplay_show_screen(void *v, void *cookie, int waitok,
659 void (*cb)(void *, int, int), void *cbarg)
660 {
661 struct omdisplay_softc *sc = v;
662 struct rasops_info *ri = cookie;
663 struct omdisplay_screen *scr = ri->ri_hw, *old;
664
665 old = sc->sc_active;
666 if (old == scr)
667 return 0;
668
669 if (old != NULL)
670 ; /* Stop old screen */
671
672 sc->sc_active = scr;
673 omdisplay_initialize(sc, sc->sc_geometry);
674
675 /* Turn on LCD */
676 omdisplay_burner(v, 1, 0);
677
678 return (0);
679 }
680
681
682
683 /*
684 * wsdisplay I/O controls
685 */
686 int
omdisplay_param(struct omdisplay_softc * sc,ulong cmd,struct wsdisplay_param * dp)687 omdisplay_param(struct omdisplay_softc *sc, ulong cmd,
688 struct wsdisplay_param *dp)
689 {
690 int res = EINVAL;
691
692 switch (dp->param) {
693 case WSDISPLAYIO_PARAM_BACKLIGHT:
694 if (cmd == WSDISPLAYIO_GETPARAM) {
695 dp->min = 0;
696 dp->max = 1;
697 dp->curval = omdisplay_get_backlight();
698 res = 0;
699 } else if (cmd == WSDISPLAYIO_SETPARAM) {
700 /* XXX */
701 // omdisplay_set_backlight(dp->curval);
702 res = 0;
703 }
704 break;
705
706 case WSDISPLAYIO_PARAM_CONTRAST:
707 /* unsupported */
708 res = ENOTTY;
709 break;
710
711 case WSDISPLAYIO_PARAM_BRIGHTNESS:
712 if (cmd == WSDISPLAYIO_GETPARAM) {
713 dp->min = 1;
714 dp->max = omdisplay_max_brightness();
715 dp->curval = omdisplay_get_brightness();
716 res = 0;
717 } else if (cmd == WSDISPLAYIO_SETPARAM) {
718 /* XXX */
719 // omdisplay_set_brightness(dp->curval);
720 res = 0;
721 }
722 break;
723 }
724
725 return res;
726 }
727
728
729 /*
730 * LCD backlight
731 */
732
733 static int lcdbrightnesscurval = 1;
734 static int lcdislit = 1;
735 static int lcdisblank = 0;
736
737 struct lcd_backlight {
738 int duty; /* LZ9JG18 DAC value */
739 int cont; /* BACKLIGHT_CONT signal */
740 int on; /* BACKLIGHT_ON signal */
741 };
742
743 const struct lcd_backlight lcd_bl[] = {
744 { 0x00, 0, 0 }, /* 0: Off */
745 { 0x00, 0, 1 }, /* 1: 0% */
746 { 0x01, 0, 1 }, /* 2: 20% */
747 { 0x07, 0, 1 }, /* 3: 40% */
748 { 0x01, 1, 1 }, /* 4: 60% */
749 { 0x07, 1, 1 }, /* 5: 80% */
750 { 0x11, 1, 1 }, /* 6: 100% */
751 { -1, -1, -1 } /* 7: Invalid */
752 };
753 #define CURRENT_BACKLIGHT lcd_bl
754
755 int
omdisplay_max_brightness(void)756 omdisplay_max_brightness(void)
757 {
758 int i;
759
760 for (i = 0; CURRENT_BACKLIGHT[i].duty != -1; i++)
761 ;
762 return i - 1;
763 }
764
765 int
omdisplay_get_brightness(void)766 omdisplay_get_brightness(void)
767 {
768
769 return lcdbrightnesscurval;
770 }
771
772 void
omdisplay_set_brightness(int newval)773 omdisplay_set_brightness(int newval)
774 {
775 int max;
776
777 max = omdisplay_max_brightness();
778 if (newval < 0)
779 newval = 0;
780 else if (newval > max)
781 newval = max;
782
783 if (omdisplay_get_backlight() && !lcdisblank)
784 omdisplay_set_brightness_internal(newval);
785
786 if (newval > 0)
787 lcdbrightnesscurval = newval;
788 }
789
790 void
omdisplay_set_brightness_internal(int newval)791 omdisplay_set_brightness_internal(int newval)
792 {
793 static int curval = 1;
794 int i;
795
796 /*
797 * It appears that the C3000 backlight can draw too much power if we
798 * switch it from a low to a high brightness. Increasing brightness
799 * in steps avoids this issue.
800 */
801 if (newval > curval) {
802 for (i = curval + 1; i <= newval; i++) {
803 /* atlas controls */
804 /* CURRENT_BACKLIGHT[newval].duty); */
805 }
806 } else {
807 /* atlas controls */
808 /* CURRENT_BACKLIGHT[newval].duty); */
809 }
810
811 curval = newval;
812 }
813
814 int
omdisplay_get_backlight(void)815 omdisplay_get_backlight(void)
816 {
817
818 return lcdislit;
819 }
820
821 void
omdisplay_set_backlight(int on)822 omdisplay_set_backlight(int on)
823 {
824
825 if (!on) {
826 omdisplay_set_brightness(0);
827 lcdislit = 0;
828 } else {
829 lcdislit = 1;
830 omdisplay_set_brightness(omdisplay_get_brightness());
831 }
832 }
833
834 void
omdisplay_blank(int blank)835 omdisplay_blank(int blank)
836 {
837
838 if (blank) {
839 omdisplay_set_brightness(0);
840 lcdisblank = 1;
841 } else {
842 lcdisblank = 0;
843 omdisplay_set_brightness(omdisplay_get_brightness());
844 }
845 }
846
847 void
omdisplay_suspend(struct omdisplay_softc * sc)848 omdisplay_suspend(struct omdisplay_softc *sc)
849 {
850 if (sc->sc_active != NULL) {
851 omdisplay_stop(sc);
852 /* XXX disable clocks */
853 }
854 }
855
856 void
omdisplay_resume(struct omdisplay_softc * sc)857 omdisplay_resume(struct omdisplay_softc *sc)
858 {
859 if (sc->sc_active != NULL) {
860 /* XXX - clocks? */
861 omdisplay_initialize(sc, sc->sc_geometry);
862 omdisplay_start(sc);
863 }
864 }
865
866 void
omdisplay_activate(struct device * self,int act)867 omdisplay_activate(struct device *self, int act)
868 {
869 struct omdisplay_softc *sc = (struct omdisplay_softc *)self;
870
871 switch (act) {
872 case DVACT_SUSPEND:
873 omdisplay_set_brightness(0);
874 omdisplay_suspend(sc);
875 break;
876 case DVACT_RESUME:
877 omdisplay_resume(sc);
878 omdisplay_set_brightness(omdisplay_get_brightness());
879 break;
880 }
881 return 0;
882 }
883
884 void
omdisplay_initialize(struct omdisplay_softc * sc,struct omdisplay_panel_data * geom)885 omdisplay_initialize(struct omdisplay_softc *sc,
886 struct omdisplay_panel_data *geom)
887 {
888 struct omdisplay_screen *scr;
889 u_int32_t reg;
890 u_int32_t mode;
891 #if 0
892 int den, nom; /* pixel rate */
893 #endif
894
895
896 reg = bus_space_read_4(sc->sc_iot, sc->sc_dcioh, DISPC_CONTROL);
897
898 scr = sc->sc_active;
899
900 if (reg & (DISPC_CONTROL_LCDENABLE|DISPC_CONTROL_DIGITALENABLE)) {
901 omdisplay_stop(sc);
902 }
903
904 /* XXX - enable clocks */
905
906 /* disable all interrupts */
907 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_IRQENABLE, 0);
908
909 /* GPIOs ? */
910
911 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_CONFIG,
912 DISPC_CONFIG_LOADMODE_PG|DISPC_CONFIG_LOADMODE_DATA);
913
914 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_DEFAULT_COLOR0, 0);
915 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_DEFAULT_COLOR1, 0);
916 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_TRANS_COLOR0, 0);
917 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_TRANS_COLOR1, 0);
918 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_LINE_NUMBER, 0);
919 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_DATA_CYCLE1, 0);
920 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_DATA_CYCLE2, 0);
921 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_DATA_CYCLE3, 0);
922
923 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_SYSCONFIG,
924 DISPC_SYSCONFIG_SIDLEMODE_NONE|
925 DISPC_SYSCONFIG_MIDLEMODE_NONE);
926
927 #if 0
928 if (geom->panel_flags & LCDPANEL_TDM) {
929 nom = tdmflags >>8 & 0x3;
930 den = tdmflags & 0x3;
931 } else {
932 nom = 1;
933 den = 1;
934 }
935 hsync = geom->width*den/nom + geom->horiz_sync_width +
936 geom->horiz_front_porch + geom->horiz_back_porch;
937 #endif
938
939 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_TIMING_H,
940 DISPC_TIMING_H_HSW_s(geom->horiz_sync_width) |
941 DISPC_TIMING_H_HFP_s(geom->horiz_front_porch) |
942 DISPC_TIMING_H_HBP_s(geom->horiz_back_porch));
943 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_TIMING_V,
944 DISPC_TIMING_V_VSW_s(geom->vert_sync_width) |
945 DISPC_TIMING_V_VFP_s(geom->vert_front_porch) |
946 DISPC_TIMING_V_VBP_s(geom->vert_back_porch));
947
948 reg = 0;
949 if (geom->sync & PANEL_SYNC_H_ACTIVE_HIGH)
950 reg |= DISPC_POL_FREQ_IHS;
951 if (geom->sync & PANEL_SYNC_V_ACTIVE_HIGH)
952 reg |= DISPC_POL_FREQ_IVS;
953 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_POL_FREQ, reg);
954
955
956 /* clkdiv = pixclock/period; */
957 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_SIZE_LCD,
958 DISPC_SIZE_LCD_PPL_s(geom->width-1) |
959 DISPC_SIZE_LCD_LPP_s(geom->height-1));
960 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_SIZE_DIG,
961 DISPC_SIZE_LCD_PPL_s(geom->width-1) |
962 DISPC_SIZE_LCD_LPP_s(geom->height-1));
963
964 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_SIZE,
965 DISPC_GFX_SIZE_X_s(geom->width-1) |
966 DISPC_GFX_SIZE_Y_s(geom->height-1));
967
968
969 /* XXX!!! */
970 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_DIVISOR,
971 DISPC_DIVISOR_LCD_s(1) | DISPC_DIVISOR_PCD_s(6));
972
973 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_BA0,
974 scr->segs[0].ds_addr);
975 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_BA1,
976 scr->segs[0].ds_addr);
977
978 /* non-rotated */
979 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_PIXEL_INC, 1);
980
981
982 /* XXX 24bit -> 32 pixels */
983 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_ROW_INC,
984 1 + scr->rinfo.ri_stride -
985 (scr->rinfo.ri_width * scr->rinfo.ri_depth / 8));
986
987 switch (geom->depth) {
988 case 1:
989 mode = DISPC_GFX_ATTRIBUTES_GFXFMT_1;
990 break;
991 case 2:
992 mode = DISPC_GFX_ATTRIBUTES_GFXFMT_2;
993 break;
994 case 4:
995 mode = DISPC_GFX_ATTRIBUTES_GFXFMT_4;
996 break;
997 case 8:
998 mode = DISPC_GFX_ATTRIBUTES_GFXFMT_8;
999 break;
1000 case 12:
1001 mode = DISPC_GFX_ATTRIBUTES_GFXFMT_12;
1002 break;
1003 case 16:
1004 mode = DISPC_GFX_ATTRIBUTES_GFXFMT_16;
1005 break;
1006 case 24:
1007 mode = DISPC_GFX_ATTRIBUTES_GFXFMT_24;
1008 break;
1009 default:
1010 panic("invalid depth %d", geom->depth);
1011 }
1012 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_ATTRIBUTES,
1013 DISPC_GFX_ATTRIBUTES_GFXENABLE | mode |
1014 DISPC_GFX_ATTRIBUTES_BURST_8);
1015
1016 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_POSITION, 0);
1017 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_WINDOW_SKIP, 0);
1018 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_FIFO_THRESHOLD,
1019 (0xfc << DISPC_GFX_FIFO_THRESHOLD_HIGH_SHIFT) |
1020 (0xc0 << DISPC_GFX_FIFO_THRESHOLD_LOW_SHIFT));
1021
1022 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_ROW_INC, 1);
1023 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_PIXEL_INC, 1);
1024
1025 /* DISPC_CONFIG_PALETTEGAMMA not enabled */
1026 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_GFX_TABLE_BA,
1027 scr->segs[0].ds_addr);
1028
1029 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_BA0, 0);
1030 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_BA1, 0);
1031 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_SIZE, 0);
1032 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_ATTRIBUTES, 0);
1033 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIFO_THRESHOLD,
1034 0xc00040); /* XXX */
1035 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIFO_SIZE_STATUS,
1036 0);
1037 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_ROW_INC, 1);
1038 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_PIXEL_INC, 1);
1039 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR, 0);
1040 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_PICTURE_SIZE, 0);
1041 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_ACCU0, 0);
1042 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_ACCU1, 0);
1043 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_H0, 0);
1044 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_H1, 0);
1045 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_H2, 0);
1046 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_H3, 0);
1047 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_H4, 0);
1048 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_H5, 0);
1049 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_H6, 0);
1050 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_H7, 0);
1051 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_HV0, 0);
1052 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_HV1, 0);
1053 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_HV2, 0);
1054 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_HV3, 0);
1055 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_HV4, 0);
1056 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_HV5, 0);
1057 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_HV6, 0);
1058 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_FIR_COEF_HV7, 0);
1059 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_CONV_COEF0, 0);
1060 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_CONV_COEF1, 0);
1061 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_CONV_COEF2, 0);
1062 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_CONV_COEF3, 0);
1063 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID1_CONV_COEF4, 0);
1064
1065 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_BA0, 0);
1066 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_BA1, 0);
1067 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_SIZE, 0);
1068 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_ATTRIBUTES, 0);
1069 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIFO_THRESHOLD,
1070 0xc00040); /* XXX */
1071 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIFO_SIZE_STATUS,
1072 0);
1073 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_ROW_INC, 1);
1074 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_PIXEL_INC, 1);
1075 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR, 0);
1076 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_PICTURE_SIZE, 0);
1077 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_ACCU0, 0);
1078 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_ACCU1, 0);
1079 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_H0, 0);
1080 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_H1, 0);
1081 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_H2, 0);
1082 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_H3, 0);
1083 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_H4, 0);
1084 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_H5, 0);
1085 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_H6, 0);
1086 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_H7, 0);
1087 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_HV0, 0);
1088 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_HV1, 0);
1089 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_HV2, 0);
1090 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_HV3, 0);
1091 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_HV4, 0);
1092 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_HV5, 0);
1093 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_HV6, 0);
1094 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_FIR_COEF_HV7, 0);
1095 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_CONV_COEF0, 0);
1096 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_CONV_COEF1, 0);
1097 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_CONV_COEF2, 0);
1098 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_CONV_COEF3, 0);
1099 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_VID2_CONV_COEF4, 0);
1100
1101 omdisplay_start(sc);
1102 }
1103
1104 void
omdisplay_setup_rasops(struct omdisplay_softc * sc,struct rasops_info * rinfo)1105 omdisplay_setup_rasops(struct omdisplay_softc *sc, struct rasops_info *rinfo)
1106 {
1107 struct omdisplay_wsscreen_descr *descr;
1108 struct omdisplay_panel_data *geom;
1109
1110 descr = &omdisplay_screen;
1111 geom = sc->sc_geometry;
1112
1113 rinfo->ri_flg = descr->flags;
1114 rinfo->ri_depth = descr->depth;
1115 rinfo->ri_width = geom->width;
1116 rinfo->ri_height = geom->height;
1117 rinfo->ri_stride = geom->linebytes;
1118
1119 /* pixel position */
1120 if (descr->depth == 16) {
1121 rinfo->ri_rnum = 5;
1122 rinfo->ri_rpos = 11;
1123 rinfo->ri_gnum = 6;
1124 rinfo->ri_gpos = 5;
1125 rinfo->ri_bnum = 5;
1126 rinfo->ri_bpos = 0;
1127 }
1128
1129 if (descr->c.nrows == 0) {
1130 /* get rasops to compute screen size the first time */
1131 rasops_init(rinfo, 100, 100);
1132 } else {
1133 if (descr->flags != 0) /* rotate */
1134 rasops_init(rinfo, descr->c.ncols, descr->c.nrows);
1135 else
1136 rasops_init(rinfo, descr->c.nrows, descr->c.ncols);
1137 }
1138
1139 descr->c.nrows = rinfo->ri_rows;
1140 descr->c.ncols = rinfo->ri_cols;
1141 descr->c.capabilities = rinfo->ri_caps;
1142 descr->c.textops = &rinfo->ri_ops;
1143
1144 }
1145
1146
1147 int
omdisplay_alloc_screen(void * v,const struct wsscreen_descr * _type,void ** cookiep,int * curxp,int * curyp,uint32_t * attrp)1148 omdisplay_alloc_screen(void *v, const struct wsscreen_descr *_type,
1149 void **cookiep, int *curxp, int *curyp, uint32_t *attrp)
1150 {
1151 struct omdisplay_softc *sc = v;
1152 struct omdisplay_screen *scr;
1153 struct rasops_info *ri;
1154 struct omdisplay_wsscreen_descr *type =
1155 (struct omdisplay_wsscreen_descr *)_type;
1156 int error;
1157
1158 scr = malloc(sizeof *scr, M_DEVBUF, (cold ? M_NOWAIT : M_WAITOK));
1159 if (scr == NULL)
1160 return (ENOMEM);
1161
1162 error = omdisplay_new_screen(sc, scr, type->depth);
1163 if (error != 0) {
1164 free(scr, M_DEVBUF, 0);
1165 return (error);
1166 }
1167
1168 /*
1169 * initialize raster operation for this screen.
1170 */
1171 ri = &scr->rinfo;
1172 ri->ri_hw = (void *)scr;
1173 ri->ri_bits = scr->buf_va;
1174 omdisplay_setup_rasops(sc, ri);
1175
1176 /* assumes 16 bpp */
1177 ri->ri_ops.pack_attr(ri, 0, 0, 0, attrp);
1178
1179 *cookiep = ri;
1180 *curxp = 0;
1181 *curyp = 0;
1182
1183 return 0;
1184 }
1185
1186 /*
1187 * Create and initialize a new screen buffer.
1188 */
1189 int
omdisplay_new_screen(struct omdisplay_softc * sc,struct omdisplay_screen * scr,int depth)1190 omdisplay_new_screen(struct omdisplay_softc *sc,
1191 struct omdisplay_screen *scr, int depth)
1192 {
1193 bus_space_tag_t iot;
1194 bus_space_handle_t ioh;
1195 bus_dma_tag_t dma_tag;
1196 struct omdisplay_panel_data *geometry;
1197 int width, height;
1198 bus_size_t size;
1199 int error, palette_size;
1200 int busdma_flag = (cold ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
1201
1202 if (sc != NULL) {
1203 iot = sc->sc_iot;
1204 ioh = sc->sc_dcioh;
1205 dma_tag = sc->sc_dma_tag;
1206 geometry = sc->sc_geometry;
1207 } else {
1208 /* We are creating the console screen. */
1209 #if 0
1210 iot = omdisplay_console.iot;
1211 ioh = omdisplay_console.ioh;
1212 dma_tag = omdisplay_console.dma_tag;
1213 geometry = omdisplay_console.geometry;
1214 #endif
1215 }
1216
1217 width = geometry->width;
1218 height = geometry->height;
1219 palette_size = 0;
1220
1221 switch (depth) {
1222 case 1:
1223 case 2:
1224 case 4:
1225 case 8:
1226 palette_size = (1 << depth) * sizeof (uint16_t);
1227 /* FALLTHROUGH */
1228 case 16:
1229 case 24:
1230 size = geometry->height * geometry->linebytes;
1231 break;
1232 default:
1233 printf("%s: Unknown depth (%d)\n",
1234 sc != NULL ? sc->sc_dev.dv_xname : "console", depth);
1235 return (EINVAL);
1236 }
1237
1238 bzero(scr, sizeof *scr);
1239
1240 scr->nsegs = 0;
1241 scr->depth = depth;
1242 scr->buf_size = size;
1243 scr->buf_va = NULL;
1244 size = roundup(size, 16);
1245 #if 0
1246 + 3 * sizeof (struct lcd_dma_descriptor)
1247 + palette_size;
1248 #endif
1249
1250 error = bus_dmamem_alloc(dma_tag, size, 0x100000, 0,
1251 scr->segs, 1, &(scr->nsegs), busdma_flag);
1252 if (error != 0 || scr->nsegs != 1) {
1253 /* XXX: Actually we can handle nsegs > 1 case by means
1254 of multiple DMA descriptors for a panel. It would
1255 make code here a bit hairy */
1256 if (error == 0)
1257 error = E2BIG;
1258 goto bad;
1259 }
1260
1261 error = bus_dmamem_map(dma_tag, scr->segs, scr->nsegs,
1262 size, (caddr_t *)&(scr->buf_va), busdma_flag | BUS_DMA_COHERENT);
1263 if (error != 0)
1264 goto bad;
1265
1266 memset(scr->buf_va, 0, scr->buf_size);
1267 bcopy(splash, scr->buf_va,
1268 sizeof (splash) > scr->buf_size ? scr->buf_size : sizeof (splash));
1269
1270 /* map memory for DMA */
1271 if (bus_dmamap_create(dma_tag, 1024 * 1024 * 2, 1,
1272 1024 * 1024 * 2, 0, busdma_flag, &scr->dma))
1273 goto bad;
1274 error = bus_dmamap_load(dma_tag, scr->dma,
1275 scr->buf_va, size, NULL, busdma_flag);
1276 if (error != 0) {
1277 goto bad;
1278 }
1279
1280 scr->map_size = size; /* used when unmap this. */
1281
1282 if (sc != NULL) {
1283 LIST_INSERT_HEAD(&(sc->sc_screens), scr, link);
1284 sc->sc_nscreens++;
1285 }
1286
1287 omdisplay_initialize(sc, geometry);
1288
1289 return (0);
1290
1291 bad:
1292 if (scr->buf_va)
1293 bus_dmamem_unmap(dma_tag, scr->buf_va, size);
1294 if (scr->nsegs)
1295 bus_dmamem_free(dma_tag, scr->segs, scr->nsegs);
1296 return (error);
1297 }
1298 paddr_t
omdisplay_mmap(void * v,off_t offset,int prot)1299 omdisplay_mmap(void *v, off_t offset, int prot)
1300 {
1301 struct omdisplay_softc *sc = v;
1302 struct omdisplay_screen *screen = sc->sc_active; /* ??? */
1303
1304 if ((offset & PAGE_MASK) != 0)
1305 return (-1);
1306
1307 if (screen == NULL)
1308 return (-1);
1309
1310 if (offset < 0 ||
1311 offset >= screen->rinfo.ri_stride * screen->rinfo.ri_height)
1312 return (-1);
1313
1314 return (bus_dmamem_mmap(sc->sc_dma_tag, screen->segs, screen->nsegs,
1315 offset, prot, BUS_DMA_WAITOK | BUS_DMA_COHERENT));
1316 }
1317
1318 void
omdisplay_free_screen(void * v,void * cookie)1319 omdisplay_free_screen(void *v, void *cookie)
1320 {
1321 struct omdisplay_softc *sc = v;
1322 struct rasops_info *ri = cookie;
1323 struct omdisplay_screen *scr = ri->ri_hw;
1324
1325 LIST_REMOVE(scr, link);
1326 sc->sc_nscreens--;
1327 if (scr == sc->sc_active) {
1328 /* at first, we need to stop LCD DMA */
1329 sc->sc_active = NULL;
1330
1331 #ifdef DEBUG
1332 printf("lcd_free on active screen\n");
1333 #endif
1334
1335 omdisplay_stop(sc);
1336 }
1337
1338 if (scr->buf_va)
1339 bus_dmamem_unmap(sc->sc_dma_tag, scr->buf_va, scr->map_size);
1340
1341 if (scr->nsegs > 0)
1342 bus_dmamem_free(sc->sc_dma_tag, scr->segs, scr->nsegs);
1343
1344 free(scr, M_DEVBUF, 0);
1345 }
1346
1347 int
omdisplay_load_font(void * v,void * emulcookie,struct wsdisplay_font * font)1348 omdisplay_load_font(void *v, void *emulcookie, struct wsdisplay_font *font)
1349 {
1350 struct omdisplay_softc *sc = v;
1351 struct omdisplay_screen *scr = sc->sc_active;
1352
1353 if (scr == NULL)
1354 return ENXIO;
1355
1356 return rasops_load_font(scr->rinfo, emulcookie, font);
1357 }
1358
1359 int
omdisplay_list_font(void * v,struct wsdisplay_font * font)1360 omdisplay_list_font(void *v, struct wsdisplay_font *font)
1361 {
1362 struct omdisplay_softc *sc = v;
1363 struct omdisplay_screen *scr = sc->sc_active;
1364
1365 if (scr == NULL)
1366 return ENXIO;
1367
1368 return rasops_list_font(scr->rinfo, font);
1369 }
1370
1371 void
omdisplay_start(struct omdisplay_softc * sc)1372 omdisplay_start(struct omdisplay_softc *sc)
1373 {
1374 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_CONTROL,
1375 DISPC_CONTROL_GPOUT0 | DISPC_CONTROL_GPOUT1 |
1376 DISPC_CONTROL_TFTDATALINES_18 /*XXX 18? */ |
1377 DISPC_CONTROL_STNTFT |
1378 DISPC_CONTROL_GOLCD |
1379 DISPC_CONTROL_LCDENABLE);
1380 }
1381
1382 void
omdisplay_stop(struct omdisplay_softc * sc)1383 omdisplay_stop(struct omdisplay_softc *sc)
1384 {
1385 bus_space_write_4(sc->sc_iot, sc->sc_dcioh, DISPC_CONTROL,
1386 bus_space_read_4(sc->sc_iot, sc->sc_dcioh, DISPC_CONTROL) &
1387 ~(DISPC_CONTROL_DIGITALENABLE|DISPC_CONTROL_LCDENABLE));
1388
1389 /* XXX - wait for end of frame? */
1390 }
1391
1392 int
omdisplay_intr(void * v)1393 omdisplay_intr(void *v)
1394 {
1395 /* XXX */
1396 return 1;
1397 }
1398
1399