1 /* 2 hc12mem - HC12 memory reader & writer 3 io_mc9s12.h: MC9S12 generic I/O registers 4 $Id: io_mc9s12.h,v 1.1 2005/11/17 22:51:15 mk Exp $ 5 6 Copyright (C) 2005 Michal Konieczny <mk@cml.mfk.net.pl> 7 8 Redistribution and use in source and binary forms, with or without 9 modification, are permitted provided that the following conditions 10 are met: 11 1. Redistributions of source code must retain the above copyright 12 notice, this list of conditions and the following disclaimer. 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 3. Neither the name of the project nor the names of its contributors 17 may be used to endorse or promote products derived from this software 18 without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND 21 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT OR CONTRIBUTORS BE LIABLE 24 FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 SUCH DAMAGE. 31 */ 32 33 #ifndef __IO_MC9S12_H 34 #define __IO_MC9S12_H 35 36 /* MEBI map 1 of 3 */ 37 38 #define PORTA 0x0000 39 # define PORTA_BIT7 0x80 40 # define PORTA_BIT6 0x40 41 # define PORTA_BIT5 0x20 42 # define PORTA_BIT4 0x10 43 # define PORTA_BIT3 0x08 44 # define PORTA_BIT2 0x04 45 # define PORTA_BIT1 0x02 46 # define PORTA_BIT0 0x01 47 #define PORTB 0x0001 48 # define PORTB_BIT7 0x80 49 # define PORTB_BIT6 0x40 50 # define PORTB_BIT5 0x20 51 # define PORTB_BIT4 0x10 52 # define PORTB_BIT3 0x08 53 # define PORTB_BIT2 0x04 54 # define PORTB_BIT1 0x02 55 # define PORTB_BIT0 0x01 56 #define DDRA 0x0002 57 # define DDRA_BIT7 0x80 58 # define DDRA_BIT6 0x40 59 # define DDRA_BIT5 0x20 60 # define DDRA_BIT4 0x10 61 # define DDRA_BIT3 0x08 62 # define DDRA_BIT2 0x04 63 # define DDRA_BIT1 0x02 64 # define DDRA_BIT0 0x01 65 #define DDRB 0x0003 66 # define DDRB_BIT7 0x80 67 # define DDRB_BIT6 0x40 68 # define DDRB_BIT5 0x20 69 # define DDRB_BIT4 0x10 70 # define DDRB_BIT3 0x08 71 # define DDRB_BIT2 0x04 72 # define DDRB_BIT1 0x02 73 # define DDRB_BIT0 0x01 74 /* #define RESERVED_0x0004 0x0004 */ 75 /* #define RESERVED_0x0005 0x0005 */ 76 /* #define RESERVED_0x0006 0x0006 */ 77 /* #define RESERVED_0x0007 0x0007 */ 78 #define PORTE 0x0008 79 # define PORTE_BIT7 0x80 80 # define PORTE_BIT6 0x40 81 # define PORTE_BIT5 0x20 82 # define PORTE_BIT4 0x10 83 # define PORTE_BIT3 0x08 84 # define PORTE_BIT2 0x04 85 # define PORTE_BIT1 0x02 86 # define PORTE_BIT0 0x01 87 #define DDRE 0x0009 88 # define DDRE_BIT7 0x80 89 # define DDRE_BIT6 0x40 90 # define DDRE_BIT5 0x20 91 # define DDRE_BIT4 0x10 92 # define DDRE_BIT3 0x08 93 # define DDRE_BIT2 0x04 94 # define DDRE_BIT1 0x02 95 # define DDRE_BIT0 0x01 96 #define PEAR 0x000a 97 # define PEAR_NOACCE 0x80 98 /* # define PEAR_ 0x40 */ 99 # define PEAR_PIP0E 0x20 100 # define PEAR_NECLK 0x10 101 # define PEAR_LSTRE 0x08 102 # define PEAR_RDWE 0x04 103 /* # define PEAR_ 0x02 */ 104 /* # define PEAR_ 0x01 */ 105 #define MODE 0x000b 106 # define MODE_MODC 0x80 107 # define MODE_MODB 0x40 108 # define MODE_MODA 0x20 109 /* # define MODE_ 0x10 */ 110 # define MODE_IVIS 0x08 111 /* # define MODE_ 0x04 */ 112 # define MODE_EMK 0x02 113 # define MODE_EME 0x01 114 #define PUCR 0x000c 115 # define PUCR_PUPKE 0x80 116 /* # define PUCR_ 0x40 */ 117 /* # define PUCR_ 0x20 */ 118 # define PUCR_PUPEE 0x10 119 /* # define PUCR_ 0x08 */ 120 /* # define PUCR_ 0x04 */ 121 # define PUCR_PUPBE 0x02 122 # define PUCR_PUPAE 0x01 123 #define RDRIV 0x000d 124 # define RDRIV_RDPK 0x80 125 /* # define RDRIV_ 0x40 */ 126 /* # define RDRIV_ 0x20 */ 127 # define RDRIV_RDPE 0x10 128 /* # define RDRIV_ 0x08 */ 129 /* # define RDRIV_ 0x04 */ 130 # define RDRIV_RDPB 0x02 131 # define RDRIV_DRPA 0x01 132 #define EBICTL 0x00e 133 /* # define EBICTL_ 0x80 */ 134 /* # define EBICTL_ 0x40 */ 135 /* # define EBICTL_ 0x20 */ 136 /* # define EBICTL_ 0x10 */ 137 /* # define EBICTL_ 0x08 */ 138 /* # define EBICTL_ 0x04 */ 139 /* # define EBICTL_ 0x02 */ 140 # define EBICTL_ESTR 0x01 141 /* #define RESERVED_0x000f 0x000f */ 142 143 /* MMC map 1 of 4 */ 144 145 #define INITRM 0x0010 146 # define INITRM_RAM15 0x80 147 # define INITRM_RAM14 0x40 148 # define INITRM_RAM13 0x20 149 # define INITRM_RAM12 0x10 150 # define INITRM_RAM11 0x08 151 /* # define INITRM_ 0x04 */ 152 /* # define INITRM_ 0x02 */ 153 # define INITRM_RAMHAL 0x01 154 #define INITRG 0x0011 155 /* # define INITRG_ 0x80 */ 156 # define INITRG_REG14 0x40 157 # define INITRG_REG13 0x20 158 # define INITRG_REG12 0x10 159 # define INITRG_REG11 0x08 160 /* # define INITRG_ 0x04 */ 161 /* # define INITRG_ 0x02 */ 162 /* # define INITRG_ 0x01 */ 163 #define INITEE 0x0012 164 # define INITEE_EE15 0x80 165 # define INITEE_EE14 0x40 166 # define INITEE_EE13 0x20 167 # define INITEE_EE12 0x10 168 # define INITEE_EE11 0x08 169 /* # define INITEE_ 0x04 */ 170 /* # define INITEE_ 0x02 */ 171 # define INITEE_EEON 0x01 172 #define MISC 0x0013 173 /* # define MISC_ 0x80 */ 174 /* # define MISC_ 0x40 */ 175 /* # define MISC_ 0x20 */ 176 /* # define MISC_ 0x10 */ 177 # define MISC_EXSTR1 0x08 178 # define MISC_EXSTR0 0x04 179 # define MISC_ROMHM 0x02 180 # define MISC_ROMON 0x01 181 /* #define RESERVED_0x0014 0x0014 */ 182 183 /* INT map 1 of 2 */ 184 185 #define ITCR 0x0015 186 /* # define ITCR_ 0x80 */ 187 /* # define ITCR_ 0x40 */ 188 /* # define ITCR_ 0x20 */ 189 # define ITCR_WRINT 0x10 190 # define ITCR_ADR3 0x08 191 # define ITCR_ADR2 0x04 192 # define ITCR_ADR1 0x02 193 # define ITCR_ADR0 0x01 194 #define ITEST 0x0016 195 # define ITEST_INTE 0x80 196 # define ITEST_INTC 0x40 197 # define ITEST_INTA 0x20 198 # define ITEST_INT8 0x10 199 # define ITEST_INT6 0x08 200 # define ITEST_INT4 0x04 201 # define ITEST_INT2 0x02 202 # define ITEST_INT0 0x01 203 204 /* reserved 0x0017..0x0019 */ 205 206 /* device id register */ 207 208 #define PARTIDH 0x001a 209 # define PARTIDH_ID15 0x80 210 # define PARTIDH_ID14 0x40 211 # define PARTIDH_ID13 0x20 212 # define PARTIDH_ID12 0x10 213 # define PARTIDH_ID11 0x08 214 # define PARTIDH_ID10 0x04 215 # define PARTIDH_ID9 0x02 216 # define PARTIDH_ID8 0x01 217 #define PARTIDL 0x001b 218 # define PARTIDL_ID7 0x80 219 # define PARTIDL_ID6 0x40 220 # define PARTIDL_ID5 0x20 221 # define PARTIDL_ID4 0x10 222 # define PARTIDL_ID3 0x08 223 # define PARTIDL_ID2 0x04 224 # define PARTIDL_ID1 0x02 225 # define PARTIDL_ID0 0x01 226 227 /* MMC map 3 of 4 */ 228 229 #define MEMSIZ0 0x001c 230 # define MEMSIZ0_REG_SW0 0x80 231 /* # define MEMSIZ0_ 0x40 */ 232 # define MEMSIZ0_EEP_SW1 0x20 233 # define MEMSIZ0_EEP_SW0 0x10 234 /* # define MEMSIZ0_ 0x08 */ 235 # define MEMSIZ0_RAM_SW2 0x04 236 # define MEMSIZ0_RAM_SW1 0x02 237 # define MEMSIZ0_RAM_SW0 0x01 238 #define MEMSIZ1 0x001d 239 # define MEMSIZ1_ROM_SW1 0x80 240 # define MEMSIZ1_ROM_SW0 0x40 241 /* # define MEMSIZ1_ 0x20 */ 242 /* # define MEMSIZ1_ 0x10 */ 243 /* # define MEMSIZ1_ 0x08 */ 244 /* # define MEMSIZ1_ 0x04 */ 245 # define MEMSIZ1_PAG_SW1 0x02 246 # define MEMSIZ1_PAG_SW0 0x01 247 248 /* MEBI map 2 of 3 */ 249 250 #define INTCR 0x001e 251 # define INTCR_IRQE 0x80 252 # define INTCR_IRQEN 0x40 253 /* # define INTCR_ 0x20 */ 254 /* # define INTCR_ 0x10 */ 255 /* # define INTCR_ 0x08 */ 256 /* # define INTCR_ 0x04 */ 257 /* # define INTCR_ 0x02 */ 258 /* # define INTCR_ 0x01 */ 259 260 /* INT map 2 of 2 */ 261 262 #define HPRIO 0x001f 263 # define HPRIO_PSEL7 0x80 264 # define HPRIO_PSEL6 0x40 265 # define HPRIO_PSEL5 0x20 266 # define HPRIO_PSEL4 0x10 267 # define HPRIO_PSEL3 0x08 268 # define HPRIO_PSEL2 0x04 269 # define HPRIO_PSEL1 0x02 270 /* # define HPRIO_ 0x01 */ 271 272 /* MMC map 4 of 4 */ 273 274 #define PPAGE 0x0030 275 /* # define PPAGE_ 0x80 */ 276 /* # define PPAGE_ 0x40 */ 277 # define PPAGE_PIX5 0x20 278 # define PPAGE_PIX4 0x10 279 # define PPAGE_PIX3 0x08 280 # define PPAGE_PIX2 0x04 281 # define PPAGE_PIX1 0x02 282 # define PPAGE_PIX0 0x01 283 /* #define RESERVED_0x0031 0x0031 */ 284 285 /* MEBI map 3 of 3 */ 286 287 #define PORTK 0x0032 288 # define PORTK_BIT7 0x80 289 # define PORTK_BIT6 0x40 290 # define PORTK_BIT5 0x20 291 # define PORTK_BIT4 0x10 292 # define PORTK_BIT3 0x08 293 # define PORTK_BIT2 0x04 294 # define PORTK_BIT1 0x02 295 # define PORTK_BIT0 0x01 296 #define DDRK 0x0033 297 # define DDRK_BIT7 0x80 298 # define DDRK_BIT6 0x40 299 # define DDRK_BIT5 0x20 300 # define DDRK_BIT4 0x10 301 # define DDRK_BIT3 0x08 302 # define DDRK_BIT2 0x04 303 # define DDRK_BIT1 0x02 304 # define DDRK_BIT0 0x01 305 #define SYNR 0x0034 306 /* # define SYNR_ 0x80 */ 307 /* # define SYNR_ 0x40 */ 308 # define SYNR_SYN5 0x20 309 # define SYNR_SYN4 0x10 310 # define SYNR_SYN3 0x08 311 # define SYNR_SYN2 0x04 312 # define SYNR_SYN1 0x02 313 # define SYNR_SYN0 0x01 314 #define REFDV 0x0035 315 /* # define REFDV_ 0x80 */ 316 /* # define REFDV_ 0x40 */ 317 /* # define REFDV_ 0x20 */ 318 /* # define REFDV_ 0x10 */ 319 # define REFDV_REFDV3 0x08 320 # define REFDV_REFDV2 0x04 321 # define REFDV_REFDV1 0x02 322 # define REFDV_REFDV0 0x01 323 #define CTFLG 0x0036 /* test only */ 324 #define CRGFLG 0x0037 325 # define CRGFLG_RTIF 0x80 326 # define CRGFLG_PORF 0x40 327 /* # define CRGFLG_ 0x20 */ 328 # define CRGFLG_LOCKIF 0x10 329 # define CRGFLG_LOCK 0x08 330 # define CRGFLG_TRACK 0x04 331 # define CRGFLG_SCMIF 0x02 332 # define CRGFLG_SCM 0x01 333 #define CRGINT 0x0038 334 # define CRGINT_RTIE 0x80 335 /* # define CRGINT_ 0x40 */ 336 /* # define CRGINT_ 0x20 */ 337 # define CRGINT_LOCKIE 0x10 338 /* # define CRGINT_ 0x08 */ 339 /* # define CRGINT_ 0x04 */ 340 # define CRGINT_SCMIE 0x02 341 /* # define CRGINT_ 0x01 */ 342 #define CLKSEL 0x0039 343 # define CLKSEL_PLLSEL 0x80 344 # define CLKSEL_PSTP 0x40 345 # define CLKSEL_SYSWAI 0x20 346 # define CLKSEL_ROAWAI 0x10 347 # define CLKSEL_PLLWAI 0x08 348 # define CLKSEL_CWAI 0x04 349 # define CLKSEL_RTIWAI 0x02 350 # define CLKSEL_COPWAI 0x01 351 #define PLLCTL 0x003a 352 # define PLLCTL_CME 0x80 353 # define PLLCTL_PLLON 0x40 354 # define PLLCTL_AUTO 0x20 355 # define PLLCTL_ACQ 0x10 356 /* # define PLLCTL_ 0x08 */ 357 # define PLLCTL_PRE 0x04 358 # define PLLCTL_PCE 0x02 359 # define PLLCTL_SCME 0x01 360 #define RTICTL 0x003b 361 /* # define RTICTL_ 0x80 */ 362 # define RTICTL_RTR6 0x40 363 # define RTICTL_RTR5 0x20 364 # define RTICTL_RTR4 0x10 365 # define RTICTL_RTR3 0x08 366 # define RTICTL_RTR2 0x04 367 # define RTICTL_RTR1 0x02 368 # define RTICTL_RTR0 0x01 369 #define COPCTL 0x003c 370 # define COPCTL_WCOP 0x80 371 # define COPCTL_RSBCK 0x40 372 /* # define COPCTL_ 0x20 */ 373 /* # define COPCTL_ 0x10 */ 374 /* # define COPCTL_ 0x08 */ 375 # define COPCTL_CR2 0x04 376 # define COPCTL_CR1 0x02 377 # define COPCTL_CR0 0x01 378 #define FORBYP 0x003d /* test only */ 379 #define CTCTL 0x003e /* test only */ 380 #define ARMCOP 0x003f 381 382 /* SCI0 */ 383 384 #define SCI0BD 0x00c8 385 #define SCI0BDH 0x00c8 386 /* # define SCI0BDH_ 0x80 */ 387 /* # define SCI0BDH_ 0x40 */ 388 /* # define SCI0BDH_ 0x20 */ 389 # define SCI0BDH_SBR12 0x10 390 # define SCI0BDH_SBR11 0x08 391 # define SCI0BDH_SBR10 0x04 392 # define SCI0BDH_SBR9 0x02 393 # define SCI0BDH_SBR8 0x01 394 #define SCI0BDL 0x00c9 395 # define SCI0BDL_SBR7 0x80 396 # define SCI0BDL_SBR6 0x40 397 # define SCI0BDL_SBR5 0x20 398 # define SCI0BDL_SBR4 0x10 399 # define SCI0BDL_SBR3 0x08 400 # define SCI0BDL_SBR2 0x04 401 # define SCI0BDL_SBR1 0x02 402 # define SCI0BDL_SBR0 0x01 403 #define SCI0CR1 0x00ca 404 # define SCI0CR1_LOOPS 0x80 405 # define SCI0CR1_SCISWAI 0x40 406 # define SCI0CR1_RSRC 0x20 407 # define SCI0CR1_M 0x10 408 # define SCI0CR1_WAKE 0x08 409 # define SCI0CR1_ILT 0x04 410 # define SCI0CR1_PE 0x02 411 # define SCI0CR1_PT 0x01 412 #define SCI0CR2 0x00cb 413 # define SCI0CR2_TIE 0x80 414 # define SCI0CR2_TCIE 0x40 415 # define SCI0CR2_RIE 0x20 416 # define SCI0CR2_ILIE 0x10 417 # define SCI0CR2_TE 0x08 418 # define SCI0CR2_RE 0x04 419 # define SCI0CR2_RWU 0x02 420 # define SCI0CR2_SBK 0x01 421 #define SCI0SR1 0x00cc 422 # define SCI0SR1_TDRE 0x80 423 # define SCI0SR1_TC 0x40 424 # define SCI0SR1_RDRF 0x20 425 # define SCI0SR1_IDLE 0x10 426 # define SCI0SR1_OR 0x08 427 # define SCI0SR1_NF 0x04 428 # define SCI0SR1_FE 0x02 429 # define SCI0SR1_PF 0x01 430 #define SCI0SR2 0x00cd 431 /* # define SCI0SR2_ 0x80 */ 432 /* # define SCI0SR2_ 0x40 */ 433 /* # define SCI0SR2_ 0x20 */ 434 /* # define SCI0SR2_ 0x10 */ 435 /* # define SCI0SR2_ 0x08 */ 436 # define SCI0SR2_BRK13 0x04 437 # define SCI0SR2_TXDIR 0x02 438 # define SCI0SR2_RAF 0x01 439 #define SCI0DRH 0x00ce 440 # define SCI0DRH_R8 0x80 441 # define SCI0DRH_T8 0x40 442 /* # define SCI0DRH_ 0x20 */ 443 /* # define SCI0DRH_ 0x10 */ 444 /* # define SCI0DRH_ 0x08 */ 445 /* # define SCI0DRH_ 0x04 */ 446 /* # define SCI0DRH_ 0x02 */ 447 /* # define SCI0DRH_ 0x01 */ 448 #define SCI0DRL 0x00cf 449 # define SCI0DRL_R7_T7 0x80 450 # define SCI0DRL_R6_T6 0x40 451 # define SCI0DRL_R5_T5 0x20 452 # define SCI0DRL_R4_T4 0x10 453 # define SCI0DRL_R3_T3 0x08 454 # define SCI0DRL_R2_T2 0x04 455 # define SCI0DRL_R1_T1 0x02 456 # define SCI0DRL_R0_T0 0x01 457 458 /* SCI1 */ 459 460 #define SCI1BD 0x00d0 461 #define SCI1BDH 0x00d0 462 /* # define SCI1BDH_ 0x80 */ 463 /* # define SCI1BDH_ 0x40 */ 464 /* # define SCI1BDH_ 0x20 */ 465 # define SCI1BDH_SBR12 0x10 466 # define SCI1BDH_SBR11 0x08 467 # define SCI1BDH_SBR10 0x04 468 # define SCI1BDH_SBR9 0x02 469 # define SCI1BDH_SBR8 0x01 470 #define SCI1BDL 0x00d1 471 # define SCI1BDL_SBR7 0x80 472 # define SCI1BDL_SBR6 0x40 473 # define SCI1BDL_SBR5 0x20 474 # define SCI1BDL_SBR4 0x10 475 # define SCI1BDL_SBR3 0x08 476 # define SCI1BDL_SBR2 0x04 477 # define SCI1BDL_SBR1 0x02 478 # define SCI1BDL_SBR0 0x01 479 #define SCI1CR1 0x00d2 480 # define SCI1CR1_LOOPS 0x80 481 # define SCI1CR1_SCISWAI 0x40 482 # define SCI1CR1_RSRC 0x20 483 # define SCI1CR1_M 0x10 484 # define SCI1CR1_WAKE 0x08 485 # define SCI1CR1_ILT 0x04 486 # define SCI1CR1_PE 0x02 487 # define SCI1CR1_PT 0x01 488 #define SCI1CR2 0x00d3 489 # define SCI1CR2_TIE 0x80 490 # define SCI1CR2_TCIE 0x40 491 # define SCI1CR2_RIE 0x20 492 # define SCI1CR2_ILIE 0x10 493 # define SCI1CR2_TE 0x08 494 # define SCI1CR2_RE 0x04 495 # define SCI1CR2_RWU 0x02 496 # define SCI1CR2_SBK 0x01 497 #define SCI1SR1 0x00d4 498 # define SCI1SR1_TDRE 0x80 499 # define SCI1SR1_TC 0x40 500 # define SCI1SR1_RDRF 0x20 501 # define SCI1SR1_IDLE 0x10 502 # define SCI1SR1_OR 0x08 503 # define SCI1SR1_NF 0x04 504 # define SCI1SR1_FE 0x02 505 # define SCI1SR1_PF 0x01 506 #define SCI1SR2 0x00d5 507 /* # define SCI1SR2_ 0x80 */ 508 /* # define SCI1SR2_ 0x40 */ 509 /* # define SCI1SR2_ 0x20 */ 510 /* # define SCI1SR2_ 0x10 */ 511 /* # define SCI1SR2_ 0x08 */ 512 # define SCI1SR2_BRK13 0x04 513 # define SCI1SR2_TXDIR 0x02 514 # define SCI1SR2_RAF 0x01 515 #define SCI1DRH 0x00d6 516 # define SCI1DRH_R8 0x80 517 # define SCI1DRH_T8 0x40 518 /* # define SCI1DRH_ 0x20 */ 519 /* # define SCI1DRH_ 0x10 */ 520 /* # define SCI1DRH_ 0x08 */ 521 /* # define SCI1DRH_ 0x04 */ 522 /* # define SCI1DRH_ 0x02 */ 523 /* # define SCI1DRH_ 0x01 */ 524 #define SCI1DRL 0x00d7 525 # define SCI1DRL_R7_T7 0x80 526 # define SCI1DRL_R6_T6 0x40 527 # define SCI1DRL_R5_T5 0x20 528 # define SCI1DRL_R4_T4 0x10 529 # define SCI1DRL_R3_T3 0x08 530 # define SCI1DRL_R2_T2 0x04 531 # define SCI1DRL_R1_T1 0x02 532 # define SCI1DRL_R0_T0 0x01 533 534 /* IIC */ 535 536 #define IBAD 0x00e0 537 # define IBAD_ADR7 0x80 538 # define IBAD_ADR6 0x40 539 # define IBAD_ADR5 0x20 540 # define IBAD_ADR4 0x10 541 # define IBAD_ADR3 0x08 542 # define IBAD_ADR2 0x04 543 # define IBAD_ADR1 0x02 544 /* # define IBAD_ 0x01 */ 545 #define IBFD 0x00e1 546 # define IBFD_IBC7 0x80 547 # define IBFD_IBC6 0x40 548 # define IBFD_IBC5 0x20 549 # define IBFD_IBC4 0x10 550 # define IBFD_IBC3 0x08 551 # define IBFD_IBC2 0x04 552 # define IBFD_IBC1 0x02 553 # define IBFD_IBC0 0x01 554 #define IBCR 0x00e2 555 # define IBCR_IBEN 0x80 556 # define IBCR_IBIE 0x40 557 # define IBCR_MSSL 0x20 558 # define IBCR_TXRX 0x10 559 # define IBCR_TXAK 0x08 560 # define IBCR_RSTA 0x04 561 /* # define IBCR_ 0x02 */ 562 # define IBCR_IBSWAI 0x01 563 #define IBSR 0x00e3 564 # define IBSR_TCF 0x80 565 # define IBSR_IAAS 0x40 566 # define IBSR_IBB 0x20 567 # define IBSR_IBAL 0x10 568 /* # define IBSR_ 0x08 */ 569 # define IBSR_SRW 0x04 570 # define IBSR_IBIF 0x02 571 # define IBSR_RXAK 0x01 572 #define IBDR 0x00e4 573 /* #define RESERVED_0x00e5 0x00e5 */ 574 /* #define RESERVED_0x00e6 0x00e6 */ 575 /* #define RESERVED_0x00e7 0x00e7 */ 576 577 /* FLASH */ 578 579 #define FCLKDIV 0x0100 580 # define FCLKDIV_FDIVLD 0x80 581 # define FCLKDIV_PRDIV8 0x40 582 # define FCLKDIV_FDIV5 0x20 583 # define FCLKDIV_FDIV4 0x10 584 # define FCLKDIV_FDIV3 0x08 585 # define FCLKDIV_FDIV2 0x04 586 # define FCLKDIV_FDIV1 0x02 587 # define FCLKDIV_FDIV0 0x01 588 #define FSEC 0x0101 589 # define FSEC_KEYEN 0x80 590 # define FSEC_NV6 0x40 591 # define FSEC_NV5 0x20 592 # define FSEC_NV4 0x10 593 # define FSEC_NV3 0x08 594 # define FSEC_NV2 0x04 595 # define FSEC_SEC1 0x02 596 # define FSEC_SEC0 0x01 597 /* #define RESERVED_0x0102 0x0102 */ 598 #define FCNFG 0x0103 599 # define FCNFG_CBEIE 0x80 600 # define FCNFG_CCIE 0x40 601 # define FCNFG_KEYACC 0x20 602 /* # define FCNFG_ 0x10 */ 603 /* # define FCNFG_ 0x08 */ 604 /* # define FCNFG_ 0x04 */ 605 /* # define FCNFG_ 0x02 */ 606 /* # define FCNFG_ 0x01 */ 607 #define FPROT 0x0104 608 # define FPROT_FPOPEN 0x80 609 # define FPROT_NV6 0x40 610 # define FPROT_FPHDIS 0x20 611 # define FPROT_FPHS1 0x10 612 # define FPROT_FPHS0 0x08 613 # define FPROT_FPLDIS 0x04 614 # define FPROT_FPLS1 0x02 615 # define FPROT_FPLS0 0x01 616 #define FSTAT 0x0105 617 # define FSTAT_CBEIF 0x80 618 # define FSTAT_CCIF 0x40 619 # define FSTAT_PVIOL 0x20 620 # define FSTAT_ACCERR 0x10 621 /* # define FSTAT_ 0x08 */ 622 # define FSTAT_BLANK 0x04 623 /* # define FSTAT_ 0x02 */ 624 /* # define FSTAT_ 0x01 */ 625 #define FCMD 0x0106 626 /* # define FCMD_ 0x80 */ 627 # define FCMD_CMDB6 0x40 628 # define FCMD_CMDB5 0x20 629 /* # define FCMD_ 0x10 */ 630 /* # define FCMD_ 0x08 */ 631 # define FCMD_CMDB2 0x04 632 /* # define FCMD_ 0x02 */ 633 # define FCMD_CMDB0 0x01 634 /* #define RESERVED_0x0107 0x0107 */ 635 #define FADDR 0x0108 636 #define FADDRHI 0x0108 637 #define FADDRLO 0x0109 638 #define FDATA 0x010a 639 #define FDATAHI 0x010a 640 #define FDATALO 0x010b 641 /* #define RESERVED_0x010c 0x010c */ 642 /* #define RESERVED_0x010d 0x010d */ 643 /* #define RESERVED_0x010e 0x010e */ 644 /* #define RESERVED_0x010f 0x010f */ 645 646 /* EEPROM */ 647 648 #define ECLKDIV 0x0110 649 # define ECLKDIV_EDIVLD 0x80 650 # define ECLKDIV_PRDIV8 0x40 651 # define ECLKDIV_EDIV5 0x20 652 # define ECLKDIV_EDIV4 0x10 653 # define ECLKDIV_EDIV3 0x08 654 # define ECLKDIV_EDIV2 0x04 655 # define ECLKDIV_EDIV1 0x02 656 # define ECLKDIV_EDIV0 0x01 657 /* #define RESERVED_0x0111 0x0111 */ 658 /* #define RESERVED_0x0112 0x0112 */ 659 #define ECNFG 0x0113 660 # define ECNFG_CBEIE 0x80 661 # define ECNFG_CCIE 0x40 662 /* # define ECNFG_ 0x20 */ 663 /* # define ECNFG_ 0x10 */ 664 /* # define ECNFG_ 0x08 */ 665 /* # define ECNFG_ 0x04 */ 666 /* # define ECNFG_ 0x02 */ 667 /* # define ECNFG_ 0x01 */ 668 #define EPROT 0x0114 669 # define EPROT_EPOPEN 0x80 670 # define EPROT_NV6 0x40 671 # define EPROT_NV5 0x20 672 # define EPROT_NV4 0x10 673 # define EPROT_EPDIS 0x08 674 # define EPROT_EP2 0x04 675 # define EPROT_EP1 0x02 676 # define EPROT_EP0 0x01 677 #define ESTAT 0x0115 678 # define ESTAT_CBEIF 0x80 679 # define ESTAT_CCIF 0x40 680 # define ESTAT_PVIOL 0x20 681 # define ESTAT_ACCERR 0x10 682 /* # define ESTAT_ 0x08 */ 683 # define ESTAT_BLANK 0x04 684 /* # define ESTAT_ 0x02 */ 685 /* # define ESTAT_ 0x01 */ 686 #define ECMD 0x0116 687 /* # define ECMD_ 0x80 */ 688 # define ECMD_CMDB6 0x40 689 # define ECMD_CMDB5 0x20 690 /* # define ECMD_ 0x10 */ 691 /* # define ECMD_ 0x08 */ 692 # define ECMD_CMDB2 0x04 693 /* # define ECMD_ 0x02 */ 694 # define ECMD_CMDB0 0x01 695 /* #define RESERVED_0x0117 0x0117 */ 696 #define EADDR 0x0118 697 #define EADDRHI 0x0118 698 #define EADDRLO 0x0119 699 #define EDATA 0x011a 700 #define EDATAHI 0x011a 701 #define EDATALO 0x011b 702 /* #define RESERVED_0x011c 0x011c */ 703 /* #define RESERVED_0x011d 0x011d */ 704 /* #define RESERVED_0x011e 0x011e */ 705 /* #define RESERVED_0x011f 0x011f */ 706 707 /* ATD1 */ 708 709 #define ATD1CTL0 0x0120 710 #define ATD1CTL1 0x0121 711 #define ATD1CTL2 0x0122 712 # define ATD1CTL2_ADPU 0x80 713 # define ATD1CTL2_AFFC 0x40 714 # define ATD1CTL2_AWAI 0x20 715 # define ATD1CTL2_ETRIGLE 0x10 716 # define ATD1CTL2_ETRIGP 0x08 717 # define ATD1CTL2_ETRIG 0x04 718 # define ATD1CTL2_ASCIE 0x02 719 # define ATD1CTL2_ASCIF 0x01 720 #define ATD1CTL3 0x0123 721 /* # define ATD1CTL3_ 0x80 */ 722 # define ATD1CTL3_S8C 0x40 723 # define ATD1CTL3_S4C 0x20 724 # define ATD1CTL3_S2C 0x10 725 # define ATD1CTL3_S1C 0x08 726 # define ATD1CTL3_FIFO 0x04 727 # define ATD1CTL3_FRZ1 0x02 728 # define ATD1CTL3_FRZ0 0x01 729 #define ATD1CTL4 0x0124 730 # define ATD1CTL4_SRES8 0x80 731 # define ATD1CTL4_SMP1 0x40 732 # define ATD1CTL4_SMP0 0x20 733 # define ATD1CTL4_PRS4 0x10 734 # define ATD1CTL4_PRS3 0x08 735 # define ATD1CTL4_PRS2 0x04 736 # define ATD1CTL4_PRS1 0x02 737 # define ATD1CTL4_PRS0 0x01 738 #define ATD1CTL5 0x0125 739 # define ATD1CTL5_DJM 0x80 740 # define ATD1CTL5_DSGN 0x40 741 # define ATD1CTL5_SCAN 0x20 742 # define ATD1CTL5_MULT 0x10 743 /* # define ATD1CTL5_ 0x08 */ 744 # define ATD1CTL5_CC 0x04 745 # define ATD1CTL5_CB 0x02 746 # define ATD1CTL5_CA 0x01 747 #define ATD1STAT0 0x0126 748 # define ATD1STAT0_SCF 0x80 749 /* # define ATD1STAT0_ 0x40 */ 750 # define ATD1STAT0_ETORF 0x20 751 # define ATD1STAT0_FIFOR 0x10 752 /* # define ATD1STAT0_ 0x08 */ 753 # define ATD1STAT0_CC2 0x04 754 # define ATD1STAT0_CC1 0x02 755 # define ATD1STAT0_CC0 0x01 756 /* #define RESERVED_0x0127 0x0127 */ 757 #define ATD1TEST0 0x0128 758 #define ATD1TEST1 0x0129 759 # define ATD1TEST1_SC 0x01 760 /* #define RESERVED_0x012a 0x012a */ 761 #define ATD1STAT1 0x012b 762 # define ATD1STAT1_CCF7 0x80 763 # define ATD1STAT1_CCF6 0x40 764 # define ATD1STAT1_CCF5 0x20 765 # define ATD1STAT1_CCF4 0x10 766 # define ATD1STAT1_CCF3 0x08 767 # define ATD1STAT1_CCF2 0x04 768 # define ATD1STAT1_CCF1 0x02 769 # define ATD1STAT1_CCF0 0x01 770 /* #define RESERVED_0x012c 0x012c */ 771 #define ATD1DIEN 0x012d 772 /* #define RESERVED_0x012e 0x012e */ 773 #define PORTAD1 0x012f 774 # define PORTAD1_BIT7 0x80 775 # define PORTAD1_BIT6 0x40 776 # define PORTAD1_BIT5 0x20 777 # define PORTAD1_BIT4 0x10 778 # define PORTAD1_BIT3 0x08 779 # define PORTAD1_BIT2 0x04 780 # define PORTAD1_BIT1 0x02 781 # define PORTAD1_BIT0 0x01 782 #define ATD1DR0H 0x0130 783 #define ATD1DR0L 0x0131 784 #define ATD1DR1H 0x0132 785 #define ATD1DR1L 0x0133 786 #define ATD1DR2H 0x0134 787 #define ATD1DR2L 0x0135 788 #define ATD1DR3H 0x0136 789 #define ATD1DR3L 0x0137 790 #define ATD1DR4H 0x0138 791 #define ATD1DR4L 0x0139 792 #define ATD1DR5H 0x013a 793 #define ATD1DR5L 0x013b 794 #define ATD1DR6H 0x013c 795 #define ATD1DR6L 0x013d 796 #define ATD1DR7H 0x013e 797 #define ATD1DR7L 0x013f 798 799 /* CAN0 */ 800 801 #define CAN0CTL0 0x0140 802 #define CAN0CTL1 0x0141 803 #define CAN0BTR0 0x0142 804 #define CAN0BTR1 0x0143 805 #define CAN0RFLG 0x0144 806 #define CAN0RIER 0x0145 807 #define CAN0TFLG 0x0146 808 #define CAN0TIER 0x0147 809 #define CAN0TARQ 0x0148 810 #define CAN0TAAK 0x0149 811 #define CAN0TBSEL 0x014a 812 #define CAN0IDAC 0x014b 813 /* #define 0x014c */ 814 /* #define 0x014d */ 815 #define CAN0RXERR 0x014e 816 #define CAN0TXERR 0x014f 817 #define CAN0IDAR0 0x0150 818 #define CAN0IDAR1 0x0151 819 #define CAN0IDAR2 0x0152 820 #define CAN0IDAR3 0x0153 821 #define CAN0IDMR0 0x0154 822 #define CAN0IDMR1 0x0155 823 #define CAN0IDMR2 0x0156 824 #define CAN0IDMR3 0x0157 825 #define CAN0IDAR4 0x0158 826 #define CAN0IDAR5 0x0159 827 #define CAN0IDAR6 0x015a 828 #define CAN0IDAR7 0x015b 829 #define CAN0IDMR4 0x015c 830 #define CAN0IDMR5 0x015d 831 #define CAN0IDMR6 0x015e 832 #define CAN0IDMR7 0x015f 833 #define CAN0RXFG 0x0160 /* 0x0160..0x016f */ 834 #define CAN0TXFG 0x0170 /* 0x0170..0x017f */ 835 836 /* reserved: 0x0180..0x23f */ 837 838 /* PIM */ 839 840 #define PTT 0x0240 841 # define PTT_PTT7 0x80 842 # define PTT_PTT6 0x40 843 # define PTT_PTT5 0x20 844 # define PTT_PTT4 0x10 845 # define PTT_PTT3 0x08 846 # define PTT_PTT2 0x04 847 # define PTT_PTT1 0x02 848 # define PTT_PTT0 0x01 849 #define PTIT 0x0241 850 # define PTIT_PTIT7 0x80 851 # define PTIT_PTIT6 0x40 852 # define PTIT_PTIT5 0x20 853 # define PTIT_PTIT4 0x10 854 # define PTIT_PTIT3 0x08 855 # define PTIT_PTIT2 0x04 856 # define PTIT_PTIT1 0x02 857 # define PTIT_PTIT0 0x01 858 #define DDRT 0x0242 859 # define DDRT_DDRT7 0x80 860 # define DDRT_DDRT6 0x40 861 # define DDRT_DDRT5 0x20 862 # define DDRT_DDRT4 0x10 863 # define DDRT_DDRT3 0x08 864 # define DDRT_DDRT2 0x04 865 # define DDRT_DDRT1 0x02 866 # define DDRT_DDRT0 0x01 867 #define RDRT 0x0243 868 # define RDRT_RDRT7 0x80 869 # define RDRT_RDRT6 0x40 870 # define RDRT_RDRT5 0x20 871 # define RDRT_RDRT4 0x10 872 # define RDRT_RDRT3 0x08 873 # define RDRT_RDRT2 0x04 874 # define RDRT_RDRT1 0x02 875 # define RDRT_RDRT0 0x01 876 #define PERT 0x0244 877 # define PERT_PERT7 0x80 878 # define PERT_PERT6 0x40 879 # define PERT_PERT5 0x20 880 # define PERT_PERT4 0x10 881 # define PERT_PERT3 0x08 882 # define PERT_PERT2 0x04 883 # define PERT_PERT1 0x02 884 # define PERT_PERT0 0x01 885 #define PPST 0x0245 886 # define PPST_PPST7 0x80 887 # define PPST_PPST6 0x40 888 # define PPST_PPST5 0x20 889 # define PPST_PPST4 0x10 890 # define PPST_PPST3 0x08 891 # define PPST_PPST2 0x04 892 # define PPST_PPST1 0x02 893 # define PPST_PPST0 0x01 894 /* #define RESERVED_0x0246 0x0246 */ 895 /* #define RESERVED_0x0247 0x0247 */ 896 #define PTS 0x0248 897 # define PTS_PTS7 0x80 898 # define PTS_PTS6 0x40 899 # define PTS_PTS5 0x20 900 # define PTS_PTS4 0x10 901 # define PTS_PTS3 0x08 902 # define PTS_PTS2 0x04 903 # define PTS_PTS1 0x02 904 # define PTS_PTS0 0x01 905 #define PTIS 0x0249 906 # define PTIS_PTIS7 0x80 907 # define PTIS_PTIS6 0x40 908 # define PTIS_PTIS5 0x20 909 # define PTIS_PTIS4 0x10 910 # define PTIS_PTIS3 0x08 911 # define PTIS_PTIS2 0x04 912 # define PTIS_PTIS1 0x02 913 # define PTIS_PTIS0 0x01 914 #define DDRS 0x024a 915 # define DDRS_DDRS7 0x80 916 # define DDRS_DDRS6 0x40 917 # define DDRS_DDRS5 0x20 918 # define DDRS_DDRS4 0x10 919 # define DDRS_DDRS3 0x08 920 # define DDRS_DDRS2 0x04 921 # define DDRS_DDRS1 0x02 922 # define DDRS_DDRS0 0x01 923 #define RDRS 0x024b 924 # define RDRS_RDRS7 0x80 925 # define RDRS_RDRS6 0x40 926 # define RDRS_RDRS5 0x20 927 # define RDRS_RDRS4 0x10 928 # define RDRS_RDRS3 0x08 929 # define RDRS_RDRS2 0x04 930 # define RDRS_RDRS1 0x02 931 # define RDRS_RDRS0 0x01 932 #define PERS 0x024c 933 # define PERS_PERS7 0x80 934 # define PERS_PERS6 0x40 935 # define PERS_PERS5 0x20 936 # define PERS_PERS4 0x10 937 # define PERS_PERS3 0x08 938 # define PERS_PERS2 0x04 939 # define PERS_PERS1 0x02 940 # define PERS_PERS0 0x01 941 #define PPSS 0x024d 942 # define PPSS_PPSS7 0x80 943 # define PPSS_PPSS6 0x40 944 # define PPSS_PPSS5 0x20 945 # define PPSS_PPSS4 0x10 946 # define PPSS_PPSS3 0x08 947 # define PPSS_PPSS2 0x04 948 # define PPSS_PPSS1 0x02 949 # define PPSS_PPSS0 0x01 950 #define WOMS 0x024e 951 # define WOMS_WOMS7 0x80 952 # define WOMS_WOMS6 0x40 953 # define WOMS_WOMS5 0x20 954 # define WOMS_WOMS4 0x10 955 # define WOMS_WOMS3 0x08 956 # define WOMS_WOMS2 0x04 957 # define WOMS_WOMS1 0x02 958 # define WOMS_WOMS0 0x01 959 /* #define RESERVED_0x024f 0x024f */ 960 #define PTM 0x0250 961 # define PTM_PTM7 0x80 962 # define PTM_PTM6 0x40 963 # define PTM_PTM5 0x20 964 # define PTM_PTM4 0x10 965 # define PTM_PTM3 0x08 966 # define PTM_PTM2 0x04 967 # define PTM_PTM1 0x02 968 # define PTM_PTM0 0x01 969 #define PTIM 0x0251 970 # define PTIM_PTIM7 0x80 971 # define PTIM_PTIM6 0x40 972 # define PTIM_PTIM5 0x20 973 # define PTIM_PTIM4 0x10 974 # define PTIM_PTIM3 0x08 975 # define PTIM_PTIM2 0x04 976 # define PTIM_PTIM1 0x02 977 # define PTIM_PTIM0 0x01 978 #define DDRM 0x0252 979 # define DDRM_DDRM7 0x80 980 # define DDRM_DDRM6 0x40 981 # define DDRM_DDRM5 0x20 982 # define DDRM_DDRM4 0x10 983 # define DDRM_DDRM3 0x08 984 # define DDRM_DDRM2 0x04 985 # define DDRM_DDRM1 0x02 986 # define DDRM_DDRM0 0x01 987 #define RDRM 0x0253 988 # define RDRM_RDRM7 0x80 989 # define RDRM_RDRM6 0x40 990 # define RDRM_RDRM5 0x20 991 # define RDRM_RDRM4 0x10 992 # define RDRM_RDRM3 0x08 993 # define RDRM_RDRM2 0x04 994 # define RDRM_RDRM1 0x02 995 # define RDRM_RDRM0 0x01 996 #define PERM 0x0254 997 # define PERM_PERM7 0x80 998 # define PERM_PERM6 0x40 999 # define PERM_PERM5 0x20 1000 # define PERM_PERM4 0x10 1001 # define PERM_PERM3 0x08 1002 # define PERM_PERM2 0x04 1003 # define PERM_PERM1 0x02 1004 # define PERM_PERM0 0x01 1005 #define PPSM 0x0255 1006 # define PPSM_PPSM7 0x80 1007 # define PPSM_PPSM6 0x40 1008 # define PPSM_PPSM5 0x20 1009 # define PPSM_PPSM4 0x10 1010 # define PPSM_PPSM3 0x08 1011 # define PPSM_PPSM2 0x04 1012 # define PPSM_PPSM1 0x02 1013 # define PPSM_PPSM0 0x01 1014 #define WOMM 0x0256 1015 # define WOMM_WOMM7 0x80 1016 # define WOMM_WOMM6 0x40 1017 # define WOMM_WOMM5 0x20 1018 # define WOMM_WOMM4 0x10 1019 # define WOMM_WOMM3 0x08 1020 # define WOMM_WOMM2 0x04 1021 # define WOMM_WOMM1 0x02 1022 # define WOMM_WOMM0 0x01 1023 #define MODRR 0x0257 1024 # define MODRR_MODRR7 0x80 1025 # define MODRR_MODRR6 0x40 1026 # define MODRR_MODRR5 0x20 1027 # define MODRR_MODRR4 0x10 1028 # define MODRR_MODRR3 0x08 1029 # define MODRR_MODRR2 0x04 1030 # define MODRR_MODRR1 0x02 1031 # define MODRR_MODRR0 0x01 1032 #define PTP 0x0258 1033 # define PTP_PTP7 0x80 1034 # define PTP_PTP6 0x40 1035 # define PTP_PTP5 0x20 1036 # define PTP_PTP4 0x10 1037 # define PTP_PTP3 0x08 1038 # define PTP_PTP2 0x04 1039 # define PTP_PTP1 0x02 1040 # define PTP_PTP0 0x01 1041 #define PTIP 0x0259 1042 # define PTIP_PTIP7 0x80 1043 # define PTIP_PTIP6 0x40 1044 # define PTIP_PTIP5 0x20 1045 # define PTIP_PTIP4 0x10 1046 # define PTIP_PTIP3 0x08 1047 # define PTIP_PTIP2 0x04 1048 # define PTIP_PTIP1 0x02 1049 # define PTIP_PTIP0 0x01 1050 #define DDRP 0x025a 1051 # define DDRP_DDRP7 0x80 1052 # define DDRP_DDRP6 0x40 1053 # define DDRP_DDRP5 0x20 1054 # define DDRP_DDRP4 0x10 1055 # define DDRP_DDRP3 0x08 1056 # define DDRP_DDRP2 0x04 1057 # define DDRP_DDRP1 0x02 1058 # define DDRP_DDRP0 0x01 1059 #define RDRP 0x025b 1060 # define RDRP_RDRP7 0x80 1061 # define RDRP_RDRP6 0x40 1062 # define RDRP_RDRP5 0x20 1063 # define RDRP_RDRP4 0x10 1064 # define RDRP_RDRP3 0x08 1065 # define RDRP_RDRP2 0x04 1066 # define RDRP_RDRP1 0x02 1067 # define RDRP_RDRP0 0x01 1068 #define PERP 0x025c 1069 # define PERP_PERP7 0x80 1070 # define PERP_PERP6 0x40 1071 # define PERP_PERP5 0x20 1072 # define PERP_PERP4 0x10 1073 # define PERP_PERP3 0x08 1074 # define PERP_PERP2 0x04 1075 # define PERP_PERP1 0x02 1076 # define PERP_PERP0 0x01 1077 #define PPSP 0x025d 1078 # define PPSP_PPSP7 0x80 1079 # define PPSP_PPSP6 0x40 1080 # define PPSP_PPSP5 0x20 1081 # define PPSP_PPSP4 0x10 1082 # define PPSP_PPSP3 0x08 1083 # define PPSP_PPSP2 0x04 1084 # define PPSP_PPSP1 0x02 1085 # define PPSP_PPSP0 0x01 1086 #define PIEP 0x025e 1087 # define PIEP_PIEP7 0x80 1088 # define PIEP_PIEP6 0x40 1089 # define PIEP_PIEP5 0x20 1090 # define PIEP_PIEP4 0x10 1091 # define PIEP_PIEP3 0x08 1092 # define PIEP_PIEP2 0x04 1093 # define PIEP_PIEP1 0x02 1094 # define PIEP_PIEP0 0x01 1095 #define PIFP 0x025f 1096 # define PIFP_PIFP7 0x80 1097 # define PIFP_PIFP6 0x40 1098 # define PIFP_PIFP5 0x20 1099 # define PIFP_PIFP4 0x10 1100 # define PIFP_PIFP3 0x08 1101 # define PIFP_PIFP2 0x04 1102 # define PIFP_PIFP1 0x02 1103 # define PIFP_PIFP0 0x01 1104 #define PTH 0x0260 1105 # define PTH_PTH7 0x80 1106 # define PTH_PTH6 0x40 1107 # define PTH_PTH5 0x20 1108 # define PTH_PTH4 0x10 1109 # define PTH_PTH3 0x08 1110 # define PTH_PTH2 0x04 1111 # define PTH_PTH1 0x02 1112 # define PTH_PTH0 0x01 1113 #define PTIH 0x0261 1114 # define PTIH_PTIH7 0x80 1115 # define PTIH_PTIH6 0x40 1116 # define PTIH_PTIH5 0x20 1117 # define PTIH_PTIH4 0x10 1118 # define PTIH_PTIH3 0x08 1119 # define PTIH_PTIH2 0x04 1120 # define PTIH_PTIH1 0x02 1121 # define PTIH_PTIH0 0x01 1122 #define DDRH 0x0262 1123 # define DDRH_DDRH7 0x80 1124 # define DDRH_DDRH6 0x40 1125 # define DDRH_DDRH5 0x20 1126 # define DDRH_DDRH4 0x10 1127 # define DDRH_DDRH3 0x08 1128 # define DDRH_DDRH2 0x04 1129 # define DDRH_DDRH1 0x02 1130 # define DDRH_DDRH0 0x01 1131 #define RDRH 0x0263 1132 # define RDRH_RDRH7 0x80 1133 # define RDRH_RDRH6 0x40 1134 # define RDRH_RDRH5 0x20 1135 # define RDRH_RDRH4 0x10 1136 # define RDRH_RDRH3 0x08 1137 # define RDRH_RDRH2 0x04 1138 # define RDRH_RDRH1 0x02 1139 # define RDRH_RDRH0 0x01 1140 #define PERH 0x0264 1141 # define PERH_PERH7 0x80 1142 # define PERH_PERH6 0x40 1143 # define PERH_PERH5 0x20 1144 # define PERH_PERH4 0x10 1145 # define PERH_PERH3 0x08 1146 # define PERH_PERH2 0x04 1147 # define PERH_PERH1 0x02 1148 # define PERH_PERH0 0x01 1149 #define PPSH 0x0265 1150 # define PPSH_PPSH7 0x80 1151 # define PPSH_PPSH6 0x40 1152 # define PPSH_PPSH5 0x20 1153 # define PPSH_PPSH4 0x10 1154 # define PPSH_PPSH3 0x08 1155 # define PPSH_PPSH2 0x04 1156 # define PPSH_PPSH1 0x02 1157 # define PPSH_PPSH0 0x01 1158 #define PIEH 0x0266 1159 # define PIEH_PIEH7 0x80 1160 # define PIEH_PIEH6 0x40 1161 # define PIEH_PIEH5 0x20 1162 # define PIEH_PIEH4 0x10 1163 # define PIEH_PIEH3 0x08 1164 # define PIEH_PIEH2 0x04 1165 # define PIEH_PIEH1 0x02 1166 # define PIEH_PIEH0 0x01 1167 #define PIFH 0x0267 1168 # define PIFH_PIFH7 0x80 1169 # define PIFH_PIFH6 0x40 1170 # define PIFH_PIFH5 0x20 1171 # define PIFH_PIFH4 0x10 1172 # define PIFH_PIFH3 0x08 1173 # define PIFH_PIFH2 0x04 1174 # define PIFH_PIFH1 0x02 1175 # define PIFH_PIFH0 0x01 1176 #define PTJ 0x0268 1177 # define PTJ_PTJ7 0x80 1178 # define PTJ_PTJ6 0x40 1179 # define PTJ_PTJ5 0x20 1180 # define PTJ_PTJ4 0x10 1181 # define PTJ_PTJ3 0x08 1182 # define PTJ_PTJ2 0x04 1183 # define PTJ_PTJ1 0x02 1184 # define PTJ_PTJ0 0x01 1185 #define PTIJ 0x0269 1186 # define PTIJ_PTIJ7 0x80 1187 # define PTIJ_PTIJ6 0x40 1188 # define PTIJ_PTIJ5 0x20 1189 # define PTIJ_PTIJ4 0x10 1190 # define PTIJ_PTIJ3 0x08 1191 # define PTIJ_PTIJ2 0x04 1192 # define PTIJ_PTIJ1 0x02 1193 1194 #endif /* __IO_MC9S12_H */ 1195