1 //***************************************************************************** 2 // 3 // Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ 4 // 5 // 6 // Redistribution and use in source and binary forms, with or without 7 // modification, are permitted provided that the following conditions 8 // are met: 9 // 10 // Redistributions of source code must retain the above copyright 11 // notice, this list of conditions and the following disclaimer. 12 // 13 // Redistributions in binary form must reproduce the above copyright 14 // notice, this list of conditions and the following disclaimer in the 15 // documentation and/or other materials provided with the 16 // distribution. 17 // 18 // Neither the name of Texas Instruments Incorporated nor the names of 19 // its contributors may be used to endorse or promote products derived 20 // from this software without specific prior written permission. 21 // 22 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 25 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 26 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 28 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 // 34 //***************************************************************************** 35 36 #ifndef __HW_DES_H__ 37 #define __HW_DES_H__ 38 39 //***************************************************************************** 40 // 41 // The following are defines for the DES_P register offsets. 42 // 43 //***************************************************************************** 44 #define DES_O_KEY3_L 0x00000000 // KEY3 (LSW) for 192-bit key 45 #define DES_O_KEY3_H 0x00000004 // KEY3 (MSW) for 192-bit key 46 #define DES_O_KEY2_L 0x00000008 // KEY2 (LSW) for 192-bit key 47 #define DES_O_KEY2_H 0x0000000C // KEY2 (MSW) for 192-bit key 48 #define DES_O_KEY1_L 0x00000010 // KEY1 (LSW) for 128-bit 49 // key/192-bit key 50 #define DES_O_KEY1_H 0x00000014 // KEY1 (LSW) for 128-bit 51 // key/192-bit key 52 #define DES_O_IV_L 0x00000018 // Initialization vector LSW 53 #define DES_O_IV_H 0x0000001C // Initialization vector MSW 54 #define DES_O_CTRL 0x00000020 55 #define DES_O_LENGTH 0x00000024 // Indicates the cryptographic data 56 // length in bytes for all modes. 57 // Once processing is started with 58 // this context this length 59 // decrements to zero. Data lengths 60 // up to (2^32 – 1) bytes are 61 // allowed. A write to this register 62 // triggers the engine to start 63 // using this context. For a Host 64 // read operation these registers 65 // return all-zeroes. 66 #define DES_O_DATA_L 0x00000028 // Data register(LSW) to read/write 67 // encrypted/decrypted data. 68 #define DES_O_DATA_H 0x0000002C // Data register(MSW) to read/write 69 // encrypted/decrypted data. 70 #define DES_O_REVISION 0x00000030 71 #define DES_O_SYSCONFIG 0x00000034 72 #define DES_O_SYSSTATUS 0x00000038 73 #define DES_O_IRQSTATUS 0x0000003C // This register indicates the 74 // interrupt status. If one of the 75 // interrupt bits is set the 76 // interrupt output will be asserted 77 #define DES_O_IRQENABLE 0x00000040 // This register contains an enable 78 // bit for each unique interrupt 79 // generated by the module. It 80 // matches the layout of 81 // DES_IRQSTATUS register. An 82 // interrupt is enabled when the bit 83 // in this register is set to 1 84 85 86 87 //****************************************************************************** 88 // 89 // The following are defines for the bit fields in the DES_O_KEY3_L register. 90 // 91 //****************************************************************************** 92 #define DES_KEY3_L_KEY3_L_M 0xFFFFFFFF // data for key3 93 #define DES_KEY3_L_KEY3_L_S 0 94 //****************************************************************************** 95 // 96 // The following are defines for the bit fields in the DES_O_KEY3_H register. 97 // 98 //****************************************************************************** 99 #define DES_KEY3_H_KEY3_H_M 0xFFFFFFFF // data for key3 100 #define DES_KEY3_H_KEY3_H_S 0 101 //****************************************************************************** 102 // 103 // The following are defines for the bit fields in the DES_O_KEY2_L register. 104 // 105 //****************************************************************************** 106 #define DES_KEY2_L_KEY2_L_M 0xFFFFFFFF // data for key2 107 #define DES_KEY2_L_KEY2_L_S 0 108 //****************************************************************************** 109 // 110 // The following are defines for the bit fields in the DES_O_KEY2_H register. 111 // 112 //****************************************************************************** 113 #define DES_KEY2_H_KEY2_H_M 0xFFFFFFFF // data for key2 114 #define DES_KEY2_H_KEY2_H_S 0 115 //****************************************************************************** 116 // 117 // The following are defines for the bit fields in the DES_O_KEY1_L register. 118 // 119 //****************************************************************************** 120 #define DES_KEY1_L_KEY1_L_M 0xFFFFFFFF // data for key1 121 #define DES_KEY1_L_KEY1_L_S 0 122 //****************************************************************************** 123 // 124 // The following are defines for the bit fields in the DES_O_KEY1_H register. 125 // 126 //****************************************************************************** 127 #define DES_KEY1_H_KEY1_H_M 0xFFFFFFFF // data for key1 128 #define DES_KEY1_H_KEY1_H_S 0 129 //****************************************************************************** 130 // 131 // The following are defines for the bit fields in the DES_O_IV_L register. 132 // 133 //****************************************************************************** 134 #define DES_IV_L_IV_L_M 0xFFFFFFFF // initialization vector for CBC 135 // CFB modes 136 #define DES_IV_L_IV_L_S 0 137 //****************************************************************************** 138 // 139 // The following are defines for the bit fields in the DES_O_IV_H register. 140 // 141 //****************************************************************************** 142 #define DES_IV_H_IV_H_M 0xFFFFFFFF // initialization vector for CBC 143 // CFB modes 144 #define DES_IV_H_IV_H_S 0 145 //****************************************************************************** 146 // 147 // The following are defines for the bit fields in the DES_O_CTRL register. 148 // 149 //****************************************************************************** 150 #define DES_CTRL_CONTEXT 0x80000000 // If ‘1’ this read-only status bit 151 // indicates that the context data 152 // registers can be overwritten and 153 // the host is permitted to write 154 // the next context. 155 #define DES_CTRL_MODE_M 0x00000030 // Select CBC ECB or CFB mode 0x0 156 // ecb mode 0x1 cbc mode 0x2 cfb 157 // mode 0x3 reserved 158 #define DES_CTRL_MODE_S 4 159 #define DES_CTRL_TDES 0x00000008 // Select DES or triple DES 160 // encryption/decryption. 0 des mode 161 // 1 tdes mode 162 #define DES_CTRL_DIRECTION 0x00000004 // select encryption/decryption 0 163 // decryption is selected 1 164 // Encryption is selected 165 #define DES_CTRL_INPUT_READY 0x00000002 // When '1' ready to 166 // encrypt/decrypt data 167 #define DES_CTRL_OUTPUT_READY 0x00000001 // When '1' Data 168 // decrypted/encrypted ready 169 //****************************************************************************** 170 // 171 // The following are defines for the bit fields in the DES_O_LENGTH register. 172 // 173 //****************************************************************************** 174 #define DES_LENGTH_LENGTH_M 0xFFFFFFFF 175 #define DES_LENGTH_LENGTH_S 0 176 //****************************************************************************** 177 // 178 // The following are defines for the bit fields in the DES_O_DATA_L register. 179 // 180 //****************************************************************************** 181 #define DES_DATA_L_DATA_L_M 0xFFFFFFFF // data for encryption/decryption 182 #define DES_DATA_L_DATA_L_S 0 183 //****************************************************************************** 184 // 185 // The following are defines for the bit fields in the DES_O_DATA_H register. 186 // 187 //****************************************************************************** 188 #define DES_DATA_H_DATA_H_M 0xFFFFFFFF // data for encryption/decryption 189 #define DES_DATA_H_DATA_H_S 0 190 //****************************************************************************** 191 // 192 // The following are defines for the bit fields in the DES_O_REVISION register. 193 // 194 //****************************************************************************** 195 #define DES_REVISION_SCHEME_M 0xC0000000 196 #define DES_REVISION_SCHEME_S 30 197 #define DES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software 198 // compatible module family. If 199 // there is no level of software 200 // compatibility a new Func number 201 // (and hence REVISION) should be 202 // assigned. 203 #define DES_REVISION_FUNC_S 16 204 #define DES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP 205 // design owner. RTL follows a 206 // numbering such as X.Y.R.Z which 207 // are explained in this table. R 208 // changes ONLY when: (1) PDS 209 // uploads occur which may have been 210 // due to spec changes (2) Bug fixes 211 // occur (3) Resets to '0' when X or 212 // Y changes. Design team has an 213 // internal 'Z' (customer invisible) 214 // number which increments on every 215 // drop that happens due to DV and 216 // RTL updates. Z resets to 0 when R 217 // increments. 218 #define DES_REVISION_R_RTL_S 11 219 #define DES_REVISION_X_MAJOR_M \ 220 0x00000700 // Major Revision (X) maintained by 221 // IP specification owner. X changes 222 // ONLY when: (1) There is a major 223 // feature addition. An example 224 // would be adding Master Mode to 225 // Utopia Level2. The Func field (or 226 // Class/Type in old PID format) 227 // will remain the same. X does NOT 228 // change due to: (1) Bug fixes (2) 229 // Change in feature parameters. 230 231 #define DES_REVISION_X_MAJOR_S 8 232 #define DES_REVISION_CUSTOM_M 0x000000C0 233 #define DES_REVISION_CUSTOM_S 6 234 #define DES_REVISION_Y_MINOR_M \ 235 0x0000003F // Minor Revision (Y) maintained by 236 // IP specification owner. Y changes 237 // ONLY when: (1) Features are 238 // scaled (up or down). Flexibility 239 // exists in that this feature 240 // scalability may either be 241 // represented in the Y change or a 242 // specific register in the IP that 243 // indicates which features are 244 // exactly available. (2) When 245 // feature creeps from Is-Not list 246 // to Is list. But this may not be 247 // the case once it sees silicon; in 248 // which case X will change. Y does 249 // NOT change due to: (1) Bug fixes 250 // (2) Typos or clarifications (3) 251 // major functional/feature 252 // change/addition/deletion. Instead 253 // these changes may be reflected 254 // via R S X as applicable. Spec 255 // owner maintains a 256 // customer-invisible number 'S' 257 // which changes due to: (1) 258 // Typos/clarifications (2) Bug 259 // documentation. Note that this bug 260 // is not due to a spec change but 261 // due to implementation. 262 // Nevertheless the spec tracks the 263 // IP bugs. An RTL release (say for 264 // silicon PG1.1) that occurs due to 265 // bug fix should document the 266 // corresponding spec number (X.Y.S) 267 // in its release notes. 268 269 #define DES_REVISION_Y_MINOR_S 0 270 //****************************************************************************** 271 // 272 // The following are defines for the bit fields in the DES_O_SYSCONFIG register. 273 // 274 //****************************************************************************** 275 #define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ 276 0x00000080 // If set to ‘1’ the DMA context 277 // request is enabled. 0 Dma 278 // disabled 1 Dma enabled 279 280 #define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ 281 0x00000040 // If set to ‘1’ the DMA output 282 // request is enabled. 0 Dma 283 // disabled 1 Dma enabled 284 285 #define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ 286 0x00000020 // If set to ‘1’ the DMA input 287 // request is enabled. 0 Dma 288 // disabled 1 Dma enabled 289 290 //****************************************************************************** 291 // 292 // The following are defines for the bit fields in the DES_O_SYSSTATUS register. 293 // 294 //****************************************************************************** 295 #define DES_SYSSTATUS_RESETDONE \ 296 0x00000001 297 298 //****************************************************************************** 299 // 300 // The following are defines for the bit fields in the DES_O_IRQSTATUS register. 301 // 302 //****************************************************************************** 303 #define DES_IRQSTATUS_DATA_OUT \ 304 0x00000004 // This bit indicates data output 305 // interrupt is active and triggers 306 // the interrupt output. 307 308 #define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input 309 // interrupt is active and triggers 310 // the interrupt output. 311 #define DES_IRQSTATUS_CONTEX_IN \ 312 0x00000001 // This bit indicates context 313 // interrupt is active and triggers 314 // the interrupt output. 315 316 //****************************************************************************** 317 // 318 // The following are defines for the bit fields in the DES_O_IRQENABLE register. 319 // 320 //****************************************************************************** 321 #define DES_IRQENABLE_M_DATA_OUT \ 322 0x00000004 // If this bit is set to ‘1’ the 323 // secure data output interrupt is 324 // enabled. 325 326 #define DES_IRQENABLE_M_DATA_IN \ 327 0x00000002 // If this bit is set to ‘1’ the 328 // secure data input interrupt is 329 // enabled. 330 331 #define DES_IRQENABLE_M_CONTEX_IN \ 332 0x00000001 // If this bit is set to ‘1’ the 333 // secure context interrupt is 334 // enabled. 335 336 337 338 339 #endif // __HW_DES_H__ 340