1 /** 2 @file LMS7002M_parameters.cpp 3 @author Lime Microsystems (www.limemicro.com) 4 @brief Definition of LMS7002M transceiver control parameters registers 5 */ 6 #ifndef LMS7002M_PARAMETERS_COMPACT_H 7 #define LMS7002M_PARAMETERS_COMPACT_H 8 9 #define MSB_LSB(m, l) (m << 4 | l) 10 11 #include "typedefs.h" 12 13 typedef struct 14 { 15 uint16_t address; 16 uint8_t msblsb; 17 } LMS7Parameter; 18 19 //#define DCOFFI_RFE 0x010E, 13<<4 | 7 20 //#define DCOFFQ_RFE 0x010E, 6<<4 | 0 21 extern ROM const LMS7Parameter DCOFFI_RFE; 22 extern ROM const LMS7Parameter DCOFFQ_RFE; 23 24 //#define IQCORR_TXTSP 0x0203, 11<<4 | 0 25 //#define DCCORRI_TXTSP 0x0204, 15<<4 | 8 26 //#define DCCORRQ_TXTSP 0x0204, 7<<4 | 0 27 28 extern ROM const LMS7Parameter DCCORRI_TXTSP; 29 extern ROM const LMS7Parameter DCCORRQ_TXTSP; 30 extern ROM const LMS7Parameter IQCORR_TXTSP; 31 //#define IQCORR_RXTSP 0x0403, 11<<4 | 0 32 extern ROM const LMS7Parameter IQCORR_RXTSP; 33 34 //#define GCORRQ_TXTSP 0x0201, 10<<4 | 0 35 //#define GCORRI_TXTSP 0x0202, 10<<4 | 0 36 extern ROM const LMS7Parameter GCORRI_TXTSP; 37 extern ROM const LMS7Parameter GCORRQ_TXTSP; 38 //#define GCORRQ_RXTSP 0x0401, 10<<4 | 0 39 //#define GCORRI_RXTSP 0x0402, 10<<4 | 0 40 extern ROM const LMS7Parameter GCORRI_RXTSP; 41 extern ROM const LMS7Parameter GCORRQ_RXTSP; 42 43 #define SECTION_LimeLight 0x0020, 0x002F 44 #define SECTION_AFE 0x0082, 0x0082 45 #define SECTION_BIAS 0x0084, 0x0084 46 #define SECTION_XBUF 0x0085, 0x0085 47 #define SECTION_CGEN 0x0086, 0x008C 48 #define SECTION_LDO 0x0092, 0x00A7 49 #define SECTION_BIST 0x00A8, 0x00A8 50 #define SECTION_CDS 0x00AD, 0x00AE 51 #define SECTION_TRF 0x0100, 0x0104 52 #define SECTION_TBB 0x0105, 0x010A 53 #define SECTION_RFE 0x010C, 0x0114 54 #define SECTION_RBB 0x0115, 0x011A 55 #define SECTION_SX 0x011C, 0x0124 56 #define SECTION_TxTSP 0x0200, 0x020C 57 #define SECTION_TxNCO 0x0240, 0x0261 58 #define SECTION_RxTSP 0x0400, 0x040F 59 #define SECTION_RxNCO 0x0440, 0x0461 60 #define SECTION_RSSI_DC_CALIBRATION 0x05C0,0x05CC 61 62 //parameters are defines as uint16_t address, uint16_t msb_lsb bits 63 #define MRST_TX_B 0x0020, 14<<4 | 14 64 #define LRST_TX_A 0x0020, 13<<4 | 13 65 #define MRST_TX_A 0x0020, 12<<4 | 12 66 #define LRST_RX_B 0x0020, 11<<4 | 11 67 #define MRST_RX_B 0x0020, 10<<4 | 10 68 #define LRST_RX_A 0x0020, 9<<4 | 9 69 #define MRST_RX_A 0x0020, 8<<4 | 8 70 #define SRST_RXFIFO 0x0020, 7<<4 | 7 71 #define SRST_TXFIFO 0x0020, 6<<4 | 6 72 #define RXEN_B 0x0020, 5<<4 | 5 73 #define RXEN_A 0x0020, 4<<4 | 4 74 #define TXEN_B 0x0020, 3<<4 | 3 75 #define TXEN_A 0x0020, 2<<4 | 2 76 #define MAC 0x0020, 1<<4 | 0 77 #define TX_CLK_PE 0x0021, 11<<4 | 11 78 #define RX_CLK_PE 0x0021, 10<<4 | 10 79 #define SDA_PE 0x0021, 9<<4 | 9 80 #define SDA_DS 0x0021, 8<<4 | 8 81 #define SCL_PE 0x0021, 7<<4 | 7 82 #define SCL_DS 0x0021, 6<<4 | 6 83 #define SDIO_DS 0x0021, 5<<4 | 5 84 #define SDIO_PE 0x0021, 4<<4 | 4 85 #define SDO_PE 0x0021, 3<<4 | 3 86 #define SCLK_PE 0x0021, 2<<4 | 2 87 #define SEN_PE 0x0021, 1<<4 | 1 88 #define SPIMODE 0x0021, 0<<4 | 0 89 #define DIQ2_DS 0x0022, 11<<4 | 11 90 #define DIQ2_PE 0x0022, 10<<4 | 10 91 #define IQ_SEL_EN_2_PE 0x0022, 9<<4 | 9 92 #define TXNRX2_PE 0x0022, 8<<4 | 8 93 #define FCLK2_PE 0x0022, 7<<4 | 7 94 #define MCLK2_PE 0x0022, 6<<4 | 6 95 #define DIQ1_DS 0x0022, 5<<4 | 5 96 #define DIQ1_PE 0x0022, 4<<4 | 4 97 #define IQ_SEL_EN_1_PE 0x0022, 3<<4 | 3 98 #define TXNRX1_PE 0x0022, 2<<4 | 2 99 #define FCLK1_PE 0x0022, 1<<4 | 1 100 #define MCLK1_PE 0x0022, 0<<4 | 0 101 #define DIQDIRCTR2 0x0023, 15<<4 | 15 102 #define DIQDIR2 0x0023, 14<<4 | 14 103 #define DIQDIRCTR1 0x0023, 13<<4 | 13 104 #define DIQDIR1 0x0023, 12<<4 | 12 105 #define ENABLEDIRCTR2 0x0023, 11<<4 | 11 106 #define ENABLEDIR2 0x0023, 10<<4 | 10 107 #define ENABLEDIRCTR1 0x0023, 9<<4 | 9 108 #define ENABLEDIR1 0x0023, 8<<4 | 8 109 #define MOD_EN 0x0023, 6<<4 | 6 110 #define LML2_FIDM 0x0023, 5<<4 | 5 111 #define LML2_TXNRXIQ 0x0023, 4<<4 | 4 112 #define LML2_MODE 0x0023, 3<<4 | 3 113 #define LML1_FIDM 0x0023, 2<<4 | 2 114 #define LML1_TXNRXIQ 0x0023, 1<<4 | 1 115 #define LML1_MODE 0x0023, 0<<4 | 0 116 #define LML1_S3S 0x0024, 15<<4 | 14 117 #define LML1_S2S 0x0024, 13<<4 | 12 118 #define LML1_S1S 0x0024, 11<<4 | 10 119 #define LML1_S0S 0x0024, 9<<4 | 8 120 #define LML1_BQP 0x0024, 7<<4 | 6 121 #define LML1_BIP 0x0024, 5<<4 | 4 122 #define LML1_AQP 0x0024, 3<<4 | 2 123 #define LML1_AIP 0x0024, 1<<4 | 0 124 #define LML1_BB2RF_PST 0x0025, 15<<4 | 8 125 #define LML1_BB2RF_PRE 0x0025, 7<<4 | 0 126 #define LML1_RF2BB_PST 0x0026, 15<<4 | 8 127 #define LML1_RF2BB_PRE 0x0026, 7<<4 | 0 128 #define LML2_S3S 0x0027, 15<<4 | 14 129 #define LML2_S2S 0x0027, 13<<4 | 12 130 #define LML2_S1S 0x0027, 11<<4 | 10 131 #define LML2_S0S 0x0027, 9<<4 | 8 132 #define LML2_BQP 0x0027, 7<<4 | 6 133 #define LML2_BIP 0x0027, 5<<4 | 4 134 #define LML2_AQP 0x0027, 3<<4 | 2 135 #define LML2_AIP 0x0027, 1<<4 | 0 136 #define LML2_BB2RF_PST 0x0028, 15<<4 | 8 137 #define LML2_BB2RF_PRE 0x0028, 7<<4 | 0 138 #define LML2_RF2BB_PST 0x0029, 15<<4 | 8 139 #define LML2_RF2BB_PRE 0x0029, 7<<4 | 0 140 #define RX_MUX 0x002A, 11<<4 | 10 141 #define TX_MUX 0x002A, 9<<4 | 8 142 #define TXRDCLK_MUX 0x002A, 7<<4 | 6 143 #define TXWRCLK_MUX 0x002A, 5<<4 | 4 144 #define RXRDCLK_MUX 0x002A, 3<<4 | 2 145 #define RXWRCLK_MUX 0x002A, 1<<4 | 0 146 #define FCLK2_INV 0x002B, 15<<4 | 15 147 #define FCLK1_INV 0x002B, 14<<4 | 14 148 #define MCLK2DLY 0x002B, 13<<4 | 12 149 #define MCLK1DLY 0x002B, 11<<4 | 10 150 #define MCLK2SRC 0x002B, 5<<4 | 4 151 #define MCLK1SRC 0x002B, 3<<4 | 2 152 #define TXDIVEN 0x002B, 1<<4 | 1 153 #define RXDIVEN 0x002B, 0<<4 | 0 154 #define TXTSPCLKA_DIV 0x002C, 15<<4 | 8 155 #define RXTSPCLKA_DIV 0x002C, 7<<4 | 0 156 #define MIMO_SISO 0x002E, 15<<4 | 15 157 #define VER 0x002F, 15<<4 | 11 158 #define REV 0x002F, 10<<4 | 6 159 #define MASK 0x002F, 5<<4 | 0 160 #define EN_DIR_LDO 0x0081, 3<<4 | 3 161 #define EN_DIR_CGEN 0x0081, 2<<4 | 2 162 #define EN_DIR_XBUF 0x0081, 1<<4 | 1 163 #define EN_DIR_AFE 0x0081, 0<<4 | 0 164 #define ISEL_DAC_AFE 0x0082, 15<<4 | 13 165 #define MODE_INTERLEAVE_AFE 0x0082, 12<<4 | 12 166 #define MUX_AFE_1 0x0082, 11<<4 | 10 167 #define MUX_AFE_2 0x0082, 9<<4 | 8 168 #define PD_AFE 0x0082, 5<<4 | 5 169 #define PD_RX_AFE1 0x0082, 4<<4 | 4 170 #define PD_RX_AFE2 0x0082, 3<<4 | 3 171 #define PD_TX_AFE1 0x0082, 2<<4 | 2 172 #define PD_TX_AFE2 0x0082, 1<<4 | 1 173 #define EN_G_AFE 0x0082, 0<<4 | 0 174 #define MUX_BIAS_OUT 0x0084, 12<<4 | 11 175 #define RP_CALIB_BIAS 0x0084, 10<<4 | 6 176 #define PD_FRP_BIAS 0x0084, 4<<4 | 4 177 #define PD_F_BIAS 0x0084, 3<<4 | 3 178 #define PD_PTRP_BIAS 0x0084, 2<<4 | 2 179 #define PD_PT_BIAS 0x0084, 1<<4 | 1 180 #define PD_BIAS_MASTER 0x0084, 0<<4 | 0 181 #define SLFB_XBUF_RX 0x0085, 8<<4 | 8 182 #define SLFB_XBUF_TX 0x0085, 7<<4 | 7 183 #define BYP_XBUF_RX 0x0085, 6<<4 | 6 184 #define BYP_XBUF_TX 0x0085, 5<<4 | 5 185 #define EN_OUT2_XBUF_TX 0x0085, 4<<4 | 4 186 #define EN_TBUFIN_XBUF_RX 0x0085, 3<<4 | 3 187 #define PD_XBUF_RX 0x0085, 2<<4 | 2 188 #define PD_XBUF_TX 0x0085, 1<<4 | 1 189 #define EN_G_XBUF 0x0085, 0<<4 | 0 190 #define SPDUP_VCO_CGEN 0x0086, 15<<4 | 15 191 #define RESET_N_CGEN 0x0086, 14<<4 | 14 192 #define EN_ADCCLKH_CLKGN 0x0086, 11<<4 | 11 193 #define EN_COARSE_CKLGEN 0x0086, 10<<4 | 10 194 #define EN_INTONLY_SDM_CGEN 0x0086, 9<<4 | 9 195 #define EN_SDM_CLK_CGEN 0x0086, 8<<4 | 8 196 #define PD_CP_CGEN 0x0086, 6<<4 | 6 197 #define PD_FDIV_FB_CGEN 0x0086, 5<<4 | 5 198 #define PD_FDIV_O_CGEN 0x0086, 4<<4 | 4 199 #define PD_SDM_CGEN 0x0086, 3<<4 | 3 200 #define PD_VCO_CGEN 0x0086, 2<<4 | 2 201 #define PD_VCO_COMP_CGEN 0x0086, 1<<4 | 1 202 #define EN_G_CGEN 0x0086, 0<<4 | 0 203 #define FRAC_SDM_CGEN 0x0087, 19<<4 | 0 204 #define INT_SDM_CGEN 0x0088, 13<<4 | 4 205 #define REV_SDMCLK_CGEN 0x0089, 15<<4 | 15 206 #define SEL_SDMCLK_CGEN 0x0089, 14<<4 | 14 207 #define SX_DITHER_EN_CGEN 0x0089, 13<<4 | 13 208 #define CLKH_OV_CLKL_CGEN 0x0089, 12<<4 | 11 209 #define DIV_OUTCH_CGEN 0x0089, 10<<4 | 3 210 #define TST_CGEN 0x0089, 2<<4 | 0 211 #define REV_CLKDAC_CGEN 0x008A, 14<<4 | 14 212 #define REV_CLKADC_CGEN 0x008A, 13<<4 | 13 213 #define REVPH_PFD_CGEN 0x008A, 12<<4 | 12 214 #define IOFFSET_CP_CGEN 0x008A, 11<<4 | 6 215 #define IPULSE_CP_CGEN 0x008A, 5<<4 | 0 216 #define ICT_VCO_CGEN 0x008B, 13<<4 | 9 217 #define CSW_VCO_CGEN 0x008B, 8<<4 | 1 218 #define COARSE_START_CGEN 0x008B, 0<<4 | 0 219 #define COARSE_STEPDONE_CGEN 0x008C, 15<<4 | 15 220 #define COARSEPLL_COMPO_CGEN 0x008C, 14<<4 | 14 221 #define VCO_CMPHO_CGEN 0x008C, 13<<4 | 13 222 #define VCO_CMPLO_CGEN 0x008C, 12<<4 | 12 223 #define CP2_CGEN 0x008C, 11<<4 | 8 224 #define CP3_CGEN 0x008C, 7<<4 | 4 225 #define CZ_CGEN 0x008C, 3<<4 | 0 226 #define EN_LDO_DIG 0x0092, 15<<4 | 15 227 #define EN_LDO_DIGGN 0x0092, 14<<4 | 14 228 #define EN_LDO_DIGSXR 0x0092, 13<<4 | 13 229 #define EN_LDO_DIGSXT 0x0092, 12<<4 | 12 230 #define EN_LDO_DIVGN 0x0092, 11<<4 | 11 231 #define EN_LDO_DIVSXR 0x0092, 10<<4 | 10 232 #define EN_LDO_DIVSXT 0x0092, 9<<4 | 9 233 #define EN_LDO_LNA12 0x0092, 8<<4 | 8 234 #define EN_LDO_LNA14 0x0092, 7<<4 | 7 235 #define EN_LDO_MXRFE 0x0092, 6<<4 | 6 236 #define EN_LDO_RBB 0x0092, 5<<4 | 5 237 #define EN_LDO_RXBUF 0x0092, 4<<4 | 4 238 #define EN_LDO_TBB 0x0092, 3<<4 | 3 239 #define EN_LDO_TIA12 0x0092, 2<<4 | 2 240 #define EN_LDO_TIA14 0x0092, 1<<4 | 1 241 #define EN_G_LDO 0x0092, 0<<4 | 0 242 #define EN_LOADIMP_LDO_TLOB 0x0093, 15<<4 | 15 243 #define EN_LOADIMP_LDO_TPAD 0x0093, 14<<4 | 14 244 #define EN_LOADIMP_LDO_TXBUF 0x0093, 13<<4 | 13 245 #define EN_LOADIMP_LDO_VCOGN 0x0093, 12<<4 | 12 246 #define EN_LOADIMP_LDO_VCOSXR 0x0093, 11<<4 | 11 247 #define EN_LOADIMP_LDO_VCOSXT 0x0093, 10<<4 | 10 248 #define EN_LDO_AFE 0x0093, 9<<4 | 9 249 #define EN_LDO_CPGN 0x0093, 8<<4 | 8 250 #define EN_LDO_CPSXR 0x0093, 7<<4 | 7 251 #define EN_LDO_TLOB 0x0093, 6<<4 | 6 252 #define EN_LDO_TPAD 0x0093, 5<<4 | 5 253 #define EN_LDO_TXBUF 0x0093, 4<<4 | 4 254 #define EN_LDO_VCOGN 0x0093, 3<<4 | 3 255 #define EN_LDO_VCOSXR 0x0093, 2<<4 | 2 256 #define EN_LDO_VCOSXT 0x0093, 1<<4 | 1 257 #define EN_LDO_CPSXT 0x0093, 0<<4 | 0 258 #define EN_LOADIMP_LDO_CPSXT 0x0094, 15<<4 | 15 259 #define EN_LOADIMP_LDO_DIG 0x0094, 14<<4 | 14 260 #define EN_LOADIMP_LDO_DIGGN 0x0094, 13<<4 | 13 261 #define EN_LOADIMP_LDO_DIGSXR 0x0094, 12<<4 | 12 262 #define EN_LOADIMP_LDO_DIGSXT 0x0094, 11<<4 | 11 263 #define EN_LOADIMP_LDO_DIVGN 0x0094, 10<<4 | 10 264 #define EN_LOADIMP_LDO_DIVSXR 0x0094, 9<<4 | 9 265 #define EN_LOADIMP_LDO_DIVSXT 0x0094, 8<<4 | 8 266 #define EN_LOADIMP_LDO_LNA12 0x0094, 7<<4 | 7 267 #define EN_LOADIMP_LDO_LNA14 0x0094, 6<<4 | 6 268 #define EN_LOADIMP_LDO_MXRFE 0x0094, 5<<4 | 5 269 #define EN_LOADIMP_LDO_RBB 0x0094, 4<<4 | 4 270 #define EN_LOADIMP_LDO_RXBUF 0x0094, 3<<4 | 3 271 #define EN_LOADIMP_LDO_TBB 0x0094, 2<<4 | 2 272 #define EN_LOADIMP_LDO_TIA12 0x0094, 1<<4 | 1 273 #define EN_LOADIMP_LDO_TIA14 0x0094, 0<<4 | 0 274 #define BYP_LDO_TBB 0x0095, 15<<4 | 15 275 #define BYP_LDO_TIA12 0x0095, 14<<4 | 14 276 #define BYP_LDO_TIA14 0x0095, 13<<4 | 13 277 #define BYP_LDO_TLOB 0x0095, 12<<4 | 12 278 #define BYP_LDO_TPAD 0x0095, 11<<4 | 11 279 #define BYP_LDO_TXBUF 0x0095, 10<<4 | 10 280 #define BYP_LDO_VCOGN 0x0095, 9<<4 | 9 281 #define BYP_LDO_VCOSXR 0x0095, 8<<4 | 8 282 #define BYP_LDO_VCOSXT 0x0095, 7<<4 | 7 283 #define EN_LOADIMP_LDO_AFE 0x0095, 2<<4 | 2 284 #define EN_LOADIMP_LDO_CPGN 0x0095, 1<<4 | 1 285 #define EN_LOADIMP_LDO_CPSXR 0x0095, 0<<4 | 0 286 #define BYP_LDO_AFE 0x0096, 15<<4 | 15 287 #define BYP_LDO_CPGN 0x0096, 14<<4 | 14 288 #define BYP_LDO_CPSXR 0x0096, 13<<4 | 13 289 #define BYP_LDO_CPSXT 0x0096, 12<<4 | 12 290 #define BYP_LDO_DIG 0x0096, 11<<4 | 11 291 #define BYP_LDO_DIGGN 0x0096, 10<<4 | 10 292 #define BYP_LDO_DIGSXR 0x0096, 9<<4 | 9 293 #define BYP_LDO_DIGSXT 0x0096, 8<<4 | 8 294 #define BYP_LDO_DIVGN 0x0096, 7<<4 | 7 295 #define BYP_LDO_DIVSXR 0x0096, 6<<4 | 6 296 #define BYP_LDO_DIVSXT 0x0096, 5<<4 | 5 297 #define BYP_LDO_LNA12 0x0096, 4<<4 | 4 298 #define BYP_LDO_LNA14 0x0096, 3<<4 | 3 299 #define BYP_LDO_MXRFE 0x0096, 2<<4 | 2 300 #define BYP_LDO_RBB 0x0096, 1<<4 | 1 301 #define BYP_LDO_RXBUF 0x0096, 0<<4 | 0 302 #define SPDUP_LDO_DIVSXR 0x0097, 15<<4 | 15 303 #define SPDUP_LDO_DIVSXT 0x0097, 14<<4 | 14 304 #define SPDUP_LDO_LNA12 0x0097, 13<<4 | 13 305 #define SPDUP_LDO_LNA14 0x0097, 12<<4 | 12 306 #define SPDUP_LDO_MXRFE 0x0097, 11<<4 | 11 307 #define SPDUP_LDO_RBB 0x0097, 10<<4 | 10 308 #define SPDUP_LDO_RXBUF 0x0097, 9<<4 | 9 309 #define SPDUP_LDO_TBB 0x0097, 8<<4 | 8 310 #define SPDUP_LDO_TIA12 0x0097, 7<<4 | 7 311 #define SPDUP_LDO_TIA14 0x0097, 6<<4 | 6 312 #define SPDUP_LDO_TLOB 0x0097, 5<<4 | 5 313 #define SPDUP_LDO_TPAD 0x0097, 4<<4 | 4 314 #define SPDUP_LDO_TXBUF 0x0097, 3<<4 | 3 315 #define SPDUP_LDO_VCOGN 0x0097, 2<<4 | 2 316 #define SPDUP_LDO_VCOSXR 0x0097, 1<<4 | 1 317 #define SPDUP_LDO_VCOSXT 0x0097, 0<<4 | 0 318 #define SPDUP_LDO_AFE 0x0098, 8<<4 | 8 319 #define SPDUP_LDO_CPGN 0x0098, 7<<4 | 7 320 #define SPDUP_LDO_CPSXR 0x0098, 6<<4 | 6 321 #define SPDUP_LDO_CPSXT 0x0098, 5<<4 | 5 322 #define SPDUP_LDO_DIG 0x0098, 4<<4 | 4 323 #define SPDUP_LDO_DIGGN 0x0098, 3<<4 | 3 324 #define SPDUP_LDO_DIGSXR 0x0098, 2<<4 | 2 325 #define SPDUP_LDO_DIGSXT 0x0098, 1<<4 | 1 326 #define SPDUP_LDO_DIVGN 0x0098, 0<<4 | 0 327 #define RDIV_VCOSXR 0x0099, 15<<4 | 8 328 #define RDIV_VCOSXT 0x0099, 7<<4 | 0 329 #define RDIV_TXBUF 0x009A, 15<<4 | 8 330 #define RDIV_VCOGN 0x009A, 7<<4 | 0 331 #define RDIV_TLOB 0x009B, 15<<4 | 8 332 #define RDIV_TPAD 0x009B, 7<<4 | 0 333 #define RDIV_TIA12 0x009C, 15<<4 | 8 334 #define RDIV_TIA14 0x009C, 7<<4 | 0 335 #define RDIV_RXBUF 0x009D, 15<<4 | 8 336 #define RDIV_TBB 0x009D, 7<<4 | 0 337 #define RDIV_MXRFE 0x009E, 15<<4 | 8 338 #define RDIV_RBB 0x009E, 7<<4 | 0 339 #define RDIV_LNA12 0x009F, 15<<4 | 8 340 #define RDIV_LNA14 0x009F, 7<<4 | 0 341 #define RDIV_DIVSXR 0x00A0, 15<<4 | 8 342 #define RDIV_DIVSXT 0x00A0, 7<<4 | 0 343 #define RDIV_DIGSXT 0x00A1, 15<<4 | 8 344 #define RDIV_DIVGN 0x00A1, 7<<4 | 0 345 #define RDIV_DIGGN 0x00A2, 15<<4 | 8 346 #define RDIV_DIGSXR 0x00A2, 7<<4 | 0 347 #define RDIV_CPSXT 0x00A3, 15<<4 | 8 348 #define RDIV_DIG 0x00A3, 7<<4 | 0 349 #define RDIV_CPGN 0x00A4, 15<<4 | 8 350 #define RDIV_CPSXR 0x00A4, 7<<4 | 0 351 #define RDIV_SPIBUF 0x00A5, 15<<4 | 8 352 #define RDIV_AFE 0x00A5, 7<<4 | 0 353 #define SPDUP_LDO_SPIBUF 0x00A6, 12<<4 | 12 354 #define SPDUP_LDO_DIGIp2 0x00A6, 11<<4 | 11 355 #define SPDUP_LDO_DIGIp1 0x00A6, 10<<4 | 10 356 #define BYP_LDO_SPIBUF 0x00A6, 9<<4 | 9 357 #define BYP_LDO_DIGIp2 0x00A6, 8<<4 | 8 358 #define BYP_LDO_DIGIp1 0x00A6, 7<<4 | 7 359 #define EN_LOADIMP_LDO_SPIBUF 0x00A6, 6<<4 | 6 360 #define EN_LOADIMP_LDO_DIGIp2 0x00A6, 5<<4 | 5 361 #define EN_LOADIMP_LDO_DIGIp1 0x00A6, 4<<4 | 4 362 #define PD_LDO_SPIBUF 0x00A6, 3<<4 | 3 363 #define PD_LDO_DIGIp2 0x00A6, 2<<4 | 2 364 #define PD_LDO_DIGIp1 0x00A6, 1<<4 | 1 365 #define EN_G_LDOP 0x00A6, 0<<4 | 0 366 #define RDIV_DIGIp2 0x00A7, 15<<4 | 8 367 #define RDIV_DIGIp1 0x00A7, 7<<4 | 0 368 #define BSIGT 0x00A8, 31<<4 | 9 369 #define BSTATE 0x00A8, 8<<4 | 8 370 #define EN_SDM_TSTO_SXT 0x00A8, 6<<4 | 6 371 #define EN_SDM_TSTO_SXR 0x00A8, 5<<4 | 5 372 #define EN_SDM_TSTO_CGEN 0x00A8, 4<<4 | 4 373 #define BENC 0x00A8, 3<<4 | 3 374 #define BENR 0x00A8, 2<<4 | 2 375 #define BENT 0x00A8, 1<<4 | 1 376 #define BSTART 0x00A8, 0<<4 | 0 377 #define BSIGR 0x00AA, 22<<4 | 0 378 #define BSIGC 0x00AB, 29<<4 | 7 379 #define CDS_MCLK2 0x00AD, 15<<4 | 14 380 #define CDS_MCLK1 0x00AD, 13<<4 | 12 381 #define CDSN_TXBTSP 0x00AD, 9<<4 | 9 382 #define CDSN_TXATSP 0x00AD, 8<<4 | 8 383 #define CDSN_RXBTSP 0x00AD, 7<<4 | 7 384 #define CDSN_RXATSP 0x00AD, 6<<4 | 6 385 #define CDSN_TXBLML 0x00AD, 5<<4 | 5 386 #define CDSN_TXALML 0x00AD, 4<<4 | 4 387 #define CDSN_RXBLML 0x00AD, 3<<4 | 3 388 #define CDSN_RXALML 0x00AD, 2<<4 | 2 389 #define CDSN_MCLK2 0x00AD, 1<<4 | 1 390 #define CDSN_MCLK1 0x00AD, 0<<4 | 0 391 #define CDS_TXBTSP 0x00AE, 15<<4 | 14 392 #define CDS_TXATSP 0x00AE, 13<<4 | 12 393 #define CDS_RXBTSP 0x00AE, 11<<4 | 10 394 #define CDS_RXATSP 0x00AE, 9<<4 | 8 395 #define CDS_TXBLML 0x00AE, 7<<4 | 6 396 #define CDS_TXALML 0x00AE, 5<<4 | 4 397 #define CDS_RXBLML 0x00AE, 3<<4 | 2 398 #define CDS_RXALML 0x00AE, 1<<4 | 0 399 #define EN_LOWBWLOMX_TMX_TRF 0x0100, 15<<4 | 15 400 #define EN_NEXTTX_TRF 0x0100, 14<<4 | 14 401 #define EN_AMPHF_PDET_TRF 0x0100, 13<<4 | 12 402 #define LOADR_PDET_TRF 0x0100, 11<<4 | 10 403 #define PD_PDET_TRF 0x0100, 3<<4 | 3 404 #define PD_TLOBUF_TRF 0x0100, 2<<4 | 2 405 #define PD_TXPAD_TRF 0x0100, 1<<4 | 1 406 #define EN_G_TRF 0x0100, 0<<4 | 0 407 #define F_TXPAD_TRF 0x0101, 15<<4 | 13 408 #define L_LOOPB_TXPAD_TRF 0x0101, 12<<4 | 11 409 #define LOSS_LIN_TXPAD_TRF 0x0101, 10<<4 | 6 410 #define LOSS_MAIN_TXPAD_TRF 0x0101, 5<<4 | 1 411 #define EN_LOOPB_TXPAD_TRF 0x0101, 0<<4 | 0 412 #define GCAS_GNDREF_TXPAD_TRF 0x0102, 15<<4 | 15 413 #define ICT_LIN_TXPAD_TRF 0x0102, 14<<4 | 10 414 #define ICT_MAIN_TXPAD_TRF 0x0102, 9<<4 | 5 415 #define VGCAS_TXPAD_TRF 0x0102, 4<<4 | 0 416 #define SEL_BAND1_TRF 0x0103, 11<<4 | 11 417 #define SEL_BAND2_TRF 0x0103, 10<<4 | 10 418 #define LOBIASN_TXM_TRF 0x0103, 9<<4 | 5 419 #define LOBIASP_TXX_TRF 0x0103, 4<<4 | 0 420 #define CDC_I_TRF 0x0104, 7<<4 | 4 421 #define CDC_Q_TRF 0x0104, 3<<4 | 0 422 #define STATPULSE_TBB 0x0105, 15<<4 | 15 423 #define LOOPB_TBB 0x0105, 14<<4 | 12 424 #define PD_LPFH_TBB 0x0105, 4<<4 | 4 425 #define PD_LPFIAMP_TBB 0x0105, 3<<4 | 3 426 #define PD_LPFLAD_TBB 0x0105, 2<<4 | 2 427 #define PD_LPFS5_TBB 0x0105, 1<<4 | 1 428 #define EN_G_TBB 0x0105, 0<<4 | 0 429 #define ICT_LPFS5_F_TBB 0x0106, 14<<4 | 10 430 #define ICT_LPFS5_PT_TBB 0x0106, 9<<4 | 5 431 #define ICT_LPF_H_PT_TBB 0x0106, 4<<4 | 0 432 #define ICT_LPFH_F_TBB 0x0107, 14<<4 | 10 433 #define ICT_LPFLAD_F_TBB 0x0107, 9<<4 | 5 434 #define ICT_LPFLAD_PT_TBB 0x0107, 4<<4 | 0 435 #define CG_IAMP_TBB 0x0108, 15<<4 | 10 436 #define ICT_IAMP_FRP_TBB 0x0108, 9<<4 | 5 437 #define ICT_IAMP_GG_FRP_TBB 0x0108, 4<<4 | 0 438 #define RCAL_LPFH_TBB 0x0109, 15<<4 | 8 439 #define RCAL_LPFLAD_TBB 0x0109, 7<<4 | 0 440 #define TSTIN_TBB 0x010A, 15<<4 | 14 441 #define BYPLADDER_TBB 0x010A, 13<<4 | 13 442 #define CCAL_LPFLAD_TBB 0x010A, 12<<4 | 8 443 #define RCAL_LPFS5_TBB 0x010A, 7<<4 | 0 444 #define CDC_I_RFE 0x010C, 15<<4 | 12 445 #define CDC_Q_RFE 0x010C, 11<<4 | 8 446 #define PD_LNA_RFE 0x010C, 7<<4 | 7 447 #define PD_RLOOPB_1_RFE 0x010C, 6<<4 | 6 448 #define PD_RLOOPB_2_RFE 0x010C, 5<<4 | 5 449 #define PD_MXLOBUF_RFE 0x010C, 4<<4 | 4 450 #define PD_QGEN_RFE 0x010C, 3<<4 | 3 451 #define PD_RSSI_RFE 0x010C, 2<<4 | 2 452 #define PD_TIA_RFE 0x010C, 1<<4 | 1 453 #define EN_G_RFE 0x010C, 0<<4 | 0 454 #define SEL_PATH_RFE 0x010D, 8<<4 | 7 455 #define EN_DCOFF_RXFE_RFE 0x010D, 6<<4 | 6 456 #define EN_INSHSW_LB1_RFE 0x010D, 4<<4 | 4 457 #define EN_INSHSW_LB2_RFE 0x010D, 3<<4 | 3 458 #define EN_INSHSW_L_RFE 0x010D, 2<<4 | 2 459 #define EN_INSHSW_W_RFE 0x010D, 1<<4 | 1 460 #define EN_NEXTRX_RFE 0x010D, 0<<4 | 0 461 #define ICT_LOOPB_RFE 0x010F, 14<<4 | 10 462 #define ICT_TIAMAIN_RFE 0x010F, 9<<4 | 5 463 #define ICT_TIAOUT_RFE 0x010F, 4<<4 | 0 464 #define ICT_LNACMO_RFE 0x0110, 14<<4 | 10 465 #define ICT_LNA_RFE 0x0110, 9<<4 | 5 466 #define ICT_LODC_RFE 0x0110, 4<<4 | 0 467 #define CAP_RXMXO_RFE 0x0111, 9<<4 | 5 468 #define CGSIN_LNA_RFE 0x0111, 4<<4 | 0 469 #define CCOMP_TIA_RFE 0x0112, 15<<4 | 12 470 #define CFB_TIA_RFE 0x0112, 11<<4 | 0 471 #define G_LNA_RFE 0x0113, 9<<4 | 6 472 #define G_RXLOOPB_RFE 0x0113, 5<<4 | 2 473 #define G_TIA_RFE 0x0113, 1<<4 | 0 474 #define RCOMP_TIA_RFE 0x0114, 8<<4 | 5 475 #define RFB_TIA_RFE 0x0114, 4<<4 | 0 476 #define EN_LB_LPFH_RBB 0x0115, 15<<4 | 15 477 #define EN_LB_LPFL_RBB 0x0115, 14<<4 | 14 478 #define PD_LPFH_RBB 0x0115, 3<<4 | 3 479 #define PD_LPFL_RBB 0x0115, 2<<4 | 2 480 #define PD_PGA_RBB 0x0115, 1<<4 | 1 481 #define EN_G_RBB 0x0115, 0<<4 | 0 482 #define R_CTL_LPF_RBB 0x0116, 15<<4 | 11 483 #define RCC_CTL_LPFH_RBB 0x0116, 10<<4 | 8 484 #define C_CTL_LPFH_RBB 0x0116, 7<<4 | 0 485 #define RCC_CTL_LPFL_RBB 0x0117, 13<<4 | 11 486 #define C_CTL_LPFL_RBB 0x0117, 10<<4 | 0 487 #define INPUT_CTL_PGA_RBB 0x0118, 15<<4 | 13 488 #define ICT_LPF_IN_RBB 0x0118, 9<<4 | 5 489 #define ICT_LPF_OUT_RBB 0x0118, 4<<4 | 0 490 #define OSW_PGA_RBB 0x0119, 15<<4 | 15 491 #define ICT_PGA_OUT_RBB 0x0119, 14<<4 | 10 492 #define ICT_PGA_IN_RBB 0x0119, 9<<4 | 5 493 #define G_PGA_RBB 0x0119, 4<<4 | 0 494 #define RCC_CTL_PGA_RBB 0x011A, 13<<4 | 9 495 #define C_CTL_PGA_RBB 0x011A, 6<<4 | 0 496 #define RESET_N 0x011C, 15<<4 | 15 497 #define SPDUP_VCO 0x011C, 14<<4 | 14 498 #define BYPLDO_VCO 0x011C, 13<<4 | 13 499 #define EN_COARSEPLL 0x011C, 12<<4 | 12 500 #define CURLIM_VCO 0x011C, 11<<4 | 11 501 #define EN_DIV2_DIVPROG 0x011C, 10<<4 | 10 502 #define EN_INTONLY_SDM 0x011C, 9<<4 | 9 503 #define EN_SDM_CLK 0x011C, 8<<4 | 8 504 #define PD_FBDIV 0x011C, 7<<4 | 7 505 #define PD_LOCH_T2RBUF 0x011C, 6<<4 | 6 506 #define PD_CP 0x011C, 5<<4 | 5 507 #define PD_FDIV 0x011C, 4<<4 | 4 508 #define PD_SDM 0x011C, 3<<4 | 3 509 #define PD_VCO_COMP 0x011C, 2<<4 | 2 510 #define PD_VCO 0x011C, 1<<4 | 1 511 #define EN_G 0x011C, 0<<4 | 0 512 #define FRAC_SDM 0x011D, 19<<4 | 0 513 #define INT_SDM 0x011E, 13<<4 | 4 514 #define PW_DIV2_LOCH 0x011F, 14<<4 | 12 515 #define PW_DIV4_LOCH 0x011F, 11<<4 | 9 516 #define DIV_LOCH 0x011F, 8<<4 | 6 517 #define TST_SX 0x011F, 5<<4 | 3 518 #define SEL_SDMCLK 0x011F, 2<<4 | 2 519 #define SX_DITHER_EN 0x011F, 1<<4 | 1 520 #define REV_SDMCLK 0x011F, 0<<4 | 0 521 #define VDIV_VCO 0x0120, 15<<4 | 8 522 #define ICT_VCO 0x0120, 7<<4 | 0 523 #define RSEL_LDO_VCO 0x0121, 15<<4 | 11 524 #define CSW_VCO 0x0121, 10<<4 | 3 525 #define SEL_VCO 0x0121, 2<<4 | 1 526 #define COARSE_START 0x0121, 0<<4 | 0 527 #define REVPH_PFD 0x0122, 12<<4 | 12 528 #define IOFFSET_CP 0x0122, 11<<4 | 6 529 #define IPULSE_CP 0x0122, 5<<4 | 0 530 #define COARSE_STEPDONE 0x0123, 15<<4 | 15 531 #define COARSEPLL_COMPO 0x0123, 14<<4 | 14 532 #define VCO_CMPHO 0x0123, 13<<4 | 13 533 #define VCO_CMPLO 0x0123, 12<<4 | 12 534 #define CP2_PLL 0x0123, 11<<4 | 8 535 #define CP3_PLL 0x0123, 7<<4 | 4 536 #define CZ 0x0123, 3<<4 | 0 537 #define EN_DIR_SXRSXT 0x0124, 4<<4 | 4 538 #define EN_DIR_RBB 0x0124, 3<<4 | 3 539 #define EN_DIR_RFE 0x0124, 2<<4 | 2 540 #define EN_DIR_TBB 0x0124, 1<<4 | 1 541 #define EN_DIR_TRF 0x0124, 0<<4 | 0 542 #define TSGFC_TXTSP 0x0200, 9<<4 | 9 543 #define TSGFCW_TXTSP 0x0200, 8<<4 | 7 544 #define TSGDCLDQ_TXTSP 0x0200, 6<<4 | 6 545 #define TSGDCLDI_TXTSP 0x0200, 5<<4 | 5 546 #define TSGSWAPIQ_TXTSP 0x0200, 4<<4 | 4 547 #define TSGMODE_TXTSP 0x0200, 3<<4 | 3 548 #define INSEL_TXTSP 0x0200, 2<<4 | 2 549 #define BSTART_TXTSP 0x0200, 1<<4 | 1 550 #define EN_TXTSP 0x0200, 0<<4 | 0 551 #define HBI_OVR_TXTSP 0x0203, 14<<4 | 12 552 #define GFIR1_L_TXTSP 0x0205, 10<<4 | 8 553 #define GFIR1_N_TXTSP 0x0205, 7<<4 | 0 554 #define GFIR2_L_TXTSP 0x0206, 10<<4 | 8 555 #define GFIR2_N_TXTSP 0x0206, 7<<4 | 0 556 #define GFIR3_L_TXTSP 0x0207, 10<<4 | 8 557 #define GFIR3_N_TXTSP 0x0207, 7<<4 | 0 558 #define CMIX_GAIN_TXTSP 0x0208, 15<<4 | 14 559 #define CMIX_GAIN_TXTSP_R3 0x0208, 12<<4 | 12 560 #define CMIX_SC_TXTSP 0x0208, 13<<4 | 13 561 #define CMIX_BYP_TXTSP 0x0208, 8<<4 | 8 562 #define ISINC_BYP_TXTSP 0x0208, 7<<4 | 7 563 #define GFIR3_BYP_TXTSP 0x0208, 6<<4 | 6 564 #define GFIR2_BYP_TXTSP 0x0208, 5<<4 | 5 565 #define GFIR1_BYP_TXTSP 0x0208, 4<<4 | 4 566 #define DC_BYP_TXTSP 0x0208, 3<<4 | 3 567 #define GC_BYP_TXTSP 0x0208, 1<<4 | 1 568 #define PH_BYP_TXTSP 0x0208, 0<<4 | 0 569 #define BSIGI_TXTSP 0x0209, 23<<4 | 1 570 #define BSTATE_TXTSP 0x0209, 0<<4 | 0 571 #define BSIGQ_TXTSP 0x020A, 30<<4 | 8 572 #define DC_REG_TXTSP 0x020C, 15<<4 | 0 573 #define DTHBIT_TX 0x0240, 8<<4 | 5 574 #define SEL_TX 0x0240, 4<<4 | 1 575 #define MODE_TX 0x0240, 0<<4 | 0 576 #define CAPTURE 0x0400, 15<<4 | 15 577 #define CAPSEL 0x0400, 14<<4 | 13 578 #define TSGFC_RXTSP 0x0400, 9<<4 | 9 579 #define TSGFCW_RXTSP 0x0400, 8<<4 | 7 580 #define TSGDCLDQ_RXTSP 0x0400, 6<<4 | 6 581 #define TSGDCLDI_RXTSP 0x0400, 5<<4 | 5 582 #define TSGSWAPIQ_RXTSP 0x0400, 4<<4 | 4 583 #define TSGMODE_RXTSP 0x0400, 3<<4 | 3 584 #define INSEL_RXTSP 0x0400, 2<<4 | 2 585 #define BSTART_RXTSP 0x0400, 1<<4 | 1 586 #define EN_RXTSP 0x0400, 0<<4 | 0 587 #define HBD_OVR_RXTSP 0x0403, 14<<4 | 12 588 #define DCCORR_AVG_RXTSP 0x0404, 2<<4 | 0 589 #define GFIR1_L_RXTSP 0x0405, 10<<4 | 8 590 #define GFIR1_N_RXTSP 0x0405, 7<<4 | 0 591 #define GFIR2_L_RXTSP 0x0406, 10<<4 | 8 592 #define GFIR2_N_RXTSP 0x0406, 7<<4 | 0 593 #define GFIR3_L_RXTSP 0x0407, 10<<4 | 8 594 #define GFIR3_N_RXTSP 0x0407, 7<<4 | 0 595 #define AGC_K_RXTSP 0x0408, 17<<4 | 0 596 #define AGC_ADESIRED_RXTSP 0x0409, 15<<4 | 4 597 #define AGC_MODE_RXTSP 0x040A, 13<<4 | 12 598 #define AGC_AVG_RXTSP 0x040A, 2<<4 | 0 599 #define DC_REG_RXTSP 0x040B, 15<<4 | 0 600 #define CMIX_GAIN_RXTSP 0x040C, 15<<4 | 14 601 #define CMIX_SC_RXTSP 0x040C, 13<<4 | 13 602 #define CMIX_GAIN_RXTSP_R3 0x040C, 12<<4 | 12 603 #define CMIX_BYP_RXTSP 0x040C, 7<<4 | 7 604 #define AGC_BYP_RXTSP 0x040C, 6<<4 | 6 605 #define GFIR3_BYP_RXTSP 0x040C, 5<<4 | 5 606 #define GFIR2_BYP_RXTSP 0x040C, 4<<4 | 4 607 #define GFIR1_BYP_RXTSP 0x040C, 3<<4 | 3 608 #define DC_BYP_RXTSP 0x040C, 2<<4 | 2 609 #define GC_BYP_RXTSP 0x040C, 1<<4 | 1 610 #define PH_BYP_RXTSP 0x040C, 0<<4 | 0 611 #define CAPD 0x040E, 31<<4 | 0 612 #define DTHBIT_RX 0x0440, 8<<4 | 5 613 #define SEL_RX 0x0440, 4<<4 | 1 614 #define MODE_RX 0x0440, 0<<4 | 0 615 616 #define DCMODE 0x05C0, 15<<4 | 15 617 #define PD_DCDAC_RXB 0x05C0, 7<<4 | 7 618 #define PD_DCDAC_RXA 0x05C0, 6<<4 | 6 619 #define PD_DCDAC_TXB 0x05C0, 5<<4 | 5 620 #define PD_DCDAC_TXA 0x05C0, 4<<4 | 4 621 #define PD_DCCMP_RXB 0x05C0, 3<<4 | 3 622 #define PD_DCCMP_RXA 0x05C0, 2<<4 | 2 623 #define PD_DCCMP_TXB 0x05C0, 1<<4 | 1 624 #define PD_DCCMP_TXA 0x05C0, 0<<4 | 0 625 626 #define DCWR_TXAI 0x05C3, 15<<4 | 15 627 #define DCRD_TXAI 0x05C3, 14<<4 | 14 628 #define DC_TXAI 0x05C3, 10<<4 | 0 629 #define DCWR_TXAQ 0x05C4, 15<<4 | 15 630 #define DCRD_TXAQ 0x05C4, 14<<4 | 14 631 #define DC_TXAQ 0x05C4, 10<<4 | 0 632 #define DCWR_TXBI 0x05C5, 15<<4 | 15 633 #define DCRD_TXBI 0x05C5, 14<<4 | 14 634 #define DC_TXBI 0x05C5, 10<<4 | 0 635 #define DCWR_TXBQ 0x05C6, 15<<4 | 15 636 #define DCRD_TXBQ 0x05C6, 14<<4 | 14 637 #define DC_TXBQ 0x05C6, 10<<4 | 0 638 #define DCWR_RXAI 0x05C7, 15<<4 | 15 639 #define DCRD_RXAI 0x05C7, 14<<4 | 14 640 #define DC_RXAI 0x05C7, 6<<4 | 0 641 #define DCWR_RXAQ 0x05C8, 15<<4 | 15 642 #define DCRD_RXAQ 0x05C8, 14<<4 | 14 643 #define DC_RXAQ 0x05C8, 6<<4 | 0 644 #define DCWR_RXBI 0x05C9, 15<<4 | 15 645 #define DCRD_RXBI 0x05C9, 14<<4 | 14 646 #define DC_RXBI 0x05C9, 6<<4 | 0 647 #define DCWR_RXBQ 0x05CA, 15<<4 | 15 648 #define DCRD_RXBQ 0x05CA, 14<<4 | 14 649 650 #define R5_LPF_BYP_TBB 0x010B, 0<<4 | 0 651 #define RSSI_RSSI1_VAL 0x0605, 7 << 4 | 0 652 #define TRX_GAIN_SRC 0x0081, 15 << 4 | 15 653 #define G_LNA_RFE_R3 0x0126, 5 << 4 | 2 654 #define G_PGA_RBB_R3 0x0126, 10 << 4 | 6 655 #define G_TIA_RFE_R3 0x0126, 1 << 4 | 0 656 #define CG_IAMP_TBB_R3 0x0125, 15 << 4 | 10 657 #define LOSS_LIN_TXPAD_TRF_R3 0x0125, 9 << 4 | 5 658 #define LOSS_MAIN_TXPAD_TRF_R3 0x0125, 4 << 4 | 0 659 660 #define DCOFFI_RFE 0x010E, 13<<4 | 7 661 #define DCOFFQ_RFE 0x010E, 6<<4 | 0 662 #define DCCORRI_TXTSP 0x0204, 15<<4 | 8 663 #define DCCORRQ_TXTSP 0x0204, 7<<4 | 0 664 #define IQCORR_TXTSP 0x0203, 11<<4 | 0 665 #define IQCORR_RXTSP 0x0403, 11<<4 | 0 666 #define GCORRI_TXTSP 0x0202, 10<<4 | 0 667 #define GCORRQ_TXTSP 0x0201, 10<<4 | 0 668 #define GCORRI_RXTSP 0x0402, 10<<4 | 0 669 #define GCORRQ_RXTSP 0x0401, 10<<4 | 0 670 671 #endif 672