1 /* $OpenBSD: pcscpreg.h,v 1.4 2022/01/09 05:42:58 jsg Exp $ */ 2 /* $NetBSD$ */ 3 4 /*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Izumi Tsutsui. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Am53c974 DMA engine registers 35 */ 36 37 #define DMA_CMD 0x40 /* Command */ 38 #define DMACMD_RSVD 0xFFFFFF28 /* reserved */ 39 #define DMACMD_DIR 0x00000080 /* Transfer Direction (read:1) */ 40 #define DMACMD_INTE 0x00000040 /* DMA Interrupt Enable */ 41 #define DMACMD_MDL 0x00000010 /* Map to Memory Description List */ 42 #define DMACMD_DIAG 0x00000004 /* Diagnostic */ 43 #define DMACMD_CMD 0x00000003 /* Command Code Bit */ 44 #define DMACMD_IDLE 0x00000000 /* Idle */ 45 #define DMACMD_BLAST 0x00000001 /* Blast */ 46 #define DMACMD_ABORT 0x00000002 /* Abort */ 47 #define DMACMD_START 0x00000003 /* Start */ 48 49 #define DMA_STC 0x44 /* Start Transfer Count */ 50 #define DMA_SPA 0x48 /* Start Physical Address */ 51 #define DMA_WBC 0x4C /* Working Byte Counter */ 52 #define DMA_WAC 0x50 /* Working Address Counter */ 53 54 #define DMA_STAT 0x54 /* Status Register */ 55 #define DMASTAT_RSVD 0xFFFFFF80 /* reserved */ 56 #define DMASTAT_PABT 0x00000040 /* PCI master/target Abort */ 57 #define DMASTAT_BCMP 0x00000020 /* BLAST Complete */ 58 #define DMASTAT_SINT 0x00000010 /* SCSI Interrupt */ 59 #define DMASTAT_DONE 0x00000008 /* DMA Transfer Terminated */ 60 #define DMASTAT_ABT 0x00000004 /* DMA Transfer Aborted */ 61 #define DMASTAT_ERR 0x00000002 /* DMA Transfer Error */ 62 #define DMASTAT_PWDN 0x00000001 /* Power Down Indicator */ 63 64 #define DMA_SMDLA 0x58 /* Starting Memory Descriptor List Address */ 65 #define DMA_WMAC 0x5C /* Working MDL Counter */ 66 #define DMA_SBAC 0x70 /* SCSI Bus and Control */ 67