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Searched defs:DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_OCCURRED_MASK (Results 1 – 2 of 2) sorted by path

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_11_2_sh_mask.h8709 #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 macro
H A Ddce_12_0_sh_mask.h5678 #define DMCU_PERFMON_INTERRUPT_STATUS5__DCFEV0_PERFMON_COUNTER4_INT_OCCURRED_MASK … macro