| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/example_design/ |
| H A D | fifo_short_2clk_exdes.vhd | 84 DOUT : OUT std_logic_vector(72-1 DOWNTO 0); port
109 DOUT : OUT std_logic_vector(72-1 DOWNTO 0); port in fifo_short_2clk_exdes.xilinx.fifo_short_2clk
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/example_design/ |
| H A D | fifo_4k_2clk_exdes.vhd | 84 DOUT : OUT std_logic_vector(72-1 DOWNTO 0); port
109 DOUT : OUT std_logic_vector(72-1 DOWNTO 0); port in fifo_4k_2clk_exdes.xilinx.fifo_4k_2clk
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/example_design/ |
| H A D | fifo_4k_2clk_exdes.vhd | 84 DOUT : OUT std_logic_vector(72-1 DOWNTO 0); port
109 DOUT : OUT std_logic_vector(72-1 DOWNTO 0); port in fifo_4k_2clk_exdes.xilinx.fifo_4k_2clk
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/fifo_short_2clk/example_design/ |
| H A D | fifo_short_2clk_exdes.vhd | 84 DOUT : OUT std_logic_vector(72-1 DOWNTO 0); port
109 DOUT : OUT std_logic_vector(72-1 DOWNTO 0); port in fifo_short_2clk_exdes.xilinx.fifo_short_2clk
|
| /dports/cad/yosys/yosys-yosys-0.12/manual/PRESENTATION_ExSyn/ |
| H A D | memory_01.v | 3 output reg [7:0] DOUT); port
|
| /dports/security/yubico-piv-tool/yubico-piv-tool-2.2.0/ykcs11/ |
| H A D | debug.h | 45 #define DOUT DBG(("Out")); macro
|
| /dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue672/ |
| H A D | SQR.vhd | 27 DOUT : OUT std_logic_vector(31 downto 0); port
|
| H A D | SQRTb.vhd | 33 DOUT : OUT std_logic_vector(31 downto 0); port in SQRTb.TB.SQR
|
| /dports/devel/openocd/openocd-0.11.0/contrib/loaders/flash/ |
| H A D | mrvlqspi_write.S | 54 #define DOUT 0x8 macro
|
| /dports/lang/ruby26/ruby-2.6.9/lib/irb/ |
| H A D | slex.rb | 24 DOUT = Notifier::def_notifier("SLex::") constant in IRB.SLex
|
| /dports/math/gap/gap-4.11.0/pkg/grape-4.8.3/nauty22/ |
| H A D | sumlines.c | 134 #define DOUT "%ld" /* Formats used to output %d/%x/%p,%f,%v quantities */ macro
139 #define DOUT "%lld" macro
144 #define DOUT "%Ld" macro
|
| /dports/textproc/pict/pict-3.7.1/api/ |
| H A D | generator.h | 29 #define DOUT(arg) logfile << arg macro
31 #define DOUT(arg) wcerr << arg macro
34 #define DOUT(arg) macro
|
| /dports/math/plantri/plantri52/ |
| H A D | sumlines.c | 137 #define DOUT "%ld" /* Format used to output %d/%x/%n/%p quantities */ macro
144 #define DOUT "%lld" macro
151 #define DOUT "%Ld" macro
|
| /dports/math/nauty/nauty27r3/ |
| H A D | sumlines.c | 137 #define DOUT "%ld" /* Format used to output %d/%x/%n/%p quantities */ macro
144 #define DOUT "%lld" macro
151 #define DOUT "%Ld" macro
|
| /dports/math/py-pynauty/pynauty-1.0.2/src/nauty27r1/ |
| H A D | sumlines.c | 137 #define DOUT "%ld" /* Format used to output %d/%x/%n/%p quantities */ macro
144 #define DOUT "%lld" macro
151 #define DOUT "%Ld" macro
|
| /dports/math/blaze/blaze-3.8/blazetest/blazetest/mathtest/adaptors/uppermatrix/ |
| H A D | ColumnTest.h | 84 using DOUT = DUT::OppositeType; variable
|
| H A D | RowTest.h | 84 using DOUT = DUT::OppositeType; variable
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/fifo_4k_2clk/simulation/ |
| H A D | fifo_4k_2clk_pkg.vhd | 209 DOUT : OUT std_logic_vector(72-1 DOWNTO 0); port in fifo_4k_2clk_pkg.fifo_4k_2clk_exdes
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen/fifo_4k_2clk/simulation/ |
| H A D | fifo_4k_2clk_pkg.vhd | 209 DOUT : OUT std_logic_vector(72-1 DOWNTO 0); port in fifo_4k_2clk_pkg.fifo_4k_2clk_exdes
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen/fifo_short_2clk/simulation/ |
| H A D | fifo_short_2clk_pkg.vhd | 209 DOUT : OUT std_logic_vector(72-1 DOWNTO 0); port in fifo_short_2clk_pkg.fifo_short_2clk_exdes
|
| /dports/math/blaze/blaze-3.8/blazetest/blazetest/mathtest/adaptors/strictlyuppermatrix/ |
| H A D | RowTest.h | 84 using DOUT = DUT::OppositeType; variable
|
| H A D | ColumnTest.h | 84 using DOUT = DUT::OppositeType; variable
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/fifo_short_2clk/simulation/ |
| H A D | fifo_short_2clk_pkg.vhd | 209 DOUT : OUT std_logic_vector(72-1 DOWNTO 0); port in fifo_short_2clk_pkg.fifo_short_2clk_exdes
|
| /dports/math/blaze/blaze-3.8/blazetest/blazetest/mathtest/adaptors/uniuppermatrix/ |
| H A D | RowTest.h | 84 using DOUT = DUT::OppositeType; variable
|
| H A D | ColumnTest.h | 84 using DOUT = DUT::OppositeType; variable
|