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Searched defs:DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h31234 #define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_sh_mask.h38130 #define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT macro