1 /* $NetBSD: display.h,v 1.2 2021/12/18 23:45:31 riastradh Exp $ */
2
3 /*
4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Ke Yu
27 * Zhiyuan Lv <zhiyuan.lv@intel.com>
28 *
29 * Contributors:
30 * Terrence Xu <terrence.xu@intel.com>
31 * Changbin Du <changbin.du@intel.com>
32 * Bing Niu <bing.niu@intel.com>
33 * Zhi Wang <zhi.a.wang@intel.com>
34 *
35 */
36
37 #ifndef _GVT_DISPLAY_H_
38 #define _GVT_DISPLAY_H_
39
40 #include <linux/types.h>
41
42 struct intel_gvt;
43 struct intel_vgpu;
44
45 #define SBI_REG_MAX 20
46 #define DPCD_SIZE 0x700
47
48 #define intel_vgpu_port(vgpu, port) \
49 (&(vgpu->display.ports[port]))
50
51 #define intel_vgpu_has_monitor_on_port(vgpu, port) \
52 (intel_vgpu_port(vgpu, port)->edid && \
53 intel_vgpu_port(vgpu, port)->edid->data_valid)
54
55 #define intel_vgpu_port_is_dp(vgpu, port) \
56 ((intel_vgpu_port(vgpu, port)->type == GVT_DP_A) || \
57 (intel_vgpu_port(vgpu, port)->type == GVT_DP_B) || \
58 (intel_vgpu_port(vgpu, port)->type == GVT_DP_C) || \
59 (intel_vgpu_port(vgpu, port)->type == GVT_DP_D))
60
61 #define INTEL_GVT_MAX_UEVENT_VARS 3
62
63 /* DPCD start */
64 #define DPCD_SIZE 0x700
65
66 /* DPCD */
67 #define DP_SET_POWER 0x600
68 #define DP_SET_POWER_D0 0x1
69 #define AUX_NATIVE_WRITE 0x8
70 #define AUX_NATIVE_READ 0x9
71
72 #define AUX_NATIVE_REPLY_MASK (0x3 << 4)
73 #define AUX_NATIVE_REPLY_ACK (0x0 << 4)
74 #define AUX_NATIVE_REPLY_NAK (0x1 << 4)
75 #define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
76
77 #define AUX_BURST_SIZE 20
78
79 /* DPCD addresses */
80 #define DPCD_REV 0x000
81 #define DPCD_MAX_LINK_RATE 0x001
82 #define DPCD_MAX_LANE_COUNT 0x002
83
84 #define DPCD_TRAINING_PATTERN_SET 0x102
85 #define DPCD_SINK_COUNT 0x200
86 #define DPCD_LANE0_1_STATUS 0x202
87 #define DPCD_LANE2_3_STATUS 0x203
88 #define DPCD_LANE_ALIGN_STATUS_UPDATED 0x204
89 #define DPCD_SINK_STATUS 0x205
90
91 /* link training */
92 #define DPCD_TRAINING_PATTERN_SET_MASK 0x03
93 #define DPCD_LINK_TRAINING_DISABLED 0x00
94 #define DPCD_TRAINING_PATTERN_1 0x01
95 #define DPCD_TRAINING_PATTERN_2 0x02
96
97 #define DPCD_CP_READY_MASK (1 << 6)
98
99 /* lane status */
100 #define DPCD_LANES_CR_DONE 0x11
101 #define DPCD_LANES_EQ_DONE 0x22
102 #define DPCD_SYMBOL_LOCKED 0x44
103
104 #define DPCD_INTERLANE_ALIGN_DONE 0x01
105
106 #define DPCD_SINK_IN_SYNC 0x03
107 /* DPCD end */
108
109 #define SBI_RESPONSE_MASK 0x3
110 #define SBI_RESPONSE_SHIFT 0x1
111 #define SBI_STAT_MASK 0x1
112 #define SBI_STAT_SHIFT 0x0
113 #define SBI_OPCODE_SHIFT 8
114 #define SBI_OPCODE_MASK (0xff << SBI_OPCODE_SHIFT)
115 #define SBI_CMD_IORD 2
116 #define SBI_CMD_IOWR 3
117 #define SBI_CMD_CRRD 6
118 #define SBI_CMD_CRWR 7
119 #define SBI_ADDR_OFFSET_SHIFT 16
120 #define SBI_ADDR_OFFSET_MASK (0xffff << SBI_ADDR_OFFSET_SHIFT)
121
122 struct intel_vgpu_sbi_register {
123 unsigned int offset;
124 u32 value;
125 };
126
127 struct intel_vgpu_sbi {
128 int number;
129 struct intel_vgpu_sbi_register registers[SBI_REG_MAX];
130 };
131
132 enum intel_gvt_plane_type {
133 PRIMARY_PLANE = 0,
134 CURSOR_PLANE,
135 SPRITE_PLANE,
136 MAX_PLANE
137 };
138
139 struct intel_vgpu_dpcd_data {
140 bool data_valid;
141 u8 data[DPCD_SIZE];
142 };
143
144 enum intel_vgpu_port_type {
145 GVT_CRT = 0,
146 GVT_DP_A,
147 GVT_DP_B,
148 GVT_DP_C,
149 GVT_DP_D,
150 GVT_HDMI_B,
151 GVT_HDMI_C,
152 GVT_HDMI_D,
153 GVT_PORT_MAX
154 };
155
156 enum intel_vgpu_edid {
157 GVT_EDID_1024_768,
158 GVT_EDID_1920_1200,
159 GVT_EDID_NUM,
160 };
161
162 struct intel_vgpu_port {
163 /* per display EDID information */
164 struct intel_vgpu_edid_data *edid;
165 /* per display DPCD information */
166 struct intel_vgpu_dpcd_data *dpcd;
167 int type;
168 enum intel_vgpu_edid id;
169 };
170
vgpu_edid_str(enum intel_vgpu_edid id)171 static inline char *vgpu_edid_str(enum intel_vgpu_edid id)
172 {
173 switch (id) {
174 case GVT_EDID_1024_768:
175 return "1024x768";
176 case GVT_EDID_1920_1200:
177 return "1920x1200";
178 default:
179 return "";
180 }
181 }
182
vgpu_edid_xres(enum intel_vgpu_edid id)183 static inline unsigned int vgpu_edid_xres(enum intel_vgpu_edid id)
184 {
185 switch (id) {
186 case GVT_EDID_1024_768:
187 return 1024;
188 case GVT_EDID_1920_1200:
189 return 1920;
190 default:
191 return 0;
192 }
193 }
194
vgpu_edid_yres(enum intel_vgpu_edid id)195 static inline unsigned int vgpu_edid_yres(enum intel_vgpu_edid id)
196 {
197 switch (id) {
198 case GVT_EDID_1024_768:
199 return 768;
200 case GVT_EDID_1920_1200:
201 return 1200;
202 default:
203 return 0;
204 }
205 }
206
207 void intel_gvt_emulate_vblank(struct intel_gvt *gvt);
208 void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt);
209
210 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution);
211 void intel_vgpu_reset_display(struct intel_vgpu *vgpu);
212 void intel_vgpu_clean_display(struct intel_vgpu *vgpu);
213
214 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe);
215
216 #endif
217