1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 #ifndef __DAL_DDC_SERVICE_TYPES_H__
26 #define __DAL_DDC_SERVICE_TYPES_H__
27 
28 /* 0010FA dongles (ST Micro) external converter chip id */
29 #define DP_BRANCH_DEVICE_ID_0010FA 0x0010FA
30 /* 0022B9 external converter chip id */
31 #define DP_BRANCH_DEVICE_ID_0022B9 0x0022B9
32 #define DP_BRANCH_DEVICE_ID_00001A 0x00001A
33 #define DP_BRANCH_DEVICE_ID_0080E1 0x0080e1
34 #define DP_BRANCH_DEVICE_ID_90CC24 0x90CC24
35 #define DP_BRANCH_DEVICE_ID_00E04C 0x00E04C
36 #define DP_BRANCH_DEVICE_ID_006037 0x006037
37 #define DP_BRANCH_DEVICE_ID_001CF8 0x001CF8
38 #define DP_BRANCH_DEVICE_ID_0060AD 0x0060AD
39 #define DP_BRANCH_HW_REV_10 0x10
40 #define DP_BRANCH_HW_REV_20 0x20
41 
42 #define DP_DEVICE_ID_0022B9 0x0022B9
43 #define DP_DEVICE_ID_38EC11 0x38EC11
44 #define DP_DEVICE_ID_BA4159 0xBA4159
45 #define DP_FORCE_PSRSU_CAPABILITY 0x40F
46 
47 #define DP_SINK_PSR_ACTIVE_VTOTAL		0x373
48 #define DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE	0x375
49 #define DP_SOURCE_PSR_ACTIVE_VTOTAL		0x376
50 
51 enum ddc_result {
52 	DDC_RESULT_UNKNOWN = 0,
53 	DDC_RESULT_SUCESSFULL,
54 	DDC_RESULT_FAILED_CHANNEL_BUSY,
55 	DDC_RESULT_FAILED_TIMEOUT,
56 	DDC_RESULT_FAILED_PROTOCOL_ERROR,
57 	DDC_RESULT_FAILED_NACK,
58 	DDC_RESULT_FAILED_INCOMPLETE,
59 	DDC_RESULT_FAILED_OPERATION,
60 	DDC_RESULT_FAILED_INVALID_OPERATION,
61 	DDC_RESULT_FAILED_BUFFER_OVERFLOW,
62 	DDC_RESULT_FAILED_HPD_DISCON
63 };
64 
65 enum ddc_service_type {
66 	DDC_SERVICE_TYPE_CONNECTOR,
67 	DDC_SERVICE_TYPE_DISPLAY_PORT_MST,
68 };
69 
70 /**
71  * display sink capability
72  */
73 struct display_sink_capability {
74 	/* dongle type (DP converter, CV smart dongle) */
75 	enum display_dongle_type dongle_type;
76 	bool is_dongle_type_one;
77 
78 	/**********************************************************
79 	 capabilities going INTO SINK DEVICE (stream capabilities)
80 	 **********************************************************/
81 	/* Dongle's downstream count. */
82 	uint32_t downstrm_sink_count;
83 	/* Is dongle's downstream count info field (downstrm_sink_count)
84 	 * valid. */
85 	bool downstrm_sink_count_valid;
86 
87 	/* Maximum additional audio delay in microsecond (us) */
88 	uint32_t additional_audio_delay;
89 	/* Audio latency value in microsecond (us) */
90 	uint32_t audio_latency;
91 	/* Interlace video latency value in microsecond (us) */
92 	uint32_t video_latency_interlace;
93 	/* Progressive video latency value in microsecond (us) */
94 	uint32_t video_latency_progressive;
95 	/* Dongle caps: Maximum pixel clock supported over dongle for HDMI */
96 	uint32_t max_hdmi_pixel_clock;
97 	/* Dongle caps: Maximum deep color supported over dongle for HDMI */
98 	enum dc_color_depth max_hdmi_deep_color;
99 
100 	/************************************************************
101 	 capabilities going OUT OF SOURCE DEVICE (link capabilities)
102 	 ************************************************************/
103 	/* support for Spread Spectrum(SS) */
104 	bool ss_supported;
105 	/* DP link settings (laneCount, linkRate, Spread) */
106 	uint32_t dp_link_lane_count;
107 	uint32_t dp_link_rate;
108 	uint32_t dp_link_spead;
109 
110 	/* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
111 	indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
112 	bool is_dp_hdmi_s3d_converter;
113 	/* to check if we have queried the display capability
114 	 * for eDP panel already. */
115 	bool is_edp_sink_cap_valid;
116 
117 	enum ddc_transaction_type transaction_type;
118 	enum signal_type signal;
119 };
120 
121 struct av_sync_data {
122 	uint8_t av_granularity;/* DPCD 00023h */
123 	uint8_t aud_dec_lat1;/* DPCD 00024h */
124 	uint8_t aud_dec_lat2;/* DPCD 00025h */
125 	uint8_t aud_pp_lat1;/* DPCD 00026h */
126 	uint8_t aud_pp_lat2;/* DPCD 00027h */
127 	uint8_t vid_inter_lat;/* DPCD 00028h */
128 	uint8_t vid_prog_lat;/* DPCD 00029h */
129 	uint8_t aud_del_ins1;/* DPCD 0002Bh */
130 	uint8_t aud_del_ins2;/* DPCD 0002Ch */
131 	uint8_t aud_del_ins3;/* DPCD 0002Dh */
132 };
133 
134 #endif /* __DAL_DDC_SERVICE_TYPES_H__ */
135