1 /******************************Module*Header**********************************\
2 *
3 * Module Name: d3dkmdt.h
4 *
5 * Content: Windows Display Driver Model (WDDM) kernel mode
6 * data type definitions
7 *
8 * Copyright (c) Microsoft Corporation.
9 * Licensed under the MIT License.
10 *
11 \*****************************************************************************/
12 #ifndef _D3DKMDT_H
13 #define _D3DKMDT_H
14
15 #if !defined(_D3DKMDDI_H_) && \
16 !defined(_D3DKMDDI_PEXT_H_) && \
17 !defined(_DXGDMM_H_) && \
18 !defined(_VIDPRIV_H_) && \
19 !defined(_DISPMPRT_H_) && \
20 !defined(_DMM_DIAG_H_) && \
21 !defined(_D3DKMTHK_H_)
22 #error This header should not be included directly!
23 #endif
24
25 #include "d3dukmdt.h"
26
27 #ifndef __REACTOS__
28
29 #define NTSTATUS int32_t
30
31 /*
32 * Some of the Windows return codes, which needs to be translated to Linux
33 * IOCTL return codes. Positive values are success codes and need to be
34 * returned from the driver IOCTLs. libdxcore.so depends on returning
35 * specific return codes.
36 */
37 #define STATUS_SUCCESS ((NTSTATUS)(0))
38 #define STATUS_OBJECT_NAME_INVALID ((NTSTATUS)(0xC0000033L))
39 #define STATUS_DEVICE_REMOVED ((NTSTATUS)(0xC00002B6L))
40 #define STATUS_INVALID_HANDLE ((NTSTATUS)(0xC0000008L))
41 #define STATUS_ILLEGAL_INSTRUCTION ((NTSTATUS)(0xC000001DL))
42 #define STATUS_NOT_IMPLEMENTED ((NTSTATUS)(0xC0000002L))
43 #define STATUS_PENDING ((NTSTATUS)(0x00000103L))
44 #define STATUS_ACCESS_DENIED ((NTSTATUS)(0xC0000022L))
45 #define STATUS_BUFFER_TOO_SMALL ((NTSTATUS)(0xC0000023L))
46 #define STATUS_OBJECT_TYPE_MISMATCH ((NTSTATUS)(0xC0000024L))
47 #define STATUS_GRAPHICS_ALLOCATION_BUSY ((NTSTATUS)(0xC01E0102L))
48 #define STATUS_NOT_SUPPORTED ((NTSTATUS)(0xC00000BBL))
49 #define STATUS_TIMEOUT ((NTSTATUS)(0x00000102L))
50 #define STATUS_INVALID_PARAMETER ((NTSTATUS)(0xC000000DL))
51 #define STATUS_NO_MEMORY ((NTSTATUS)(0xC0000017L))
52 #define STATUS_OBJECT_NAME_COLLISION ((NTSTATUS)(0xC0000035L))
53 #define STATUS_OBJECT_NAME_NOT_FOUND ((NTSTATUS)(0xC0000034L))
54 #define STATUS_UNSUCCESSFUL ((NTSTATUS)(0xC0000001L))
55 #define STATUS_INVALID_PARAMETER ((NTSTATUS)(0xC000000DL))
56 #define NT_SUCCESS(status) (status >= 0)
57
58 typedef enum {
59 PowerActionNone = 0,
60 PowerActionReserved,
61 PowerActionSleep,
62 PowerActionHibernate,
63 PowerActionShutdown,
64 PowerActionShutdownReset,
65 PowerActionShutdownOff,
66 PowerActionWarmEject,
67 PowerActionDisplayOff
68 } POWER_ACTION, *PPOWER_ACTION;
69
70 typedef enum _DEVICE_POWER_STATE {
71 PowerDeviceUnspecified = 0,
72 PowerDeviceD0,
73 PowerDeviceD1,
74 PowerDeviceD2,
75 PowerDeviceD3,
76 PowerDeviceMaximum
77 } DEVICE_POWER_STATE, *PDEVICE_POWER_STATE;
78
79 #else
80
81 #ifndef NTSTATUS
82 typedef LONG NTSTATUS;
83 #endif
84
85 #endif // !__REACTOS__
86
87 #pragma region Desktop Family
88 #if WINAPI_FAMILY_PARTITION(WINAPI_PARTITION_DESKTOP)
89
90 #pragma warning(push)
91 #pragma warning(disable:4201) // anonymous unions warning
92 #pragma warning(disable:4214) // nonstandard extension used: bit field types other than int
93
94 //
95 // Available only for Vista (LONGHORN) and later and for
96 // multiplatform tools such as debugger extensions
97 //
98 #if defined(__REACTOS__) || ((NTDDI_VERSION >= NTDDI_LONGHORN) || defined(D3DKMDT_SPECIAL_MULTIPLATFORM_TOOL))
99
100 //
101 // Hardcoded overlay count
102 //
103 #define D3DKMDT_MAX_OVERLAYS_BITCOUNT 2
104 #define D3DKMDT_MAX_OVERLAYS (1 << D3DKMDT_MAX_OVERLAYS_BITCOUNT)
105
106
107 //////////////////// VidPN management DDI handles /////////////////////////////////////////////////////////
108 DECLARE_HANDLE(D3DKMDT_HVIDPN);
109 DECLARE_HANDLE(D3DKMDT_HVIDEOPRESENTSOURCESET);
110 DECLARE_HANDLE(D3DKMDT_HVIDEOPRESENTTARGETSET);
111 DECLARE_HANDLE(D3DKMDT_HVIDPNTOPOLOGY);
112 DECLARE_HANDLE(D3DKMDT_HVIDPNSOURCEMODESET);
113 DECLARE_HANDLE(D3DKMDT_HVIDPNTARGETMODESET);
114 DECLARE_HANDLE(D3DKMDT_HMONITORSOURCEMODESET);
115 DECLARE_HANDLE(D3DKMDT_HMONITORFREQUENCYRANGESET);
116 DECLARE_HANDLE(D3DKMDT_HMONITORDESCRIPTORSET);
117
118 // Alias VOID* to make LDDM kernel mode interface prototypes using adapter handles self-explanatory.
119 typedef VOID* D3DKMDT_ADAPTER;
120
121
122
123 //////////////////// VidPN management DDI constants /////////////////////////////////////////////////////////
124
125 // Special values representing that given variable has not been initialized to a valid value intended
126 // to catch development time errors. A valid parameter should never have this value.
127 #define D3DKMDT_DIMENSION_UNINITIALIZED (UINT)(~0)
128 #define D3DKMDT_FREQUENCY_UNINITIALIZED (UINT)(~0)
129
130 // Special values representing that given parameter is not-specified.
131 // A parameter having this value should be ignored.
132 #define D3DKMDT_DIMENSION_NOTSPECIFIED (UINT)(~1)
133 #define D3DKMDT_FREQUENCY_NOTSPECIFIED (UINT)(~1)
134
135
136
137 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
138 // Purpose: Video mode standard descriptor type, listing standards that are explicitly supported by Windows.
139 //
140 // Remarks: This enum specifies based on which standard the video signal timing parameters should be computed.
141 // Note that NTSC, PAL, and SECAM mode variants are treated as individual groups to avoid complicating
142 // the DDI with the notion of "sub-standard" (because they don't differ from each other in the parameters
143 // used to describe the video signal in the DDI and the parameters that they do differ in are of no
144 // interest to us in DMM).
145 //
146 typedef enum _D3DKMDT_VIDEO_SIGNAL_STANDARD
147 {
148 D3DKMDT_VSS_UNINITIALIZED = 0,
149
150 // VESA standards
151 D3DKMDT_VSS_VESA_DMT = 1, // See VESA Display Monitor Timings specification
152 D3DKMDT_VSS_VESA_GTF = 2, // See VESA Generalized Timing Formula standard
153 D3DKMDT_VSS_VESA_CVT = 3, // See VESA Coordinated Video Timings standard
154
155 // De-facto standards
156 D3DKMDT_VSS_IBM = 4,
157 D3DKMDT_VSS_APPLE = 5,
158
159 // Legacy STV standards W x H{i|p} @ ( VR / HR )
160 D3DKMDT_VSS_NTSC_M = 6, // 720 x 525i @ (59.94 [Hz] / 15,734.27[Hz])
161 D3DKMDT_VSS_NTSC_J = 7, // 720 x 525i @ (59.94 [Hz] / 15,734.27[Hz])
162 D3DKMDT_VSS_NTSC_443 = 8, // 720 x 525i @ (59.94 [Hz] / 15,734.27[Hz])
163 D3DKMDT_VSS_PAL_B = 9, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
164 D3DKMDT_VSS_PAL_B1 = 10, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
165 D3DKMDT_VSS_PAL_G = 11, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
166 D3DKMDT_VSS_PAL_H = 12, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
167 D3DKMDT_VSS_PAL_I = 13, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
168 D3DKMDT_VSS_PAL_D = 14, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
169 D3DKMDT_VSS_PAL_N = 15, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
170 D3DKMDT_VSS_PAL_NC = 16, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
171 D3DKMDT_VSS_SECAM_B = 17, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
172 D3DKMDT_VSS_SECAM_D = 18, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
173 D3DKMDT_VSS_SECAM_G = 19, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
174 D3DKMDT_VSS_SECAM_H = 20, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
175 D3DKMDT_VSS_SECAM_K = 21, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
176 D3DKMDT_VSS_SECAM_K1 = 22, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
177 D3DKMDT_VSS_SECAM_L = 23, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
178 D3DKMDT_VSS_SECAM_L1 = 24, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
179
180 // CEA/EIA standards
181 D3DKMDT_VSS_EIA_861 = 25,
182 D3DKMDT_VSS_EIA_861A = 26,
183 D3DKMDT_VSS_EIA_861B = 27,
184
185 // More legacy STV standards
186 D3DKMDT_VSS_PAL_K = 28, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
187 D3DKMDT_VSS_PAL_K1 = 29, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
188 D3DKMDT_VSS_PAL_L = 30, // 720 x 625i @ (50 [Hz] / 15,625 [Hz])
189 D3DKMDT_VSS_PAL_M = 31, // 720 x 525i @ (59.94 [Hz] / 15,734 [Hz])
190
191 D3DKMDT_VSS_OTHER = 255
192 }
193 D3DKMDT_VIDEO_SIGNAL_STANDARD;
194
195
196
197 //////////////////// Video present sources //////////////////////////////////////////////////////////////////
198
199
200 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
201 // Purpose: Video present source descriptor type.
202 //
203 typedef struct _D3DKMDT_VIDEO_PRESENT_SOURCE
204 {
205 // Unique ID used to reference the respective video present source by the miniport and the OS.
206 D3DDDI_VIDEO_PRESENT_SOURCE_ID Id;
207
208 // Other video present source descriptor properties go here.
209 DWORD dwReserved;
210 }
211 D3DKMDT_VIDEO_PRESENT_SOURCE;
212
213
214 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
215 // Purpose: VidPN source mode enumeration type descriptor type.
216 //
217 // Remarks: This type is used to specify whether a VidPN source mode is a graphics or a text mode
218 // (see VIDEO_PRESENT_SOURCE_MODE for more details).
219 //
220 typedef enum _D3DKMDT_VIDPN_SOURCE_MODE_TYPE
221 {
222 D3DKMDT_RMT_UNINITIALIZED = 0,
223 D3DKMDT_RMT_GRAPHICS = 1,
224 D3DKMDT_RMT_TEXT = 2,
225 D3DKMDT_RMT_GRAPHICS_STEREO = 3,
226 D3DKMDT_RMT_GRAPHICS_STEREO_ADVANCED_SCAN = 4
227 }
228 D3DKMDT_VIDPN_SOURCE_MODE_TYPE;
229
230
231 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
232 // Purpose: Pixel value access mode descriptor type.
233 //
234 // Remarks: Use Direct to represent VidPN source modes with colors stored directly in the primary surface.
235 // Use PresetPalette to represent VidPN source modes with colors' indices stored in the primary
236 // surface and actual color values stored in a palette specific to the video card, that must
237 // be queried from the video miniport.
238 // Use SettablePalette to represent VidPN source modes with colors' indices stored in the primary
239 // surface and actual color values stored in a settable palette that can be dynamically set on
240 // the video card, by specifying it to the video miniport.
241 //
242 typedef enum _D3DKMDT_PIXEL_VALUE_ACCESS_MODE
243 {
244 D3DKMDT_PVAM_UNINITIALIZED = 0,
245 D3DKMDT_PVAM_DIRECT = 1,
246 D3DKMDT_PVAM_PRESETPALETTE = 2,
247 D3DKMDT_PVAM_SETTABLEPALETTE = 3,
248 }
249 D3DKMDT_PIXEL_VALUE_ACCESS_MODE;
250
251
252 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
253 // Purpose: Descriptor type of the color basis with respect to which the pixels' colors are expanded,
254 // or conversely, based on which the color values are synthesized.
255 //
256 // Remarks: The commonly used color bases in graphics industry are RGB, which has the basis (red, green, blue),
257 // as well as YPbPr and YCbCr, which have scaled variants of basis:
258 // (1, blue-1, red-1)*intensity(red,green,blue).
259 // Tri-stimulus linear RGB is well suited for real-time rendering, since most filtering algorithms
260 // use tri-stimulus values to approximate light's spectral transformations caused by its interaction
261 // with the environment, primarily due to the fact that there is a linear relationship between the
262 // perceived light level and the light's spectral intensity. Ideally, all processing of video content
263 // (i.e. scaling, filtering, etc) should be performed in a linear RGB space.
264 // Y'PbPr spaces store data using a nonlinear curve which is approximately the inverse of a gamma
265 // 2.2 curve (i.e. x^0.45). This allows more precision to be stored in darker intensities where the
266 // human eye is more sensitive.
267 // sRGB (more accurately, sR'G'B') stores light intensities relative to a gamma curve.
268 // scRGB stores linear values and requires much higher precision to represent the same perceptually
269 // similar signal.
270 // The light-intensity based YPbPr and YCbCr is better suited for persistence of pre-rendered content,
271 // such as video streaming. This is due to the fact that a human visual system is more responsive to
272 // small differences in photons' intensity rather than frequency (i.e. perceived color), and, hence,
273 // a light-intensity based color expansion over a finite dynamic range, yields a better perceptual
274 // image quality for the human eye than a tri-stimulus based color expansion in that same range
275 // (e.g non-linear Y8Cb8Cr8 appears slightly better than R8G8B8 and is comparable to R9G9B9).
276 // To represent monochrome modes, use Intensity. Grayscale imaging is heavily used in medical imaging.
277 // Note: the apostrophe notation Y'PbPr is used to remind you that you are working with non-linear data.
278 //
279 typedef enum _D3DKMDT_COLOR_BASIS
280 {
281 D3DKMDT_CB_UNINITIALIZED = 0,
282 D3DKMDT_CB_INTENSITY = 1,
283 D3DKMDT_CB_SRGB = 2,
284 D3DKMDT_CB_SCRGB = 3,
285 D3DKMDT_CB_YCBCR = 4,
286 D3DKMDT_CB_YPBPR = 5,
287 }
288 D3DKMDT_COLOR_BASIS;
289
290 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
291 // Purpose: Descriptor type of the color coefficients dynamic range, whose linear combination with the
292 // respective color basis produces final pixel values.
293 //
294 // Remarks: Examples include (5,6,5,0) for R5G6B5, (8,8,8,8) for R8G8B8A8, and (24, 0, 0, 0) for 24-bit
295 // grayscale pixel encoding format.
296 // NOTE: Currently this is only used for target modes, none of which has the 4th channel (e.g. alpha).
297 // We are keeping the 4th field for extensibility purpose to avoid miniport interface revision
298 // if 4-channel video interfaces became available between display adapter and monitor.
299 //
300 typedef struct _D3DKMDT_COLOR_COEFF_DYNAMIC_RANGES
301 {
302 UINT FirstChannel;
303 UINT SecondChannel;
304 UINT ThirdChannel;
305 UINT FourthChannel;
306 }
307 D3DKMDT_COLOR_COEFF_DYNAMIC_RANGES;
308
309
310 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
311 // Purpose: 2D region descriptor type.
312 //
313 // Remarks: We define our own rather than reusing SIZE type to avoid dependency on SDK headers.
314 //
315 typedef struct _D3DKMDT_2DREGION
316 {
317 UINT cx;
318 UINT cy;
319 }
320 D3DKMDT_2DREGION;
321
322
323 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
324 // Purpose: 2D offset descriptor type.
325 //
326 // Remarks: We define our own rather than reusing SIZE type to avoid dependency on SDK headers.
327 //
328 typedef D3DKMDT_2DREGION D3DKMDT_2DOFFSET;
329
330
331 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
332 // Purpose: Graphics video present source mode descriptor type.
333 //
334 // Remarks: Graphics video present source mode is the dominantly used subtype of the video present source
335 // modes (other being the text video present source mode).
336 // Note that whenever video present source mode's visible size,
337 // VIDEO_PRESENT_SOURCE_MODE.GRAPHICS_RENDERING_FORMAT.sizeVisible is not equal to the respective
338 // video mode's visible size, VIDEO_PRESENT_TARGET_MODE.sizeVisible, h/w scaling is undertaken by
339 // the video output codec.
340 //
341 // Miniport is free to support any D3D pixel format for its graphics modes that is meaningful
342 // as a primary surface pixel format.
343 //
344 typedef struct _D3DKMDT_GRAPHICS_RENDERING_FORMAT
345 {
346 // Size of the primary surface required for this VidPN source mode.
347 D3DKMDT_2DREGION PrimSurfSize;
348
349 // Size of the visible part of the primary surface, used for panned modes including zoom modes.
350 // The visible region size is required to be the same as the primary surface
351 D3DKMDT_2DREGION VisibleRegionSize;
352
353 // Number of bytes between the start of one scan line and the next.
354 DWORD Stride;
355
356 // Pixel format type
357 D3DDDIFORMAT PixelFormat;
358
359 // Color basis with respect to which rendering client encodes pixel values.
360 D3DKMDT_COLOR_BASIS ColorBasis;
361
362 // Access mode for the pixel value information.
363 D3DKMDT_PIXEL_VALUE_ACCESS_MODE PixelValueAccessMode;
364 }
365 D3DKMDT_GRAPHICS_RENDERING_FORMAT;
366
367
368 typedef enum _D3DKMDT_TEXT_RENDERING_FORMAT
369 {
370 D3DKMDT_TRF_UNINITIALIZED = 0
371 }
372 D3DKMDT_TEXT_RENDERING_FORMAT;
373
374
375 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
376 // Purpose: Video present source mode ID type.
377 typedef UINT D3DKMDT_VIDEO_PRESENT_SOURCE_MODE_ID;
378
379 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
380 // Purpose: VidPN source mode descriptor type.
381 //
382 // Remarks: VidPN source (rendering) mode is the mode of operation of a given video present source and determines
383 // the format of this source's primary surface to which the graphics subsystem is rendering
384 // the visual image to be presented to the user, and from which the video output codec is reading
385 // the visual image content to be converted into a respective video mode signal.
386 //
387 typedef struct _D3DKMDT_VIDPN_SOURCE_MODE
388 {
389 D3DKMDT_VIDEO_PRESENT_SOURCE_MODE_ID Id;
390
391 // Specifies whether the mode is a graphics or a text rendering mode.
392 D3DKMDT_VIDPN_SOURCE_MODE_TYPE Type;
393
394 union
395 {
396 // Descriptor of the graphics rendering mode (valid only if Type==D3DKMDT_RMT_GRAPHICS).
397 D3DKMDT_GRAPHICS_RENDERING_FORMAT Graphics;
398
399 // Descriptor of the text rendering mode (valid only if Type==D3DKMDT_RMT_TEXT).
400 D3DKMDT_TEXT_RENDERING_FORMAT Text;
401 }
402 Format;
403 }
404 D3DKMDT_VIDPN_SOURCE_MODE;
405
406
407
408 //////////////////////// Video present targets///////////////////////////////////////////////////////////////
409
410
411 // NOTE: Child device (e.g. video output) HPD awareness is used to represent the level of external
412 // device (e.g. monitor) connectivity sensed by a display adapter. Child device can either be
413 // always connected to an external device (e.g. integrated LCD in a mobile system) or have:
414 // 1. No HPD-awareness iff miniport is *not* aware of external device arrivals/departures
415 // whether through interrupts or polling,
416 // 2. Polled HPD-awareness iff miniport can not asynchronously notify the OS about external
417 // device arrivals/departures, but OS can sporadically poll for its presence, and of a
418 // monitor, causing visual artifacts on each poll.
419 // 3. Interruptible HPD-awareness iff miniport can asynchronously notify the OS about
420 // external device arrivals/departures.
421 typedef enum _DXGK_CHILD_DEVICE_HPD_AWARENESS {
422 HpdAwarenessUninitialized = 0,
423 HpdAwarenessAlwaysConnected = 1,
424 HpdAwarenessNone = 2,
425 HpdAwarenessPolled = 3,
426 HpdAwarenessInterruptible = 4
427 } DXGK_CHILD_DEVICE_HPD_AWARENESS, *PDXGK_CHILD_DEVICE_HPD_AWARENESS;
428
429 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
430 // Purpose: Monitor orientation descriptor type.
431 //
432 typedef enum _D3DKMDT_MONITOR_ORIENTATION
433 {
434 D3DKMDT_MO_UNINITIALIZED = 0,
435 D3DKMDT_MO_0DEG = 1,
436 D3DKMDT_MO_90DEG = 2,
437 D3DKMDT_MO_180DEG = 3,
438 D3DKMDT_MO_270DEG = 4
439 }
440 D3DKMDT_MONITOR_ORIENTATION;
441
442
443 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
444 // Purpose: Video output technology descriptor type.
445 //
446 // Remarks: Video output technology is used to determine the hard-coded list of video modes supported
447 // by the monitor, when monitor descriptor is not available.
448 //
449 typedef enum _D3DKMDT_VIDEO_OUTPUT_TECHNOLOGY
450 {
451 D3DKMDT_VOT_UNINITIALIZED = -2,
452 D3DKMDT_VOT_OTHER = -1,
453 D3DKMDT_VOT_HD15 = 0,
454 D3DKMDT_VOT_SVIDEO = 1,
455 D3DKMDT_VOT_COMPOSITE_VIDEO = 2,
456 D3DKMDT_VOT_COMPONENT_VIDEO = 3,
457 D3DKMDT_VOT_DVI = 4,
458 D3DKMDT_VOT_HDMI = 5,
459 D3DKMDT_VOT_LVDS = 6,
460 D3DKMDT_VOT_D_JPN = 8,
461 D3DKMDT_VOT_SDI = 9,
462 D3DKMDT_VOT_DISPLAYPORT_EXTERNAL = 10,
463 D3DKMDT_VOT_DISPLAYPORT_EMBEDDED = 11,
464 D3DKMDT_VOT_UDI_EXTERNAL = 12,
465 D3DKMDT_VOT_UDI_EMBEDDED = 13,
466 D3DKMDT_VOT_SDTVDONGLE = 14,
467 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3_M1)
468 D3DKMDT_VOT_MIRACAST = 15,
469 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_1)
470 D3DKMDT_VOT_INDIRECT_WIRED = 16,
471 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_1)
472 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3_M1)
473 D3DKMDT_VOT_INTERNAL = 0x80000000,
474
475 // Remove when DDI is unlocked.
476 D3DKMDT_VOT_SVIDEO_4PIN = D3DKMDT_VOT_SVIDEO,
477 D3DKMDT_VOT_SVIDEO_7PIN = D3DKMDT_VOT_SVIDEO,
478 D3DKMDT_VOT_RF = D3DKMDT_VOT_COMPOSITE_VIDEO,
479 D3DKMDT_VOT_RCA_3COMPONENT = D3DKMDT_VOT_COMPONENT_VIDEO,
480 D3DKMDT_VOT_BNC = D3DKMDT_VOT_COMPONENT_VIDEO,
481 }
482 D3DKMDT_VIDEO_OUTPUT_TECHNOLOGY;
483
484 typedef enum _DXGKMDT_OPM_CONNECTOR_TYPE
485 {
486 DXGKMDT_OPM_CONNECTOR_TYPE_OTHER = -1,
487 DXGKMDT_OPM_CONNECTOR_TYPE_HD15 = 0,
488 DXGKMDT_OPM_CONNECTOR_TYPE_SVIDEO = 1,
489 DXGKMDT_OPM_CONNECTOR_TYPE_COMPOSITE_VIDEO = 2,
490 DXGKMDT_OPM_CONNECTOR_TYPE_COMPONENT_VIDEO = 3,
491 DXGKMDT_OPM_CONNECTOR_TYPE_DVI = 4,
492 DXGKMDT_OPM_CONNECTOR_TYPE_HDMI = 5,
493 DXGKMDT_OPM_CONNECTOR_TYPE_LVDS = 6,
494 DXGKMDT_OPM_CONNECTOR_TYPE_D_JPN = 8,
495 DXGKMDT_OPM_CONNECTOR_TYPE_SDI = 9,
496 DXGKMDT_OPM_CONNECTOR_TYPE_DISPLAYPORT_EXTERNAL = 10,
497 DXGKMDT_OPM_CONNECTOR_TYPE_DISPLAYPORT_EMBEDDED = 11,
498 DXGKMDT_OPM_CONNECTOR_TYPE_UDI_EXTERNAL = 12,
499 DXGKMDT_OPM_CONNECTOR_TYPE_UDI_EMBEDDED = 13,
500 DXGKMDT_OPM_CONNECTOR_TYPE_RESERVED = 14,
501 DXGKMDT_OPM_CONNECTOR_TYPE_MIRACAST = 15,
502 DXGKMDT_OPM_CONNECTOR_TYPE_TRANSPORT_AGNOSTIC_DIGITAL_MODE_A = 16,
503 DXGKMDT_OPM_CONNECTOR_TYPE_TRANSPORT_AGNOSTIC_DIGITAL_MODE_B = 17,
504 DXGKMDT_OPM_COPP_COMPATIBLE_CONNECTOR_TYPE_INTERNAL = 0x80000000
505 } DXGKMDT_OPM_CONNECTOR_TYPE;
506
507 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
508 // Purpose: Monitor orientation awareness descriptor type.
509 //
510 typedef enum _D3DKMDT_MONITOR_ORIENTATION_AWARENESS
511 {
512 D3DKMDT_MOA_UNINITIALIZED = 0,
513 D3DKMDT_MOA_NONE = 1,
514 D3DKMDT_MOA_POLLED = 2,
515 D3DKMDT_MOA_INTERRUPTIBLE = 3
516 }
517 D3DKMDT_MONITOR_ORIENTATION_AWARENESS;
518
519
520 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
521 // Purpose: Video present target descriptor type.
522 //
523 typedef struct _D3DKMDT_VIDEO_PRESENT_TARGET
524 {
525 // Unique ID used to reference the respective video present target by the miniport and the OS.
526 D3DDDI_VIDEO_PRESENT_TARGET_ID Id;
527
528 // Type of the video output technology (see D3DKMDT_VIDEO_OUTPUT_TECHNOLOGY for more details).
529 D3DKMDT_VIDEO_OUTPUT_TECHNOLOGY VideoOutputTechnology;
530
531 // Type of the video output's HPD awareness (see D3DKMDT_VIDEO_OUTPUT_HPD_AWARENESS for more details).
532 DXGK_CHILD_DEVICE_HPD_AWARENESS VideoOutputHpdAwareness;
533
534 D3DKMDT_MONITOR_ORIENTATION_AWARENESS MonitorOrientationAwareness;
535
536 // NOTE: On monitor arrival, OS will leave monitor mode set empty for monitors connected to video outputs
537 // supporting SDTV modes, expecting miniport to populate modes it wants to expose for that monitor.
538 //
539 // NOTE: This predicate is also used when selecting video output for presentation on a TV via
540 // APIs that don't support explicit specification of monitors/video outputs (e.g. VIDEOPARAMETERS).
541 //
542 // Predicate specifying whether corresponding video output supports SDTV modes.
543 BOOLEAN SupportsSdtvModes;
544 }
545 D3DKMDT_VIDEO_PRESENT_TARGET;
546
547
548
549 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
550 // Purpose: Video present target mode GTF compliance descriptor type.
551 typedef enum _D3DKMDT_GTFCOMPLIANCE
552 {
553 D3DKMDT_GTF_UNINITIALIZED = 0,
554 D3DKMDT_GTF_COMPLIANT = 1,
555 D3DKMDT_GTF_NOTCOMPLIANT = 2
556 }
557 D3DKMDT_GTFCOMPLIANCE;
558
559
560 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
561 // Purpose: VidPN target mode preference descriptor type.
562
563 typedef enum _D3DKMDT_MODE_PREFERENCE
564 {
565 D3DKMDT_MP_UNINITIALIZED = 0,
566 D3DKMDT_MP_PREFERRED = 1,
567 D3DKMDT_MP_NOTPREFERRED = 2,
568 }
569 D3DKMDT_MODE_PREFERENCE;
570
571
572 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
573 // Purpose: Video signal info descriptor type.
574 //
575 // Remarks: Video signal info is the mode of operation of a given video output that's driving a connected
576 // moitor and is driven by an internal video output codec.
577 // Note that this descriptor supersedes subset of the XDDM's VIDEO_MODE_INFORMATION structure
578 // related to video mode. In XDDM, both video and rendering modes were described in this struct.
579 // LDDM separates these two notions, and hence their descriptors.
580 // The video standard field, vidStandard, should be used for video mode comparisons, when it's
581 // set to a well-defined video standard. Note that most of the standard modes do not comply with
582 // the VESA GTF frequency constraints.
583 //
584 // If color basis of the target mode does not correspond to that of the source mode, appropriate
585 // color conversion is performed by the respective video output codec.
586 //
587 typedef struct _D3DKMDT_VIDEO_SIGNAL_INFO
588 {
589 // Video mode standard this mode is defined by (if any).
590 D3DKMDT_VIDEO_SIGNAL_STANDARD VideoStandard;
591
592 // Video signal's size in pixels (i.e. HTotal & VTotal).
593 D3DKMDT_2DREGION TotalSize;
594
595 // Presented image's size in active pixels (i.e. HActive & VActive).
596 D3DKMDT_2DREGION ActiveSize;
597
598 // Vertical refresh frequency (in Hz).
599 D3DDDI_RATIONAL VSyncFreq;
600
601 // Horizontal refresh frequency (in Hz).
602 D3DDDI_RATIONAL HSyncFreq;
603
604 // Pixel clock rate (in Hz).
605 SIZE_T PixelRate;
606
607 union
608 {
609 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3_M1)
610 struct
611 {
612 // Scan line ordering (e.g. progressive, interlaced).
613 #ifdef __REACTOS__
614 UINT ScanLineOrdering : 3; // D3DDDI_VIDEO_SIGNAL_SCANLINE_ORDERING
615 #else
616 D3DDDI_VIDEO_SIGNAL_SCANLINE_ORDERING ScanLineOrdering : 3;
617 #endif
618
619 // Vertical refresh frequency divider
620 UINT VSyncFreqDivider : 6;
621
622 UINT Reserved : 23;
623
624 } AdditionalSignalInfo;
625 #endif // DXGKDDI_INTERFACE_VERSION_WDDM1_3_M1
626
627 // Scan line ordering (e.g. progressive, interlaced).
628 D3DDDI_VIDEO_SIGNAL_SCANLINE_ORDERING ScanLineOrdering;
629 };
630 }
631 D3DKMDT_VIDEO_SIGNAL_INFO;
632
633
634 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
635
636 #define D3DKMDT_BITS_PER_COMPONENT_06 0x01
637 #define D3DKMDT_BITS_PER_COMPONENT_08 0x02
638 #define D3DKMDT_BITS_PER_COMPONENT_10 0x04
639 #define D3DKMDT_BITS_PER_COMPONENT_12 0x08
640 #define D3DKMDT_BITS_PER_COMPONENT_14 0x10
641 #define D3DKMDT_BITS_PER_COMPONENT_16 0x20
642
643 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
644
645
646 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
647 // Purpose: Video present target mode ID type.
648 typedef UINT D3DKMDT_VIDEO_PRESENT_TARGET_MODE_ID;
649
650 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
651 // Purpose: Describe bit-fields for wire format and preference
652 // In the D3DKMDT_VIDPN_TARGET_MODE structure all fields are valid and the wire format fields indicate
653 // supported bit depts per color encoding format.
654 // In the DXGK_SET_TIMING_PATH_INFO structure the Preference field is unused so should be ignored by the
655 // driver and will be set to zero by the OS in case of future usage. The wire format fields are used to
656 // indicate which wire format has been selected so only one bit across the five fields will be set.
657 //
658
659 typedef union _D3DKMDT_WIRE_FORMAT_AND_PREFERENCE
660 {
661 struct
662 {
663 D3DKMDT_MODE_PREFERENCE Preference : 2;
664
665 // Flags indicating supported formats of color components transmitted between source and target
666 UINT Rgb : 6;
667 UINT YCbCr444 : 6;
668 UINT YCbCr422 : 6;
669 UINT YCbCr420 : 6;
670 UINT Intensity : 6;
671 };
672 UINT Value;
673 } D3DKMDT_WIRE_FORMAT_AND_PREFERENCE, *PD3DKMDT_WIRE_FORMAT_AND_PREFERENCE;
674
675
676 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
677 // Purpose: Video present target mode descriptor type.
678 typedef struct _D3DKMDT_VIDPN_TARGET_MODE
679 {
680 // Identifier unique within the set this mode is part of.
681 D3DKMDT_VIDEO_PRESENT_TARGET_MODE_ID Id;
682
683 // Video signal parameters.
684 D3DKMDT_VIDEO_SIGNAL_INFO VideoSignalInfo;
685
686 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
687 union
688 {
689 D3DKMDT_WIRE_FORMAT_AND_PREFERENCE WireFormatAndPreference;
690 struct
691 {
692 D3DKMDT_MODE_PREFERENCE Preference : 2;
693 UINT :30;
694 };
695 };
696 #else
697 // Predicate specifying whether this mode is preferred by the adapter given the mode pinned on
698 // the source of the respective present path.
699 D3DKMDT_MODE_PREFERENCE Preference;
700 #endif // (DXGKDDI_INTERFACE_VERSION < DXGKDDI_INTERFACE_VERSION_WDDM2_2)
701
702 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_9)
703
704 D3DDDI_RATIONAL MinimumVSyncFreq;
705
706 #endif // (DXGKDDI_INTERFACE_VERSION < DXGKDDI_INTERFACE_VERSION_WDDM2_9)
707
708 }
709 D3DKMDT_VIDPN_TARGET_MODE;
710
711 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
712 // Purpose: VESA Display ID detailed timing type I.
713
714 #pragma pack(push, 1)
715 #define DISPLAYID_DETAILED_TIMING_TYPE_I_SIZE 20
716
717 // Enum specifying monitor's aspect ratio (see DISPLAYID_DETAILED_TIMING_TYPE_I.AspectRatio)
718 enum _DISPLAYID_DETAILED_TIMING_TYPE_I_ASPECT_RATIO
719 {
720 DIDDT1_AspectRatio_1x1 = 0, // 000 = 1:1
721 DIDDT1_AspectRatio_5x4 = 1, // 001 = 5:4
722 DIDDT1_AspectRatio_4x3 = 2, // 010 = 4:3
723 DIDDT1_AspectRatio_15x9 = 3, // 011 = 15:9
724 DIDDT1_AspectRatio_16x9 = 4, // 100 = 16:9
725 DIDDT1_AspectRatio_16x10 = 5, // 101 = 16:10
726 };
727
728 enum _DISPLAYID_DETAILED_TIMING_TYPE_I_SCANNING_MODE
729 {
730 DIDDT1_Progressive = 0, // 0 = Progressive mode
731 DIDDT1_Interlaced = 1, // 1 = Interlaced mode
732 };
733
734 enum _DISPLAYID_DETAILED_TIMING_TYPE_I_STEREO_MODE
735 {
736 DIDDT1_Monoscopic = 0, // 00 = Monoscopic (no stereo) mode
737 DIDDT1_Stereo = 1, // 01 = Stereo mode
738 DIDDT1_Dependent = 2, // 10 = Stereo mode despends on user action
739 };
740
741 enum _DISPLAYID_DETAILED_TIMING_TYPE_I_SYNC_POLARITY
742 {
743 DIDDT1_Sync_Positive = 0,
744 DIDDT1_Sync_Negative = 1,
745 };
746
747 typedef struct _DISPLAYID_DETAILED_TIMING_TYPE_I
748 {
749 struct
750 {
751 ULONG PixelClock : 24; // Pixel clock / 10000
752 ULONG AspectRatio : 3; // Aspect ratio
753 ULONG Reserved : 1;
754 ULONG ScanningType : 1; // Frame scanning type
755 ULONG StereoMode : 2; // 3D stereo mode
756 ULONG PreferredTiming : 1; // preferred timing
757 };
758
759 USHORT HorizontalActivePixels; // Horizontal active image pixel number
760 USHORT HorizontalBlankPixels; // Horizontal blank pixel number
761 struct
762 {
763 USHORT HorizontalFrontPorch : 15; // Horizontal offset (front porch) pixel number
764 USHORT HorizontalSyncPolarity : 1; // Horizontal sync polarity
765 };
766 USHORT HorizontalSyncWidth; // Horizontal sync pixel number
767
768 USHORT VerticalActiveLines; // Number of lines of vertical active image
769 USHORT VerticalBlankLines; // Number of lines of vertical blank
770 struct
771 {
772 USHORT VerticalFrontPorch : 15; // Number of lines of vertical offset (front porch)
773 USHORT VerticalSyncPolarity : 1; // Vertical sync polarity
774 };
775 USHORT VerticalSyncWidth; // Number of lines of vertical sync
776 }DISPLAYID_DETAILED_TIMING_TYPE_I;
777
778 C_ASSERT(sizeof(DISPLAYID_DETAILED_TIMING_TYPE_I) == DISPLAYID_DETAILED_TIMING_TYPE_I_SIZE);
779
780 #pragma pack(pop)
781
782 typedef struct _DXGK_TARGETMODE_DETAIL_TIMING
783 {
784 // Video standard this detail timing comes from.
785 D3DKMDT_VIDEO_SIGNAL_STANDARD VideoStandard;
786
787 // ID of this detail timing in VideoStandard.
788 UINT TimingId;
789
790 // Detail timing.
791 DISPLAYID_DETAILED_TIMING_TYPE_I DetailTiming;
792 }DXGK_TARGETMODE_DETAIL_TIMING;
793
794
795 // Structure of hardware capability
796 typedef struct _D3DKMDT_VIDPN_HW_CAPABILITY
797 {
798 UINT DriverRotation : 1;
799 UINT DriverScaling : 1;
800 UINT DriverCloning : 1;
801 UINT DriverColorConvert : 1;
802 UINT DriverLinkedAdapaterOutput : 1;
803 UINT DriverRemoteDisplay : 1;
804 UINT Reserved : 26;
805 }
806 D3DKMDT_VIDPN_HW_CAPABILITY;
807
808
809 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
810 // Purpose: Video present target mode ID type.
811 typedef UINT D3DKMDT_MONITOR_SOURCE_MODE_ID;
812
813
814 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
815 // Purpose: Monitor capability origin type.
816 typedef enum _D3DKMDT_MONITOR_CAPABILITIES_ORIGIN
817 {
818 D3DKMDT_MCO_UNINITIALIZED = 0, // mode information is coming from the:
819 D3DKMDT_MCO_DEFAULTMONITORPROFILE = 1, // + default monitor profile.
820 D3DKMDT_MCO_MONITORDESCRIPTOR = 2, // + monitor's descriptor.
821 D3DKMDT_MCO_MONITORDESCRIPTOR_REGISTRYOVERRIDE = 3, // + registry override of the monitor descriptor.
822 D3DKMDT_MCO_SPECIFICCAP_REGISTRYOVERRIDE = 4, // + registry override of a specific capability.
823 D3DKMDT_MCO_DRIVER = 5, // + display adapter driver.
824 }
825 D3DKMDT_MONITOR_CAPABILITIES_ORIGIN;
826
827 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
828 // Purpose: Monitor timing type.
829 typedef enum _D3DKMDT_MONITOR_TIMING_TYPE
830 {
831 D3DKMDT_MTT_UNINITIALIZED = 0, // mode timing information is coming from:
832 D3DKMDT_MTT_ESTABLISHED = 1, // + established timings block.
833 D3DKMDT_MTT_STANDARD = 2, // + standard timings block.
834 D3DKMDT_MTT_EXTRASTANDARD = 3, // + extra standard timings block.
835 D3DKMDT_MTT_DETAILED = 4, // + detailed timings block.
836 D3DKMDT_MTT_DEFAULTMONITORPROFILE = 5, // + default monitor profile.
837 D3DKMDT_MTT_DRIVER = 6, // + display adapter driver.
838 }
839 D3DKMDT_MONITOR_TIMING_TYPE;
840
841 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
842 // Purpose: Video present target mode descriptor type.
843 typedef struct _D3DKMDT_MONITOR_SOURCE_MODE
844 {
845 // Identifier unique within the set this mode is part of.
846 D3DKMDT_MONITOR_SOURCE_MODE_ID Id;
847
848 // Video signal parameters.
849 D3DKMDT_VIDEO_SIGNAL_INFO VideoSignalInfo;
850
851 // Color basis with respect to which monitor is presenting the pixels sampled from the video signal.
852 D3DKMDT_COLOR_BASIS ColorBasis;
853
854 // Supported dynamic range of each of the pixel color component coefficients by the monitor's
855 // presentational technology - e.g. for a DFP LCD with 12-bit bit-depth, this will be (4, 4, 4, 0).
856 // A TV supporting 10-bit per component YCbCr this will be (10, 10, 10, 0) regardless of chroma compression.
857 D3DKMDT_COLOR_COEFF_DYNAMIC_RANGES ColorCoeffDynamicRanges;
858
859 // Origins of the monitor source mode information.
860 D3DKMDT_MONITOR_CAPABILITIES_ORIGIN Origin;
861
862 // Predicate specifying whether this mode is preferred by the monitor connected to the respective video output.
863 D3DKMDT_MODE_PREFERENCE Preference;
864 }
865 D3DKMDT_MONITOR_SOURCE_MODE;
866
867
868 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
869 // Purpose: Frequency range type.
870 typedef struct _D3DKMDT_FREQUENCY_RANGE
871 {
872 // Minimum vertical refresh frequency (in Hz) supported by the monitor.
873 D3DDDI_RATIONAL MinVSyncFreq;
874
875 // Maximum vertical refresh frequency (in Hz) supported by the monitor.
876 D3DDDI_RATIONAL MaxVSyncFreq;
877
878 // Minimum horizontal refresh frequency (in Hz) supported by the monitor.
879 D3DDDI_RATIONAL MinHSyncFreq;
880
881 // Maximum horizontal refresh frequency (in Hz) supported by the monitor.
882 D3DDDI_RATIONAL MaxHSyncFreq;
883 }
884 D3DKMDT_FREQUENCY_RANGE;
885
886
887 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
888 // Purpose: Monitor frequency range constraint type.
889 typedef enum _D3DKMDT_MONITOR_FREQUENCY_RANGE_CONSTRAINT
890 {
891 D3DKMDT_MFRC_UNINITIALIZED = 0,
892 D3DKMDT_MFRC_ACTIVESIZE = 1,
893 D3DKMDT_MFRC_MAXPIXELRATE = 2
894 }
895 D3DKMDT_MONITOR_FREQUENCY_RANGE_CONSTRAINT;
896
897
898 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
899 // Purpose: Monitor frequency range type.
900 typedef struct _D3DKMDT_MONITOR_FREQUENCY_RANGE
901 {
902 // Origins of the monitor frequency range information.
903 D3DKMDT_MONITOR_CAPABILITIES_ORIGIN Origin;
904
905 // Frequency range limits.
906 D3DKMDT_FREQUENCY_RANGE RangeLimits;
907
908 // Type of the frequency range constraint.
909 D3DKMDT_MONITOR_FREQUENCY_RANGE_CONSTRAINT ConstraintType;
910
911 // Constraint under which this frequency range is supported.
912 union
913 {
914 // Active region size this frequency range applies to.
915 D3DKMDT_2DREGION ActiveSize;
916
917 // Maximum pixel clock rate (in Hz) to which this pixel rate applies.
918 SIZE_T MaxPixelRate;
919
920 } Constraint;
921 }
922 D3DKMDT_MONITOR_FREQUENCY_RANGE;
923
924
925
926
927 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
928 // VidPN present paths
929
930 // VidPN present path index used during enumeration of paths satisfying certain criteria
931 // (e.g. originating from the same source).
932 typedef SIZE_T D3DKMDT_VIDPN_PRESENT_PATH_INDEX;
933
934 // Purpose: VidPN present path scaling type.
935 typedef enum _D3DKMDT_VIDPN_PRESENT_PATH_SCALING
936 {
937 D3DKMDT_VPPS_UNINITIALIZED = 0,
938
939 // For the following transformation, spatial resolutions must be equal on both the source and the target.
940
941 // Source content is not modified in any way.
942 D3DKMDT_VPPS_IDENTITY = 1,
943
944 // For the following three transformations, spatial resolution of the source differs from that of the target.
945
946 // Source content is centered on the target.
947 D3DKMDT_VPPS_CENTERED = 2,
948
949 // Source content is scaled to fit the target, no aspect ratio preserving.
950 D3DKMDT_VPPS_STRETCHED = 3,
951
952 // Source content is scaled to fit the target. Aspect ratio preserving.
953 D3DKMDT_VPPS_ASPECTRATIOCENTEREDMAX = 4,
954
955 // Scaling that cannot be described by any other D3DKMDT_VPPS_XXX value
956 D3DKMDT_VPPS_CUSTOM = 5,
957
958
959 // Reserved for internal OS use
960 D3DKMDT_VPPS_RESERVED1 = 253,
961
962 // Source content scaling mode is not pinned.
963 D3DKMDT_VPPS_UNPINNED = 254,
964
965 // OS does not specify the scaling mode, and miniport should decide based on its own settings.
966 D3DKMDT_VPPS_NOTSPECIFIED = 255
967 }
968 D3DKMDT_VIDPN_PRESENT_PATH_SCALING;
969
970
971 // Purpose: VidPN present path rotation type.
972 typedef enum _D3DKMDT_VIDPN_PRESENT_PATH_ROTATION
973 {
974 D3DKMDT_VPPR_UNINITIALIZED = 0,
975
976 // Source content is not modified in any way.
977 D3DKMDT_VPPR_IDENTITY = 1,
978
979 // Source content is rotated 90 degrees.
980 D3DKMDT_VPPR_ROTATE90 = 2,
981
982 // Source content is rotated 180 degrees.
983 D3DKMDT_VPPR_ROTATE180 = 3,
984
985 // Source content is rotated 270 degrees.
986 D3DKMDT_VPPR_ROTATE270 = 4,
987
988 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3_PATH_INDEPENDENT_ROTATION)
989 // Source content is not modified in any way. Driver should rotate this content an extra 90 degrees.
990 D3DKMDT_VPPR_IDENTITY_OFFSET90 = 5,
991
992 // Source content is rotated 90 degrees. Driver should rotate this content an extra 90 degrees.
993 D3DKMDT_VPPR_ROTATE90_OFFSET90 = 6,
994
995 // Source content is rotated 180 degrees. Driver should rotate this content an extra 90 degrees.
996 D3DKMDT_VPPR_ROTATE180_OFFSET90 = 7,
997
998 // Source content is rotated 270 degrees. Driver should rotate this content an extra 90 degrees.
999 D3DKMDT_VPPR_ROTATE270_OFFSET90 = 8,
1000
1001 // Source content is not modified in any way. Driver should rotate this content an extra 180 degrees.
1002 D3DKMDT_VPPR_IDENTITY_OFFSET180 = 9,
1003
1004 // Source content is rotated 90 degrees. Driver should rotate this content an extra 180 degrees.
1005 D3DKMDT_VPPR_ROTATE90_OFFSET180 = 10,
1006
1007 // Source content is rotated 180 degrees. Driver should rotate this content an extra 180 degrees.
1008 D3DKMDT_VPPR_ROTATE180_OFFSET180 = 11,
1009
1010 // Source content is rotated 270 degrees. Driver should rotate this content an extra 180 degrees.
1011 D3DKMDT_VPPR_ROTATE270_OFFSET180 = 12,
1012
1013 // Source content is not modified in any way. Driver should rotate this content an extra 270 degrees.
1014 D3DKMDT_VPPR_IDENTITY_OFFSET270 = 13,
1015
1016 // Source content is rotated 90 degrees. Driver should rotate this content an extra 270 degrees.
1017 D3DKMDT_VPPR_ROTATE90_OFFSET270 = 14,
1018
1019 // Source content is rotated 180 degrees. Driver should rotate this content an extra 270 degrees.
1020 D3DKMDT_VPPR_ROTATE180_OFFSET270 = 15,
1021
1022 // Source content is rotated 270 degrees. Driver should rotate this content an extra 270 degrees.
1023 D3DKMDT_VPPR_ROTATE270_OFFSET270 = 16,
1024 #endif // DXGKDDI_INTERFACE_VERSION
1025
1026 // Source content rotation setting is not pinned.
1027 D3DKMDT_VPPR_UNPINNED = 254,
1028
1029 // OS does not specify the rotation mode, and miniport should decide based on its own settings.
1030 D3DKMDT_VPPR_NOTSPECIFIED = 255
1031 }
1032 D3DKMDT_VIDPN_PRESENT_PATH_ROTATION;
1033
1034 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3_PATH_INDEPENDENT_ROTATION)
1035
1036 __inline
D3DKMDT_VPPR_GET_OFFSET_ROTATION(D3DKMDT_VIDPN_PRESENT_PATH_ROTATION Rotation)1037 D3DKMDT_VIDPN_PRESENT_PATH_ROTATION D3DKMDT_VPPR_GET_OFFSET_ROTATION(D3DKMDT_VIDPN_PRESENT_PATH_ROTATION Rotation)
1038 {
1039 if ((Rotation >= D3DKMDT_VPPR_IDENTITY) &&
1040 (Rotation <= D3DKMDT_VPPR_ROTATE270_OFFSET270))
1041 {
1042 Rotation = (D3DKMDT_VIDPN_PRESENT_PATH_ROTATION)(((Rotation - 1) / 4) + 1);
1043 }
1044 return Rotation;
1045 }
1046
1047 __inline
D3DKMDT_VPPR_GET_CONTENT_ROTATION_PART(D3DKMDT_VIDPN_PRESENT_PATH_ROTATION Rotation)1048 D3DKMDT_VIDPN_PRESENT_PATH_ROTATION D3DKMDT_VPPR_GET_CONTENT_ROTATION_PART(D3DKMDT_VIDPN_PRESENT_PATH_ROTATION Rotation)
1049 {
1050 if ((Rotation >= D3DKMDT_VPPR_IDENTITY_OFFSET90) &&
1051 (Rotation <= D3DKMDT_VPPR_ROTATE270_OFFSET270))
1052 {
1053 Rotation = (D3DKMDT_VIDPN_PRESENT_PATH_ROTATION)(((Rotation - 1) % 4) + 1);
1054 }
1055 return Rotation;
1056 }
1057
1058 __inline
D3DKMDT_VPPR_GET_CONTENT_ROTATION(D3DKMDT_VIDPN_PRESENT_PATH_ROTATION Rotation)1059 D3DKMDT_VIDPN_PRESENT_PATH_ROTATION D3DKMDT_VPPR_GET_CONTENT_ROTATION(D3DKMDT_VIDPN_PRESENT_PATH_ROTATION Rotation)
1060 {
1061 if ((Rotation >= D3DKMDT_VPPR_IDENTITY_OFFSET90) &&
1062 (Rotation <= D3DKMDT_VPPR_ROTATE270_OFFSET270))
1063 {
1064 D3DKMDT_VIDPN_PRESENT_PATH_ROTATION ContentPart = D3DKMDT_VPPR_GET_CONTENT_ROTATION_PART(Rotation);
1065 D3DKMDT_VIDPN_PRESENT_PATH_ROTATION OffsetPart = D3DKMDT_VPPR_GET_OFFSET_ROTATION(Rotation);
1066 Rotation = (D3DKMDT_VIDPN_PRESENT_PATH_ROTATION)((((ContentPart - 1) + (OffsetPart - 1)) % 4) + 1);
1067 }
1068 return Rotation;
1069 }
1070 #endif // DXGKDDI_INTERFACE_VERSION
1071
1072
1073 #define D3DKMDT_SCALING_SUPPORT_MASK 0x1f;
1074
1075 // Purpose: Specifies what scaling modes are supported given current path configuration.
1076 typedef struct _D3DKMDT_VIDPN_PRESENT_PATH_SCALING_SUPPORT
1077 {
1078 UINT Identity : 1;
1079 UINT Centered : 1;
1080 UINT Stretched : 1;
1081 UINT AspectRatioCenteredMax : 1;
1082 UINT Custom : 1;
1083 } D3DKMDT_VIDPN_PRESENT_PATH_SCALING_SUPPORT;
1084
1085 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3_PATH_INDEPENDENT_ROTATION)
1086 #define D3DKMDT_ROTATION_SUPPORT_MASK 0xff;
1087 #else
1088 #define D3DKMDT_ROTATION_SUPPORT_MASK 0xf;
1089 #endif // DXGKDDI_INTERFACE_VERSION
1090
1091 // Purpose: Specifies what rotation modes are supported given current path configuration.
1092 typedef struct _D3DKMDT_VIDPN_PRESENT_PATH_ROTATION_SUPPORT
1093 {
1094 UINT Identity : 1;
1095 UINT Rotate90 : 1;
1096 UINT Rotate180 : 1;
1097 UINT Rotate270 : 1;
1098 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3_PATH_INDEPENDENT_ROTATION)
1099 UINT Offset0 : 1;
1100 UINT Offset90 : 1;
1101 UINT Offset180 : 1;
1102 UINT Offset270 : 1;
1103 #endif // DXGKDDI_INTERFACE_VERSION
1104 } D3DKMDT_VIDPN_PRESENT_PATH_ROTATION_SUPPORT;
1105
1106 // Purpose: Combines all the transformation related fields into one structure.
1107 typedef struct _D3DKMDT_VIDPN_PRESENT_PATH_TRANSFORMATION
1108 {
1109 // Scaling applied to the content presented on this video present path.
1110 D3DKMDT_VIDPN_PRESENT_PATH_SCALING Scaling;
1111
1112 // Scaling support given the currently pinned modes.
1113 D3DKMDT_VIDPN_PRESENT_PATH_SCALING_SUPPORT ScalingSupport;
1114
1115 // Rotation applied to the content presented on this video present path.
1116 D3DKMDT_VIDPN_PRESENT_PATH_ROTATION Rotation;
1117
1118 // Rotation support given the currently pinned modes.
1119 D3DKMDT_VIDPN_PRESENT_PATH_ROTATION_SUPPORT RotationSupport;
1120 } D3DKMDT_VIDPN_PRESENT_PATH_TRANSFORMATION;
1121
1122 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
1123 // Purpose: VidPN present path importance ordinal type.
1124 //
1125 // Note: Higher order importance ordinals can be used (upto 255), but only the first 10 have been explicitly named.
1126 //
1127 typedef enum _D3DKMDT_VIDPN_PRESENT_PATH_IMPORTANCE
1128 {
1129 D3DKMDT_VPPI_UNINITIALIZED = 0,
1130 D3DKMDT_VPPI_PRIMARY = 1,
1131 D3DKMDT_VPPI_SECONDARY = 2,
1132 D3DKMDT_VPPI_TERTIARY = 3,
1133 D3DKMDT_VPPI_QUATERNARY = 4,
1134 D3DKMDT_VPPI_QUINARY = 5,
1135 D3DKMDT_VPPI_SENARY = 6,
1136 D3DKMDT_VPPI_SEPTENARY = 7,
1137 D3DKMDT_VPPI_OCTONARY = 8,
1138 D3DKMDT_VPPI_NONARY = 9,
1139 D3DKMDT_VPPI_DENARY = 10,
1140 }
1141 D3DKMDT_VIDPN_PRESENT_PATH_IMPORTANCE;
1142
1143 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
1144 // Purpose: VidPN present path content ordinal type.
1145 //
1146 // Indicates whether the content being displayed is video or graphics.
1147 //
1148 typedef enum _D3DKMDT_VIDPN_PRESENT_PATH_CONTENT
1149 {
1150 D3DKMDT_VPPC_UNINITIALIZED = 0,
1151
1152 // Miniport should optimize presentation of the present path for graphics content.
1153 D3DKMDT_VPPC_GRAPHICS = 1,
1154
1155 // Miniport should optimize presentation of the present path for video content.
1156 D3DKMDT_VPPC_VIDEO = 2,
1157
1158 // OS does not specify the content type, and miniport should decide based on its own settings.
1159 D3DKMDT_VPPC_NOTSPECIFIED = 255
1160 }
1161 D3DKMDT_VIDPN_PRESENT_PATH_CONTENT;
1162
1163 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
1164 // Purpose: VidPN present path macrovision information.
1165 //
1166 // Contains macrovision caps and controls.
1167 //
1168 typedef enum _D3DKMDT_VIDPN_PRESENT_PATH_COPYPROTECTION_TYPE
1169 {
1170 D3DKMDT_VPPMT_UNINITIALIZED = 0,
1171
1172 D3DKMDT_VPPMT_NOPROTECTION = 1,
1173
1174 D3DKMDT_VPPMT_MACROVISION_APSTRIGGER = 2,
1175
1176 D3DKMDT_VPPMT_MACROVISION_FULLSUPPORT = 3,
1177
1178 }
1179 D3DKMDT_VIDPN_PRESENT_PATH_COPYPROTECTION_TYPE;
1180
1181 typedef struct _D3DKMDT_VIDPN_PRESENT_PATH_COPYPROTECTION_SUPPORT
1182 {
1183 UINT NoProtection : 1;
1184 UINT MacroVisionApsTrigger : 1;
1185 UINT MacroVisionFull : 1;
1186 UINT Reserved : 29;
1187 }
1188 D3DKMDT_VIDPN_PRESENT_PATH_COPYPROTECTION_SUPPORT;
1189
1190 #define D3DKMDT_MACROVISION_OEMCOPYPROTECTION_SIZE 256
1191
1192 typedef struct _D3DKMDT_VIDPN_PRESENT_PATH_COPYPROTECTION
1193 {
1194 // Macrovision controls.
1195 D3DKMDT_VIDPN_PRESENT_PATH_COPYPROTECTION_TYPE CopyProtectionType;
1196 UINT APSTriggerBits;
1197 BYTE OEMCopyProtection[D3DKMDT_MACROVISION_OEMCOPYPROTECTION_SIZE];
1198
1199 // Level of available copy protection support.
1200 D3DKMDT_VIDPN_PRESENT_PATH_COPYPROTECTION_SUPPORT CopyProtectionSupport;
1201 } D3DKMDT_VIDPN_PRESENT_PATH_COPYPROTECTION;
1202
1203 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
1204 // Purpose: VidPN present path gamma ramp descriptor type.
1205 //
1206 typedef struct _D3DKMDT_GAMMA_RAMP
1207 {
1208 D3DDDI_GAMMARAMP_TYPE Type;
1209 SIZE_T DataSize;
1210
1211 // If (Type == D3DDDI_GAMMARAMP_DEFAULT), (DataSize == 0) and (Data.pRaw == NULL )
1212 union
1213 {
1214 D3DDDI_GAMMA_RAMP_RGB256x3x16* pRgb256x3x16; // Type == D3DDDI_GAMMARAMP_RGB256x3x16.
1215 D3DDDI_GAMMA_RAMP_DXGI_1* pDxgi1; // Type == D3DDDI_GAMMARAMP_DXGI_1.
1216 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_3)
1217 D3DKMDT_3x4_COLORSPACE_TRANSFORM* p3x4; // Type == D3DDDI_GAMMARAMP_MATRIX_3x4.
1218 #endif // DXGKDDI_INTERFACE_VERSION_WDDM2_3
1219 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_6)
1220 D3DKMDT_COLORSPACE_TRANSFORM_MATRIX_V2* pMatrixV2; // Type == D3DDDI_GAMMARAMP_MATRIX_V2.
1221 #endif // DXGKDDI_INTERFACE_VERSION_WDDM2_6
1222 VOID* pRaw;
1223 }
1224 Data;
1225 }
1226 D3DKMDT_GAMMA_RAMP;
1227
1228
1229 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
1230 // Purpose: Video present target to source mapping.
1231 //
1232 // Remarks: This type is used to describe a mapping from a single video present target to a single
1233 // video present source in a VidPN topology.
1234 //
1235 typedef struct _D3DKMDT_VIDPN_PRESENT_PATH
1236 {
1237 D3DDDI_VIDEO_PRESENT_SOURCE_ID VidPnSourceId;
1238
1239 D3DDDI_VIDEO_PRESENT_TARGET_ID VidPnTargetId;
1240
1241 // Video present path importance ordinal (e.g. path presenting the primary view may have higher
1242 // importance set on it in order to guarantee that it gets the best source/target mode sets).
1243 D3DKMDT_VIDPN_PRESENT_PATH_IMPORTANCE ImportanceOrdinal;
1244
1245 // Contains all the transformation related fields.
1246 D3DKMDT_VIDPN_PRESENT_PATH_TRANSFORMATION ContentTransformation;
1247
1248 // Storing deltas for visible/active pixels mapping rather than visible pixels'
1249 // size & offset has the added benefit of ideal/default state being zeros.
1250
1251 // Monitor screen's offset of visible pixels' top-left corner from
1252 // video signal's active pixels top-left corner.
1253 // Note: Default = (0,0).
1254 D3DKMDT_2DOFFSET VisibleFromActiveTLOffset;
1255
1256 // Monitor screen's offset of visible pixels' bottom-right corner from
1257 // video signal's active pixels bottom-right corner.
1258 // Note: Default = (0,0).
1259 D3DKMDT_2DOFFSET VisibleFromActiveBROffset;
1260
1261 // Video signal color basis with respect to which video output codec encodes the pixels from the respective
1262 // source's primary surface (e.g. on HDMI this can be either RGB or YCbCr).
1263 D3DKMDT_COLOR_BASIS VidPnTargetColorBasis;
1264
1265 // Supported dynamic range of each of the color bases' coefficients by the video output codec's output
1266 // E.g. With a DAC scaning out A2R10G10B10 primary surface at R8G8B8 color resolution, this would be (8,8,8,0),
1267 D3DKMDT_COLOR_COEFF_DYNAMIC_RANGES VidPnTargetColorCoeffDynamicRanges;
1268
1269 // Indicates the content being diplayed. The driver can use this to determine whether the flicker filter
1270 // and overscan should be enabled or disabled.
1271 D3DKMDT_VIDPN_PRESENT_PATH_CONTENT Content;
1272
1273 // Contains all the copy protection related fields.
1274 D3DKMDT_VIDPN_PRESENT_PATH_COPYPROTECTION CopyProtection;
1275
1276 // A lookup table (LUT) used to compensate intensity of presented content for the color response of the monitor
1277 // connected to present path's target.
1278 D3DKMDT_GAMMA_RAMP GammaRamp;
1279 }
1280 D3DKMDT_VIDPN_PRESENT_PATH;
1281
1282
1283 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
1284 // Purpose: Specifies whether to ignore monitor connectivity checks or enforce them.
1285 //
1286 typedef enum _D3DKMDT_MONITOR_CONNECTIVITY_CHECKS
1287 {
1288 D3DKMDT_MCC_UNINITIALIZED = 0,
1289 D3DKMDT_MCC_IGNORE = 1,
1290 D3DKMDT_MCC_ENFORCE = 2
1291 }
1292 D3DKMDT_MONITOR_CONNECTIVITY_CHECKS;
1293
1294
1295 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
1296 // Purpose: Type of the owner whose mode set does not change during an enumeration.
1297 //
1298 // Remarks: When OS pins/unpins a mode in one of VidPN's mode sets, the only mode set that is guaranteed to
1299 // stay the same is the mode set whose mode was pinned/unpinned. Enumeration pivot lets the OS
1300 // specify to the miniport which mode set it should not update (because this mode set could not have
1301 // been invalidated as a result of the change the OS made to the VidPN.
1302 //
1303 typedef enum _D3DKMDT_ENUMCOFUNCMODALITY_PIVOT_TYPE
1304 {
1305 D3DKMDT_EPT_UNINITIALIZED,
1306 D3DKMDT_EPT_VIDPNSOURCE,
1307 D3DKMDT_EPT_VIDPNTARGET,
1308 D3DKMDT_EPT_SCALING,
1309 D3DKMDT_EPT_ROTATION,
1310 D3DKMDT_EPT_NOPIVOT
1311 }
1312 D3DKMDT_ENUMCOFUNCMODALITY_PIVOT_TYPE;
1313
1314 //
1315 // Monitor descriptor related types.
1316 //
1317
1318 typedef UINT D3DKMDT_MONITOR_DESCRIPTOR_ID;
1319
1320 typedef enum _D3DKMDT_MONITOR_DESCRIPTOR_TYPE
1321 {
1322 D3DKMDT_MDT_UNINITIALIZED = 0,
1323 D3DKMDT_MDT_VESA_EDID_V1_BASEBLOCK = 1,
1324 D3DKMDT_MDT_VESA_EDID_V1_BLOCKMAP = 2,
1325 D3DKMDT_MDT_OTHER = 255
1326 }
1327 D3DKMDT_MONITOR_DESCRIPTOR_TYPE;
1328
1329 typedef struct _D3DKMDT_MONITOR_DESCRIPTOR
1330 {
1331 D3DKMDT_MONITOR_DESCRIPTOR_ID Id;
1332 D3DKMDT_MONITOR_DESCRIPTOR_TYPE Type;
1333 SIZE_T DataSize;
1334 VOID* pData;
1335 D3DKMDT_MONITOR_CAPABILITIES_ORIGIN Origin;
1336 }
1337 D3DKMDT_MONITOR_DESCRIPTOR;
1338
1339
1340 typedef enum _D3DKMDT_STANDARDALLOCATION_TYPE
1341 {
1342 D3DKMDT_STANDARDALLOCATION_SHAREDPRIMARYSURFACE = 1,
1343 D3DKMDT_STANDARDALLOCATION_SHADOWSURFACE = 2,
1344 D3DKMDT_STANDARDALLOCATION_STAGINGSURFACE = 3,
1345 D3DKMDT_STANDARDALLOCATION_GDISURFACE = 4,
1346 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_1)
1347 D3DKMDT_STANDARDALLOCATION_VGPU = 5,
1348 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_1)
1349 } D3DKMDT_STANDARDALLOCATION_TYPE;
1350
1351 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WIN8)
1352 typedef enum _D3DKMDT_GRAPHICS_PREEMPTION_GRANULARITY
1353 {
1354 D3DKMDT_GRAPHICS_PREEMPTION_NONE = 0,
1355 D3DKMDT_GRAPHICS_PREEMPTION_DMA_BUFFER_BOUNDARY = 100,
1356 D3DKMDT_GRAPHICS_PREEMPTION_PRIMITIVE_BOUNDARY = 200,
1357 D3DKMDT_GRAPHICS_PREEMPTION_TRIANGLE_BOUNDARY = 300,
1358 D3DKMDT_GRAPHICS_PREEMPTION_PIXEL_BOUNDARY = 400,
1359 D3DKMDT_GRAPHICS_PREEMPTION_SHADER_BOUNDARY = 500,
1360 } D3DKMDT_GRAPHICS_PREEMPTION_GRANULARITY;
1361
1362 typedef enum _D3DKMDT_COMPUTE_PREEMPTION_GRANULARITY
1363 {
1364 D3DKMDT_COMPUTE_PREEMPTION_NONE = 0,
1365 D3DKMDT_COMPUTE_PREEMPTION_DMA_BUFFER_BOUNDARY = 100,
1366 D3DKMDT_COMPUTE_PREEMPTION_DISPATCH_BOUNDARY = 200,
1367 D3DKMDT_COMPUTE_PREEMPTION_THREAD_GROUP_BOUNDARY = 300,
1368 D3DKMDT_COMPUTE_PREEMPTION_THREAD_BOUNDARY = 400,
1369 D3DKMDT_COMPUTE_PREEMPTION_SHADER_BOUNDARY = 500,
1370 } D3DKMDT_COMPUTE_PREEMPTION_GRANULARITY;
1371
1372 typedef struct _D3DKMDT_PREEMPTION_CAPS
1373 {
1374 D3DKMDT_GRAPHICS_PREEMPTION_GRANULARITY GraphicsPreemptionGranularity;
1375 D3DKMDT_COMPUTE_PREEMPTION_GRANULARITY ComputePreemptionGranularity;
1376 } D3DKMDT_PREEMPTION_CAPS;
1377
1378 typedef struct _D3DKMT_WDDM_1_2_CAPS
1379 {
1380 D3DKMDT_PREEMPTION_CAPS PreemptionCaps;
1381 union
1382 {
1383 struct
1384 {
1385 UINT SupportNonVGA : 1;
1386 UINT SupportSmoothRotation : 1;
1387 UINT SupportPerEngineTDR : 1;
1388 UINT SupportKernelModeCommandBuffer : 1;
1389 UINT SupportCCD : 1;
1390 UINT SupportSoftwareDeviceBitmaps : 1;
1391 UINT SupportGammaRamp : 1;
1392 UINT SupportHWCursor : 1;
1393 UINT SupportHWVSync : 1;
1394 UINT SupportSurpriseRemovalInHibernation : 1;
1395 UINT Reserved : 22;
1396 };
1397 UINT Value;
1398 };
1399 } D3DKMT_WDDM_1_2_CAPS;
1400
1401
1402 #endif // DXGKDDI_INTERFACE_VERSION
1403
1404 typedef struct _D3DKMDT_SHAREDPRIMARYSURFACEDATA
1405 {
1406 UINT Width;
1407 UINT Height;
1408 D3DDDIFORMAT Format;
1409 D3DDDI_RATIONAL RefreshRate;
1410 D3DDDI_VIDEO_PRESENT_SOURCE_ID VidPnSourceId;
1411 } D3DKMDT_SHAREDPRIMARYSURFACEDATA;
1412
1413 typedef struct _D3DKMDT_SHADOWSURFACEDATA
1414 {
1415 UINT Width;
1416 UINT Height;
1417 D3DDDIFORMAT Format;
1418 UINT Pitch; //out: Driver must return Pitch as this allocation will be lockabale
1419 } D3DKMDT_SHADOWSURFACEDATA;
1420
1421 //Staging Surface is a surface created potentially
1422 //during present when a direct Blt to primary is
1423 //not possible in cases like multimon or sprites.
1424 //This surface is always in the format of D3DDDIFMT_X8R8G8B8
1425
1426 typedef struct _D3DKMDT_STAGINGSURFACEDATA
1427 {
1428 UINT Width; //in: Width of the staging buffer
1429 UINT Height; //in: Height of the staging buffer
1430 UINT Pitch; //out: Driver must return Pitch as this allocation will be lockabale
1431 } D3DKMDT_STAGINGSURFACEDATA;
1432
1433 typedef struct _D3DKMDT_GDISURFACEFLAGS
1434 {
1435 union
1436 {
1437 struct
1438 {
1439 UINT Reserved : 32;
1440 };
1441 UINT Value;
1442 };
1443 } D3DKMDT_GDISURFACEFLAGS;
1444
1445 typedef enum _D3DKMDT_GDISURFACETYPE
1446 {
1447 D3DKMDT_GDISURFACE_INVALID = 0,
1448 D3DKMDT_GDISURFACE_TEXTURE = 1,
1449 D3DKMDT_GDISURFACE_STAGING_CPUVISIBLE = 2,
1450 D3DKMDT_GDISURFACE_STAGING = 3,
1451 D3DKMDT_GDISURFACE_LOOKUPTABLE = 4,
1452 D3DKMDT_GDISURFACE_EXISTINGSYSMEM = 5,
1453 D3DKMDT_GDISURFACE_TEXTURE_CPUVISIBLE = 6,
1454 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3_M1)
1455 D3DKMDT_GDISURFACE_TEXTURE_CROSSADAPTER = 7,
1456 D3DKMDT_GDISURFACE_TEXTURE_CPUVISIBLE_CROSSADAPTER = 8, // Reserved for OS
1457 #endif // DXGKDDI_INTERFACE_VERSION
1458 } D3DKMDT_GDISURFACETYPE;
1459
1460 typedef struct _D3DKMDT_GDISURFACEDATA
1461 {
1462 UINT Width;
1463 UINT Height;
1464 D3DDDIFORMAT Format;
1465 D3DKMDT_GDISURFACETYPE Type;
1466 D3DKMDT_GDISURFACEFLAGS Flags;
1467 UINT Pitch; // out: The driver must return pitch if allocation is CPU visible
1468 } D3DKMDT_GDISURFACEDATA;
1469
1470 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_1)
1471
1472 typedef struct _D3DKMDT_VIRTUALGPUSURFACEDATA
1473 {
1474 UINT64 Size;
1475 UINT Alignment;
1476 UINT DriverSegmentId;
1477 UINT PrivateDriverData;
1478 } D3DKMDT_VIRTUALGPUSURFACEDATA;
1479
1480 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_1)
1481
1482 typedef struct _D3DKMDT_PALETTEDATA
1483 {
1484 BYTE Red;
1485 BYTE Green;
1486 BYTE Blue;
1487 BYTE Unused;
1488 } D3DKMDT_PALETTEDATA;
1489
1490 //
1491 //Red - Bits to be put in the Red portion of the color registers.
1492 //
1493 //Green - Bits to be put in the Green portion of the color registers.
1494 //
1495 //Blue - Bits to be put in the Blue portion of the color registers.
1496 //
1497
1498 typedef struct _DXGKARG_SETPALETTE
1499 {
1500 D3DDDI_VIDEO_PRESENT_SOURCE_ID VidPnSourceId;
1501 UINT FirstEntry;
1502 UINT NumEntries;
1503 D3DKMDT_PALETTEDATA* pLookupTable;
1504 } DXGKARG_SETPALETTE;
1505
1506 //
1507 //NumEntries - Number of entries in the LookupTable of color values.
1508 //
1509 //FirstEntry - Location in the device palette to which the first entry in the
1510 // LookupTable of colors should be copied to. The other entries in the
1511 // LookupTable should be copied sequentially, from this starting point into
1512 // the device's palette.
1513 //
1514 //pLookupTable - Array of color entries to copy into the device's color
1515 // registers/palette. The color entries can be accessed as a genric 32 bit
1516 // value or as Red/Green/Blue/Unused fields.
1517 //
1518
1519 typedef struct _D3DKMT_MOVE_RECT
1520 {
1521 POINT SourcePoint;
1522 RECT DestRect;
1523 }D3DKMT_MOVE_RECT;
1524
1525 //
1526 // Display information structure.
1527 //
1528
1529 #ifndef PHYSICAL_ADDRESS
1530 typedef LARGE_INTEGER PHYSICAL_ADDRESS;
1531 #endif
1532
1533 typedef struct _DXGK_DISPLAY_INFORMATION
1534 {
1535 UINT Width;
1536 UINT Height;
1537 UINT Pitch;
1538 D3DDDIFORMAT ColorFormat;
1539 PHYSICAL_ADDRESS PhysicAddress;
1540 D3DDDI_VIDEO_PRESENT_TARGET_ID TargetId;
1541 ULONG AcpiId;
1542 } DXGK_DISPLAY_INFORMATION, *PDXGK_DISPLAY_INFORMATION;
1543
1544
1545 //////////////////// I2C ////////////////////////////////////////////////////////////////////////////////////
1546
1547 #define DXGKMDT_I2C_NO_FLAGS 0
1548 #define DXGKMDT_I2C_DEVICE_TRANSMITS_DATA_LENGTH 1
1549
1550 //////////////////// OPM (Output Protection Manager) ////////////////////////////////////////////////////////
1551
1552 #pragma pack( push, 1 )
1553
1554 #define DXGKMDT_OPM_OMAC_SIZE 16
1555 #define DXGKMDT_OPM_128_BIT_RANDOM_NUMBER_SIZE 16
1556 #define DXGKMDT_OPM_ENCRYPTED_PARAMETERS_SIZE 256
1557 #define DXGKMDT_OPM_CONFIGURE_SETTING_DATA_SIZE 4056
1558 #define DXGKMDT_OPM_GET_INFORMATION_PARAMETERS_SIZE 4056
1559 #define DXGKMDT_OPM_REQUESTED_INFORMATION_SIZE 4076
1560 #define DXGKMDT_OPM_HDCP_KEY_SELECTION_VECTOR_SIZE 5
1561 #define DXGKMDT_OPM_PROTECTION_TYPE_SIZE 4
1562
1563 DEFINE_GUID(DXGKMDT_OPM_GET_CURRENT_HDCP_SRM_VERSION, 0x99c5ceff, 0x5f1d, 0x4879, 0x81, 0xc1, 0xc5, 0x24, 0x43, 0xc9, 0x48, 0x2b);
1564 DEFINE_GUID(DXGKMDT_OPM_GET_CONNECTED_HDCP_DEVICE_INFORMATION, 0x0db59d74, 0xa992, 0x492e, 0xa0, 0xbd, 0xc2, 0x3f, 0xda, 0x56, 0x4e, 0x00);
1565 DEFINE_GUID(DXGKMDT_OPM_GET_CONNECTOR_TYPE, 0x81d0bfd5, 0x6afe, 0x48c2, 0x99, 0xc0, 0x95, 0xa0, 0x8f, 0x97, 0xc5, 0xda);
1566 DEFINE_GUID(DXGKMDT_OPM_GET_SUPPORTED_PROTECTION_TYPES, 0x38f2a801, 0x9a6c, 0x48bb, 0x91, 0x07, 0xb6, 0x69, 0x6e, 0x6f, 0x17, 0x97);
1567 DEFINE_GUID(DXGKMDT_OPM_GET_VIRTUAL_PROTECTION_LEVEL, 0xb2075857, 0x3eda, 0x4d5d, 0x88, 0xdb, 0x74, 0x8f, 0x8c, 0x1a, 0x05, 0x49);
1568 DEFINE_GUID(DXGKMDT_OPM_GET_ACTUAL_PROTECTION_LEVEL, 0x1957210a, 0x7766, 0x452a, 0xb9, 0x9a, 0xd2, 0x7a, 0xed, 0x54, 0xf0, 0x3a);
1569 DEFINE_GUID(DXGKMDT_OPM_GET_ACTUAL_OUTPUT_FORMAT, 0xd7bf1ba3, 0xad13, 0x4f8e, 0xaf, 0x98, 0x0d, 0xcb, 0x3c, 0xa2, 0x04, 0xcc);
1570 DEFINE_GUID(DXGKMDT_OPM_GET_ADAPTER_BUS_TYPE, 0xc6f4d673, 0x6174, 0x4184, 0x8e, 0x35, 0xf6, 0xdb, 0x52, 0x0, 0xbc, 0xba);
1571 DEFINE_GUID(DXGKMDT_OPM_GET_ACP_AND_CGMSA_SIGNALING, 0x6629a591, 0x3b79, 0x4cf3, 0x92, 0x4a, 0x11, 0xe8, 0xe7, 0x81, 0x16, 0x71);
1572 DEFINE_GUID(DXGKMDT_OPM_GET_OUTPUT_ID, 0x72cb6df3, 0x244f, 0x40ce, 0xb0, 0x9e, 0x20, 0x50, 0x6a, 0xf6, 0x30, 0x2f);
1573 DEFINE_GUID(DXGKMDT_OPM_GET_DVI_CHARACTERISTICS, 0xa470b3bb, 0x5dd7, 0x4172, 0x83, 0x9c, 0x3d, 0x37, 0x76, 0xe0, 0xeb, 0xf5);
1574 DEFINE_GUID(DXGKMDT_OPM_GET_OUTPUT_HARDWARE_PROTECTION_SUPPORT, 0x3b129589, 0x2af8, 0x4ef0, 0x96, 0xa2, 0x70, 0x4a, 0x84, 0x5a, 0x21, 0x8e);
1575 DEFINE_GUID(DXGKMDT_OPM_GET_CODEC_INFO, 0x4f374491, 0x8f5f, 0x4445, 0x9d, 0xba, 0x95, 0x58, 0x8f, 0x6b, 0x58, 0xb4);
1576 DEFINE_GUID(DXGKMDT_OPM_SET_PROTECTION_LEVEL, 0x9bb9327c, 0x4eb5, 0x4727, 0x9f, 0x00, 0xb4, 0x2b, 0x09, 0x19, 0xc0, 0xda);
1577 DEFINE_GUID(DXGKMDT_OPM_SET_ACP_AND_CGMSA_SIGNALING, 0x09a631a5, 0xd684, 0x4c60, 0x8e, 0x4d, 0xd3, 0xbb, 0x0f, 0x0b, 0xe3, 0xee);
1578 DEFINE_GUID(DXGKMDT_OPM_SET_HDCP_SRM, 0x8b5ef5d1, 0xc30d, 0x44ff, 0x84, 0xa5, 0xea, 0x71, 0xdc, 0xe7, 0x8f, 0x13);
1579 DEFINE_GUID(DXGKMDT_OPM_SET_PROTECTION_LEVEL_ACCORDING_TO_CSS_DVD, 0x39ce333e, 0x4cc0, 0x44ae, 0xbf, 0xcc, 0xda, 0x50, 0xb5, 0xf8, 0x2e, 0x72);
1580
1581 typedef enum _DXGKMDT_CERTIFICATE_TYPE
1582 {
1583 DXGKMDT_OPM_CERTIFICATE = 0,
1584 DXGKMDT_COPP_CERTIFICATE = 1,
1585 DXGKMDT_UAB_CERTIFICATE = 2,
1586 DXGKMDT_INDIRECT_DISPLAY_CERTIFICATE = 3,
1587 DXGKMDT_FORCE_ULONG = 0xFFFFFFFF
1588 } DXGKMDT_CERTIFICATE_TYPE;
1589
1590 typedef enum _DXGKMDT_OPM_VIDEO_OUTPUT_SEMANTICS
1591 {
1592 DXGKMDT_OPM_VOS_COPP_SEMANTICS = 0,
1593 DXGKMDT_OPM_VOS_OPM_SEMANTICS = 1,
1594 DXGKMDT_OPM_VOS_OPM_INDIRECT_DISPLAY = 2
1595 } DXGKMDT_OPM_VIDEO_OUTPUT_SEMANTICS;
1596
1597 typedef enum _DXGKMDT_DPCP_PROTECTION_LEVEL
1598 {
1599 DXGKMDT_OPM_DPCP_OFF = 0,
1600 DXGKMDT_OPM_DPCP_ON = 1,
1601 DXGKMDT_OPM_DPCP_FORCE_ULONG = 0x7fffffff
1602
1603 } DXGKMDT_OPM_DPCP_PROTECTION_LEVEL;
1604
1605 typedef enum _DXGKMDT_OPM_HDCP_FLAG
1606 {
1607 DXGKMDT_OPM_HDCP_FLAG_NONE = 0x00,
1608 DXGKMDT_OPM_HDCP_FLAG_REPEATER = 0x01
1609 } DXGKMDT_OPM_HDCP_FLAG;
1610
1611 typedef enum _DXGKMDT_OPM_STATUS
1612 {
1613 DXGKMDT_OPM_STATUS_NORMAL = 0x00,
1614 DXGKMDT_OPM_STATUS_LINK_LOST = 0x01,
1615 DXGKMDT_OPM_STATUS_RENEGOTIATION_REQUIRED = 0x02,
1616 DXGKMDT_OPM_STATUS_TAMPERING_DETECTED = 0x04,
1617 DXGKMDT_OPM_STATUS_REVOKED_HDCP_DEVICE_ATTACHED = 0x08
1618 } DXGKMDT_OPM_STATUS;
1619
1620 // NUAE stands for Non-User Accessible Enclosure
1621 typedef enum _DXGKMDT_OPM_BUS_TYPE_AND_IMPLEMENTATION
1622 {
1623 DXGKMDT_OPM_BUS_TYPE_OTHER = 0x00000000,
1624 DXGKMDT_OPM_BUS_TYPE_PCI = 0x00000001,
1625 DXGKMDT_OPM_BUS_TYPE_PCIX = 0x00000002,
1626 DXGKMDT_OPM_BUS_TYPE_PCIEXPRESS = 0x00000003,
1627 DXGKMDT_OPM_BUS_TYPE_AGP = 0x00000004,
1628 DXGKMDT_OPM_BUS_IMPLEMENTATION_MODIFIER_INSIDE_OF_CHIPSET = 0x00010000,
1629 DXGKMDT_OPM_BUS_IMPLEMENTATION_MODIFIER_TRACKS_ON_MOTHER_BOARD_TO_CHIP = 0x00020000,
1630 DXGKMDT_OPM_BUS_IMPLEMENTATION_MODIFIER_TRACKS_ON_MOTHER_BOARD_TO_SOCKET = 0x00030000,
1631 DXGKMDT_OPM_BUS_IMPLEMENTATION_MODIFIER_DAUGHTER_BOARD_CONNECTOR = 0x00040000,
1632 DXGKMDT_OPM_BUS_IMPLEMENTATION_MODIFIER_DAUGHTER_BOARD_CONNECTOR_INSIDE_OF_NUAE = 0x00050000,
1633 DXGKMDT_OPM_BUS_IMPLEMENTATION_MODIFIER_NON_STANDARD = 0x80000000,
1634 DXGKMDT_OPM_COPP_COMPATIBLE_BUS_TYPE_INTEGRATED = 0x80000000
1635 } DXGKMDT_OPM_BUS_TYPE_AND_IMPLEMENTATION;
1636
1637 typedef enum _DXGKMDT_OPM_HDCP_PROTECTION_LEVEL
1638 {
1639 DXGKMDT_OPM_HDCP_OFF = 0,
1640 DXGKMDT_OPM_HDCP_ON = 1,
1641 DXGKMDT_OPM_HDCP_FORCE_ULONG = 0x7fffffff
1642 } DXGKMDT_OPM_HDCP_PROTECTION_LEVEL;
1643
1644 typedef enum _DXGKMDT_OPM_TYPE_ENFORCEMENT_HDCP_PROTECTION_LEVEL
1645 {
1646 DXGKMDT_OPM_TYPE_ENFORCEMENT_HDCP_OFF = DXGKMDT_OPM_HDCP_OFF,
1647 DXGKMDT_OPM_TYPE_ENFORCEMENT_HDCP_ON_WITH_NO_TYPE_RESTRICTION = DXGKMDT_OPM_HDCP_ON, // No Type restriction on output topology nodes
1648 DXGKMDT_OPM_TYPE_ENFORCEMENT_HDCP_ON_WITH_TYPE1_RESTRICTION = DXGKMDT_OPM_HDCP_ON + 1, // Restrict to Type 1 compliant output topology nodes
1649 DXGKMDT_OPM_TYPE_ENFORCEMENT_HDCP_FORCE_ULONG = 0x7fffffff
1650 } DXGKMDT_OPM_TYPE_ENFORCEMENT_HDCP_PROTECTION_LEVEL;
1651
1652 typedef enum _DXGKMDT_OPM_CGMSA
1653 {
1654 DXGKMDT_OPM_CGMSA_OFF = 0,
1655 DXGKMDT_OPM_CGMSA_COPY_FREELY = 1,
1656 DXGKMDT_OPM_CGMSA_COPY_NO_MORE = 2,
1657 DXGKMDT_OPM_CGMSA_COPY_ONE_GENERATION = 3,
1658 DXGKMDT_OPM_CGMSA_COPY_NEVER = 4,
1659 DXGKMDT_OPM_REDISTRIBUTION_CONTROL_REQUIRED = 0x08,
1660 } DXGKMDT_OPM_CGMSA;
1661
1662 typedef enum _DXGKMDT_OPM_ACP_PROTECTION_LEVEL
1663 {
1664 DXGKMDT_OPM_ACP_OFF = 0,
1665 DXGKMDT_OPM_ACP_LEVEL_ONE = 1,
1666 DXGKMDT_OPM_ACP_LEVEL_TWO = 2,
1667 DXGKMDT_OPM_ACP_LEVEL_THREE = 3,
1668 DXGKMDT_OPM_ACP_FORCE_ULONG = 0x7fffffff
1669 } DXGKMDT_OPM_ACP_PROTECTION_LEVEL;
1670
1671 typedef enum _DXGKMDT_OPM_PROTECTION_TYPE
1672 {
1673 DXGKMDT_OPM_PROTECTION_TYPE_OTHER = 0x80000000,
1674 DXGKMDT_OPM_PROTECTION_TYPE_NONE = 0x00000000,
1675 DXGKMDT_OPM_PROTECTION_TYPE_COPP_COMPATIBLE_HDCP = 0x00000001,
1676 DXGKMDT_OPM_PROTECTION_TYPE_ACP = 0x00000002,
1677 DXGKMDT_OPM_PROTECTION_TYPE_CGMSA = 0x00000004,
1678 DXGKMDT_OPM_PROTECTION_TYPE_HDCP = 0x00000008,
1679 DXGKMDT_OPM_PROTECTION_TYPE_DPCP = 0x00000010,
1680 DXGKMDT_OPM_PROTECTION_TYPE_TYPE_ENFORCEMENT_HDCP = 0x00000020,
1681 DXGKMDT_OPM_PROTECTION_TYPE_MASK = 0x8000003F
1682 } DXGKMDT_OPM_PROTECTION_TYPE;
1683
1684 typedef enum _DXGKMDT_OPM_PROTECTION_STANDARD
1685 {
1686 DXGKMDT_OPM_PROTECTION_STANDARD_OTHER = 0x80000000,
1687 DXGKMDT_OPM_PROTECTION_STANDARD_NONE = 0x00000000,
1688 DXGKMDT_OPM_PROTECTION_STANDARD_IEC61880_525I = 0x00000001,
1689 DXGKMDT_OPM_PROTECTION_STANDARD_IEC61880_2_525I = 0x00000002,
1690 DXGKMDT_OPM_PROTECTION_STANDARD_IEC62375_625P = 0x00000004,
1691 DXGKMDT_OPM_PROTECTION_STANDARD_EIA608B_525 = 0x00000008,
1692 DXGKMDT_OPM_PROTECTION_STANDARD_EN300294_625I = 0x00000010,
1693 DXGKMDT_OPM_PROTECTION_STANDARD_CEA805A_TYPEA_525P = 0x00000020,
1694 DXGKMDT_OPM_PROTECTION_STANDARD_CEA805A_TYPEA_750P = 0x00000040,
1695 DXGKMDT_OPM_PROTECTION_STANDARD_CEA805A_TYPEA_1125I = 0x00000080,
1696 DXGKMDT_OPM_PROTECTION_STANDARD_CEA805A_TYPEB_525P = 0x00000100,
1697 DXGKMDT_OPM_PROTECTION_STANDARD_CEA805A_TYPEB_750P = 0x00000200,
1698 DXGKMDT_OPM_PROTECTION_STANDARD_CEA805A_TYPEB_1125I = 0x00000400,
1699 DXGKMDT_OPM_PROTECTION_STANDARD_ARIBTRB15_525I = 0x00000800,
1700 DXGKMDT_OPM_PROTECTION_STANDARD_ARIBTRB15_525P = 0x00001000,
1701 DXGKMDT_OPM_PROTECTION_STANDARD_ARIBTRB15_750P = 0x00002000,
1702 DXGKMDT_OPM_PROTECTION_STANDARD_ARIBTRB15_1125I = 0x00004000,
1703 } DXGKMDT_OPM_PROTECTION_STANDARD;
1704
1705 typedef enum _DXGKMDT_OPM_IMAGE_ASPECT_RATIO_EN300294
1706 {
1707 DXGKMDT_OPM_ASPECT_RATIO_EN300294_FULL_FORMAT_4_BY_3 = 0,
1708 DXGKMDT_OPM_ASPECT_RATIO_EN300294_BOX_14_BY_9_CENTER = 1,
1709 DXGKMDT_OPM_ASPECT_RATIO_EN300294_BOX_14_BY_9_TOP = 2,
1710 DXGKMDT_OPM_ASPECT_RATIO_EN300294_BOX_16_BY_9_CENTER = 3,
1711 DXGKMDT_OPM_ASPECT_RATIO_EN300294_BOX_16_BY_9_TOP = 4,
1712 DXGKMDT_OPM_ASPECT_RATIO_EN300294_BOX_GT_16_BY_9_CENTER = 5,
1713 DXGKMDT_OPM_ASPECT_RATIO_EN300294_FULL_FORMAT_4_BY_3_PROTECTED_CENTER = 6,
1714 DXGKMDT_OPM_ASPECT_RATIO_EN300294_FULL_FORMAT_16_BY_9_ANAMORPHIC = 7,
1715 DXGKMDT_OPM_ASPECT_RATIO_FORCE_ULONG = 0x7FFFFFFF
1716 } DXGKMDT_OPM_IMAGE_ASPECT_RATIO_EN300294;
1717
1718 typedef enum _DXGKMDT_OPM_INTERLEAVE_FORMAT
1719 {
1720 DXGKMDT_OPM_INTERLEAVE_FORMAT_OTHER = 0,
1721 DXGKMDT_OPM_INTERLEAVE_FORMAT_PROGRESSIVE = 2,
1722 DXGKMDT_OPM_INTERLEAVE_FORMAT_INTERLEAVED_EVEN_FIRST = 3,
1723 DXGKMDT_OPM_INTERLEAVE_FORMAT_INTERLEAVED_ODD_FIRST = 4,
1724 DXGKMDT_OPM_INTERLEAVE_FORMAT_FORCE_ULONG = 0xFFFFFFFF
1725
1726 } DXGKMDT_OPM_INTERLEAVE_FORMAT;
1727
1728 typedef enum _DXGKDT_OPM_DVI_CHARACTERISTICS
1729 {
1730 DXGKMDT_OPM_DVI_CHARACTERISTIC_1_0 = 1,
1731 DXGKMDT_OPM_DVI_CHARACTERISTIC_1_1_OR_ABOVE = 2,
1732 DXGKMDT_OPM_DVI_CHARACTERISTICS_FORCE_ULONG = 0xFFFFFFFF
1733 } DXGKDT_OPM_DVI_CHARACTERISTICS;
1734
1735 typedef enum _DXGKMDT_OPM_OUTPUT_HARDWARE_PROTECTION
1736 {
1737 DXGKMDT_OPM_OUTPUT_HARDWARE_PROTECTION_NOT_SUPPORTED = 0x0,
1738 DXGKMDT_OPM_OUTPUT_HARDWARE_PROTECTION_SUPPORTED = 0x1
1739 } DXGKMDT_OPM_OUTPUT_HARDWARE_PROTECTION;
1740
1741 typedef struct _DXGKMDT_OPM_RANDOM_NUMBER
1742 {
1743 BYTE abRandomNumber[DXGKMDT_OPM_128_BIT_RANDOM_NUMBER_SIZE];
1744 } DXGKMDT_OPM_RANDOM_NUMBER, *PDXGKMDT_OPM_RANDOM_NUMBER;
1745
1746 typedef struct _DXGKMDT_OPM_OMAC
1747 {
1748 BYTE abOMAC[DXGKMDT_OPM_OMAC_SIZE];
1749 } DXGKMDT_OPM_OMAC, *PDXGKMDT_OPM_OMAC;
1750
1751 typedef struct _DXGKMDT_OPM_ENCRYPTED_PARAMETERS
1752 {
1753 BYTE abEncryptedParameters[DXGKMDT_OPM_ENCRYPTED_PARAMETERS_SIZE];
1754 } DXGKMDT_OPM_ENCRYPTED_PARAMETERS, *PDXGKMDT_OPM_ENCRYPTED_PARAMETERS;
1755
1756 typedef struct _DXGKMDT_OPM_GET_INFO_PARAMETERS
1757 {
1758 DXGKMDT_OPM_OMAC omac;
1759 DXGKMDT_OPM_RANDOM_NUMBER rnRandomNumber;
1760 GUID guidInformation;
1761 ULONG ulSequenceNumber;
1762 ULONG cbParametersSize;
1763 BYTE abParameters[DXGKMDT_OPM_GET_INFORMATION_PARAMETERS_SIZE];
1764 } DXGKMDT_OPM_GET_INFO_PARAMETERS, *PDXGKMDT_OPM_GET_INFO_PARAMETERS;
1765
1766 typedef struct _DXGKMDT_OPM_COPP_COMPATIBLE_GET_INFO_PARAMETERS
1767 {
1768 DXGKMDT_OPM_RANDOM_NUMBER rnRandomNumber;
1769 GUID guidInformation;
1770 ULONG ulSequenceNumber;
1771 ULONG cbParametersSize;
1772 BYTE abParameters[DXGKMDT_OPM_GET_INFORMATION_PARAMETERS_SIZE];
1773 } DXGKMDT_OPM_COPP_COMPATIBLE_GET_INFO_PARAMETERS, *PDXGKMDT_OPM_COPP_COMPATIBLE_GET_INFO_PARAMETERS;
1774
1775 typedef struct _DXGKMDT_OPM_HDCP_KEY_SELECTION_VECTOR
1776 {
1777 BYTE abKeySelectionVector[DXGKMDT_OPM_HDCP_KEY_SELECTION_VECTOR_SIZE];
1778 } DXGKMDT_OPM_HDCP_KEY_SELECTION_VECTOR;
1779
1780 typedef struct _DXGKMDT_OPM_CONNECTED_HDCP_DEVICE_INFORMATION
1781 {
1782 DXGKMDT_OPM_RANDOM_NUMBER rnRandomNumber;
1783 ULONG ulStatusFlags;
1784 ULONG ulHDCPFlags;
1785 DXGKMDT_OPM_HDCP_KEY_SELECTION_VECTOR ksvB;
1786 BYTE Reserved[11];
1787 BYTE Reserved2[16];
1788 BYTE Reserved3[16];
1789 } DXGKMDT_OPM_CONNECTED_HDCP_DEVICE_INFORMATION;
1790
1791 typedef struct _DXGKMDT_OPM_REQUESTED_INFORMATION
1792 {
1793 DXGKMDT_OPM_OMAC omac;
1794 ULONG cbRequestedInformationSize;
1795 BYTE abRequestedInformation[DXGKMDT_OPM_REQUESTED_INFORMATION_SIZE];
1796 } DXGKMDT_OPM_REQUESTED_INFORMATION, *PDXGKMDT_OPM_REQUESTED_INFORMATION;
1797
1798 typedef struct _DXGKMDT_OPM_STANDARD_INFORMATION
1799 {
1800 DXGKMDT_OPM_RANDOM_NUMBER rnRandomNumber;
1801 ULONG ulStatusFlags;
1802 ULONG ulInformation;
1803 ULONG ulReserved;
1804 ULONG ulReserved2;
1805 } DXGKMDT_OPM_STANDARD_INFORMATION;
1806
1807 typedef struct _DXGKMDT_OPM_ACTUAL_OUTPUT_FORMAT
1808 {
1809 DXGKMDT_OPM_RANDOM_NUMBER rnRandomNumber;
1810 ULONG ulStatusFlags;
1811 ULONG ulDisplayWidth;
1812 ULONG ulDisplayHeight;
1813 DXGKMDT_OPM_INTERLEAVE_FORMAT ifInterleaveFormat;
1814 ULONG d3dFormat;
1815 ULONG ulFrequencyNumerator;
1816 ULONG ulFrequencyDenominator;
1817 } DXGKMDT_OPM_ACTUAL_OUTPUT_FORMAT;
1818
1819 typedef struct _DXGKMDT_OPM_ACP_AND_CGMSA_SIGNALING
1820 {
1821 DXGKMDT_OPM_RANDOM_NUMBER rnRandomNumber;
1822 ULONG ulStatusFlags;
1823 ULONG ulAvailableTVProtectionStandards;
1824 ULONG ulActiveTVProtectionStandard;
1825 ULONG ulReserved;
1826 ULONG ulAspectRatioValidMask1;
1827 ULONG ulAspectRatioData1;
1828 ULONG ulAspectRatioValidMask2;
1829 ULONG ulAspectRatioData2;
1830 ULONG ulAspectRatioValidMask3;
1831 ULONG ulAspectRatioData3;
1832 ULONG ulReserved2[4];
1833 ULONG ulReserved3[4];
1834 } DXGKMDT_OPM_ACP_AND_CGMSA_SIGNALING;
1835
1836 typedef struct _DXGKMDT_OPM_OUTPUT_ID
1837 {
1838 DXGKMDT_OPM_RANDOM_NUMBER rnRandomNumber;
1839 ULONG ulStatusFlags;
1840 UINT64 OutputId;
1841 } DXGKMDT_OPM_OUTPUT_ID;
1842
1843 typedef struct _DXGKMDT_OPM_CONFIGURE_PARAMETERS
1844 {
1845 DXGKMDT_OPM_OMAC omac;
1846 GUID guidSetting;
1847 ULONG ulSequenceNumber;
1848 ULONG cbParametersSize;
1849 BYTE abParameters[DXGKMDT_OPM_CONFIGURE_SETTING_DATA_SIZE];
1850 } DXGKMDT_OPM_CONFIGURE_PARAMETERS, *PDXGKMDT_OPM_CONFIGURE_PARAMETERS;
1851
1852 typedef struct _DXGKMDT_OPM_SET_PROTECTION_LEVEL_PARAMETERS
1853 {
1854 ULONG ulProtectionType;
1855 ULONG ulProtectionLevel;
1856 ULONG Reserved;
1857 ULONG Reserved2;
1858 } DXGKMDT_OPM_SET_PROTECTION_LEVEL_PARAMETERS;
1859
1860 typedef struct _DXGKMDT_OPM_SET_ACP_AND_CGMSA_SIGNALING_PARAMETERS
1861 {
1862 ULONG ulNewTVProtectionStandard;
1863 ULONG ulAspectRatioChangeMask1;
1864 ULONG ulAspectRatioData1;
1865 ULONG ulAspectRatioChangeMask2;
1866 ULONG ulAspectRatioData2;
1867 ULONG ulAspectRatioChangeMask3;
1868 ULONG ulAspectRatioData3;
1869 ULONG ulReserved[4];
1870 ULONG ulReserved2[4];
1871 ULONG ulReserved3;
1872 } DXGKMDT_OPM_SET_ACP_AND_CGMSA_SIGNALING_PARAMETERS;
1873
1874 typedef struct _DXGKMDT_OPM_SET_HDCP_SRM_PARAMETERS
1875 {
1876 ULONG ulSRMVersion;
1877 } DXGKMDT_OPM_SET_HDCP_SRM_PARAMETERS;
1878
1879 typedef struct _DXGKMDT_OPM_CREATE_VIDEO_OUTPUT_FOR_TARGET_PARAMETERS
1880 {
1881 LUID AdapterLuid;
1882 D3DDDI_VIDEO_PRESENT_TARGET_ID TargetId;
1883 DXGKMDT_OPM_VIDEO_OUTPUT_SEMANTICS Vos;
1884 } DXGKMDT_OPM_CREATE_VIDEO_OUTPUT_FOR_TARGET_PARAMETERS;
1885
1886 typedef struct _DXGK_BRIGHTNESS_CAPS
1887 {
1888 union
1889 {
1890 struct
1891 {
1892 UINT SmoothBrightness : 1; // 0x00000001
1893 UINT AdaptiveBrightness : 1; // 0x00000002
1894 UINT NitsBrightness : 1; // 0x00000004
1895 UINT Reserved : 29; // 0xFFFFFFF8
1896 };
1897
1898 UINT Value;
1899 };
1900 } DXGK_BRIGHTNESS_CAPS;
1901
1902 typedef struct _DXGK_BRIGHTNESS_STATE
1903 {
1904 union
1905 {
1906 struct
1907 {
1908 UINT SmoothBrightness : 1; // 0x00000001
1909 UINT Reserved : 31; // 0xFFFFFFFE
1910 };
1911
1912 UINT Value;
1913 };
1914 } DXGK_BRIGHTNESS_STATE;
1915
1916 typedef enum
1917 {
1918 DxgkBacklightOptimizationDisable = 0,
1919 DxgkBacklightOptimizationDesktop = 1,
1920 DxgkBacklightOptimizationDynamic = 2,
1921 DxgkBacklightOptimizationDimmed = 3,
1922 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
1923 DxgkBacklightOptimizationEDR = 4,
1924 #endif // DXGKDDI_INTERFACE_VERSION_WDDM2_2
1925 } DXGK_BACKLIGHT_OPTIMIZATION_LEVEL;
1926
1927 typedef struct _DXGK_BACKLIGHT_INFO
1928 {
1929 OUT USHORT BacklightUsersetting;
1930 OUT USHORT BacklightEffective;
1931 OUT D3DDDI_GAMMA_RAMP_RGB256x3x16 GammaRamp;
1932 } DXGK_BACKLIGHT_INFO;
1933
1934 typedef struct _DXGK_BRIGHTNESS_SENSOR_DATA_CHROMATICITY
1935 {
1936 float ChromaticityX;
1937 float ChromaticityY;
1938 } DXGK_BRIGHTNESS_SENSOR_DATA_CHROMATICITY;
1939
1940 typedef struct _DXGK_BRIGHTNESS_SENSOR_DATA
1941 {
1942 UINT32 Size;
1943 union
1944 {
1945 struct
1946 {
1947 UINT AlsReadingValid : 1;
1948 UINT ChromaticityValid : 1;
1949 UINT ColorTemperatureValid : 1;
1950 UINT Reserved : 29;
1951 } Flags;
1952 UINT ValidSensorValues;
1953 };
1954 float AlsReading;
1955 DXGK_BRIGHTNESS_SENSOR_DATA_CHROMATICITY Chromaticity;
1956 float ColorTemperature;
1957 } DXGK_BRIGHTNESS_SENSOR_DATA;
1958
1959
1960 typedef struct _DXGK_BRIGHTNESS_SET_IN
1961 {
1962 UINT32 BrightnessMillinits;
1963 UINT32 TransitionTimeMs;
1964 DXGK_BRIGHTNESS_SENSOR_DATA SensorReadings;
1965 } DXGK_BRIGHTNESS_SET_IN, *PDXGK_BRIGHTNESS_SET_IN;
1966
1967 typedef struct _DXGK_BRIGHTNESS_GET_OUT
1968 {
1969 UINT32 CurrentBrightnessMillinits;
1970 UINT32 TargetBrightnessMillinits;
1971 } DXGK_BRIGHTNESS_GET_OUT, *PDXGK_BRIGHTNESS_GET_OUT;
1972
1973 typedef struct _DXGK_BRIGHTNESS_NIT_RANGE
1974 {
1975 UINT32 MinimumLevelMillinit;
1976 UINT32 MaximumLevelMillinit;
1977 UINT32 StepSizeMillinit;
1978 } DXGK_BRIGHTNESS_NIT_RANGE;
1979
1980 #define DXGK_BRIGHTNESS_MAXIMUM_NIT_RANGE_COUNT 16
1981
1982 typedef struct _DXGK_BRIGHTNESS_GET_NIT_RANGES_OUT
1983 {
1984 UINT32 NormalRangeCount;
1985 UINT32 RangeCount;
1986 UINT32 PreferredMaximumBrightness;
1987 DXGK_BRIGHTNESS_NIT_RANGE SupportedRanges[DXGK_BRIGHTNESS_MAXIMUM_NIT_RANGE_COUNT];
1988 } DXGK_BRIGHTNESS_GET_NIT_RANGES_OUT, *PDXGK_BRIGHTNESS_GET_NIT_RANGES_OUT;
1989
1990 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3)
1991
1992 typedef struct _D3DKMT_WDDM_1_3_CAPS
1993 {
1994 union
1995 {
1996 struct
1997 {
1998 UINT SupportMiracast : 1;
1999 UINT IsHybridIntegratedGPU : 1;
2000 UINT IsHybridDiscreteGPU : 1;
2001 UINT SupportPowerManagementPStates : 1;
2002 UINT SupportVirtualModes : 1;
2003 UINT SupportCrossAdapterResource : 1;
2004 UINT Reserved : 26;
2005 };
2006 UINT Value;
2007 };
2008 } D3DKMT_WDDM_1_3_CAPS;
2009
2010 #define DXGK_MAX_METADATA_NAME_LENGTH 32
2011 typedef enum
2012 {
2013 DXGK_ENGINE_TYPE_OTHER,
2014 DXGK_ENGINE_TYPE_3D,
2015 DXGK_ENGINE_TYPE_VIDEO_DECODE,
2016 DXGK_ENGINE_TYPE_VIDEO_ENCODE,
2017 DXGK_ENGINE_TYPE_VIDEO_PROCESSING,
2018 DXGK_ENGINE_TYPE_SCENE_ASSEMBLY,
2019 DXGK_ENGINE_TYPE_COPY,
2020 DXGK_ENGINE_TYPE_OVERLAY,
2021 DXGK_ENGINE_TYPE_CRYPTO,
2022 DXGK_ENGINE_TYPE_MAX
2023 } DXGK_ENGINE_TYPE;
2024
2025 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
2026
2027 typedef struct _DXGK_NODEMETADATA_FLAGS
2028 {
2029 union
2030 {
2031 struct
2032 {
2033 UINT ContextSchedulingSupported : 1;
2034
2035 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5)
2036
2037 UINT RingBufferFenceRelease : 1;
2038 UINT SupportTrackedWorkload : 1;
2039 UINT Reserved : 13;
2040
2041 UINT MaxInFlightHwQueueBuffers : 16;
2042
2043 #else
2044
2045 UINT Reserved : 31;
2046
2047 #endif // !(DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5)
2048
2049 };
2050 UINT32 Value;
2051 };
2052 } DXGK_NODEMETADATA_FLAGS;
2053
2054 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
2055
2056 typedef struct _DXGK_NODEMETADATA
2057 {
2058 DXGK_ENGINE_TYPE EngineType;
2059 WCHAR FriendlyName[DXGK_MAX_METADATA_NAME_LENGTH];
2060
2061 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
2062 DXGK_NODEMETADATA_FLAGS Flags;
2063 #else
2064 UINT32 Reserved;
2065 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
2066
2067 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0)
2068 BOOLEAN GpuMmuSupported;
2069 BOOLEAN IoMmuSupported;
2070 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0)
2071 } DXGK_NODEMETADATA;
2072
2073 typedef DXGK_NODEMETADATA DXGKARG_GETNODEMETADATA;
2074
2075 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_4)
2076
2077 typedef struct _DXGK_GPUCLOCKDATA_FLAGS
2078 {
2079 union
2080 {
2081 struct
2082 {
2083 UINT ContextManagementProcessor : 1;
2084 UINT Reserved : 31;
2085 };
2086 UINT32 Value;
2087 };
2088 } DXGK_GPUCLOCKDATA_FLAGS;
2089
2090 typedef struct _DXGK_NODE_PERFDATA
2091 {
2092 ULONGLONG Frequency; // out: Clock frequency of the engine in hertz
2093 ULONGLONG MaxFrequency; // out: Max engine clock frequency
2094 ULONGLONG MaxFrequencyOC; // out: Max engine over clock frequency
2095 ULONG Voltage; // out: Voltage of the engine in milli volts mV
2096 ULONG VoltageMax; // out: Max voltage levels in milli volts.
2097 ULONG VoltageMaxOC; // out: Max voltage level while overclocked in milli volts.
2098 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5)
2099 ULONGLONG MaxTransitionLatency; // out: Max transition latency to change the frequency in 100 nanoseconds
2100 #endif
2101 } DXGK_NODE_PERFDATA;
2102
2103 typedef struct _DXGK_ADAPTER_PERFDATA
2104 {
2105 ULONGLONG MemoryFrequency; // out: Clock frequency of the memory in hertz
2106 ULONGLONG MaxMemoryFrequency; // out: Max memory clock frequency
2107 ULONGLONG MaxMemoryFrequencyOC; // out: Clock frequency of the memory while overclocked in hertz.
2108 ULONGLONG MemoryBandwidth; // out: Amount of memory transferred in bytes
2109 ULONGLONG PCIEBandwidth; // out: Amount of memory transferred over PCI-E in bytes
2110 ULONG FanRPM; // out: Fan rpm
2111 ULONG Power; // out: Power draw of the adapter in tenths of a percentage
2112 ULONG Temperature; // out: Temperature in deci-Celsius 1 = 0.1C
2113 UCHAR PowerStateOverride; // out: Overrides dxgkrnls power view of linked adapters.
2114 } DXGK_ADAPTER_PERFDATA;
2115
2116 typedef struct _DXGK_ADAPTER_PERFDATACAPS
2117 {
2118 ULONGLONG MaxMemoryBandwidth; // out: Max memory bandwidth in bytes for 1 second
2119 ULONGLONG MaxPCIEBandwidth; // out: Max pcie bandwidth in bytes for 1 second
2120 ULONG MaxFanRPM; // out: Max fan rpm
2121 ULONG TemperatureMax; // out: Max temperature before damage levels
2122 ULONG TemperatureWarning; // out: The temperature level where throttling begins.
2123 } DXGK_ADAPTER_PERFDATACAPS;
2124
2125 #define DXGK_MAX_GPUVERSION_NAME_LENGTH 32
2126 typedef struct _DXGK_GPUVERSION
2127 {
2128 WCHAR BiosVersion[DXGK_MAX_GPUVERSION_NAME_LENGTH]; //out: The gpu bios version
2129 WCHAR GpuArchitecture[DXGK_MAX_GPUVERSION_NAME_LENGTH]; //out: The gpu architectures name.
2130 } DXGK_GPUVERSION;
2131
2132 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_4)
2133
2134 typedef struct _DXGK_GPUCLOCKDATA
2135 {
2136 ULONGLONG GpuFrequency;
2137 ULONGLONG GpuClockCounter;
2138 ULONGLONG CpuClockCounter;
2139
2140 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_4)
2141 DXGK_GPUCLOCKDATA_FLAGS Flags;
2142 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_4)
2143 } DXGK_GPUCLOCKDATA;
2144
2145 typedef DXGK_GPUCLOCKDATA DXGKARG_CALIBRATEGPUCLOCK;
2146
2147 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM1_3)
2148
2149 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0)
2150
2151 typedef struct _D3DKMT_WDDM_2_0_CAPS
2152 {
2153 union
2154 {
2155 struct
2156 {
2157 UINT Support64BitAtomics : 1;
2158 UINT GpuMmuSupported : 1;
2159 UINT IoMmuSupported : 1;
2160
2161 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_4)
2162 UINT FlipOverwriteSupported : 1;
2163 UINT SupportContextlessPresent : 1;
2164 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5)
2165 UINT SupportSurpriseRemoval : 1;
2166 UINT Reserved : 26;
2167 #else
2168 UINT Reserved : 27;
2169 #endif // !(DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5)
2170 #else
2171 UINT Reserved : 29;
2172 #endif // !(DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_4)
2173 };
2174 UINT Value;
2175 };
2176 } D3DKMT_WDDM_2_0_CAPS;
2177
2178 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_7)
2179
2180 typedef struct _D3DKMT_WDDM_2_7_CAPS
2181 {
2182 union
2183 {
2184 struct
2185 {
2186 UINT HwSchSupported : 1; // Specifies whether the GPU supports hardware scheduling
2187 UINT HwSchEnabled : 1; // Specifies whether the hardware scheduling is currently enabled for this GPU
2188 UINT HwSchEnabledByDefault : 1; // Set to 1 if the OS default policy is to enable hardware scheduling for this GPU
2189 UINT IndependentVidPnVSyncControl : 1;
2190 UINT Reserved : 28;
2191 };
2192 UINT Value;
2193 };
2194 } D3DKMT_WDDM_2_7_CAPS;
2195
2196 #endif
2197
2198 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_9)
2199
2200 // DXGK_FEATURE_SUPPORT constants
2201
2202 // When a driver doesn't support a feature, it doesn't call into QueryFeatureSupport with that feature ID.
2203 // This value is provided for implementation convenience of enumerating possible driver support states
2204 // for a particular feature.
2205 #define DXGK_FEATURE_SUPPORT_ALWAYS_OFF ((UINT)0)
2206
2207 // Driver support for a feature is in the experimental state
2208 #define DXGK_FEATURE_SUPPORT_EXPERIMENTAL ((UINT)1)
2209
2210 // Driver support for a feature is in the stable state
2211 #define DXGK_FEATURE_SUPPORT_STABLE ((UINT)2)
2212
2213 // Driver support for a feature is in the always on state,
2214 // and it doesn't operate without this feature enabled.
2215 #define DXGK_FEATURE_SUPPORT_ALWAYS_ON ((UINT)3)
2216
2217 typedef struct _D3DKMT_WDDM_2_9_CAPS
2218 {
2219 union
2220 {
2221 struct
2222 {
2223 _Field_range_(DXGK_FEATURE_SUPPORT_ALWAYS_OFF, DXGK_FEATURE_SUPPORT_ALWAYS_ON)
2224 UINT HwSchSupportState : 2; // DXGK_FEATURE_SUPPORT_* value that specifies driver support state for GPU supports hardware scheduling
2225 UINT HwSchEnabled : 1; // Specifies whether the hardware scheduling is currently enabled for this GPU
2226 UINT SelfRefreshMemorySupported : 1; // Specifies whether Self Refresh Memory is supported for this GPU
2227 UINT Reserved : 28;
2228 };
2229 UINT Value;
2230 };
2231 } D3DKMT_WDDM_2_9_CAPS;
2232
2233 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_9)
2234
2235 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM3_0)
2236
2237 typedef struct _D3DKMT_WDDM_3_0_CAPS
2238 {
2239 union
2240 {
2241 struct
2242 {
2243 _Field_range_(DXGK_FEATURE_SUPPORT_ALWAYS_OFF, DXGK_FEATURE_SUPPORT_ALWAYS_ON)
2244 UINT HwFlipQueueSupportState : 2; // DXGK_FEATURE_SUPPORT_* value that specifies driver support state for GPU supports hardware flip queue
2245 UINT HwFlipQueueEnabled : 1; // Specifies whether the hardware flip queue is currently enabled for this GPU
2246 UINT DisplayableSupported : 1; // Specifies whether displayable feature is supported
2247 UINT Reserved : 28;
2248 };
2249 UINT Value;
2250 };
2251 } D3DKMT_WDDM_3_0_CAPS;
2252
2253 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM3_0)
2254
2255
2256 typedef struct _D3DKMT_TRACKEDWORKLOAD_SUPPORT
2257 {
2258 _In_ UINT PhysicalAdapterIndex;
2259 _In_ DXGK_ENGINE_TYPE EngineType;
2260 _Out_ BOOL Support;
2261 } D3DKMT_TRACKEDWORKLOAD_SUPPORT;
2262
2263 typedef struct _D3DKMT_NODEMETADATA
2264 {
2265 _In_ UINT NodeOrdinalAndAdapterIndex; // WDDMv2: High word is physical adapter index, low word is node ordinal
2266 _Out_ DXGK_NODEMETADATA NodeData;
2267 } D3DKMT_NODEMETADATA;
2268
2269 typedef struct _D3DKMT_QUERYCLOCKCALIBRATION
2270 {
2271 D3DKMT_HANDLE hAdapter; // in: The adapter to query clock information for
2272 UINT32 NodeOrdinal; // in: Node ordinal of the requested engine.
2273 UINT32 PhysicalAdapterIndex; // in: The physical adapter index, in an LDA chain
2274 DXGK_GPUCLOCKDATA ClockData; // out: Output frequency, Gpu clock, and Cpu clock on the specified engine
2275 } D3DKMT_QUERYCLOCKCALIBRATION;
2276
2277 typedef enum _DXGK_RENDER_PIPELINE_STAGE
2278 {
2279 DXGK_RENDER_PIPELINE_STAGE_UNKNOWN = 0,
2280 DXGK_RENDER_PIPELINE_STAGE_INPUT_ASSEMBLER = 1,
2281 DXGK_RENDER_PIPELINE_STAGE_VERTEX_SHADER = 2,
2282 DXGK_RENDER_PIPELINE_STAGE_GEOMETRY_SHADER = 3,
2283 DXGK_RENDER_PIPELINE_STAGE_STREAM_OUTPUT = 4,
2284 DXGK_RENDER_PIPELINE_STAGE_RASTERIZER = 5,
2285 DXGK_RENDER_PIPELINE_STAGE_PIXEL_SHADER = 6,
2286 DXGK_RENDER_PIPELINE_STAGE_OUTPUT_MERGER = 7,
2287 } DXGK_RENDER_PIPELINE_STAGE;
2288
2289 typedef enum _DXGK_PAGE_FAULT_FLAGS
2290 {
2291 DXGK_PAGE_FAULT_WRITE = 0x1, // when set, indicates that a write to a GPU virtual address failed
2292 DXGK_PAGE_FAULT_FENCE_INVALID = 0x2, // when set, indicates that a fence value for the packet that generated
2293 // the page fault could not be determined
2294 DXGK_PAGE_FAULT_ADAPTER_RESET_REQUIRED = 0x4, // when set, indicates that the page fault put the GPU in a state that requires a full adapter reset
2295 DXGK_PAGE_FAULT_ENGINE_RESET_REQUIRED = 0x8, // when set, indicates that the page fault put the GPU in a state that requires GPU engine reset
2296 DXGK_PAGE_FAULT_FATAL_HARDWARE_ERROR = 0x10, // when set, indicates that the system hardware, not just the GPU, cannot continue,
2297 // and the OS should issue a bugcheck
2298 DXGK_PAGE_FAULT_IOMMU = 0x20, // when set, indicates that the faulting GPU virtual address was mapped using IoMmu,
2299 // when not set, the faulting GPU virtual address was mapped using GPU memory management unit.
2300
2301 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
2302
2303 DXGK_PAGE_FAULT_HW_CONTEXT_VALID = 0x40, // when set, indicates that the faulting hardware queue was not identified, but faulting HW context was.
2304 DXGK_PAGE_FAULT_PROCESS_HANDLE_VALID = 0x80, // when set, indicates that the faulting hardware queue or context was not identified,
2305 // but process handle that submitted the faulted buffer was.
2306
2307 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
2308
2309 } DXGK_PAGE_FAULT_FLAGS;
2310
2311 typedef enum _DXGK_GENERAL_ERROR_CODE
2312 {
2313 DXGK_GENERAL_ERROR_PAGE_FAULT = 0,
2314 DXGK_GENERAL_ERROR_INVALID_INSTRUCTION = 1,
2315 } DXGK_GENERAL_ERROR_CODE;
2316
2317 typedef struct _DXGK_FAULT_ERROR_CODE
2318 {
2319 union
2320 {
2321 struct
2322 {
2323 UINT IsDeviceSpecificCode : 1; // when set to 1, indicates the low 31 bits correspond to a device specific error code.
2324 // when set to 0, indicates the low 31 bits correspond to a code defined by DXGK_GENERAL_ERROR_CODE.
2325 DXGK_GENERAL_ERROR_CODE GeneralErrorCode : 31; // General error code defined by DXGK_GENERAL_ERROR_CODE.
2326 };
2327 struct
2328 {
2329 UINT IsDeviceSpecificCodeReservedBit : 1; // Same as IsDeviceSpecificCode member above:
2330 // when set to 1, indicates the low 31 bits correspond to a device specific error code.
2331 // when set to 0, indicates the low 31 bits correspond to a code defined by DXGK_GENERAL_ERROR_CODE.
2332 UINT DeviceSpecificCode : 31; // A device specific error code.
2333 };
2334 };
2335 } DXGK_FAULT_ERROR_CODE;
2336
2337 typedef struct _D3DKMT_DRIVERCAPS_EXT
2338 {
2339 union
2340 {
2341 struct
2342 {
2343 UINT VirtualModeSupport : 1;
2344 UINT Usb4MonitorSupport : 1;
2345 UINT Reserved : 30;
2346 };
2347 UINT Value;
2348 };
2349 } D3DKMT_DRIVERCAPS_EXT;
2350
2351 #define DXGK_PRIMITIVE_API_SEQUENCE_NUMBER_UNKNOWN ULONGLONG_MAX
2352 #define DXGK_BIND_TABLE_ENTRY_UNKNOWN UINT_MAX
2353
2354 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_0)
2355
2356
2357 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_1)
2358
2359 typedef union _DXGK_MONITORLINKINFO_USAGEHINTS
2360 {
2361 struct
2362 {
2363 UINT Hidden : 1; // 0x00000001
2364 UINT Reserved :31; // 0xFFFFFFFE
2365 };
2366 UINT Value;
2367 } DXGK_MONITORLINKINFO_USAGEHINTS, *PDXGK_MONITORLINKINFO_USAGEHINTS;
2368
2369 typedef union _DXGK_MONITORLINKINFO_CAPABILITIES
2370 {
2371 struct
2372 {
2373 UINT Stereo : 1; // 0x00000001
2374 UINT WideColorSpace : 1; // 0x00000002
2375 UINT HighColorSpace : 1; // 0x00000004
2376
2377 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
2378 UINT DynamicColorSpace : 1; // 0x00000008
2379 UINT DynamicBitsPerColorChannel : 1; // 0x00000010
2380 UINT DynamicColorEncodingFormat : 1; // 0x00000020
2381 UINT DedicatedTimingGeneration : 1; // 0x00000040
2382 #endif // DXGKDDI_INTERFACE_VERSION_WDDM2_2
2383
2384 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_4)
2385 UINT TargetIndependentPrimary : 1; // 0x00000080
2386 UINT SyncLockIdentical : 1; // 0x00000100
2387 UINT Hdr10Plus : 1; // 0x00000200
2388 #endif // DXGKDDI_INTERFACE_VERSION_WDDM2_4
2389
2390 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5)
2391 UINT DolbyVisionLowLatency : 1; // 0x00000400
2392 #endif // DXGKDDI_INTERFACE_VERSION_WDDM2_5
2393
2394 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_6)
2395 UINT VariableRefresh : 1; // 0x00000800
2396 #endif // DXGKDDI_INTERFACE_VERSION_WDDM2_6
2397
2398 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_6)
2399 UINT Reserved :20; // 0xFFFFF000
2400 #elif (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5)
2401 UINT Reserved :21; // 0xFFFFF800
2402 #elif (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_4)
2403 UINT Reserved :22; // 0xFFFFFC00
2404 #elif (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
2405 UINT Reserved :25; // 0xFFFFFF80
2406 #else
2407 UINT Reserved :29; // 0xFFFFFFF8
2408 #endif // DXGKDDI_INTERFACE_VERSION
2409 };
2410 UINT Value;
2411 } DXGK_MONITORLINKINFO_CAPABILITIES, *PDXGK_MONITORLINKINFO_CAPABILITIES;
2412
2413 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_1)
2414
2415
2416 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
2417
2418 #if defined(__cplusplus) && !defined(SORTPP_PASS)
2419
2420 typedef enum _DXGK_DISPLAY_USAGE : BYTE
2421 {
2422 DXGK_DU_INVALID = 0,
2423 DXGK_DU_GENERIC = 1,
2424 DXGK_DU_AR = 2,
2425 DXGK_DU_VR = 3,
2426 DXGK_DU_MEDICAL_IMAGING = 4,
2427 DXGK_DU_ACCESSORY = 5,
2428 DXGK_DU_MAX = 6
2429 } DXGK_DISPLAY_USAGE, *PDXGK_DISPLAY_USAGE;
2430
2431 typedef enum _DXGK_DISPLAY_TECHNOLOGY : BYTE
2432 {
2433 DXGK_DT_INVALID = 0,
2434 DXGK_DT_OTHER = 1,
2435 DXGK_DT_LCD = 2,
2436 DXGK_DT_OLED = 3,
2437 DXGK_DT_PROJECTOR = 4,
2438 DXGK_DT_MAX = 5
2439 } DXGK_DISPLAY_TECHNOLOGY, *PDXGK_DISPLAY_TECHNOLOGY;
2440
2441 typedef enum _DXGK_DISPLAY_DESCRIPTOR_TYPE: BYTE
2442 {
2443 DXGK_DDT_INVALID = 0,
2444 DXGK_DDT_EDID,
2445 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5)
2446 DXGK_DDT_DISPLAYID,
2447 #endif
2448 } DXGK_DISPLAY_DESCRIPTOR_TYPE, *PDXGK_DISPLAY_DESCRIPTOR_TYPE;
2449
2450 #else
2451 typedef BYTE DXGK_DISPLAY_USAGE;
2452 typedef BYTE DXGK_DISPLAY_TECHNOLOGY;
2453 typedef BYTE DXGK_DISPLAY_DESCRIPTOR_TYPE;
2454 #endif // defined(__cplusplus) && !defined(SORTPP_PASS)
2455
2456 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_2)
2457
2458 #if (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5)
2459
2460 /////////////////////////////////////////////////////////////////////////////////////////////////////////////
2461 // Capabilities, preferences and other information reported by display only capable adapters.
2462
2463 typedef struct _D3DKMT_DISPLAY_CAPS
2464 {
2465 union
2466 {
2467 struct
2468 {
2469 UINT64 PreferPhysicallyContiguous : 1;
2470 UINT64 Reserved : 63;
2471 };
2472 UINT64 Value;
2473 };
2474 } D3DKMT_DISPLAY_CAPS;
2475
2476 #endif // (DXGKDDI_INTERFACE_VERSION >= DXGKDDI_INTERFACE_VERSION_WDDM2_5)
2477
2478 #pragma pack( pop )
2479
2480 #endif // (NTDDI_VERSION >= NTDDI_LONGHORN) || defined(D3DKMDT_SPECIAL_MULTIPLATFORM_TOOL)
2481
2482 #pragma warning(pop)
2483
2484
2485 #endif /* WINAPI_FAMILY_PARTITION(WINAPI_PARTITION_DESKTOP) */
2486 #pragma endregion
2487
2488 #endif /* _D3DKMDT_H */
2489
2490
2491