1 #ifndef _INCLUDE_R_BIN_MACH0_SPECS_H_ 2 #define _INCLUDE_R_BIN_MACH0_SPECS_H_ 3 4 typedef int integer_t; 5 6 // NOTE(eddyb) the following have been slightly modified to work under radare. 7 8 #include "mach0_defines.h" 9 10 // HACK(eddyb) everything below is from the old mach0_specs.h, should replace 11 // with proper original definitions. 12 13 #undef MACH0_ 14 15 #if R_BIN_MACH064 16 #define MACH0_(name) name##_64 17 #else 18 #define MACH0_(name) name 19 #endif 20 21 #define R_BIN_MACH0_SYMBOL_TYPE_EXT 0 22 #define R_BIN_MACH0_SYMBOL_TYPE_LOCAL 1 23 24 struct x86_thread_state32 { 25 ut32 eax; 26 ut32 ebx; 27 ut32 ecx; 28 ut32 edx; 29 ut32 edi; 30 ut32 esi; 31 ut32 ebp; 32 ut32 esp; 33 ut32 ss; 34 ut32 eflags; 35 ut32 eip; 36 ut32 cs; 37 ut32 ds; 38 ut32 es; 39 ut32 fs; 40 ut32 gs; 41 }; 42 43 struct x86_thread_state64 { 44 ut64 rax; 45 ut64 rbx; 46 ut64 rcx; 47 ut64 rdx; 48 ut64 rdi; 49 ut64 rsi; 50 ut64 rbp; 51 ut64 rsp; 52 ut64 r8; 53 ut64 r9; 54 ut64 r10; 55 ut64 r11; 56 ut64 r12; 57 ut64 r13; 58 ut64 r14; 59 ut64 r15; 60 ut64 rip; 61 ut64 rflags; 62 ut64 cs; 63 ut64 fs; 64 ut64 gs; 65 }; 66 67 #define X86_THREAD_STATE32 1 68 #define X86_THREAD_STATE64 4 69 70 struct ppc_thread_state32 { 71 ut32 srr0; /* Instruction address register (PC) */ 72 ut32 srr1; /* Machine state register (supervisor) */ 73 ut32 r0; 74 ut32 r1; 75 ut32 r2; 76 ut32 r3; 77 ut32 r4; 78 ut32 r5; 79 ut32 r6; 80 ut32 r7; 81 ut32 r8; 82 ut32 r9; 83 ut32 r10; 84 ut32 r11; 85 ut32 r12; 86 ut32 r13; 87 ut32 r14; 88 ut32 r15; 89 ut32 r16; 90 ut32 r17; 91 ut32 r18; 92 ut32 r19; 93 ut32 r20; 94 ut32 r21; 95 ut32 r22; 96 ut32 r23; 97 ut32 r24; 98 ut32 r25; 99 ut32 r26; 100 ut32 r27; 101 ut32 r28; 102 ut32 r29; 103 ut32 r30; 104 ut32 r31; 105 106 ut32 cr; /* Condition register */ 107 ut32 xer; /* User's integer exception register */ 108 ut32 lr; /* Link register */ 109 ut32 ctr; /* Count register */ 110 ut32 mq; /* MQ register (601 only) */ 111 112 ut32 vrsave; /* Vector Save Register */ 113 }; 114 115 struct ppc_thread_state64 { 116 ut64 srr0; /* Instruction address register (PC) */ 117 ut64 srr1; /* Machine state register (supervisor) */ 118 ut64 r0; 119 ut64 r1; 120 ut64 r2; 121 ut64 r3; 122 ut64 r4; 123 ut64 r5; 124 ut64 r6; 125 ut64 r7; 126 ut64 r8; 127 ut64 r9; 128 ut64 r10; 129 ut64 r11; 130 ut64 r12; 131 ut64 r13; 132 ut64 r14; 133 ut64 r15; 134 ut64 r16; 135 ut64 r17; 136 ut64 r18; 137 ut64 r19; 138 ut64 r20; 139 ut64 r21; 140 ut64 r22; 141 ut64 r23; 142 ut64 r24; 143 ut64 r25; 144 ut64 r26; 145 ut64 r27; 146 ut64 r28; 147 ut64 r29; 148 ut64 r30; 149 ut64 r31; 150 151 ut32 cr; /* Condition register */ 152 ut64 xer; /* User's integer exception register */ 153 ut64 lr; /* Link register */ 154 ut64 ctr; /* Count register */ 155 156 ut32 vrsave; /* Vector Save Register */ 157 }; 158 159 struct arm_thread_state32 { 160 ut32 r0; 161 ut32 r1; 162 ut32 r2; 163 ut32 r3; 164 ut32 r4; 165 ut32 r5; 166 ut32 r6; 167 ut32 r7; 168 ut32 r8; 169 ut32 r9; 170 ut32 r10; 171 ut32 r11; 172 ut32 r12; 173 ut32 r13; 174 ut32 r14; 175 ut32 r15; 176 ut32 r16; /* Apple's thread_state has this 17th reg, bug?? */ 177 }; 178 179 struct arm_thread_state64 { 180 ut64 x[29]; 181 ut64 fp; 182 ut64 lr; 183 ut64 sp; 184 ut64 pc; 185 ut32 cpsr; 186 }; 187 188 /* Cache header */ 189 190 struct cache_header { 191 char version[16]; 192 ut32 baseaddroff; //mappingOffset 193 ut32 mappingCount; 194 ut32 startaddr; 195 ut32 numlibs; 196 ut64 dyldaddr; 197 ut64 codeSignatureOffset; 198 ut64 codeSignatureSize; 199 ut64 slideInfoOffset; 200 ut64 slideInfoSize; 201 ut64 localSymbolsOffset; 202 ut64 localSymbolsSize; 203 }; 204 205 // dupe? 206 typedef struct { 207 char magic[16]; 208 uint32_t mappingOffset; 209 uint32_t mappingCount; 210 uint32_t imagesOffset; 211 uint32_t imagesCount; 212 uint64_t dyldBaseAddress; 213 uint64_t codeSignatureOffset; 214 uint64_t codeSignatureSize; 215 uint64_t slideInfoOffset; 216 uint64_t slideInfoSize; 217 uint64_t localSymbolsOffset; 218 uint64_t localSymbolsSize; 219 uint8_t uuid[16]; 220 uint64_t cacheType; 221 uint32_t branchPoolsOffset; 222 uint32_t branchPoolsCount; 223 uint64_t accelerateInfoAddr; 224 uint64_t accelerateInfoSize; 225 uint64_t imagesTextOffset; 226 uint64_t imagesTextCount; 227 } cache_hdr_t; 228 229 typedef struct { 230 uint8_t uuid[16]; 231 uint64_t loadAddress; 232 uint32_t textSegmentSize; 233 uint32_t pathOffset; 234 } cache_text_info_t; 235 236 typedef struct { 237 uint64_t address; 238 uint64_t size; 239 uint64_t fileOffset; 240 uint32_t maxProt; 241 uint32_t initProt; 242 } cache_map_t; 243 244 typedef struct { 245 uint64_t address; 246 uint64_t modTime; 247 uint64_t inode; 248 uint32_t pathFileOffset; 249 uint32_t pad; 250 } cache_img_t; 251 252 typedef struct { 253 uint32_t version; 254 uint32_t page_size; 255 uint32_t page_starts_count; 256 uint32_t padding; 257 uint64_t auth_value_add; 258 } cache_slide3_t; 259 260 typedef struct { 261 uint32_t version; 262 uint32_t page_size; 263 uint32_t page_starts_offset; 264 uint32_t page_starts_count; 265 uint32_t page_extras_offset; 266 uint32_t page_extras_count; 267 uint64_t delta_mask; 268 uint64_t value_add; 269 } cache_slide2_t; 270 271 typedef struct { 272 uint32_t version; 273 uint32_t toc_offset; 274 uint32_t toc_count; 275 uint32_t entries_offset; 276 uint32_t entries_count; 277 uint32_t entries_size; 278 } cache_slide1_t; 279 280 typedef struct { 281 uint32_t version; 282 uint32_t imageExtrasCount; 283 uint32_t imagesExtrasOffset; 284 uint32_t bottomUpListOffset; 285 uint32_t dylibTrieOffset; 286 uint32_t dylibTrieSize; 287 uint32_t initializersOffset; 288 uint32_t initializersCount; 289 uint32_t dofSectionsOffset; 290 uint32_t dofSectionsCount; 291 uint32_t reExportListOffset; 292 uint32_t reExportCount; 293 uint32_t depListOffset; 294 uint32_t depListCount; 295 uint32_t rangeTableOffset; 296 uint32_t rangeTableCount; 297 uint64_t dyldSectionAddr; 298 } cache_accel_t; 299 300 typedef struct { 301 uint64_t exportsTrieAddr; 302 uint64_t weakBindingsAddr; 303 uint32_t exportsTrieSize; 304 uint32_t weakBindingsSize; 305 uint32_t dependentsStartArrayIndex; 306 uint32_t reExportsStartArrayIndex; 307 } cache_imgxtr_t; 308 309 typedef struct { 310 uint32_t nlistOffset; 311 uint32_t nlistCount; 312 uint32_t stringsOffset; 313 uint32_t stringsSize; 314 uint32_t entriesOffset; 315 uint32_t entriesCount; 316 } cache_locsym_info_t; 317 318 typedef struct { 319 uint32_t dylibOffset; 320 uint32_t nlistStartIndex; 321 uint32_t nlistCount; 322 } cache_locsym_entry_t; 323 324 typedef struct { 325 uint64_t address; 326 uint64_t size; 327 uint64_t fileOffset; 328 uint64_t slideInfoOffset; 329 uint64_t slideInfoSize; 330 uint64_t unknown; 331 uint32_t maxProt; 332 uint32_t initProt; 333 } cache_mapping_slide; 334 335 #define DYLD_CACHE_SLIDE_PAGE_ATTRS 0xC000 336 #define DYLD_CACHE_SLIDE_PAGE_ATTR_EXTRA 0x8000 337 #define DYLD_CACHE_SLIDE_PAGE_ATTR_NO_REBASE 0x4000 338 #define DYLD_CACHE_SLIDE_PAGE_ATTR_END 0x8000 339 #define DYLD_CACHE_SLIDE_V3_PAGE_ATTR_NO_REBASE 0xFFFF 340 #endif 341