1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that PPC uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 16 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H 17 18 #include "PPC.h" 19 #include "PPCInstrInfo.h" 20 #include "PPCRegisterInfo.h" 21 #include "llvm/CodeGen/CallingConvLower.h" 22 #include "llvm/CodeGen/SelectionDAG.h" 23 #include "llvm/Target/TargetLowering.h" 24 25 namespace llvm { 26 namespace PPCISD { 27 enum NodeType { 28 // Start the numbering where the builtin ops and target ops leave off. 29 FIRST_NUMBER = ISD::BUILTIN_OP_END, 30 31 /// FSEL - Traditional three-operand fsel node. 32 /// 33 FSEL, 34 35 /// FCFID - The FCFID instruction, taking an f64 operand and producing 36 /// and f64 value containing the FP representation of the integer that 37 /// was temporarily in the f64 operand. 38 FCFID, 39 40 /// Newer FCFID[US] integer-to-floating-point conversion instructions for 41 /// unsigned integers and single-precision outputs. 42 FCFIDU, FCFIDS, FCFIDUS, 43 44 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 45 /// operand, producing an f64 value containing the integer representation 46 /// of that FP value. 47 FCTIDZ, FCTIWZ, 48 49 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for 50 /// unsigned integers. 51 FCTIDUZ, FCTIWUZ, 52 53 /// Reciprocal estimate instructions (unary FP ops). 54 FRE, FRSQRTE, 55 56 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 57 // three v4f32 operands and producing a v4f32 result. 58 VMADDFP, VNMSUBFP, 59 60 /// VPERM - The PPC VPERM Instruction. 61 /// 62 VPERM, 63 64 /// The CMPB instruction (takes two operands of i32 or i64). 65 CMPB, 66 67 /// Hi/Lo - These represent the high and low 16-bit parts of a global 68 /// address respectively. These nodes have two operands, the first of 69 /// which must be a TargetGlobalAddress, and the second of which must be a 70 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 71 /// though these are usually folded into other nodes. 72 Hi, Lo, 73 74 TOC_ENTRY, 75 76 /// The following two target-specific nodes are used for calls through 77 /// function pointers in the 64-bit SVR4 ABI. 78 79 /// Like a regular LOAD but additionally taking/producing a flag. 80 LOAD, 81 82 /// Like LOAD (taking/producing a flag), but using r2 as hard-coded 83 /// destination. 84 LOAD_TOC, 85 86 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) 87 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to 88 /// compute an allocation on the stack. 89 DYNALLOC, 90 91 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 92 /// at function entry, used for PIC code. 93 GlobalBaseReg, 94 95 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit 96 /// shift amounts. These nodes are generated by the multi-precision shift 97 /// code. 98 SRL, SRA, SHL, 99 100 /// The combination of sra[wd]i and addze used to implemented signed 101 /// integer division by a power of 2. The first operand is the dividend, 102 /// and the second is the constant shift amount (representing the 103 /// divisor). 104 SRA_ADDZE, 105 106 /// CALL - A direct function call. 107 /// CALL_NOP is a call with the special NOP which follows 64-bit 108 /// SVR4 calls. 109 CALL, CALL_NOP, 110 111 /// CALL_TLS and CALL_NOP_TLS - Versions of CALL and CALL_NOP used 112 /// to access TLS variables. 113 CALL_TLS, CALL_NOP_TLS, 114 115 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 116 /// MTCTR instruction. 117 MTCTR, 118 119 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a 120 /// BCTRL instruction. 121 BCTRL, 122 123 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl 124 /// instruction and the TOC reload required on SVR4 PPC64. 125 BCTRL_LOAD_TOC, 126 127 /// Return with a flag operand, matched by 'blr' 128 RET_FLAG, 129 130 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction. 131 /// This copies the bits corresponding to the specified CRREG into the 132 /// resultant GPR. Bits corresponding to other CR regs are undefined. 133 MFOCRF, 134 135 // FIXME: Remove these once the ANDI glue bug is fixed: 136 /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the 137 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to 138 /// implement truncation of i32 or i64 to i1. 139 ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT, 140 141 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit 142 // target (returns (Lo, Hi)). It takes a chain operand. 143 READ_TIME_BASE, 144 145 // EH_SJLJ_SETJMP - SjLj exception handling setjmp. 146 EH_SJLJ_SETJMP, 147 148 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp. 149 EH_SJLJ_LONGJMP, 150 151 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* 152 /// instructions. For lack of better number, we use the opcode number 153 /// encoding for the OPC field to identify the compare. For example, 838 154 /// is VCMPGTSH. 155 VCMP, 156 157 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the 158 /// altivec VCMP*o instructions. For lack of better number, we use the 159 /// opcode number encoding for the OPC field to identify the compare. For 160 /// example, 838 is VCMPGTSH. 161 VCMPo, 162 163 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This 164 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the 165 /// condition register to branch on, OPC is the branch opcode to use (e.g. 166 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is 167 /// an optional input flag argument. 168 COND_BRANCH, 169 170 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based 171 /// loops. 172 BDNZ, BDZ, 173 174 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding 175 /// towards zero. Used only as part of the long double-to-int 176 /// conversion sequence. 177 FADDRTZ, 178 179 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register. 180 MFFS, 181 182 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and 183 /// reserve indexed. This is used to implement atomic operations. 184 LARX, 185 186 /// STCX = This corresponds to PPC stcx. instrcution: store conditional 187 /// indexed. This is used to implement atomic operations. 188 STCX, 189 190 /// TC_RETURN - A tail call return. 191 /// operand #0 chain 192 /// operand #1 callee (register or absolute) 193 /// operand #2 stack adjustment 194 /// operand #3 optional in flag 195 TC_RETURN, 196 197 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls 198 CR6SET, 199 CR6UNSET, 200 201 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS 202 /// on PPC32. 203 PPC32_GOT, 204 205 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and 206 /// local dynamic TLS on PPC32. 207 PPC32_PICGOT, 208 209 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec 210 /// TLS model, produces an ADDIS8 instruction that adds the GOT 211 /// base to sym\@got\@tprel\@ha. 212 ADDIS_GOT_TPREL_HA, 213 214 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec 215 /// TLS model, produces a LD instruction with base register G8RReg 216 /// and offset sym\@got\@tprel\@l. This completes the addition that 217 /// finds the offset of "sym" relative to the thread pointer. 218 LD_GOT_TPREL_L, 219 220 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS 221 /// model, produces an ADD instruction that adds the contents of 222 /// G8RReg to the thread pointer. Symbol contains a relocation 223 /// sym\@tls which is to be replaced by the thread pointer and 224 /// identifies to the linker that the instruction is part of a 225 /// TLS sequence. 226 ADD_TLS, 227 228 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS 229 /// model, produces an ADDIS8 instruction that adds the GOT base 230 /// register to sym\@got\@tlsgd\@ha. 231 ADDIS_TLSGD_HA, 232 233 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS 234 /// model, produces an ADDI8 instruction that adds G8RReg to 235 /// sym\@got\@tlsgd\@l. 236 ADDI_TLSGD_L, 237 238 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS 239 /// model, produces an ADDIS8 instruction that adds the GOT base 240 /// register to sym\@got\@tlsld\@ha. 241 ADDIS_TLSLD_HA, 242 243 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS 244 /// model, produces an ADDI8 instruction that adds G8RReg to 245 /// sym\@got\@tlsld\@l. 246 ADDI_TLSLD_L, 247 248 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the 249 /// local-dynamic TLS model, produces an ADDIS8 instruction 250 /// that adds X3 to sym\@dtprel\@ha. The Chain operand is needed 251 /// to tie this in place following a copy to %X3 from the result 252 /// of a GET_TLSLD_ADDR. 253 ADDIS_DTPREL_HA, 254 255 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS 256 /// model, produces an ADDI8 instruction that adds G8RReg to 257 /// sym\@got\@dtprel\@l. 258 ADDI_DTPREL_L, 259 260 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded 261 /// during instruction selection to optimize a BUILD_VECTOR into 262 /// operations on splats. This is necessary to avoid losing these 263 /// optimizations due to constant folding. 264 VADD_SPLAT, 265 266 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned 267 /// operand identifies the operating system entry point. 268 SC, 269 270 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little 271 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x 272 /// or stxvd2x instruction. The chain is necessary because the 273 /// sequence replaces a load and needs to provide the same number 274 /// of outputs. 275 XXSWAPD, 276 277 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a 278 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of 279 /// the GPRC input, then stores it through Ptr. Type can be either i16 or 280 /// i32. 281 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, 282 283 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a 284 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, 285 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 286 /// or i32. 287 LBRX, 288 289 /// STFIWX - The STFIWX instruction. The first operand is an input token 290 /// chain, then an f64 value to store, then an address to store it to. 291 STFIWX, 292 293 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point 294 /// load which sign-extends from a 32-bit integer value into the 295 /// destination 64-bit register. 296 LFIWAX, 297 298 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point 299 /// load which zero-extends from a 32-bit integer value into the 300 /// destination 64-bit register. 301 LFIWZX, 302 303 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model, 304 /// produces an ADDIS8 instruction that adds the TOC base register to 305 /// sym\@toc\@ha. 306 ADDIS_TOC_HA, 307 308 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model, 309 /// produces a LD instruction with base register G8RReg and offset 310 /// sym\@toc\@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset. 311 LD_TOC_L, 312 313 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces 314 /// an ADDI8 instruction that adds G8RReg to sym\@toc\@l. 315 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset. 316 ADDI_TOC_L, 317 318 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian. 319 /// Maps directly to an lxvd2x instruction that will be followed by 320 /// an xxswapd. 321 LXVD2X, 322 323 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian. 324 /// Maps directly to an stxvd2x instruction that will be preceded by 325 /// an xxswapd. 326 STXVD2X 327 }; 328 } 329 330 /// Define some predicates that are used for node matching. 331 namespace PPC { 332 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a 333 /// VPKUHUM instruction. 334 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 335 SelectionDAG &DAG); 336 337 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a 338 /// VPKUWUM instruction. 339 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, 340 SelectionDAG &DAG); 341 342 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for 343 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes). 344 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 345 unsigned ShuffleKind, SelectionDAG &DAG); 346 347 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for 348 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes). 349 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, 350 unsigned ShuffleKind, SelectionDAG &DAG); 351 352 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the 353 /// shift amount, otherwise return -1. 354 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, 355 SelectionDAG &DAG); 356 357 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand 358 /// specifies a splat of a single element that is suitable for input to 359 /// VSPLTB/VSPLTH/VSPLTW. 360 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize); 361 362 /// isAllNegativeZeroVector - Returns true if all elements of build_vector 363 /// are -0.0. 364 bool isAllNegativeZeroVector(SDNode *N); 365 366 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the 367 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask. 368 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG); 369 370 /// get_VSPLTI_elt - If this is a build_vector of constants which can be 371 /// formed by using a vspltis[bhw] instruction of the specified element 372 /// size, return the constant being splatted. The ByteSize field indicates 373 /// the number of bytes of each element [124] -> [bhw]. 374 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 375 } 376 377 class PPCSubtarget; 378 class PPCTargetLowering : public TargetLowering { 379 const PPCSubtarget &Subtarget; 380 381 public: 382 explicit PPCTargetLowering(const PPCTargetMachine &TM); 383 384 /// getTargetNodeName() - This method returns the name of a target specific 385 /// DAG node. 386 const char *getTargetNodeName(unsigned Opcode) const override; 387 getScalarShiftAmountTy(EVT LHSTy)388 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; } 389 isCheapToSpeculateCttz()390 bool isCheapToSpeculateCttz() const override { 391 return true; 392 } 393 isCheapToSpeculateCtlz()394 bool isCheapToSpeculateCtlz() const override { 395 return true; 396 } 397 398 /// getSetCCResultType - Return the ISD::SETCC ValueType 399 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override; 400 401 /// Return true if target always beneficiates from combining into FMA for a 402 /// given value type. This must typically return false on targets where FMA 403 /// takes more cycles to execute than FADD. 404 bool enableAggressiveFMAFusion(EVT VT) const override; 405 406 /// getPreIndexedAddressParts - returns true by value, base pointer and 407 /// offset pointer and addressing mode by reference if the node's address 408 /// can be legally represented as pre-indexed load / store address. 409 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 410 SDValue &Offset, 411 ISD::MemIndexedMode &AM, 412 SelectionDAG &DAG) const override; 413 414 /// SelectAddressRegReg - Given the specified addressed, check to see if it 415 /// can be represented as an indexed [r+r] operation. Returns false if it 416 /// can be more efficiently represented with [r+imm]. 417 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, 418 SelectionDAG &DAG) const; 419 420 /// SelectAddressRegImm - Returns true if the address N can be represented 421 /// by a base register plus a signed 16-bit displacement [r+imm], and if it 422 /// is not better represented as reg+reg. If Aligned is true, only accept 423 /// displacements suitable for STD and friends, i.e. multiples of 4. 424 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, 425 SelectionDAG &DAG, bool Aligned) const; 426 427 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be 428 /// represented as an indexed [r+r] operation. 429 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, 430 SelectionDAG &DAG) const; 431 432 Sched::Preference getSchedulingPreference(SDNode *N) const override; 433 434 /// LowerOperation - Provide custom lowering hooks for some operations. 435 /// 436 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 437 438 /// ReplaceNodeResults - Replace the results of node with an illegal result 439 /// type with new values built out of custom code. 440 /// 441 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 442 SelectionDAG &DAG) const override; 443 444 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const; 445 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const; 446 447 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 448 449 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 450 std::vector<SDNode *> *Created) const override; 451 452 unsigned getRegisterByName(const char* RegName, EVT VT) const override; 453 454 void computeKnownBitsForTargetNode(const SDValue Op, 455 APInt &KnownZero, 456 APInt &KnownOne, 457 const SelectionDAG &DAG, 458 unsigned Depth = 0) const override; 459 460 unsigned getPrefLoopAlignment(MachineLoop *ML) const override; 461 462 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord, 463 bool IsStore, bool IsLoad) const override; 464 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord, 465 bool IsStore, bool IsLoad) const override; 466 467 MachineBasicBlock * 468 EmitInstrWithCustomInserter(MachineInstr *MI, 469 MachineBasicBlock *MBB) const override; 470 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 471 MachineBasicBlock *MBB, bool is64Bit, 472 unsigned BinOpcode) const; 473 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI, 474 MachineBasicBlock *MBB, 475 bool is8bit, unsigned Opcode) const; 476 477 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI, 478 MachineBasicBlock *MBB) const; 479 480 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI, 481 MachineBasicBlock *MBB) const; 482 483 ConstraintType 484 getConstraintType(const std::string &Constraint) const override; 485 486 /// Examine constraint string and operand type and determine a weight value. 487 /// The operand object must already have been set up with the operand type. 488 ConstraintWeight getSingleConstraintMatchWeight( 489 AsmOperandInfo &info, const char *constraint) const override; 490 491 std::pair<unsigned, const TargetRegisterClass*> 492 getRegForInlineAsmConstraint(const std::string &Constraint, 493 MVT VT) const override; 494 495 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 496 /// function arguments in the caller parameter area. This is the actual 497 /// alignment, not its logarithm. 498 unsigned getByValTypeAlignment(Type *Ty) const override; 499 500 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 501 /// vector. If it is invalid, don't add anything to Ops. 502 void LowerAsmOperandForConstraint(SDValue Op, 503 std::string &Constraint, 504 std::vector<SDValue> &Ops, 505 SelectionDAG &DAG) const override; 506 507 /// isLegalAddressingMode - Return true if the addressing mode represented 508 /// by AM is legal for this target, for a load/store of the specified type. 509 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override; 510 511 /// isLegalICmpImmediate - Return true if the specified immediate is legal 512 /// icmp immediate, that is the target has icmp instructions which can 513 /// compare a register against the immediate without having to materialize 514 /// the immediate into a register. 515 bool isLegalICmpImmediate(int64_t Imm) const override; 516 517 /// isLegalAddImmediate - Return true if the specified immediate is legal 518 /// add immediate, that is the target has add instructions which can 519 /// add a register and the immediate without having to materialize 520 /// the immediate into a register. 521 bool isLegalAddImmediate(int64_t Imm) const override; 522 523 /// isTruncateFree - Return true if it's free to truncate a value of 524 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in 525 /// register X1 to i32 by referencing its sub-register R1. 526 bool isTruncateFree(Type *Ty1, Type *Ty2) const override; 527 bool isTruncateFree(EVT VT1, EVT VT2) const override; 528 529 bool isZExtFree(SDValue Val, EVT VT2) const override; 530 531 bool isFPExtFree(EVT VT) const override; 532 533 /// \brief Returns true if it is beneficial to convert a load of a constant 534 /// to just the constant itself. 535 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 536 Type *Ty) const override; 537 538 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 539 540 bool getTgtMemIntrinsic(IntrinsicInfo &Info, 541 const CallInst &I, 542 unsigned Intrinsic) const override; 543 544 /// getOptimalMemOpType - Returns the target specific optimal type for load 545 /// and store operations as a result of memset, memcpy, and memmove 546 /// lowering. If DstAlign is zero that means it's safe to destination 547 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 548 /// means there isn't a need to check it against alignment requirement, 549 /// probably because the source does not need to be loaded. If 'IsMemset' is 550 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 551 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 552 /// source is constant so it does not need to be loaded. 553 /// It returns EVT::Other if the type should be determined using generic 554 /// target-independent logic. 555 EVT 556 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 557 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, 558 MachineFunction &MF) const override; 559 560 /// Is unaligned memory access allowed for the given type, and is it fast 561 /// relative to software emulation. 562 bool allowsMisalignedMemoryAccesses(EVT VT, 563 unsigned AddrSpace, 564 unsigned Align = 1, 565 bool *Fast = nullptr) const override; 566 567 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 568 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 569 /// expanded to FMAs when this method returns true, otherwise fmuladd is 570 /// expanded to fmul + fadd. 571 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 572 573 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 574 575 // Should we expand the build vector with shuffles? 576 bool 577 shouldExpandBuildVectorWithShuffles(EVT VT, 578 unsigned DefinedValues) const override; 579 580 /// createFastISel - This method returns a target-specific FastISel object, 581 /// or null if the target does not support "fast" instruction selection. 582 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 583 const TargetLibraryInfo *LibInfo) const override; 584 585 /// \brief Returns true if an argument of type Ty needs to be passed in a 586 /// contiguous block of registers in calling convention CallConv. functionArgumentNeedsConsecutiveRegisters(Type * Ty,CallingConv::ID CallConv,bool isVarArg)587 bool functionArgumentNeedsConsecutiveRegisters( 588 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override { 589 // We support any array type as "consecutive" block in the parameter 590 // save area. The element type defines the alignment requirement and 591 // whether the argument should go in GPRs, FPRs, or VRs if available. 592 // 593 // Note that clang uses this capability both to implement the ELFv2 594 // homogeneous float/vector aggregate ABI, and to avoid having to use 595 // "byval" when passing aggregates that might fully fit in registers. 596 return Ty->isArrayTy(); 597 } 598 599 private: 600 601 struct ReuseLoadInfo { 602 SDValue Ptr; 603 SDValue Chain; 604 SDValue ResChain; 605 MachinePointerInfo MPI; 606 bool IsInvariant; 607 unsigned Alignment; 608 AAMDNodes AAInfo; 609 const MDNode *Ranges; 610 ReuseLoadInfoReuseLoadInfo611 ReuseLoadInfo() : IsInvariant(false), Alignment(0), Ranges(nullptr) {} 612 }; 613 614 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI, 615 SelectionDAG &DAG, 616 ISD::LoadExtType ET = ISD::NON_EXTLOAD) const; 617 void spliceIntoChain(SDValue ResChain, SDValue NewResChain, 618 SelectionDAG &DAG) const; 619 620 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI, 621 SelectionDAG &DAG, SDLoc dl) const; 622 623 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const; 624 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const; 625 626 bool 627 IsEligibleForTailCallOptimization(SDValue Callee, 628 CallingConv::ID CalleeCC, 629 bool isVarArg, 630 const SmallVectorImpl<ISD::InputArg> &Ins, 631 SelectionDAG& DAG) const; 632 633 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, 634 int SPDiff, 635 SDValue Chain, 636 SDValue &LROpOut, 637 SDValue &FPOpOut, 638 bool isDarwinABI, 639 SDLoc dl) const; 640 641 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 642 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 643 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 644 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 645 std::pair<SDValue,SDValue> lowerTLSCall(SDValue Op, SDLoc dl, 646 SelectionDAG &DAG) const; 647 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 648 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 649 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 650 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 651 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 652 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 653 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 654 const PPCSubtarget &Subtarget) const; 655 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, 656 const PPCSubtarget &Subtarget) const; 657 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG, 658 const PPCSubtarget &Subtarget) const; 659 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, 660 const PPCSubtarget &Subtarget) const; 661 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, 662 const PPCSubtarget &Subtarget) const; 663 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 664 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 665 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const; 666 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 667 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const; 668 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 669 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 670 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const; 671 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; 672 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const; 673 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 674 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 675 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 676 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 677 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; 678 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 679 680 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 681 CallingConv::ID CallConv, bool isVarArg, 682 const SmallVectorImpl<ISD::InputArg> &Ins, 683 SDLoc dl, SelectionDAG &DAG, 684 SmallVectorImpl<SDValue> &InVals) const; 685 SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall, 686 bool isVarArg, bool IsPatchPoint, 687 SelectionDAG &DAG, 688 SmallVector<std::pair<unsigned, SDValue>, 8> 689 &RegsToPass, 690 SDValue InFlag, SDValue Chain, 691 SDValue &Callee, 692 int SPDiff, unsigned NumBytes, 693 const SmallVectorImpl<ISD::InputArg> &Ins, 694 SmallVectorImpl<SDValue> &InVals) const; 695 696 SDValue 697 LowerFormalArguments(SDValue Chain, 698 CallingConv::ID CallConv, bool isVarArg, 699 const SmallVectorImpl<ISD::InputArg> &Ins, 700 SDLoc dl, SelectionDAG &DAG, 701 SmallVectorImpl<SDValue> &InVals) const override; 702 703 SDValue 704 LowerCall(TargetLowering::CallLoweringInfo &CLI, 705 SmallVectorImpl<SDValue> &InVals) const override; 706 707 bool 708 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 709 bool isVarArg, 710 const SmallVectorImpl<ISD::OutputArg> &Outs, 711 LLVMContext &Context) const override; 712 713 SDValue 714 LowerReturn(SDValue Chain, 715 CallingConv::ID CallConv, bool isVarArg, 716 const SmallVectorImpl<ISD::OutputArg> &Outs, 717 const SmallVectorImpl<SDValue> &OutVals, 718 SDLoc dl, SelectionDAG &DAG) const override; 719 720 SDValue 721 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG, 722 SDValue ArgVal, SDLoc dl) const; 723 724 SDValue 725 LowerFormalArguments_Darwin(SDValue Chain, 726 CallingConv::ID CallConv, bool isVarArg, 727 const SmallVectorImpl<ISD::InputArg> &Ins, 728 SDLoc dl, SelectionDAG &DAG, 729 SmallVectorImpl<SDValue> &InVals) const; 730 SDValue 731 LowerFormalArguments_64SVR4(SDValue Chain, 732 CallingConv::ID CallConv, bool isVarArg, 733 const SmallVectorImpl<ISD::InputArg> &Ins, 734 SDLoc dl, SelectionDAG &DAG, 735 SmallVectorImpl<SDValue> &InVals) const; 736 SDValue 737 LowerFormalArguments_32SVR4(SDValue Chain, 738 CallingConv::ID CallConv, bool isVarArg, 739 const SmallVectorImpl<ISD::InputArg> &Ins, 740 SDLoc dl, SelectionDAG &DAG, 741 SmallVectorImpl<SDValue> &InVals) const; 742 743 SDValue 744 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff, 745 SDValue CallSeqStart, ISD::ArgFlagsTy Flags, 746 SelectionDAG &DAG, SDLoc dl) const; 747 748 SDValue 749 LowerCall_Darwin(SDValue Chain, SDValue Callee, 750 CallingConv::ID CallConv, 751 bool isVarArg, bool isTailCall, bool IsPatchPoint, 752 const SmallVectorImpl<ISD::OutputArg> &Outs, 753 const SmallVectorImpl<SDValue> &OutVals, 754 const SmallVectorImpl<ISD::InputArg> &Ins, 755 SDLoc dl, SelectionDAG &DAG, 756 SmallVectorImpl<SDValue> &InVals) const; 757 SDValue 758 LowerCall_64SVR4(SDValue Chain, SDValue Callee, 759 CallingConv::ID CallConv, 760 bool isVarArg, bool isTailCall, bool IsPatchPoint, 761 const SmallVectorImpl<ISD::OutputArg> &Outs, 762 const SmallVectorImpl<SDValue> &OutVals, 763 const SmallVectorImpl<ISD::InputArg> &Ins, 764 SDLoc dl, SelectionDAG &DAG, 765 SmallVectorImpl<SDValue> &InVals) const; 766 SDValue 767 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, 768 bool isVarArg, bool isTailCall, bool IsPatchPoint, 769 const SmallVectorImpl<ISD::OutputArg> &Outs, 770 const SmallVectorImpl<SDValue> &OutVals, 771 const SmallVectorImpl<ISD::InputArg> &Ins, 772 SDLoc dl, SelectionDAG &DAG, 773 SmallVectorImpl<SDValue> &InVals) const; 774 775 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 776 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 777 778 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const; 779 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const; 780 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const; 781 782 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI, 783 unsigned &RefinementSteps, 784 bool &UseOneConstNR) const override; 785 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI, 786 unsigned &RefinementSteps) const override; 787 bool combineRepeatedFPDivisors(unsigned NumUsers) const override; 788 789 CCAssignFn *useFastISelCCs(unsigned Flag) const; 790 }; 791 792 namespace PPC { 793 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo, 794 const TargetLibraryInfo *LibInfo); 795 } 796 797 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 798 CCValAssign::LocInfo &LocInfo, 799 ISD::ArgFlagsTy &ArgFlags, 800 CCState &State); 801 802 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, 803 MVT &LocVT, 804 CCValAssign::LocInfo &LocInfo, 805 ISD::ArgFlagsTy &ArgFlags, 806 CCState &State); 807 808 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, 809 MVT &LocVT, 810 CCValAssign::LocInfo &LocInfo, 811 ISD::ArgFlagsTy &ArgFlags, 812 CCState &State); 813 } 814 815 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 816