1 /** @file 2 SPD data format header file. 3 4 Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> 5 SPDX-License-Identifier: BSD-2-Clause-Patent 6 7 **/ 8 9 #ifndef _MrcSpdData_h_ 10 #define _MrcSpdData_h_ 11 #pragma pack (push, 1) 12 13 #include "MrcTypes.h" 14 15 #define MAX_XMP_PROFILES (2) 16 #define SPD3_MANUF_SIZE (SPD3_MANUF_END - SPD3_MANUF_START + 1) ///< The size of the SPD manufacturing data. 17 #define SPD4_MANUF_SIZE (SPD4_MANUF_END - SPD4_MANUF_START + 1) ///< The size of the SPD manufacturing data. 18 #define SPDLP_MANUF_SIZE (SPDLP_MANUF_END - SPDLP_MANUF_START + 1) ///< The size of the SPD manufacturing data 19 20 typedef union { 21 struct { 22 UINT8 BytesUsed : 4; ///< Bits 3:0 23 UINT8 BytesTotal : 3; ///< Bits 6:4 24 UINT8 CrcCoverage : 1; ///< Bits 7:7 25 } Bits; 26 UINT8 Data; 27 } SPD_DEVICE_DESCRIPTION_STRUCT; 28 29 typedef union { 30 struct { 31 UINT8 Minor : 4; ///< Bits 3:0 32 UINT8 Major : 4; ///< Bits 7:4 33 } Bits; 34 UINT8 Data; 35 } SPD_REVISION_STRUCT; 36 37 typedef union { 38 struct { 39 UINT8 Type : 8; ///< Bits 7:0 40 } Bits; 41 UINT8 Data; 42 } SPD_DRAM_DEVICE_TYPE_STRUCT; 43 44 typedef union { 45 struct { 46 UINT8 ModuleType : 4; ///< Bits 3:0 47 UINT8 : 4; ///< Bits 7:4 48 } Bits; 49 UINT8 Data; 50 } SPD_MODULE_TYPE_STRUCT; 51 52 typedef union { 53 struct { 54 UINT8 Density : 4; ///< Bits 3:0 55 UINT8 BankAddress : 3; ///< Bits 6:4 56 UINT8 : 1; ///< Bits 7:7 57 } Bits; 58 UINT8 Data; 59 } SPD_SDRAM_DENSITY_BANKS_STRUCT; 60 61 typedef union { 62 struct { 63 UINT8 ColumnAddress : 3; ///< Bits 2:0 64 UINT8 RowAddress : 3; ///< Bits 5:3 65 UINT8 : 2; ///< Bits 7:6 66 } Bits; 67 UINT8 Data; 68 } SPD_SDRAM_ADDRESSING_STRUCT; 69 70 typedef union { 71 struct { 72 UINT8 OperationAt1_50 : 1; ///< Bits 0:0 73 UINT8 OperationAt1_35 : 1; ///< Bits 1:1 74 UINT8 OperationAt1_25 : 1; ///< Bits 2:2 75 UINT8 : 5; ///< Bits 7:3 76 } Bits; 77 UINT8 Data; 78 } SPD_MODULE_NOMINAL_VOLTAGE_STRUCT; 79 80 typedef union { 81 struct { 82 UINT8 SdramDeviceWidth : 3; ///< Bits 2:0 83 UINT8 RankCount : 3; ///< Bits 5:3 84 UINT8 : 2; ///< Bits 7:6 85 } Bits; 86 UINT8 Data; 87 } SPD_MODULE_ORGANIZATION_STRUCT; 88 89 typedef union { 90 struct { 91 UINT8 PrimaryBusWidth : 3; ///< Bits 2:0 92 UINT8 BusWidthExtension : 2; ///< Bits 4:3 93 UINT8 : 3; ///< Bits 7:5 94 } Bits; 95 UINT8 Data; 96 } SPD_MODULE_MEMORY_BUS_WIDTH_STRUCT; 97 98 typedef union { 99 struct { 100 UINT8 Divisor : 4; ///< Bits 3:0 101 UINT8 Dividend : 4; ///< Bits 7:4 102 } Bits; 103 UINT8 Data; 104 } SPD_FINE_TIMEBASE_STRUCT; 105 106 typedef union { 107 struct { 108 UINT8 Dividend : 8; ///< Bits 7:0 109 } Bits; 110 UINT8 Data; 111 } SPD_MEDIUM_TIMEBASE_DIVIDEND_STRUCT; 112 113 typedef union { 114 struct { 115 UINT8 Divisor : 8; ///< Bits 7:0 116 } Bits; 117 UINT8 Data; 118 } SPD_MEDIUM_TIMEBASE_DIVISOR_STRUCT; 119 120 typedef struct { 121 SPD_MEDIUM_TIMEBASE_DIVIDEND_STRUCT Dividend; ///< Medium Timebase (MTB) Dividend 122 SPD_MEDIUM_TIMEBASE_DIVISOR_STRUCT Divisor; ///< Medium Timebase (MTB) Divisor 123 } SPD_MEDIUM_TIMEBASE; 124 125 typedef union { 126 struct { 127 UINT8 tCKmin : 8; ///< Bits 7:0 128 } Bits; 129 UINT8 Data; 130 } SPD_TCK_MIN_MTB_STRUCT; 131 132 typedef union { 133 struct { 134 UINT16 CL4 : 1; ///< Bits 0:0 135 UINT16 CL5 : 1; ///< Bits 1:1 136 UINT16 CL6 : 1; ///< Bits 2:2 137 UINT16 CL7 : 1; ///< Bits 3:3 138 UINT16 CL8 : 1; ///< Bits 4:4 139 UINT16 CL9 : 1; ///< Bits 5:5 140 UINT16 CL10 : 1; ///< Bits 6:6 141 UINT16 CL11 : 1; ///< Bits 7:7 142 UINT16 CL12 : 1; ///< Bits 8:8 143 UINT16 CL13 : 1; ///< Bits 9:9 144 UINT16 CL14 : 1; ///< Bits 10:10 145 UINT16 CL15 : 1; ///< Bits 11:11 146 UINT16 CL16 : 1; ///< Bits 12:12 147 UINT16 CL17 : 1; ///< Bits 13:13 148 UINT16 CL18 : 1; ///< Bits 14:14 149 UINT16 : 1; ///< Bits 15:15 150 } Bits; 151 UINT16 Data; 152 UINT8 Data8[2]; 153 } SPD_CAS_LATENCIES_SUPPORTED_STRUCT; 154 155 typedef union { 156 struct { 157 UINT8 tAAmin : 8; ///< Bits 7:0 158 } Bits; 159 UINT8 Data; 160 } SPD_TAA_MIN_MTB_STRUCT; 161 162 typedef union { 163 struct { 164 UINT8 tWRmin : 8; ///< Bits 7:0 165 } Bits; 166 UINT8 Data; 167 } SPD_TWR_MIN_MTB_STRUCT; 168 169 typedef union { 170 struct { 171 UINT8 tRCDmin : 8; ///< Bits 7:0 172 } Bits; 173 UINT8 Data; 174 } SPD_TRCD_MIN_MTB_STRUCT; 175 176 typedef union { 177 struct { 178 UINT8 tRRDmin : 8; ///< Bits 7:0 179 } Bits; 180 UINT8 Data; 181 } SPD_TRRD_MIN_MTB_STRUCT; 182 183 typedef union { 184 struct { 185 UINT8 tRPmin : 8; ///< Bits 7:0 186 } Bits; 187 UINT8 Data; 188 } SPD_TRP_MIN_MTB_STRUCT; 189 190 typedef union { 191 struct { 192 UINT8 tRPab : 8; ///< Bits 7:0 193 } Bits; 194 UINT8 Data; 195 } SPD_TRP_AB_MTB_STRUCT; 196 197 typedef union { 198 struct { 199 INT8 tRPabFine : 8; ///< Bits 7:0 200 } Bits; 201 INT8 Data; 202 } SPD_TRP_AB_FTB_STRUCT; 203 204 typedef union { 205 struct { 206 UINT8 tRPpb : 8; ///< Bits 7:0 207 } Bits; 208 UINT8 Data; 209 } SPD_TRP_PB_MTB_STRUCT; 210 211 typedef union { 212 struct { 213 INT8 tRPpbFine : 8; ///< Bits 7:0 214 } Bits; 215 INT8 Data; 216 } SPD_TRP_PB_FTB_STRUCT; 217 218 typedef union { 219 struct { 220 UINT16 tRFCab : 16; ///< Bits 15:0 221 } Bits; 222 UINT16 Data; 223 UINT8 Data8[2]; 224 } SPD_TRFC_AB_MTB_STRUCT; 225 226 typedef union { 227 struct { 228 UINT16 tRFCpb : 16; ///< Bits 15:0 229 } Bits; 230 UINT16 Data; 231 UINT8 Data8[2]; 232 } SPD_TRFC_PB_MTB_STRUCT; 233 234 typedef union { 235 struct { 236 UINT8 tRASminUpper : 4; ///< Bits 3:0 237 UINT8 tRCminUpper : 4; ///< Bits 7:4 238 } Bits; 239 UINT8 Data; 240 } SPD_TRAS_TRC_MIN_MTB_STRUCT; 241 242 typedef union { 243 struct { 244 UINT8 tRASmin : 8; ///< Bits 7:0 245 } Bits; 246 UINT8 Data; 247 } SPD_TRAS_MIN_MTB_STRUCT; 248 249 typedef union { 250 struct { 251 UINT8 tRCmin : 8; ///< Bits 7:0 252 } Bits; 253 UINT8 Data; 254 } SPD_TRC_MIN_MTB_STRUCT; 255 256 typedef union { 257 struct { 258 UINT16 tRFCmin : 16; ///< Bits 15:0 259 } Bits; 260 UINT16 Data; 261 UINT8 Data8[2]; 262 } SPD_TRFC_MIN_MTB_STRUCT; 263 264 typedef union { 265 struct { 266 UINT8 tWTRmin : 8; ///< Bits 7:0 267 } Bits; 268 UINT8 Data; 269 } SPD_TWTR_MIN_MTB_STRUCT; 270 271 typedef union { 272 struct { 273 UINT8 tRTPmin : 8; ///< Bits 7:0 274 } Bits; 275 UINT8 Data; 276 } SPD_TRTP_MIN_MTB_STRUCT; 277 278 typedef union { 279 struct { 280 UINT8 tFAWminUpper : 4; ///< Bits 3:0 281 UINT8 : 4; ///< Bits 7:4 282 } Bits; 283 UINT8 Data; 284 } SPD_TFAW_MIN_MTB_UPPER_STRUCT; 285 286 typedef union { 287 struct { 288 UINT8 tFAWmin : 8; ///< Bits 7:0 289 } Bits; 290 UINT8 Data; 291 } SPD_TFAW_MIN_MTB_STRUCT; 292 293 typedef union { 294 struct { 295 UINT8 tCWLmin : 8; ///< Bits 7:0 296 } Bits; 297 UINT8 Data; 298 } SPD_TCWL_MIN_MTB_STRUCT; 299 300 typedef union { 301 struct { 302 UINT8 NMode : 8; ///< Bits 7:0 303 } Bits; 304 UINT8 Data; 305 } SPD_SYSTEM_COMMAND_RATE_STRUCT; 306 307 typedef union { 308 struct { 309 UINT16 tREFImin : 16; ///< Bits 15:0 310 } Bits; 311 UINT16 Data; 312 UINT8 Data8[2]; 313 } SPD_TREFI_MIN_MTB_STRUCT; 314 315 typedef union { 316 struct { 317 UINT8 RZQ6 : 1; ///< Bits 0:0 318 UINT8 RZQ7 : 1; ///< Bits 1:1 319 UINT8 : 5; ///< Bits 6:2 320 UINT8 DllOff : 1; ///< Bits 7:7 321 } Bits; 322 UINT8 Data; 323 } SPD_SDRAM_OPTIONAL_FEATURES_STRUCT; 324 325 typedef union { 326 struct { 327 UINT8 ExtendedTemperatureRange : 1; ///< Bits 0:0 328 UINT8 ExtendedTemperatureRefreshRate : 1; ///< Bits 1:1 329 UINT8 AutoSelfRefresh : 1; ///< Bits 2:2 330 UINT8 OnDieThermalSensor : 1; ///< Bits 3:3 331 UINT8 : 3; ///< Bits 6:4 332 UINT8 PartialArraySelfRefresh : 1; ///< Bits 7:7 333 } Bits; 334 UINT8 Data; 335 } SPD_SDRAM_THERMAL_REFRESH_STRUCT; 336 337 typedef union { 338 struct { 339 UINT8 ThermalSensorAccuracy : 7; ///< Bits 6:0 340 UINT8 ThermalSensorPresence : 1; ///< Bits 7:7 341 } Bits; 342 UINT8 Data; 343 } SPD_MODULE_THERMAL_SENSOR_STRUCT; 344 345 typedef union { 346 struct { 347 UINT8 NonStandardDeviceDescription : 7; ///< Bits 6:0 348 UINT8 SdramDeviceType : 1; ///< Bits 7:7 349 } Bits; 350 UINT8 Data; 351 } SPD_SDRAM_DEVICE_TYPE_STRUCT; 352 353 typedef union { 354 struct { 355 UINT8 : 8; ///< Bits 7:0 356 } Bits; 357 UINT8 Data; 358 } SPD_AUTO_SELF_REFRESH_PERF_STRUCT; 359 360 typedef union { 361 struct { 362 INT8 tCKminFine : 8; ///< Bits 7:0 363 } Bits; 364 INT8 Data; 365 } SPD_TCK_MIN_FTB_STRUCT; 366 367 typedef union { 368 struct { 369 INT8 tAAminFine : 8; ///< Bits 7:0 370 } Bits; 371 INT8 Data; 372 } SPD_TAA_MIN_FTB_STRUCT; 373 374 typedef union { 375 struct { 376 INT8 tRCDminFine : 8; ///< Bits 7:0 377 } Bits; 378 INT8 Data; 379 } SPD_TRCD_MIN_FTB_STRUCT; 380 381 typedef union { 382 struct { 383 INT8 tRPminFine : 8; ///< Bits 7:0 384 } Bits; 385 INT8 Data; 386 } SPD_TRP_MIN_FTB_STRUCT; 387 388 typedef union { 389 struct { 390 INT8 tRCminFine : 8; ///< Bits 7:0 391 } Bits; 392 INT8 Data; 393 } SPD_TRC_MIN_FTB_STRUCT; 394 395 typedef union { 396 struct { 397 UINT8 tMACencoding : 4; ///< Bits 3:0 398 UINT8 tMAWencoding : 2; ///< Bits 5:4 399 UINT8 Reserved : 2; ///< Bits 7:6 400 } Bits; 401 UINT8 Data; 402 } SPD_PTRR_SUPPORT_STRUCT; 403 404 typedef union { 405 struct { 406 INT8 tRRDminFine : 8; ///< Bits 7:0 407 } Bits; 408 INT8 Data; 409 } SPD_TRRD_MIN_FTB_STRUCT; 410 411 typedef union { 412 struct { 413 UINT8 Height : 5; ///< Bits 4:0 414 UINT8 RawCardExtension : 3; ///< Bits 7:5 415 } Bits; 416 UINT8 Data; 417 } SPD_UNBUF_MODULE_NOMINAL_HEIGHT; 418 419 typedef union { 420 struct { 421 UINT8 FrontThickness : 4; ///< Bits 3:0 422 UINT8 BackThickness : 4; ///< Bits 7:4 423 } Bits; 424 UINT8 Data; 425 } SPD_UNBUF_MODULE_NOMINAL_THICKNESS; 426 427 typedef union { 428 struct { 429 UINT8 Card : 5; ///< Bits 4:0 430 UINT8 Revision : 2; ///< Bits 6:5 431 UINT8 Extension : 1; ///< Bits 7:7 432 } Bits; 433 UINT8 Data; 434 } SPD_UNBUF_REFERENCE_RAW_CARD; 435 436 typedef union { 437 struct { 438 UINT8 MappingRank1 : 1; ///< Bits 0:0 439 UINT8 : 7; ///< Bits 7:1 440 } Bits; 441 UINT8 Data; 442 } SPD_UNBUF_ADDRESS_MAPPING; 443 444 typedef union { 445 struct { 446 UINT8 Height : 5; ///< Bits 4:0 447 UINT8 : 3; ///< Bits 7:5 448 } Bits; 449 UINT8 Data; 450 } SPD_RDIMM_MODULE_NOMINAL_HEIGHT; 451 452 typedef union { 453 struct { 454 UINT8 FrontThickness : 4; ///< Bits 3:0 455 UINT8 BackThickness : 4; ///< Bits 7:4 456 } Bits; 457 UINT8 Data; 458 } SPD_RDIMM_MODULE_NOMINAL_THICKNESS; 459 460 typedef union { 461 struct { 462 UINT8 Card : 5; ///< Bits 4:0 463 UINT8 Revision : 2; ///< Bits 6:5 464 UINT8 Extension : 1; ///< Bits 7:7 465 } Bits; 466 UINT8 Data; 467 } SPD_RDIMM_REFERENCE_RAW_CARD; 468 469 typedef union { 470 struct { 471 UINT8 RegisterCount : 2; ///< Bits 1:0 472 UINT8 DramRowCount : 2; ///< Bits 3:2 473 UINT8 : 4; ///< Bits 7:4 474 } Bits; 475 UINT8 Data; 476 } SPD_RDIMM_MODULE_ATTRIBUTES; 477 478 typedef union { 479 struct { 480 UINT16 ContinuationCount : 7; ///< Bits 6:0 481 UINT16 ContinuationParity : 1; ///< Bits 7:7 482 UINT16 LastNonZeroByte : 8; ///< Bits 15:8 483 } Bits; 484 UINT16 Data; 485 UINT8 Data8[2]; 486 } SPD_MANUFACTURER_ID_CODE; 487 488 typedef struct { 489 UINT8 Year; ///< Year represented in BCD (00h = 2000) 490 UINT8 Week; ///< Year represented in BCD (47h = week 47) 491 } SPD_MANUFACTURING_DATE; 492 493 typedef union { 494 UINT32 Data; 495 UINT16 SerialNumber16[2]; 496 UINT8 SerialNumber8[4]; 497 } SPD_MANUFACTURER_SERIAL_NUMBER; 498 499 typedef struct { 500 UINT8 Location; ///< Module Manufacturing Location 501 } SPD_MANUFACTURING_LOCATION; 502 503 typedef struct { 504 SPD_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code 505 SPD_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location 506 SPD_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255) 507 SPD_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number 508 } SPD_UNIQUE_MODULE_ID; 509 510 typedef union { 511 UINT16 Crc[1]; 512 UINT8 Data8[2]; 513 } SPD_CYCLIC_REDUNDANCY_CODE; 514 515 typedef union { 516 struct { 517 UINT8 ProfileEnable1 : 1; ///< Bits 0:0 518 UINT8 ProfileEnable2 : 1; ///< Bits 1:1 519 UINT8 ProfileConfig1 : 2; ///< Bits 3:2 520 UINT8 ProfileConfig2 : 2; ///< Bits 5:4 521 UINT8 : 2; ///< Bits 7:6 522 } Bits; 523 UINT8 Data; 524 } SPD_XMP_ORG_CONFIG; 525 526 typedef struct { 527 UINT16 XmpId; ///< 176-177 XMP Identification String 528 SPD_XMP_ORG_CONFIG XmpOrgConf; ///< 178 XMP Organization & Configuration 529 SPD_REVISION_STRUCT XmpRevision; ///< 179 XMP Revision 530 SPD_MEDIUM_TIMEBASE MediumTimeBase[MAX_XMP_PROFILES]; ///< 180-183 Medium Timebase (MTB) 531 SPD_FINE_TIMEBASE_STRUCT FineTimeBase; ///< 184 Fine Timebase (FTB) Dividend / Divisor 532 } SPD_EXTREME_MEMORY_PROFILE_HEADER; 533 534 typedef union { 535 struct { 536 UINT8 Decimal : 5; 537 UINT8 Integer : 2; 538 UINT8 : 1; 539 } Bits; 540 UINT8 Data; 541 } SPD_VDD_VOLTAGE_LEVEL_STRUCT; 542 543 typedef union { 544 struct { 545 UINT8 Decimal : 7; 546 UINT8 Integer : 1; 547 } Bits; 548 UINT8 Data; 549 } SPD_VDD_VOLTAGE_LEVEL_STRUCT_2_0; 550 551 typedef union { 552 struct { 553 UINT8 Fine : 2; ///< Bits 1:0 554 UINT8 Medium : 2; ///< Bits 3:2 555 UINT8 : 4; ///< Bits 7:4 556 } Bits; 557 UINT8 Data; 558 } SPD4_TIMEBASE_STRUCT; 559 560 typedef union { 561 struct { 562 UINT32 CL7 : 1; ///< Bits 0:0 563 UINT32 CL8 : 1; ///< Bits 1:1 564 UINT32 CL9 : 1; ///< Bits 2:2 565 UINT32 CL10 : 1; ///< Bits 3:3 566 UINT32 CL11 : 1; ///< Bits 4:4 567 UINT32 CL12 : 1; ///< Bits 5:5 568 UINT32 CL13 : 1; ///< Bits 6:6 569 UINT32 CL14 : 1; ///< Bits 7:7 570 UINT32 CL15 : 1; ///< Bits 8:8 571 UINT32 CL16 : 1; ///< Bits 9:9 572 UINT32 CL17 : 1; ///< Bits 10:10 573 UINT32 CL18 : 1; ///< Bits 11:11 574 UINT32 CL19 : 1; ///< Bits 12:12 575 UINT32 CL20 : 1; ///< Bits 13:13 576 UINT32 CL21 : 1; ///< Bits 14:14 577 UINT32 CL22 : 1; ///< Bits 15:15 578 UINT32 CL23 : 1; ///< Bits 16:16 579 UINT32 CL24 : 1; ///< Bits 17:17 580 UINT32 : 14; ///< Bits 31:18 581 } Bits; 582 UINT32 Data; 583 UINT16 Data16[2]; 584 UINT8 Data8[4]; 585 } SPD4_CAS_LATENCIES_SUPPORTED_STRUCT; 586 587 typedef struct { 588 SPD_VDD_VOLTAGE_LEVEL_STRUCT Vdd; ///< 185, 220 XMP Module VDD Voltage Level 589 SPD_TCK_MIN_MTB_STRUCT tCKmin; ///< 186, 221 XMP SDRAM Minimum Cycle Time (tCKmin) 590 SPD_TAA_MIN_MTB_STRUCT tAAmin; ///< 187, 222 XMP Minimum CAS Latency Time (tAAmin) 591 SPD_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 188-189, 223-224 XMP CAS Latencies Supported, Least Significant Byte 592 SPD_TCWL_MIN_MTB_STRUCT tCWLmin; ///< 190, 225 XMP Minimum CAS Write Latency Time (tCWLmin) 593 SPD_TRP_MIN_MTB_STRUCT tRPmin; ///< 191, 226 XMP Minimum Row Precharge Delay Time (tRPmin) 594 SPD_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 192, 227 XMP Minimum RAS# to CAS# Delay Time (tRCDmin) 595 SPD_TWR_MIN_MTB_STRUCT tWRmin; ///< 193, 228 XMP Minimum Write Recovery Time (tWRmin) 596 SPD_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 194, 229 XMP Upper Nibbles for tRAS and tRC 597 SPD_TRAS_MIN_MTB_STRUCT tRASmin; ///< 195, 230 XMP Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte 598 SPD_TRC_MIN_MTB_STRUCT tRCmin; ///< 196, 231 XMP Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte 599 SPD_TREFI_MIN_MTB_STRUCT tREFImin; ///< 197-198, 232-233 XMP Maximum tREFI Time (Average Periodic Refresh Interval), Least Significant Byte 600 SPD_TRFC_MIN_MTB_STRUCT tRFCmin; ///< 199-200, 234-235 XMP Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte 601 SPD_TRTP_MIN_MTB_STRUCT tRTPmin; ///< 201, 236 XMP Minimum Internal Read to Precharge Command Delay Time (tRTPmin) 602 SPD_TRRD_MIN_MTB_STRUCT tRRDmin; ///< 202, 237 XMP Minimum Row Active to Row Active Delay Time (tRRDmin) 603 SPD_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 203, 238 XMP Upper Nibble for tFAW 604 SPD_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 204, 239 XMP Minimum Four Activate Window Delay Time (tFAWmin) 605 SPD_TWTR_MIN_MTB_STRUCT tWTRmin; ///< 205, 240 XMP Minimum Internal Write to Read Command Delay Time (tWTRmin) 606 UINT8 Reserved1[207 - 206 + 1]; ///< 206-207, 241-242 XMP Reserved 607 SPD_SYSTEM_COMMAND_RATE_STRUCT SystemCmdRate; ///< 208, 243 XMP System ADD/CMD Rate (1N or 2N mode) 608 SPD_AUTO_SELF_REFRESH_PERF_STRUCT AsrPerf; ///< 209, 244 XMP SDRAM Auto Self Refresh Performance (Sub 1x Refresh and IDD6 impact) 609 UINT8 VoltageLevel; ///< 210, 245 XMP Memory Controller Voltage Level 610 SPD_TCK_MIN_FTB_STRUCT tCKminFine; ///< 211, 246 XMP Fine Offset for SDRAM Minimum Cycle Time (tCKmin) 611 SPD_TAA_MIN_FTB_STRUCT tAAminFine; ///< 212, 247 XMP Fine Offset for Minimum CAS Latency Time (tAAmin) 612 SPD_TRP_MIN_FTB_STRUCT tRPminFine; ///< 213, 248 XMP Minimum Row Precharge Delay Time (tRPmin) 613 SPD_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 214, 249 XMP Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) 614 SPD_TRC_MIN_FTB_STRUCT tRCminFine; ///< 215, 250 XMP Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) 615 UINT8 Reserved2[218 - 216 + 1]; ///< 216-218, 251-253 XMP Reserved 616 UINT8 VendorPersonality; ///< 219, 254 XMP Vendor Personality 617 } SPD_EXTREME_MEMORY_PROFILE_DATA; 618 619 typedef struct { 620 SPD_EXTREME_MEMORY_PROFILE_HEADER Header; ///< 176-184 XMP header 621 SPD_EXTREME_MEMORY_PROFILE_DATA Data[MAX_XMP_PROFILES]; ///< 185-254 XMP profiles 622 } SPD_EXTREME_MEMORY_PROFILE; 623 624 typedef struct { 625 UINT16 XmpId; ///< 384-385 XMP Identification String 626 SPD_XMP_ORG_CONFIG XmpOrgConf; ///< 386 XMP Organization & Configuration 627 SPD_REVISION_STRUCT XmpRevision; ///< 387 XMP Revision 628 SPD4_TIMEBASE_STRUCT TimeBase[MAX_XMP_PROFILES]; ///< 388-389 Medium and Fine Timebase 629 UINT8 Reserved[392 - 390 + 1]; ///< 390-392 Reserved 630 } SPD_EXTREME_MEMORY_PROFILE_HEADER_2_0; 631 632 typedef struct { 633 SPD_VDD_VOLTAGE_LEVEL_STRUCT_2_0 Vdd; ///< 393, 440 XMP Module VDD Voltage Level 634 UINT8 Reserved1[395 - 394 + 1]; ///< 394-395, 441-442 XMP Reserved 635 SPD_TCK_MIN_MTB_STRUCT tCKAVGmin; ///< 396, 443 XMP SDRAM Minimum Cycle Time (tCKAVGmin) 636 SPD4_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 397-400, 444-447 XMP CAS Latencies Supported 637 SPD_TAA_MIN_MTB_STRUCT tAAmin; ///< 401, 448 XMP Minimum CAS Latency Time (tAAmin) 638 SPD_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 402, 449 XMP Minimum RAS# to CAS# Delay Time (tRCDmin) 639 SPD_TRP_MIN_MTB_STRUCT tRPmin; ///< 403, 450 XMP Minimum Row Precharge Delay Time (tRPmin) 640 SPD_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 404, 451 XMP Upper Nibbles for tRAS and tRC 641 SPD_TRAS_MIN_MTB_STRUCT tRASmin; ///< 405, 452 XMP Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte 642 SPD_TRC_MIN_MTB_STRUCT tRCmin; ///< 406, 453 XMP Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte 643 SPD_TRFC_MIN_MTB_STRUCT tRFC1min; ///< 407-408, 454-455 XMP Minimum Refresh Recovery Delay Time (tRFC1min) 644 SPD_TRFC_MIN_MTB_STRUCT tRFC2min; ///< 409-410, 456-457 XMP Minimum Refresh Recovery Delay Time (tRFC2min) 645 SPD_TRFC_MIN_MTB_STRUCT tRFC4min; ///< 411-412, 458-459 XMP Minimum Refresh Recovery Delay Time (tRFC4min) 646 SPD_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 413, 460 Upper Nibble for tFAW 647 SPD_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 414, 461 Minimum Four Activate Window Delay Time (tFAWmin) 648 SPD_TRRD_MIN_MTB_STRUCT tRRD_Smin; ///< 415, 462 Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group 649 SPD_TRRD_MIN_MTB_STRUCT tRRD_Lmin; ///< 416, 463 Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group 650 UINT8 Reserved2[424 - 417 + 1]; ///< 417-424, 464-471 XMP Reserved 651 SPD_TRRD_MIN_FTB_STRUCT tRRD_LminFine; ///< 425, 472 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), different bank group 652 SPD_TRRD_MIN_FTB_STRUCT tRRD_SminFine; ///< 426, 473 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), same bank group 653 SPD_TRC_MIN_FTB_STRUCT tRCminFine; ///< 427, 474 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) 654 SPD_TRP_MIN_FTB_STRUCT tRPminFine; ///< 428, 475 Minimum Row Precharge Delay Time (tRPmin) 655 SPD_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 429, 476 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) 656 SPD_TAA_MIN_FTB_STRUCT tAAminFine; ///< 430, 477 Fine Offset for Minimum CAS Latency Time (tAAmin) 657 SPD_TCK_MIN_FTB_STRUCT tCKAVGminFine; ///< 431, 478 Fine Offset for SDRAM Maximum Cycle Time (tCKAVGmin) 658 UINT8 Reserved3[439 - 432 + 1]; ///< 432-439, 479-486 XMP Reserved 659 } SPD_EXTREME_MEMORY_PROFILE_DATA_2_0; 660 661 typedef struct { 662 SPD_EXTREME_MEMORY_PROFILE_HEADER_2_0 Header; ///< 384-392 XMP header 663 SPD_EXTREME_MEMORY_PROFILE_DATA_2_0 Data[MAX_XMP_PROFILES]; ///< 393-486 XMP profiles 664 } SPD_EXTREME_MEMORY_PROFILE_2_0; 665 666 typedef struct { 667 SPD_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2 668 SPD_REVISION_STRUCT Revision; ///< 1 SPD Revision 669 SPD_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type 670 SPD_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type 671 SPD_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks 672 SPD_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing 673 SPD_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 6 Module Nominal Voltage, VDD 674 SPD_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 7 Module Organization 675 SPD_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 8 Module Memory Bus Width 676 SPD_FINE_TIMEBASE_STRUCT FineTimebase; ///< 9 Fine Timebase (FTB) Dividend / Divisor 677 SPD_MEDIUM_TIMEBASE MediumTimebase; ///< 10-11 Medium Timebase (MTB) Dividend 678 SPD_TCK_MIN_MTB_STRUCT tCKmin; ///< 12 SDRAM Minimum Cycle Time (tCKmin) 679 UINT8 Reserved1; ///< 13 Reserved 680 SPD_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 14-15 CAS Latencies Supported 681 SPD_TAA_MIN_MTB_STRUCT tAAmin; ///< 16 Minimum CAS Latency Time (tAAmin) 682 SPD_TWR_MIN_MTB_STRUCT tWRmin; ///< 17 Minimum Write Recovery Time (tWRmin) 683 SPD_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 18 Minimum RAS# to CAS# Delay Time (tRCDmin) 684 SPD_TRRD_MIN_MTB_STRUCT tRRDmin; ///< 19 Minimum Row Active to Row Active Delay Time (tRRDmin) 685 SPD_TRP_MIN_MTB_STRUCT tRPmin; ///< 20 Minimum Row Precharge Delay Time (tRPmin) 686 SPD_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 21 Upper Nibbles for tRAS and tRC 687 SPD_TRAS_MIN_MTB_STRUCT tRASmin; ///< 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte 688 SPD_TRC_MIN_MTB_STRUCT tRCmin; ///< 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte 689 SPD_TRFC_MIN_MTB_STRUCT tRFCmin; ///< 24-25 Minimum Refresh Recovery Delay Time (tRFCmin) 690 SPD_TWTR_MIN_MTB_STRUCT tWTRmin; ///< 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) 691 SPD_TRTP_MIN_MTB_STRUCT tRTPmin; ///< 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) 692 SPD_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 28 Upper Nibble for tFAW 693 SPD_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 29 Minimum Four Activate Window Delay Time (tFAWmin) 694 SPD_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 30 SDRAM Optional Features 695 SPD_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 31 SDRAMThermalAndRefreshOptions 696 SPD_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 32 Module Thermal Sensor 697 SPD_SDRAM_DEVICE_TYPE_STRUCT SdramDeviceType; ///< 33 SDRAM Device Type 698 SPD_TCK_MIN_FTB_STRUCT tCKminFine; ///< 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) 699 SPD_TAA_MIN_FTB_STRUCT tAAminFine; ///< 35 Fine Offset for Minimum CAS Latency Time (tAAmin) 700 SPD_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) 701 SPD_TRP_MIN_FTB_STRUCT tRPminFine; ///< 37 Minimum Row Precharge Delay Time (tRPmin) 702 SPD_TRC_MIN_FTB_STRUCT tRCminFine; ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) 703 SPD_TRP_AB_MTB_STRUCT tRPab; ///< 39 Minimum Row Precharge Delay Time for all banks (tRPab) 704 SPD_TRP_AB_FTB_STRUCT tRPabFine; ///< 40 Fine Offset for Minimum Row Precharge Delay Time for all banks (tRPab) 705 SPD_PTRR_SUPPORT_STRUCT pTRRsupport; ///< 41 - pTRR support with TMAC value 706 UINT8 Reserved3[59 - 42 + 1]; ///< 42 - 59 Reserved 707 } SPD_GENERAL_SECTION; 708 709 typedef struct { 710 SPD_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height 711 SPD_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness 712 SPD_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used 713 SPD_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 63 Address Mapping from Edge Connector to DRAM 714 UINT8 Reserved[116 - 64 + 1]; ///< 64-116 Reserved 715 } SPD_MODULE_UNBUFFERED; 716 717 typedef struct { 718 SPD_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height 719 SPD_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness 720 SPD_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used 721 SPD_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 DIMM Module Attributes 722 UINT8 Reserved[116 - 64 + 1]; ///< 64-116 Reserved 723 } SPD_MODULE_REGISTERED; 724 725 typedef union { 726 SPD_MODULE_UNBUFFERED Unbuffered; 727 SPD_MODULE_REGISTERED Registered; 728 } SPD_MODULE_SPECIFIC; 729 730 typedef struct { 731 UINT8 ModulePartNumber[145 - 128 + 1]; ///< 128-145 Module Part Number 732 } SPD_MODULE_PART_NUMBER; 733 734 typedef struct { 735 UINT8 ModuleRevisionCode[147 - 146 + 1]; ///< 146-147 Module Revision Code 736 } SPD_MODULE_REVISION_CODE; 737 738 typedef struct { 739 UINT8 ManufactureSpecificData[175 - 150 + 1]; ///< 150-175 Manufacturer's Specific Data 740 } SPD_MANUFACTURE_SPECIFIC; 741 742 /// 743 /// DDR3 Serial Presence Detect structure 744 /// 745 typedef struct { 746 SPD_GENERAL_SECTION General; ///< 0-59 General Section 747 SPD_MODULE_SPECIFIC Module; ///< 60-116 Module-Specific Section 748 SPD_UNIQUE_MODULE_ID ModuleId; ///< 117-125 Unique Module ID 749 SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC) 750 SPD_MODULE_PART_NUMBER ModulePartNumber; ///< 128-145 Module Part Number 751 SPD_MODULE_REVISION_CODE ModuleRevisionCode; ///< 146-147 Module Revision Code 752 SPD_MANUFACTURER_ID_CODE DramIdCode; ///< 148-149 Dram Manufacturer ID Code 753 SPD_MANUFACTURE_SPECIFIC ManufactureSpecificData; ///< 150-175 Manufacturer's Specific Data 754 SPD_EXTREME_MEMORY_PROFILE Xmp; ///< 176-254 Intel(r) Extreme Memory Profile support 755 UINT8 Reserved; ///< 255 Reserved 756 } MrcSpdDdr3; 757 758 typedef union { 759 struct { 760 UINT8 Density : 4; ///< Bits 3:0 761 UINT8 BankAddress : 2; ///< Bits 5:4 762 UINT8 BankGroup : 2; ///< Bits 7:6 763 } Bits; 764 UINT8 Data; 765 } SPD4_SDRAM_DENSITY_BANKS_STRUCT; 766 767 typedef union { 768 struct { 769 UINT8 SignalLoading : 2; ///< Bits 1:0 770 UINT8 : 2; ///< Bits 3:2 771 UINT8 DieCount : 3; ///< Bits 6:4 772 UINT8 SdramDeviceType : 1; ///< Bits 7:7 773 } Bits; 774 UINT8 Data; 775 } SPD4_SDRAM_DEVICE_TYPE_STRUCT; 776 777 typedef union { 778 struct { 779 UINT8 OperationAt1_20 : 1; ///< Bits 0:0 780 UINT8 EndurantAt1_20 : 1; ///< Bits 1:1 781 UINT8 : 6; ///< Bits 7:2 782 } Bits; 783 UINT8 Data; 784 } SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT; 785 786 typedef union { 787 struct { 788 UINT8 tCKmax : 8; ///< Bits 7:0 789 } Bits; 790 UINT8 Data; 791 } SPD4_TCK_MAX_MTB_STRUCT; 792 793 typedef union { 794 struct { 795 INT8 tCKmaxFine : 8; ///< Bits 7:0 796 } Bits; 797 INT8 Data; 798 } SPD4_TCK_MAX_FTB_STRUCT; 799 800 typedef union { 801 struct { 802 UINT8 : 8; ///< Bits 7:0 803 } Bits; 804 UINT8 Data; 805 } SPD4_SDRAM_THERMAL_REFRESH_STRUCT; 806 807 typedef union { 808 struct { 809 UINT8 Height : 5; ///< Bits 4:0 810 UINT8 RawCardExtension : 3; ///< Bits 7:5 811 } Bits; 812 UINT8 Data; 813 } SPD4_UNBUF_MODULE_NOMINAL_HEIGHT; 814 815 typedef union { 816 struct { 817 UINT8 Height : 5; ///< Bits 4:0 818 UINT8 RawCardExtension : 3; ///< Bits 7:5 819 } Bits; 820 UINT8 Data; 821 } SPD4_RDIMM_MODULE_NOMINAL_HEIGHT; 822 823 typedef struct { 824 SPD_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2 825 SPD_REVISION_STRUCT Revision; ///< 1 SPD Revision 826 SPD_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type 827 SPD_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type 828 SPD4_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks 829 SPD_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing 830 SPD4_SDRAM_DEVICE_TYPE_STRUCT SdramDeviceType; ///< 6 SDRAM Device Type 831 SPD_PTRR_SUPPORT_STRUCT pTRRsupport; ///< 7 pTRR support with TMAC value 832 SPD4_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options 833 UINT8 Reserved0[10 - 9 + 1]; ///< 9-10 Reserved 834 SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD 835 SPD_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization 836 SPD_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width 837 SPD_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor 838 UINT8 Reserved1[16 - 15 + 1]; ///< 15-16 Reserved 839 SPD4_TIMEBASE_STRUCT Timebase; ///< 17 Timebases 840 SPD_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin) 841 SPD4_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax) 842 SPD4_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported 843 SPD_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin) 844 SPD_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 25 Minimum RAS# to CAS# Delay Time (tRCDmin) 845 SPD_TRP_MIN_MTB_STRUCT tRPmin; ///< 26 Minimum Row Precharge Delay Time (tRPmin) 846 SPD_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 27 Upper Nibbles for tRAS and tRC 847 SPD_TRAS_MIN_MTB_STRUCT tRASmin; ///< 28 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte 848 SPD_TRC_MIN_MTB_STRUCT tRCmin; ///< 29 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte 849 SPD_TRFC_MIN_MTB_STRUCT tRFC1min; ///< 30-31 Minimum Refresh Recovery Delay Time (tRFC1min) 850 SPD_TRFC_MIN_MTB_STRUCT tRFC2min; ///< 32-33 Minimum Refresh Recovery Delay Time (tRFC2min) 851 SPD_TRFC_MIN_MTB_STRUCT tRFC4min; ///< 34-35 Minimum Refresh Recovery Delay Time (tRFC4min) 852 SPD_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 36 Upper Nibble for tFAW 853 SPD_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 37 Minimum Four Activate Window Delay Time (tFAWmin) 854 SPD_TRRD_MIN_MTB_STRUCT tRRD_Smin; ///< 38 Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group 855 SPD_TRRD_MIN_MTB_STRUCT tRRD_Lmin; ///< 39 Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group 856 UINT8 Reserved2[117 - 40 + 1]; ///< 40-117 Reserved 857 SPD_TRRD_MIN_FTB_STRUCT tRRD_LminFine; ///< 118 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), different bank group 858 SPD_TRRD_MIN_FTB_STRUCT tRRD_SminFine; ///< 119 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), same bank group 859 SPD_TRC_MIN_FTB_STRUCT tRCminFine; ///< 120 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) 860 SPD_TRP_MIN_FTB_STRUCT tRPminFine; ///< 121 Minimum Row Precharge Delay Time (tRPmin) 861 SPD_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) 862 SPD_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin) 863 SPD4_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax) 864 SPD_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Maximum Cycle Time (tCKmin) 865 SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC) 866 } SPD4_BASE_SECTION; 867 868 typedef struct { 869 SPD4_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height 870 SPD_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness 871 SPD_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used 872 SPD_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 131 Address Mapping from Edge Connector to DRAM 873 UINT8 Reserved[253 - 132 + 1]; ///< 132-253 Reserved 874 SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC) 875 } SPD4_MODULE_UNBUFFERED; 876 877 typedef struct { 878 SPD4_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height 879 SPD_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness 880 SPD_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used 881 SPD_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 DIMM Module Attributes 882 UINT8 Reserved[253 - 132 + 1]; ///< 253-132 Reserved 883 SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC) 884 } SPD4_MODULE_REGISTERED; 885 886 typedef union { 887 SPD4_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types 888 SPD4_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types 889 } SPD4_MODULE_SPECIFIC; 890 891 typedef struct { 892 UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number 893 } SPD4_MODULE_PART_NUMBER; 894 895 typedef struct { 896 UINT8 ManufactureSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data 897 } SPD4_MANUFACTURE_SPECIFIC; 898 899 typedef UINT8 SPD4_MODULE_REVISION_CODE;///< 349 Module Revision Code 900 typedef UINT8 SPD4_DRAM_STEPPING; ///< 352 Dram Stepping 901 902 typedef struct { 903 SPD_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID 904 SPD4_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number 905 SPD4_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code 906 SPD_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code 907 SPD4_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping 908 SPD4_MANUFACTURE_SPECIFIC ManufactureSpecificData; ///< 353-381 Manufacturer's Specific Data 909 SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 382-383 Cyclical Redundancy Code (CRC) 910 } SPD4_MANUFACTURING_DATA; 911 912 typedef union { 913 SPD_EXTREME_MEMORY_PROFILE_2_0 Xmp; ///< 384-463 Intel(r) Extreme Memory Profile support 914 UINT8 Reserved0[511 - 384 + 1]; ///< 384-511 Unbuffered Memory Module Types 915 } SPD4_END_USER_SECTION; 916 917 /// 918 /// DDR4 Serial Presence Detect structure 919 /// 920 typedef struct { 921 SPD4_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters 922 SPD4_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section 923 UINT8 Reserved0[319 - 256 + 1]; ///< 256-319 Reserved 924 SPD4_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information 925 SPD4_END_USER_SECTION EndUser; ///< 384-511 End User Programmable 926 } MrcSpdDdr4; 927 928 typedef union { 929 struct { 930 UINT8 Fine : 2; ///< Bits 1:0 931 UINT8 Medium : 2; ///< Bits 3:2 932 UINT8 : 4; ///< Bits 7:4 933 } Bits; 934 UINT8 Data; 935 } SPD_LPDDR_TIMEBASE_STRUCT; 936 937 typedef union { 938 struct { 939 UINT32 CL3 : 1; ///< Bits 0:0 940 UINT32 CL6 : 1; ///< Bits 1:1 941 UINT32 CL8 : 1; ///< Bits 2:2 942 UINT32 CL9 : 1; ///< Bits 3:3 943 UINT32 CL10 : 1; ///< Bits 4:4 944 UINT32 CL11 : 1; ///< Bits 5:5 945 UINT32 CL12 : 1; ///< Bits 6:6 946 UINT32 CL14 : 1; ///< Bits 7:7 947 UINT32 CL16 : 1; ///< Bits 8:8 948 UINT32 : 1; ///< Bits 9:9 949 UINT32 CL20 : 1; ///< Bits 10:10 950 UINT32 CL22 : 1; ///< Bits 11:11 951 UINT32 CL24 : 1; ///< Bits 12:12 952 UINT32 : 1; ///< Bits 13:13 953 UINT32 CL28 : 1; ///< Bits 14:14 954 UINT32 : 1; ///< Bits 15:15 955 UINT32 CL32 : 1; ///< Bits 16:16 956 UINT32 : 1; ///< Bits 17:17 957 UINT32 CL36 : 1; ///< Bits 18:18 958 UINT32 : 1; ///< Bits 19:19 959 UINT32 CL40 : 1; ///< Bits 20:20 960 UINT32 : 11; ///< Bits 31:21 961 } Bits; 962 UINT32 Data; 963 UINT16 Data16[2]; 964 UINT8 Data8[4]; 965 } SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT; 966 967 typedef union { 968 struct { 969 UINT8 Density : 4; ///< Bits 3:0 970 UINT8 BankAddress : 2; ///< Bits 5:4 971 UINT8 BankGroup : 2; ///< Bits 7:6 972 } Bits; 973 UINT8 Data; 974 } SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT; 975 976 typedef union { 977 struct { 978 UINT8 SignalLoading : 2; ///< Bits 1:0 979 UINT8 ChannelsPerDie : 2; ///< Bits 3:2 980 UINT8 DieCount : 3; ///< Bits 6:4 981 UINT8 SdramPackageType : 1; ///< Bits 7:7 982 } Bits; 983 UINT8 Data; 984 } SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT; 985 986 typedef union { 987 struct { 988 UINT8 OperationAt1_20 : 1; ///< Bits 0:0 989 UINT8 EndurantAt1_20 : 1; ///< Bits 1:1 990 UINT8 OperationAt1_10 : 1; ///< Bits 2:2 991 UINT8 EndurantAt1_10 : 1; ///< Bits 3:3 992 UINT8 OperationAtTBD2V : 1; ///< Bits 4:4 993 UINT8 EndurantAtTBD2V : 1; ///< Bits 5:5 994 UINT8 : 2; ///< Bits 7:6 995 } Bits; 996 UINT8 Data; 997 } SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT; 998 999 typedef union { 1000 struct { 1001 UINT8 tCKmax : 8; ///< Bits 7:0 1002 } Bits; 1003 UINT8 Data; 1004 } SPD_LPDDR_TCK_MAX_MTB_STRUCT; 1005 1006 typedef union { 1007 struct { 1008 UINT8 ReadLatencyMode : 2; ///< Bits 1:0 1009 UINT8 WriteLatencySet : 2; ///< Bits 3:2 1010 UINT8 : 4; ///< Bits 7:4 1011 } Bits; 1012 UINT8 Data; 1013 } SPD_LPDDR_RW_LATENCY_OPTION_STRUCT; 1014 1015 typedef union { 1016 struct { 1017 INT8 tCKmaxFine : 8; ///< Bits 7:0 1018 } Bits; 1019 INT8 Data; 1020 } SPD_LPDDR_TCK_MAX_FTB_STRUCT; 1021 1022 typedef union { 1023 struct { 1024 UINT8 : 8; ///< Bits 7:0 1025 } Bits; 1026 UINT8 Data; 1027 } SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT; 1028 1029 typedef union { 1030 struct { 1031 UINT8 Height : 5; ///< Bits 4:0 1032 UINT8 RawCardExtension : 3; ///< Bits 7:5 1033 } Bits; 1034 UINT8 Data; 1035 } SPD_LPDDR_UNBUF_MODULE_NOMINAL_HEIGHT; 1036 1037 typedef union { 1038 struct { 1039 UINT8 Height : 5; ///< Bits 4:0 1040 UINT8 RawCardExtension : 3; ///< Bits 7:5 1041 } Bits; 1042 UINT8 Data; 1043 } SPD_LPDDR_RDIMM_MODULE_NOMINAL_HEIGHT; 1044 1045 typedef struct { 1046 SPD_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2 1047 SPD_REVISION_STRUCT Revision; ///< 1 SPD Revision 1048 SPD_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type 1049 SPD_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type 1050 SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks 1051 SPD_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing 1052 SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT SdramPackageType; ///< 6 SDRAM Package Type 1053 SPD_PTRR_SUPPORT_STRUCT pTRRsupport; ///< 7 pTRR support with TMAC value - SDRAM Optional Features 1054 SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options 1055 UINT8 Reserved0[10 - 9 + 1]; ///< 9-10 Reserved 1056 SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD 1057 SPD_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization 1058 SPD_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width 1059 SPD_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor 1060 UINT8 Reserved1[16 - 15 + 1]; ///< 15-16 Reserved 1061 SPD_LPDDR_TIMEBASE_STRUCT Timebase; ///< 17 Timebases 1062 SPD_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin) 1063 SPD_LPDDR_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax) 1064 SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported 1065 SPD_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin) 1066 SPD_LPDDR_RW_LATENCY_OPTION_STRUCT LatencySetOptions; ///< 25 Read and Write Latency Set Options 1067 SPD_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin) 1068 SPD_TRP_AB_MTB_STRUCT tRPab; ///< 27 Minimum Row Precharge Delay Time (tRPab), all banks 1069 SPD_TRP_PB_MTB_STRUCT tRPpb; ///< 28 Minimum Row Precharge Delay Time (tRPpb), per bank 1070 SPD_TRFC_AB_MTB_STRUCT tRFCab; ///< 29-30 Minimum Refresh Recovery Delay Time (tRFCab), all banks 1071 SPD_TRFC_PB_MTB_STRUCT tRFCpb; ///< 31-32 Minimum Refresh Recovery Delay Time (tRFCpb), per bank 1072 UINT8 Reserved2[119 - 33 + 1]; ///< 33-119 Reserved 1073 SPD_TRP_PB_FTB_STRUCT tRPpbFine; ///< 120 Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per bank 1074 SPD_TRP_AB_FTB_STRUCT tRPabFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all ranks 1075 SPD_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) 1076 SPD_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin) 1077 SPD_LPDDR_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Maximum Cycle Time (tCKmax) 1078 SPD_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) 1079 SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC) 1080 } SPD_LPDDR_BASE_SECTION; 1081 1082 typedef union { 1083 struct { 1084 UINT8 FrontThickness : 4; ///< Bits 3:0 1085 UINT8 BackThickness : 4; ///< Bits 7:4 1086 } Bits; 1087 UINT8 Data; 1088 } SPD_LPDDR_MODULE_MAXIMUM_THICKNESS; 1089 1090 typedef union { 1091 struct { 1092 UINT8 Height : 5; ///< Bits 4:0 1093 UINT8 RawCardExtension : 3; ///< Bits 7:5 1094 } Bits; 1095 UINT8 Data; 1096 } SPD_LPDDR_MODULE_NOMINAL_HEIGHT; 1097 1098 typedef union { 1099 struct { 1100 UINT8 Card : 5; ///< Bits 4:0 1101 UINT8 Revision : 2; ///< Bits 6:5 1102 UINT8 Extension : 1; ///< Bits 7:7 1103 } Bits; 1104 UINT8 Data; 1105 } SPD_LPDDR_REFERENCE_RAW_CARD; 1106 1107 typedef struct { 1108 SPD_LPDDR_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height 1109 SPD_LPDDR_MODULE_MAXIMUM_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness 1110 SPD_LPDDR_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used 1111 UINT8 Reserved[253 - 131 + 1]; ///< 131-253 Reserved 1112 SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC) 1113 } SPD_LPDDR_MODULE_LPDIMM; 1114 1115 typedef union { 1116 SPD_LPDDR_MODULE_LPDIMM LpDimm; ///< 128-255 Unbuffered Memory Module Types 1117 } SPD_LPDDR_MODULE_SPECIFIC; 1118 1119 typedef struct { 1120 UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number 1121 } SPD_LPDDR_MODULE_PART_NUMBER; 1122 1123 typedef struct { 1124 UINT8 ManufactureSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data 1125 } SPD_LPDDR_MANUFACTURE_SPECIFIC; 1126 1127 typedef UINT8 SPD_LPDDR_MODULE_REVISION_CODE;///< 349 Module Revision Code 1128 typedef UINT8 SPD_LPDDR_DRAM_STEPPING; ///< 352 Dram Stepping 1129 1130 typedef struct { 1131 SPD_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID 1132 SPD_LPDDR_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number 1133 SPD_LPDDR_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code 1134 SPD_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code 1135 SPD_LPDDR_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping 1136 SPD_LPDDR_MANUFACTURE_SPECIFIC ManufactureSpecificData; ///< 353-381 Manufacturer's Specific Data 1137 UINT8 Reserved[383 - 382 + 1]; ///< 382-383 Reserved 1138 } SPD_LPDDR_MANUFACTURING_DATA; 1139 1140 typedef union { 1141 UINT8 Reserved0[511 - 384 + 1]; ///< 384-511 End User Programmable 1142 } SPD_LPDDR_END_USER_SECTION; 1143 1144 typedef struct { 1145 SPD_LPDDR_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters 1146 SPD_LPDDR_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section 1147 UINT8 Reserved0[319 - 256 + 1]; ///< 256-319 Reserved 1148 SPD_LPDDR_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information 1149 SPD_LPDDR_END_USER_SECTION EndUser; ///< 384-511 End User Programmable 1150 } MrcSpdLpDdr; 1151 1152 typedef union { 1153 MrcSpdDdr3 Ddr3; 1154 MrcSpdDdr4 Ddr4; 1155 MrcSpdLpDdr Lpddr; 1156 } MrcSpd; 1157 1158 #ifndef MAX_SPD_SAVE 1159 #define MAX_SPD_SAVE (sizeof (SPD_MANUFACTURER_ID_CODE) + \ 1160 sizeof (SPD_MANUFACTURING_LOCATION) + \ 1161 sizeof (SPD_MANUFACTURING_DATE) + \ 1162 sizeof (SPD_MANUFACTURER_SERIAL_NUMBER) + \ 1163 sizeof (SPD4_MODULE_PART_NUMBER)) 1164 #endif 1165 1166 #pragma pack (pop) 1167 #endif // _MrcSpdData_h_ 1168