1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the MCOperandInfo and MCInstrDesc classes, which 10 // are used to describe target instructions and their operands. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_MC_MCINSTRDESC_H 15 #define LLVM_MC_MCINSTRDESC_H 16 17 #include "llvm/MC/MCRegisterInfo.h" 18 #include "llvm/Support/DataTypes.h" 19 #include <string> 20 21 namespace llvm { 22 23 class MCInst; 24 25 //===----------------------------------------------------------------------===// 26 // Machine Operand Flags and Description 27 //===----------------------------------------------------------------------===// 28 29 namespace MCOI { 30 // Operand constraints 31 enum OperandConstraint { 32 TIED_TO = 0, // Must be allocated the same register as. 33 EARLY_CLOBBER // Operand is an early clobber register operand 34 }; 35 36 /// These are flags set on operands, but should be considered 37 /// private, all access should go through the MCOperandInfo accessors. 38 /// See the accessors for a description of what these are. 39 enum OperandFlags { 40 LookupPtrRegClass = 0, 41 Predicate, 42 OptionalDef, 43 BranchTarget, 44 TrapsIfSealedCapability, 45 }; 46 47 /// Operands are tagged with one of the values of this enum. 48 enum OperandType { 49 OPERAND_UNKNOWN = 0, 50 OPERAND_IMMEDIATE = 1, 51 OPERAND_REGISTER = 2, 52 OPERAND_MEMORY = 3, 53 OPERAND_PCREL = 4, 54 55 OPERAND_FIRST_GENERIC = 6, 56 OPERAND_GENERIC_0 = 6, 57 OPERAND_GENERIC_1 = 7, 58 OPERAND_GENERIC_2 = 8, 59 OPERAND_GENERIC_3 = 9, 60 OPERAND_GENERIC_4 = 10, 61 OPERAND_GENERIC_5 = 11, 62 OPERAND_LAST_GENERIC = 11, 63 64 OPERAND_FIRST_GENERIC_IMM = 12, 65 OPERAND_GENERIC_IMM_0 = 12, 66 OPERAND_LAST_GENERIC_IMM = 12, 67 68 OPERAND_FIRST_TARGET = 13, 69 }; 70 71 } 72 73 /// This holds information about one operand of a machine instruction, 74 /// indicating the register class for register operands, etc. 75 class MCOperandInfo { 76 public: 77 /// This specifies the register class enumeration of the operand 78 /// if the operand is a register. If isLookupPtrRegClass is set, then this is 79 /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to 80 /// get a dynamic register class. 81 int16_t RegClass; 82 83 /// These are flags from the MCOI::OperandFlags enum. 84 uint8_t Flags; 85 86 /// Information about the type of the operand. 87 uint8_t OperandType; 88 /// The lower 16 bits are used to specify which constraints are set. 89 /// The higher 16 bits are used to specify the value of constraints (4 bits 90 /// each). 91 uint32_t Constraints; 92 93 /// Set if this operand is a pointer value and it requires a callback 94 /// to look up its register class. isLookupPtrRegClass()95 bool isLookupPtrRegClass() const { 96 return Flags & (1 << MCOI::LookupPtrRegClass); 97 } 98 99 /// Set if this is one of the operands that made up of the predicate 100 /// operand that controls an isPredicable() instruction. isPredicate()101 bool isPredicate() const { return Flags & (1 << MCOI::Predicate); } 102 103 /// Set if this operand is a optional def. isOptionalDef()104 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } 105 106 /// Set if this operand is a branch target. isBranchTarget()107 bool isBranchTarget() const { return Flags & (1 << MCOI::BranchTarget); } 108 109 /// Whether the instruction traps if this operand is a sealed capability. mustBeUnsealedCapability()110 bool mustBeUnsealedCapability() const { 111 return Flags & (1 << MCOI::TrapsIfSealedCapability); 112 } 113 isGenericType()114 bool isGenericType() const { 115 return OperandType >= MCOI::OPERAND_FIRST_GENERIC && 116 OperandType <= MCOI::OPERAND_LAST_GENERIC; 117 } 118 getGenericTypeIndex()119 unsigned getGenericTypeIndex() const { 120 assert(isGenericType() && "non-generic types don't have an index"); 121 return OperandType - MCOI::OPERAND_FIRST_GENERIC; 122 } 123 isGenericImm()124 bool isGenericImm() const { 125 return OperandType >= MCOI::OPERAND_FIRST_GENERIC_IMM && 126 OperandType <= MCOI::OPERAND_LAST_GENERIC_IMM; 127 } 128 getGenericImmIndex()129 unsigned getGenericImmIndex() const { 130 assert(isGenericImm() && "non-generic immediates don't have an index"); 131 return OperandType - MCOI::OPERAND_FIRST_GENERIC_IMM; 132 } 133 }; 134 135 //===----------------------------------------------------------------------===// 136 // Machine Instruction Flags and Description 137 //===----------------------------------------------------------------------===// 138 139 namespace MCID { 140 /// These should be considered private to the implementation of the 141 /// MCInstrDesc class. Clients should use the predicate methods on MCInstrDesc, 142 /// not use these directly. These all correspond to bitfields in the 143 /// MCInstrDesc::Flags field. 144 enum Flag { 145 PreISelOpcode = 0, 146 Variadic, 147 HasOptionalDef, 148 Pseudo, 149 Return, 150 EHScopeReturn, 151 Call, 152 Barrier, 153 Terminator, 154 Branch, 155 IndirectBranch, 156 Compare, 157 MoveImm, 158 MoveReg, 159 Bitcast, 160 Select, 161 DelaySlot, 162 FoldableAsLoad, 163 MayLoad, 164 MayStore, 165 MayRaiseFPException, 166 MayTrap, 167 MayTrapOnSealedInput, 168 DefsCanBeSealed, 169 Predicable, 170 NotDuplicable, 171 UnmodeledSideEffects, 172 Commutable, 173 ConvertibleTo3Addr, 174 UsesCustomInserter, 175 HasPostISelHook, 176 Rematerializable, 177 CheapAsAMove, 178 ExtraSrcRegAllocReq, 179 ExtraDefRegAllocReq, 180 RegSequence, 181 ExtractSubreg, 182 InsertSubreg, 183 Convergent, 184 Add, 185 Trap, 186 VariadicOpsAreDefs, 187 Authenticated, 188 }; 189 } 190 191 /// Describe properties that are true of each instruction in the target 192 /// description file. This captures information about side effects, register 193 /// use and many other things. There is one instance of this struct for each 194 /// target instruction class, and the MachineInstr class points to this struct 195 /// directly to describe itself. 196 class MCInstrDesc { 197 public: 198 unsigned short Opcode; // The opcode number 199 unsigned short NumOperands; // Num of args (may be more if variable_ops) 200 unsigned char NumDefs; // Num of args that are definitions 201 unsigned char Size; // Number of bytes in encoding. 202 unsigned short SchedClass; // enum identifying instr sched class 203 uint64_t Flags; // Flags identifying machine instr class 204 uint64_t TSFlags; // Target Specific Flag values 205 const MCPhysReg *ImplicitUses; // Registers implicitly read by this instr 206 const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr 207 const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands 208 209 /// Returns the value of the specific constraint if 210 /// it is set. Returns -1 if it is not set. getOperandConstraint(unsigned OpNum,MCOI::OperandConstraint Constraint)211 int getOperandConstraint(unsigned OpNum, 212 MCOI::OperandConstraint Constraint) const { 213 if (OpNum < NumOperands && 214 (OpInfo[OpNum].Constraints & (1 << Constraint))) { 215 unsigned Pos = 16 + Constraint * 4; 216 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 217 } 218 return -1; 219 } 220 221 /// Return the opcode number for this descriptor. getOpcode()222 unsigned getOpcode() const { return Opcode; } 223 224 /// Return the number of declared MachineOperands for this 225 /// MachineInstruction. Note that variadic (isVariadic() returns true) 226 /// instructions may have additional operands at the end of the list, and note 227 /// that the machine instruction may include implicit register def/uses as 228 /// well. getNumOperands()229 unsigned getNumOperands() const { return NumOperands; } 230 231 using const_opInfo_iterator = const MCOperandInfo *; 232 opInfo_begin()233 const_opInfo_iterator opInfo_begin() const { return OpInfo; } opInfo_end()234 const_opInfo_iterator opInfo_end() const { return OpInfo + NumOperands; } 235 operands()236 iterator_range<const_opInfo_iterator> operands() const { 237 return make_range(opInfo_begin(), opInfo_end()); 238 } 239 240 /// Return the number of MachineOperands that are register 241 /// definitions. Register definitions always occur at the start of the 242 /// machine operand list. This is the number of "outs" in the .td file, 243 /// and does not include implicit defs. getNumDefs()244 unsigned getNumDefs() const { return NumDefs; } 245 246 /// Return flags of this instruction. getFlags()247 uint64_t getFlags() const { return Flags; } 248 249 /// \returns true if this instruction is emitted before instruction selection 250 /// and should be legalized/regbankselected/selected. isPreISelOpcode()251 bool isPreISelOpcode() const { return Flags & (1ULL << MCID::PreISelOpcode); } 252 253 /// Return true if this instruction can have a variable number of 254 /// operands. In this case, the variable operands will be after the normal 255 /// operands but before the implicit definitions and uses (if any are 256 /// present). isVariadic()257 bool isVariadic() const { return Flags & (1ULL << MCID::Variadic); } 258 259 /// Set if this instruction has an optional definition, e.g. 260 /// ARM instructions which can set condition code if 's' bit is set. hasOptionalDef()261 bool hasOptionalDef() const { return Flags & (1ULL << MCID::HasOptionalDef); } 262 263 /// Return true if this is a pseudo instruction that doesn't 264 /// correspond to a real machine instruction. isPseudo()265 bool isPseudo() const { return Flags & (1ULL << MCID::Pseudo); } 266 267 /// Return true if the instruction is a return. isReturn()268 bool isReturn() const { return Flags & (1ULL << MCID::Return); } 269 270 /// Return true if the instruction is an add instruction. isAdd()271 bool isAdd() const { return Flags & (1ULL << MCID::Add); } 272 273 /// Return true if this instruction is a trap. isTrap()274 bool isTrap() const { return Flags & (1ULL << MCID::Trap); } 275 276 /// Return true if the instruction is a register to register move. isMoveReg()277 bool isMoveReg() const { return Flags & (1ULL << MCID::MoveReg); } 278 279 /// Return true if the instruction is a call. isCall()280 bool isCall() const { return Flags & (1ULL << MCID::Call); } 281 282 /// Returns true if the specified instruction stops control flow 283 /// from executing the instruction immediately following it. Examples include 284 /// unconditional branches and return instructions. isBarrier()285 bool isBarrier() const { return Flags & (1ULL << MCID::Barrier); } 286 287 /// Returns true if this instruction part of the terminator for 288 /// a basic block. Typically this is things like return and branch 289 /// instructions. 290 /// 291 /// Various passes use this to insert code into the bottom of a basic block, 292 /// but before control flow occurs. isTerminator()293 bool isTerminator() const { return Flags & (1ULL << MCID::Terminator); } 294 295 /// Returns true if this is a conditional, unconditional, or 296 /// indirect branch. Predicates below can be used to discriminate between 297 /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to 298 /// get more information. isBranch()299 bool isBranch() const { return Flags & (1ULL << MCID::Branch); } 300 301 /// Return true if this is an indirect branch, such as a 302 /// branch through a register. isIndirectBranch()303 bool isIndirectBranch() const { return Flags & (1ULL << MCID::IndirectBranch); } 304 305 /// Return true if this is a branch which may fall 306 /// through to the next instruction or may transfer control flow to some other 307 /// block. The TargetInstrInfo::analyzeBranch method can be used to get more 308 /// information about this branch. isConditionalBranch()309 bool isConditionalBranch() const { 310 return isBranch() && !isBarrier() && !isIndirectBranch(); 311 } 312 313 /// Return true if this is a branch which always 314 /// transfers control flow to some other block. The 315 /// TargetInstrInfo::analyzeBranch method can be used to get more information 316 /// about this branch. isUnconditionalBranch()317 bool isUnconditionalBranch() const { 318 return isBranch() && isBarrier() && !isIndirectBranch(); 319 } 320 321 /// Return true if this is a branch or an instruction which directly 322 /// writes to the program counter. Considered 'may' affect rather than 323 /// 'does' affect as things like predication are not taken into account. 324 bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const; 325 326 /// Return true if this instruction has a predicate operand 327 /// that controls execution. It may be set to 'always', or may be set to other 328 /// values. There are various methods in TargetInstrInfo that can be used to 329 /// control and modify the predicate in this instruction. isPredicable()330 bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); } 331 332 /// Return true if this instruction is a comparison. isCompare()333 bool isCompare() const { return Flags & (1ULL << MCID::Compare); } 334 335 /// Return true if this instruction is a move immediate 336 /// (including conditional moves) instruction. isMoveImmediate()337 bool isMoveImmediate() const { return Flags & (1ULL << MCID::MoveImm); } 338 339 /// Return true if this instruction is a bitcast instruction. isBitcast()340 bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); } 341 342 /// Return true if this is a select instruction. isSelect()343 bool isSelect() const { return Flags & (1ULL << MCID::Select); } 344 345 /// Return true if this instruction cannot be safely 346 /// duplicated. For example, if the instruction has a unique labels attached 347 /// to it, duplicating it would cause multiple definition errors. isNotDuplicable()348 bool isNotDuplicable() const { return Flags & (1ULL << MCID::NotDuplicable); } 349 350 /// Returns true if the specified instruction has a delay slot which 351 /// must be filled by the code generator. hasDelaySlot()352 bool hasDelaySlot() const { return Flags & (1ULL << MCID::DelaySlot); } 353 354 /// Return true for instructions that can be folded as memory operands 355 /// in other instructions. The most common use for this is instructions that 356 /// are simple loads from memory that don't modify the loaded value in any 357 /// way, but it can also be used for instructions that can be expressed as 358 /// constant-pool loads, such as V_SETALLONES on x86, to allow them to be 359 /// folded when it is beneficial. This should only be set on instructions 360 /// that return a value in their only virtual register definition. canFoldAsLoad()361 bool canFoldAsLoad() const { return Flags & (1ULL << MCID::FoldableAsLoad); } 362 363 /// Return true if this instruction behaves 364 /// the same way as the generic REG_SEQUENCE instructions. 365 /// E.g., on ARM, 366 /// dX VMOVDRR rY, rZ 367 /// is equivalent to 368 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1. 369 /// 370 /// Note that for the optimizers to be able to take advantage of 371 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be 372 /// override accordingly. isRegSequenceLike()373 bool isRegSequenceLike() const { return Flags & (1ULL << MCID::RegSequence); } 374 375 /// Return true if this instruction behaves 376 /// the same way as the generic EXTRACT_SUBREG instructions. 377 /// E.g., on ARM, 378 /// rX, rY VMOVRRD dZ 379 /// is equivalent to two EXTRACT_SUBREG: 380 /// rX = EXTRACT_SUBREG dZ, ssub_0 381 /// rY = EXTRACT_SUBREG dZ, ssub_1 382 /// 383 /// Note that for the optimizers to be able to take advantage of 384 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be 385 /// override accordingly. isExtractSubregLike()386 bool isExtractSubregLike() const { 387 return Flags & (1ULL << MCID::ExtractSubreg); 388 } 389 390 /// Return true if this instruction behaves 391 /// the same way as the generic INSERT_SUBREG instructions. 392 /// E.g., on ARM, 393 /// dX = VSETLNi32 dY, rZ, Imm 394 /// is equivalent to a INSERT_SUBREG: 395 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm) 396 /// 397 /// Note that for the optimizers to be able to take advantage of 398 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be 399 /// override accordingly. isInsertSubregLike()400 bool isInsertSubregLike() const { return Flags & (1ULL << MCID::InsertSubreg); } 401 402 403 /// Return true if this instruction is convergent. 404 /// 405 /// Convergent instructions may not be made control-dependent on any 406 /// additional values. isConvergent()407 bool isConvergent() const { return Flags & (1ULL << MCID::Convergent); } 408 409 /// Return true if variadic operands of this instruction are definitions. variadicOpsAreDefs()410 bool variadicOpsAreDefs() const { 411 return Flags & (1ULL << MCID::VariadicOpsAreDefs); 412 } 413 414 /// Return true if this instruction authenticates a pointer (e.g. LDRAx/BRAx 415 /// from ARMv8.3, which perform loads/branches with authentication). 416 /// 417 /// An authenticated instruction may fail in an ABI-defined manner when 418 /// operating on an invalid signed pointer. isAuthenticated()419 bool isAuthenticated() const { 420 return Flags & (1ULL << MCID::Authenticated); 421 } 422 423 //===--------------------------------------------------------------------===// 424 // Side Effect Analysis 425 //===--------------------------------------------------------------------===// 426 427 /// Return true if this instruction could possibly read memory. 428 /// Instructions with this flag set are not necessarily simple load 429 /// instructions, they may load a value and modify it, for example. mayLoad()430 bool mayLoad() const { return Flags & (1ULL << MCID::MayLoad); } 431 432 /// Return true if this instruction could possibly modify memory. 433 /// Instructions with this flag set are not necessarily simple store 434 /// instructions, they may store a modified value based on their operands, or 435 /// may not actually modify anything, for example. mayStore()436 bool mayStore() const { return Flags & (1ULL << MCID::MayStore); } 437 438 /// Return true if this instruction may raise a floating-point exception. mayRaiseFPException()439 bool mayRaiseFPException() const { 440 return Flags & (1ULL << MCID::MayRaiseFPException); 441 } 442 443 /// Return true if this instruction has side 444 /// effects that are not modeled by other flags. This does not return true 445 /// for instructions whose effects are captured by: 446 /// 447 /// 1. Their operand list and implicit definition/use list. Register use/def 448 /// info is explicit for instructions. 449 /// 2. Memory accesses. Use mayLoad/mayStore. 450 /// 3. Calling, branching, returning: use isCall/isReturn/isBranch. 451 /// 452 /// Examples of side effects would be modifying 'invisible' machine state like 453 /// a control register, flushing a cache, modifying a register invisible to 454 /// LLVM, etc. hasUnmodeledSideEffects()455 bool hasUnmodeledSideEffects() const { 456 return Flags & (1ULL << MCID::UnmodeledSideEffects); 457 } 458 459 //===--------------------------------------------------------------------===// 460 // Flags that indicate whether an instruction can be modified by a method. 461 //===--------------------------------------------------------------------===// 462 463 /// Return true if this may be a 2- or 3-address instruction (of the 464 /// form "X = op Y, Z, ..."), which produces the same result if Y and Z are 465 /// exchanged. If this flag is set, then the 466 /// TargetInstrInfo::commuteInstruction method may be used to hack on the 467 /// instruction. 468 /// 469 /// Note that this flag may be set on instructions that are only commutable 470 /// sometimes. In these cases, the call to commuteInstruction will fail. 471 /// Also note that some instructions require non-trivial modification to 472 /// commute them. isCommutable()473 bool isCommutable() const { return Flags & (1ULL << MCID::Commutable); } 474 475 /// Return true if this is a 2-address instruction which can be changed 476 /// into a 3-address instruction if needed. Doing this transformation can be 477 /// profitable in the register allocator, because it means that the 478 /// instruction can use a 2-address form if possible, but degrade into a less 479 /// efficient form if the source and dest register cannot be assigned to the 480 /// same register. For example, this allows the x86 backend to turn a "shl 481 /// reg, 3" instruction into an LEA instruction, which is the same speed as 482 /// the shift but has bigger code size. 483 /// 484 /// If this returns true, then the target must implement the 485 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which 486 /// is allowed to fail if the transformation isn't valid for this specific 487 /// instruction (e.g. shl reg, 4 on x86). 488 /// isConvertibleTo3Addr()489 bool isConvertibleTo3Addr() const { 490 return Flags & (1ULL << MCID::ConvertibleTo3Addr); 491 } 492 493 /// Return true if this instruction requires custom insertion support 494 /// when the DAG scheduler is inserting it into a machine basic block. If 495 /// this is true for the instruction, it basically means that it is a pseudo 496 /// instruction used at SelectionDAG time that is expanded out into magic code 497 /// by the target when MachineInstrs are formed. 498 /// 499 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method 500 /// is used to insert this into the MachineBasicBlock. usesCustomInsertionHook()501 bool usesCustomInsertionHook() const { 502 return Flags & (1ULL << MCID::UsesCustomInserter); 503 } 504 505 /// Return true if this instruction requires *adjustment* after 506 /// instruction selection by calling a target hook. For example, this can be 507 /// used to fill in ARM 's' optional operand depending on whether the 508 /// conditional flag register is used. hasPostISelHook()509 bool hasPostISelHook() const { return Flags & (1ULL << MCID::HasPostISelHook); } 510 511 /// Returns true if this instruction is a candidate for remat. This 512 /// flag is only used in TargetInstrInfo method isTriviallyRematerializable. 513 /// 514 /// If this flag is set, the isReallyTriviallyReMaterializable() 515 /// or isReallyTriviallyReMaterializableGeneric methods are called to verify 516 /// the instruction is really rematable. isRematerializable()517 bool isRematerializable() const { 518 return Flags & (1ULL << MCID::Rematerializable); 519 } 520 521 /// Returns true if this instruction has the same cost (or less) than a 522 /// move instruction. This is useful during certain types of optimizations 523 /// (e.g., remat during two-address conversion or machine licm) where we would 524 /// like to remat or hoist the instruction, but not if it costs more than 525 /// moving the instruction into the appropriate register. Note, we are not 526 /// marking copies from and to the same register class with this flag. 527 /// 528 /// This method could be called by interface TargetInstrInfo::isAsCheapAsAMove 529 /// for different subtargets. isAsCheapAsAMove()530 bool isAsCheapAsAMove() const { return Flags & (1ULL << MCID::CheapAsAMove); } 531 532 /// Returns true if this instruction source operands have special 533 /// register allocation requirements that are not captured by the operand 534 /// register classes. e.g. ARM::STRD's two source registers must be an even / 535 /// odd pair, ARM::STM registers have to be in ascending order. Post-register 536 /// allocation passes should not attempt to change allocations for sources of 537 /// instructions with this flag. hasExtraSrcRegAllocReq()538 bool hasExtraSrcRegAllocReq() const { 539 return Flags & (1ULL << MCID::ExtraSrcRegAllocReq); 540 } 541 542 /// Returns true if this instruction def operands have special register 543 /// allocation requirements that are not captured by the operand register 544 /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair, 545 /// ARM::LDM registers have to be in ascending order. Post-register 546 /// allocation passes should not attempt to change allocations for definitions 547 /// of instructions with this flag. hasExtraDefRegAllocReq()548 bool hasExtraDefRegAllocReq() const { 549 return Flags & (1ULL << MCID::ExtraDefRegAllocReq); 550 } 551 552 /// Return a list of registers that are potentially read by any 553 /// instance of this machine instruction. For example, on X86, the "adc" 554 /// instruction adds two register operands and adds the carry bit in from the 555 /// flags register. In this case, the instruction is marked as implicitly 556 /// reading the flags. Likewise, the variable shift instruction on X86 is 557 /// marked as implicitly reading the 'CL' register, which it always does. 558 /// 559 /// This method returns null if the instruction has no implicit uses. getImplicitUses()560 const MCPhysReg *getImplicitUses() const { return ImplicitUses; } 561 562 /// Return the number of implicit uses this instruction has. getNumImplicitUses()563 unsigned getNumImplicitUses() const { 564 if (!ImplicitUses) 565 return 0; 566 unsigned i = 0; 567 for (; ImplicitUses[i]; ++i) /*empty*/ 568 ; 569 return i; 570 } 571 572 /// Return a list of registers that are potentially written by any 573 /// instance of this machine instruction. For example, on X86, many 574 /// instructions implicitly set the flags register. In this case, they are 575 /// marked as setting the FLAGS. Likewise, many instructions always deposit 576 /// their result in a physical register. For example, the X86 divide 577 /// instruction always deposits the quotient and remainder in the EAX/EDX 578 /// registers. For that instruction, this will return a list containing the 579 /// EAX/EDX/EFLAGS registers. 580 /// 581 /// This method returns null if the instruction has no implicit defs. getImplicitDefs()582 const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; } 583 584 /// Return the number of implicit defs this instruct has. getNumImplicitDefs()585 unsigned getNumImplicitDefs() const { 586 if (!ImplicitDefs) 587 return 0; 588 unsigned i = 0; 589 for (; ImplicitDefs[i]; ++i) /*empty*/ 590 ; 591 return i; 592 } 593 594 /// Return true if this instruction implicitly 595 /// uses the specified physical register. hasImplicitUseOfPhysReg(unsigned Reg)596 bool hasImplicitUseOfPhysReg(unsigned Reg) const { 597 if (const MCPhysReg *ImpUses = ImplicitUses) 598 for (; *ImpUses; ++ImpUses) 599 if (*ImpUses == Reg) 600 return true; 601 return false; 602 } 603 604 /// Return true if this instruction implicitly 605 /// defines the specified physical register. 606 bool hasImplicitDefOfPhysReg(unsigned Reg, 607 const MCRegisterInfo *MRI = nullptr) const; 608 609 /// Return the scheduling class for this instruction. The 610 /// scheduling class is an index into the InstrItineraryData table. This 611 /// returns zero if there is no known scheduling information for the 612 /// instruction. getSchedClass()613 unsigned getSchedClass() const { return SchedClass; } 614 615 /// Return the number of bytes in the encoding of this instruction, 616 /// or zero if the encoding size cannot be known from the opcode. getSize()617 unsigned getSize() const { return Size; } 618 619 /// Find the index of the first operand in the 620 /// operand list that is used to represent the predicate. It returns -1 if 621 /// none is found. findFirstPredOperandIdx()622 int findFirstPredOperandIdx() const { 623 if (isPredicable()) { 624 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 625 if (OpInfo[i].isPredicate()) 626 return i; 627 } 628 return -1; 629 } 630 631 /// Return true if this instruction defines the specified physical 632 /// register, either explicitly or implicitly. 633 bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg, 634 const MCRegisterInfo &RI) const; 635 }; 636 637 } // end namespace llvm 638 639 #endif 640