xref: /dragonfly/sys/dev/disk/amd/amd.h (revision 86d7f5d3)
1 /*
2  *********************************************************************
3  *	FILE NAME  : amd.h
4  *	     BY    : C.L. Huang 	(ching@tekram.com.tw)
5  *		     Erich Chen     (erich@tekram.com.tw)
6  *	Description: Device Driver for the amd53c974 PCI Bus Master
7  *		     SCSI Host adapter found on cards such as
8  *		     the Tekram DC-390(T).
9  * (C)Copyright 1995-1999 Tekram Technology Co., Ltd.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  * 3. The name of the author may not be used to endorse or promote products
20  *    derived from this software without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  *********************************************************************
33  * $FreeBSD: src/sys/pci/amd.h,v 1.1.4.1 2000/04/14 13:16:54 nyan Exp $
34  * $DragonFly: src/sys/dev/disk/amd/amd.h,v 1.2 2003/06/17 04:28:56 dillon Exp $
35  */
36 
37 #ifndef AMD_H
38 #define AMD_H
39 
40 #define AMD_TRANS_CUR		0x01	/* Modify current neogtiation status */
41 #define AMD_TRANS_ACTIVE	0x03	/* Assume this is the active target */
42 #define AMD_TRANS_GOAL		0x04	/* Modify negotiation goal */
43 #define AMD_TRANS_USER		0x08	/* Modify user negotiation settings */
44 
45 /*
46  * Per target transfer parameters.
47  */
48 struct amd_transinfo {
49 	u_int8_t period;
50 	u_int8_t offset;
51 };
52 
53 struct amd_target_info {
54 	/*
55 	 * Records the currently active and user/default settings for
56 	 * tagged queueing and disconnection for each target.
57 	 */
58 	u_int8_t disc_tag;
59 #define		AMD_CUR_DISCENB	0x01
60 #define		AMD_CUR_TAGENB	0x02
61 #define		AMD_USR_DISCENB	0x04
62 #define		AMD_USR_TAGENB	0x08
63 	u_int8_t   CtrlR1;
64 	u_int8_t   CtrlR3;
65 	u_int8_t   CtrlR4;
66 	u_int8_t   sync_period_reg;
67 	u_int8_t   sync_offset_reg;
68 
69 	/*
70 	 * Currently active transfer settings.
71 	 */
72 	struct amd_transinfo current;
73 	/*
74 	 * Transfer settings we wish to achieve
75 	 * through negotiation.
76 	 */
77 	struct amd_transinfo goal;
78 	/*
79 	 * User defined or default transfer settings.
80 	 */
81 	struct amd_transinfo user;
82 };
83 
84 /*
85  * Scatter/Gather Segment entry.
86  */
87 struct amd_sg {
88 	u_int32_t   SGXLen;
89 	u_int32_t   SGXPtr;
90 };
91 
92 /*
93  * Chipset feature limits
94  */
95 #define MAX_SCSI_ID		8
96 #define AMD_MAX_SYNC_OFFSET	15
97 #define AMD_TARGET_MAX	7
98 #define AMD_LUN_MAX		7
99 #define AMD_NSEG		(btoc(MAXPHYS) + 1)
100 #define AMD_MAXTRANSFER_SIZE	0xFFFFFF /* restricted by 24 bit counter */
101 #define MAX_DEVICES		10
102 #define MAX_TAGS_CMD_QUEUE	256
103 #define MAX_CMD_PER_LUN		6
104 #define MAX_SRB_CNT		256
105 #define MAX_START_JOB		256
106 
107 /*
108  * BIT position to integer mapping.
109  */
110 #define BIT(N) (0x01 << N)
111 
112 /*
113  * EEPROM storage offsets and data structures.
114  */
115 typedef struct _EEprom {
116 	u_int8_t   EE_MODE1;
117 	u_int8_t   EE_SPEED;
118 	u_int8_t   xx1;
119 	u_int8_t   xx2;
120 }       EEprom, *PEEprom;
121 
122 #define EE_ADAPT_SCSI_ID	64
123 #define EE_MODE2		65
124 #define EE_DELAY		66
125 #define EE_TAG_CMD_NUM		67
126 #define EE_DATA_SIZE		128
127 #define EE_CHECKSUM		0x1234
128 
129 /*
130  * EE_MODE1 bits definition
131  */
132 #define PARITY_CHK   	  	BIT(0)
133 #define SYNC_NEGO      		BIT(1)
134 #define EN_DISCONNECT  		BIT(2)
135 #define SEND_START     		BIT(3)
136 #define TAG_QUEUING    		BIT(4)
137 
138 /*
139  * EE_MODE2 bits definition
140  */
141 #define MORE2_DRV		BIT(0)
142 #define GREATER_1G		BIT(1)
143 #define RST_SCSI_BUS		BIT(2)
144 #define ACTIVE_NEGATION		BIT(3)
145 #define NO_SEEK			BIT(4)
146 #define LUN_CHECK		BIT(5)
147 
148 #define ENABLE_CE		1
149 #define DISABLE_CE		0
150 #define EEPROM_READ		0x80
151 
152 #define AMD_TAG_WILDCARD ((u_int)(~0))
153 
154 /*
155  * SCSI Request Block
156  */
157 struct amd_srb {
158 	TAILQ_ENTRY(amd_srb) links;
159 	u_int8_t	 CmdBlock[12];
160 	union		 ccb *pccb;
161 	bus_dmamap_t	 dmamap;
162 	struct		 amd_sg *pSGlist;
163 
164 	u_int32_t	 TotalXferredLen;
165 	u_int32_t	 SGPhysAddr;	/* a segment starting address */
166 	u_int32_t	 SGToBeXferLen;	/* to be xfer length */
167 	u_int32_t	 Segment0[2];
168 	u_int32_t	 Segment1[2];
169 
170 	struct		 amd_sg SGsegment[AMD_NSEG];
171 	struct		 amd_sg Segmentx;/* a one entry of S/G list table */
172 	u_int8_t	*pMsgPtr;
173 	u_int16_t	 SRBState;
174 
175 	u_int8_t	 AdaptStatus;
176 	u_int8_t	 TargetStatus;
177 	u_int8_t	 MsgCnt;
178 	u_int8_t	 EndMessage;
179 	u_int8_t	 TagNumber;
180 	u_int8_t	 SGcount;
181 	u_int8_t	 SGIndex;
182 	u_int8_t	 IORBFlag;	/* ;81h-Reset, 2-retry */
183 
184 	u_int8_t	 SRBStatus;
185 	u_int8_t	 SRBFlag;
186 	/* ; b0-AutoReqSense,b6-Read,b7-write */
187 	/* ; b4-settimeout,b5-Residual valid */
188 	u_int8_t	 ScsiCmdLen;
189 };
190 
191 TAILQ_HEAD(srb_queue, amd_srb);
192 
193 /*
194  * Per-adapter, software configuration.
195  */
196 struct amd_softc {
197 	device_t		dev;
198 	bus_space_tag_t		tag;
199 	bus_space_handle_t	bsh;
200 	bus_dma_tag_t		buffer_dmat;   /* dmat for buffer I/O */
201 	int			unit;
202 
203 	int	   last_phase;
204 	int	   cur_target;
205 	int	   cur_lun;
206 	struct	   amd_srb *active_srb;
207 	struct	   amd_srb *untagged_srbs[AMD_TARGET_MAX+1][AMD_LUN_MAX+1];
208 	struct	   amd_target_info tinfo[AMD_TARGET_MAX+1];
209 	u_int16_t  disc_count[AMD_TARGET_MAX+1][AMD_LUN_MAX+1];
210 
211 	struct	   srb_queue free_srbs;
212 	struct	   srb_queue waiting_srbs;
213 	struct	   srb_queue running_srbs;
214 
215 	struct	   amd_srb *pTmpSRB;
216 
217 	u_int16_t  SRBCount;
218 
219 	u_int16_t  max_id;
220 	u_int16_t  max_lun;
221 
222 	/* Hooks into the CAM XPT */
223 	struct	   cam_sim *psim;
224 	struct	   cam_path *ppath;
225 
226 	u_int8_t   msgin_buf[6];
227 	u_int8_t   msgout_buf[6];
228 	u_int	   msgin_index;
229 	u_int	   msgout_index;
230 	u_int	   msgout_len;
231 
232 	u_int8_t   status;
233 	u_int8_t   AdaptSCSIID;		/* ; Adapter SCSI Target ID */
234 	u_int8_t   AdaptSCSILUN;	/* ; Adapter SCSI LUN */
235 
236 	u_int8_t   ACBFlag;
237 
238 	u_int8_t   Gmode2;
239 
240 	u_int8_t   HostID_Bit;
241 
242 	u_int8_t   InitDCB_flag[8][8];	/* flag of initDCB for device */
243 	struct	   amd_srb SRB_array[MAX_SRB_CNT]; /* +45Ch, Len=	 */
244 	struct	   amd_srb TmpSRB;
245 	/* Setup data stored in an 93c46 serial eeprom */
246 	u_int8_t   eepromBuf[EE_DATA_SIZE];
247 };
248 
249 /*
250  *   ----SRB State machine definition
251  */
252 #define SRB_FREE        	0
253 #define SRB_READY       	BIT(1)
254 #define SRB_MSGOUT      	BIT(2)	/* ;arbitration+msg_out 1st byte */
255 #define SRB_MSGIN       	BIT(3)
256 #define SRB_MSGIN_MULTI		BIT(4)
257 #define SRB_COMMAND     	BIT(5)
258 #define SRB_START	     	BIT(6)	/* ;arbitration+msg_out+command_out */
259 #define SRB_DISCONNECT   	BIT(7)
260 #define SRB_DATA_XFER    	BIT(8)
261 #define SRB_XFERPAD     	BIT(9)
262 #define SRB_STATUS      	BIT(10)
263 #define SRB_COMPLETED    	BIT(11)
264 #define SRB_ABORT_SENT   	BIT(12)
265 #define DO_SYNC_NEGO    	BIT(13)
266 #define SRB_UNEXPECT_RESEL	BIT(14)
267 
268 /*
269  *   ---ACB Flag
270  */
271 #define RESET_DEV       	BIT(0)
272 #define RESET_DETECT    	BIT(1)
273 #define RESET_DONE      	BIT(2)
274 
275 /*
276  *   ---DCB Flag
277  */
278 #define ABORT_DEV_      	BIT(0)
279 
280 /*
281  *   ---SRB status
282  */
283 #define SRB_OK	        	BIT(0)
284 #define ABORTION        	BIT(1)
285 #define OVER_RUN        	BIT(2)
286 #define UNDER_RUN       	BIT(3)
287 #define PARITY_ERROR    	BIT(4)
288 #define SRB_ERROR       	BIT(5)
289 
290 /*
291  *   ---SRB Flags
292  */
293 #define DATAOUT         	BIT(7)
294 #define DATAIN	        	BIT(6)
295 #define RESIDUAL_VALID   	BIT(5)
296 #define ENABLE_TIMER    	BIT(4)
297 #define RESET_DEV0      	BIT(2)
298 #define ABORT_DEV       	BIT(1)
299 #define AUTO_REQSENSE    	BIT(0)
300 
301 /*
302  *   ---Adapter status
303  */
304 #define H_STATUS_GOOD		0
305 #define H_SEL_TIMEOUT		0x11
306 #define H_OVER_UNDER_RUN	0x12
307 #define H_UNEXP_BUS_FREE	0x13
308 #define H_TARGET_PHASE_F	0x14
309 #define H_INVALID_CCB_OP	0x16
310 #define H_LINK_CCB_BAD		0x17
311 #define H_BAD_TARGET_DIR	0x18
312 #define H_DUPLICATE_CCB		0x19
313 #define H_BAD_CCB_OR_SG		0x1A
314 #define H_ABORT			0x0FF
315 
316 /*
317  * AMD specific "status" codes returned in the SCSI status byte.
318  */
319 #define AMD_SCSI_STAT_UNEXP_BUS_F    	0xFD	/* ;  Unexpect Bus Free */
320 #define AMD_SCSI_STAT_BUS_RST_DETECT	0xFE	/* ;  Scsi Bus Reset detected */
321 #define AMD_SCSI_STAT_SEL_TIMEOUT   	0xFF	/* ;  Selection Time out */
322 
323 /*
324  *   ---Sync_Mode
325  */
326 #define SYNC_DISABLE	    0
327 #define SYNC_ENABLE 	    BIT(0)
328 #define SYNC_NEGO_DONE	    BIT(1)
329 #define WIDE_ENABLE 	    BIT(2)
330 #define WIDE_NEGO_DONE	    BIT(3)
331 #define EN_TAG_QUEUING	    BIT(4)
332 #define EN_ATN_STOP         BIT(5)
333 
334 #define SYNC_NEGO_OFFSET    15
335 
336 /*
337  *    ---SCSI bus phase
338  */
339 #define SCSI_DATA_OUT		0
340 #define SCSI_DATA_IN		1
341 #define SCSI_COMMAND		2
342 #define SCSI_STATUS		3
343 #define SCSI_NOP0		4
344 #define SCSI_ARBITRATING	5
345 #define SCSI_MSG_OUT		6
346 #define SCSI_MSG_IN		7
347 #define SCSI_BUS_FREE		8
348 
349 /*
350  *==========================================================
351  *      	AMD 53C974 Registers bit Definition
352  *==========================================================
353  */
354 
355 /*
356  *      ------SCSI Register-------
357  *      Command Reg.(+0CH)
358  */
359 #define DMA_COMMAND   	    	BIT(7)
360 #define NOP_CMD 	       	0
361 #define CLEAR_FIFO_CMD	    	1
362 #define RST_DEVICE_CMD	    	2
363 #define RST_SCSI_BUS_CMD    	3
364 #define INFO_XFER_CMD	    	0x10
365 #define INITIATOR_CMD_CMPLTE	0x11
366 #define MSG_ACCEPTED_CMD    	0x12
367 #define XFER_PAD_BYTE	     	0x18
368 #define SET_ATN_CMD	       	0x1A
369 #define RESET_ATN_CMD    	0x1B
370 #define SEL_W_ATN		0x42
371 #define SEL_W_ATN_STOP	    	0x43
372 #define EN_SEL_RESEL	    	0x44
373 #define SEL_W_ATN2	       	0x46
374 #define DATA_XFER_CMD	    	INFO_XFER_CMD
375 
376 
377 /*
378  *     ------SCSI Register-------
379  *     SCSI Status Reg.(+10H)
380  */
381 #define INTERRUPT	    	BIT(7)
382 #define ILLEGAL_OP_ERR		BIT(6)
383 #define PARITY_ERR	    	BIT(5)
384 #define COUNT_2_ZERO		BIT(4)
385 #define GROUP_CODE_VALID	BIT(3)
386 #define SCSI_PHASE_MASK 	(BIT(2)+BIT(1)+BIT(0))
387 
388 /*
389  *     ------SCSI Register-------
390  *     Interrupt Status Reg.(+14H)
391  */
392 #define SCSI_RESET_	    	BIT(7)
393 #define INVALID_CMD	    	BIT(6)
394 #define DISCONNECTED		BIT(5)
395 #define SERVICE_REQUEST 	BIT(4)
396 #define SUCCESSFUL_OP		BIT(3)
397 #define RESELECTED	    	BIT(2)
398 #define SEL_ATTENTION		BIT(1)
399 #define SELECTED	    	BIT(0)
400 
401 /*
402  *     ------SCSI Register-------
403  *    Internal State Reg.(+18H)
404  */
405 #define SYNC_OFFSET_FLAG	BIT(3)
406 #define INTRN_STATE_MASK	(BIT(2)+BIT(1)+BIT(0))
407 
408 /*
409  *     ------SCSI Register-------
410  *     Clock Factor Reg.(+24H)
411  */
412 #define CLK_FREQ_40MHZ		0
413 #define CLK_FREQ_35MHZ		(BIT(2)+BIT(1)+BIT(0))
414 #define CLK_FREQ_30MHZ		(BIT(2)+BIT(1))
415 #define CLK_FREQ_25MHZ		(BIT(2)+BIT(0))
416 #define CLK_FREQ_20MHZ		BIT(2)
417 #define CLK_FREQ_15MHZ		(BIT(1)+BIT(0))
418 #define CLK_FREQ_10MHZ		BIT(1)
419 
420 /*
421  *     ------SCSI Register-------
422  *     Control Reg. 1(+20H)
423  */
424 #define EXTENDED_TIMING 	BIT(7)
425 #define DIS_INT_ON_SCSI_RST	BIT(6)
426 #define PARITY_ERR_REPO 	BIT(4)
427 #define SCSI_ID_ON_BUS		(BIT(2)+BIT(1)+BIT(0))
428 
429 /*
430  *     ------SCSI Register-------
431  *     Control Reg. 2(+2CH)
432  */
433 #define EN_FEATURE	    	BIT(6)
434 #define EN_SCSI2_CMD		BIT(3)
435 
436 /*
437  *     ------SCSI Register-------
438  *     Control Reg. 3(+30H)
439  */
440 #define ID_MSG_CHECK		BIT(7)
441 #define EN_QTAG_MSG	    	BIT(6)
442 #define EN_GRP2_CMD	    	BIT(5)
443 #define FAST_SCSI	    	BIT(4)	/* ;10MB/SEC */
444 #define FAST_CLK	    	BIT(3)	/* ;25 - 40 MHZ */
445 
446 /*
447  *     ------SCSI Register-------
448  *     Control Reg. 4(+34H)
449  */
450 #define EATER_12NS	    	0
451 #define EATER_25NS	    	BIT(7)
452 #define EATER_35NS	    	BIT(6)
453 #define EATER_0NS	    	(BIT(7)+BIT(6))
454 #define NEGATE_REQACKDATA	BIT(2)
455 #define NEGATE_REQACK		BIT(3)
456 
457 /*
458  *========================================
459  *             DMA Register
460  *========================================
461  */
462 
463 /*
464  *        -------DMA Register--------
465  *        DMA Command Reg.(+40H)
466  */
467 #define READ_DIRECTION		BIT(7)
468 #define WRITE_DIRECTION 	0
469 #define EN_DMA_INT	    	BIT(6)
470 #define MAP_TO_MDL	    	BIT(5)
471 #define DMA_DIAGNOSTIC		BIT(4)
472 #define DMA_IDLE_CMD		0
473 #define DMA_BLAST_CMD		BIT(0)
474 #define DMA_ABORT_CMD		BIT(1)
475 #define DMA_START_CMD		(BIT(1)|BIT(0))
476 
477 /*
478  *        -------DMA Register--------
479  *         DMA Status Reg.(+54H)
480  */
481 #define PCI_MS_ABORT		BIT(6)
482 #define BLAST_COMPLETE		BIT(5)
483 #define SCSI_INTERRUPT		BIT(4)
484 #define DMA_XFER_DONE		BIT(3)
485 #define DMA_XFER_ABORT		BIT(2)
486 #define DMA_XFER_ERROR		BIT(1)
487 #define POWER_DOWN	    	BIT(0)
488 
489 /*
490  *        -------DMA Register--------
491  *        DMA SCSI Bus and Ctrl.(+70H)
492  *        EN_INT_ON_PCI_ABORT
493  */
494 
495 /*
496  *==========================================================
497  *           SCSI Chip register address offset
498  *==========================================================
499  */
500 #define CTCREG_LOW   	0x00	/* (R)   current transfer count register low */
501 #define STCREG_LOW   	0x00	/* (W)   start transfer count register low */
502 
503 #define CTCREG_MID   	0x04	/* (R)   current transfer count register
504 				 * middle */
505 #define STCREG_MID   	0x04	/* (W)   start transfer count register middle */
506 
507 #define SCSIFIFOREG    	0x08	/* (R/W) SCSI FIFO register */
508 
509 #define SCSICMDREG     	0x0C	/* (R/W) SCSI command register */
510 
511 #define SCSISTATREG  	0x10	/* (R)   SCSI status register */
512 #define SCSIDESTIDREG  	0x10	/* (W)   SCSI destination ID register */
513 
514 #define INTSTATREG   	0x14	/* (R)   interrupt status register */
515 #define SCSITIMEOUTREG 	0x14	/* (W)   SCSI timeout register */
516 
517 
518 #define INTERNSTATREG  	0x18	/* (R)   internal state register */
519 #define SYNCPERIOREG  	0x18	/* (W)   synchronous transfer period register */
520 
521 #define CURRENTFIFOREG  0x1C	/* (R)   current FIFO/internal state register */
522 #define SYNCOFFREG 	    0x1C/* (W)   synchronous transfer period register */
523 
524 #define CNTLREG1    	0x20	/* (R/W) control register 1 */
525 #define CLKFACTREG  	0x24	/* (W)   clock factor register */
526 #define CNTLREG2    	0x2C	/* (R/W) control register 2 */
527 #define CNTLREG3    	0x30	/* (R/W) control register 3 */
528 #define CNTLREG4    	0x34	/* (R/W) control register 4 */
529 
530 #define CURTXTCNTREG  	0x38	/* (R)   current transfer count register
531 				 * high/part-unique ID code */
532 #define STCREG_HIGH  	0x38	/* (W)   Start current transfer count register
533 				 * high */
534 
535 /*
536  *********************************************************
537  *
538  *                 SCSI DMA register
539  *
540  *********************************************************
541  */
542 #define DMA_Cmd     	0x40	/* (R/W) command register */
543 #define DMA_XferCnt  	0x44	/* (R/W) starting transfer count */
544 #define DMA_XferAddr	0x48	/* (R/W) starting Physical address */
545 #define DMA_Wk_ByteCntr 0x4C	/* ( R ) working byte counter */
546 #define DMA_Wk_AddrCntr 0x50	/* ( R ) working address counter */
547 #define DMA_Status   	0x54	/* ( R ) status register */
548 #define DMA_MDL_Addr	0x58	/* (R/W) starting memory descriptor list (MDL)
549 				 * address */
550 #define DMA_Wk_MDL_Cntr 0x5C	/* ( R ) working MDL counter */
551 #define DMA_ScsiBusCtrl 0x70	/* (bits R/W) SCSI BUS and control */
552 
553 /* ******************************************************* */
554 #define am_target    	SCSISTATREG
555 #define am_timeout   	INTSTATREG
556 #define am_seq_step 	SYNCPERIOREG
557 #define am_fifo_count	SYNCOFFREG
558 
559 
560 #define amd_read8(amd, port)				\
561 	bus_space_read_1((amd)->tag, (amd)->bsh, port)
562 
563 #define amd_read16(amd, port)				\
564 	bus_space_read_2((amd)->tag, (amd)->bsh, port)
565 
566 #define amd_read32(amd, port)				\
567 	bus_space_read_4((amd)->tag, (amd)->bsh, port)
568 
569 #define amd_write8(amd, port, value)			\
570 	bus_space_write_1((amd)->tag, (amd)->bsh, port, value)
571 
572 #define amd_write8_multi(amd, port, ptr, len)		\
573 	bus_space_write_multi_1((amd)->tag, (amd)->bsh, port, ptr, len)
574 
575 #define amd_write16(amd, port, value)			\
576 	bus_space_write_2((amd)->tag, (amd)->bsh, port, value)
577 
578 #define amd_write32(amd, port, value)			\
579 	bus_space_write_4((amd)->tag, (amd)->bsh, port, value)
580 
581 #endif /* AMD_H */
582