1 /* $OpenBSD: ebusreg.h,v 1.6 2019/12/05 12:46:54 mpi Exp $ */ 2 /* $NetBSD: ebusreg.h,v 1.1 1999/06/04 13:29:13 mrg Exp $ */ 3 4 /* 5 * Copyright (c) 1999 Matthew R. Green 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef _SPARC64_DEV_EBUSREG_H_ 31 #define _SPARC64_DEV_EBUSREG_H_ 32 33 /* 34 * UltraSPARC `ebus' 35 * 36 * The `ebus' bus is designed to plug traditional PC-ISA devices into 37 * an SPARC system with as few costs as possible, without sacrificing 38 * to performance. Typically, it is implemented in the PCIO IC from 39 * SME, which also implements a `hme-compatible' PCI network device 40 * (`network'). The ebus has 4 DMA channels, similar to the DMA seen 41 * in the ESP SCSI DMA. 42 * 43 * Typical UltraSPARC systems have a NatSemi SuperIO IC to provide 44 * serial ports for the keyboard and mouse (`se'), floppy disk 45 * controller (`fdthree'), parallel port controller (`bpp') connected 46 * to the ebus, and a PCI-IDE controller (connected directly to the 47 * PCI bus, of course), as well as a Siemens Nixdorf SAB82532 dual 48 * channel serial controller (`su' providing ttya and ttyb), an MK48T59 49 * EEPROM/clock controller (also where the idprom, including the 50 * ethernet address, is located), the audio system (`SUNW,CS4231', same 51 * as other UltraSPARC and some SPARC systems), and other various 52 * internal devices found on traditional SPARC systems such as the 53 * `power', `flashprom', etc., devices. 54 * 55 * The ebus uses an interrupt mapping scheme similar to PCI, though 56 * the actual structures are different. 57 */ 58 59 /* 60 * ebus PROM structures 61 */ 62 63 struct ebus_regs { 64 u_int32_t hi; /* high bits of physaddr */ 65 u_int32_t lo; 66 u_int32_t size; 67 }; 68 69 #define EBUS_PADDR_FROM_REG(reg) ((((paddr_t)((reg)->hi)) << 32UL) | ((paddr_t)(reg)->lo)) 70 71 struct ebus_ranges { 72 u_int32_t child_hi; /* child high phys addr */ 73 u_int32_t child_lo; /* child low phys addr */ 74 u_int32_t phys_hi; /* parent high phys addr */ 75 u_int32_t phys_mid; /* parent mid phys addr */ 76 u_int32_t phys_lo; /* parent low phys addr */ 77 u_int32_t size; 78 }; 79 80 struct ebus_mainbus_ranges { 81 u_int32_t child_hi; 82 u_int32_t child_lo; 83 u_int32_t phys_hi; 84 u_int32_t phys_lo; 85 u_int32_t size; 86 }; 87 88 struct ebus_interrupt_map { 89 u_int32_t hi; /* high phys addr mask */ 90 u_int32_t lo; /* low phys addr mask */ 91 u_int32_t intr; /* interrupt mask */ 92 int32_t cnode; /* child node */ 93 u_int32_t cintr; /* child interrupt */ 94 }; 95 96 struct ebus_interrupt_map_mask { 97 u_int32_t hi; /* high phys addr */ 98 u_int32_t lo; /* low phys addr */ 99 u_int32_t intr; /* interrupt */ 100 }; 101 102 /* EBUS dma registers */ 103 #define EBDMA_DCSR 0x0 /* control/status */ 104 #define EBDMA_DADDR 0x4 /* DMA address */ 105 #define EBDMA_DCNT 0x8 /* DMA count */ 106 107 /* EBUS DMA control/status (EBDMA_DCSR) */ 108 #define EBDCSR_INT 0x00000001 /* interrupt pending */ 109 #define EBDCSR_ERR 0x00000002 /* error pending */ 110 #define EBDCSR_DRAIN 0x00000004 /* drain */ 111 #define EBDCSR_INTEN 0x00000010 /* interrupt enable */ 112 #define EBDCSR_RESET 0x00000080 /* reset */ 113 #define EBDCSR_WRITE 0x00000100 /* write */ 114 #define EBDCSR_DMAEN 0x00000200 /* dma enable */ 115 #define EBDCSR_CYC 0x00000400 /* cyc pending */ 116 #define EBDCSR_DIAGRD 0x00000800 /* diagnostic read done */ 117 #define EBDCSR_DIAGWR 0x00001000 /* diagnostic write done */ 118 #define EBDCSR_CNTEN 0x00002000 /* count enable */ 119 #define EBDCSR_TC 0x00004000 /* terminal count */ 120 #define EBDCSR_CSRDRNDIS 0x00010000 /* disable csr drain */ 121 #define EBDCSR_BURSTMASK 0x000c0000 /* burst size mask */ 122 #define EBDCSR_BURST_1 0x00080000 /* burst 1 */ 123 #define EBDCSR_BURST_4 0x00000000 /* burst 4 */ 124 #define EBDCSR_BURST_8 0x00040000 /* burst 8 */ 125 #define EBDCSR_BURST_16 0x000c0000 /* burst 16 */ 126 #define EBDCSR_DIAGEN 0x00100000 /* enable diagnostics */ 127 #define EBDCSR_ERRDIS 0x00400000 /* disable error pending */ 128 #define EBDCSR_TCIDIS 0x00800000 /* disable TCI */ 129 #define EBDCSR_NEXTEN 0x01000000 /* enable next */ 130 #define EBDCSR_DMAON 0x02000000 /* dma on */ 131 #define EBDCSR_A_LOADED 0x04000000 /* address loaded */ 132 #define EBDCSR_NA_LOADED 0x08000000 /* next address loaded */ 133 #define EBDCSR_DEVMASK 0xf0000000 /* device id mask */ 134 135 #endif /* _SPARC64_DEV_EBUSREG_H_ */ 136