1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 #ifndef ECORE_SP_H
31 #define ECORE_SP_H
32
33
34 #include <sys/types.h>
35 #include <sys/endian.h>
36 #include <sys/param.h>
37 #include <sys/lock.h>
38 #include <sys/mutex.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <machine/bus.h>
42 #include <net/ethernet.h>
43
44 #if _BYTE_ORDER == _LITTLE_ENDIAN
45 #ifndef LITTLE_ENDIAN
46 #define LITTLE_ENDIAN
47 #endif
48 #ifndef __LITTLE_ENDIAN
49 #define __LITTLE_ENDIAN
50 #endif
51 #undef BIG_ENDIAN
52 #undef __BIG_ENDIAN
53 #else /* _BIG_ENDIAN */
54 #ifndef BIG_ENDIAN
55 #define BIG_ENDIAN
56 #endif
57 #ifndef __BIG_ENDIAN
58 #define __BIG_ENDIAN
59 #endif
60 #undef LITTLE_ENDIAN
61 #undef __LITTLE_ENDIAN
62 #endif
63
64 #include "ecore_mfw_req.h"
65 #include "ecore_fw_defs.h"
66 #include "ecore_hsi.h"
67 #include "ecore_reg.h"
68
69 struct bxe_softc;
70 typedef bus_addr_t ecore_dma_addr_t; /* expected to be 64 bit wide */
71 typedef volatile int ecore_atomic_t;
72
73 #ifndef __bool_true_false_are_defined
74 #ifndef __cplusplus
75 #define bool _Bool
76 #endif /* !__cplusplus */
77 #endif /* !__bool_true_false_are_defined$ */
78
79 #define ETH_ALEN ETHER_ADDR_LEN /* 6 */
80
81 #define ECORE_SWCID_SHIFT 17
82 #define ECORE_SWCID_MASK ((0x1 << ECORE_SWCID_SHIFT) - 1)
83
84 #define ECORE_MC_HASH_SIZE 8
85 #define ECORE_MC_HASH_OFFSET(sc, i) \
86 (BAR_TSTRORM_INTMEM + \
87 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(FUNC_ID(sc)) + i*4)
88
89 #define ECORE_MAX_MULTICAST 64
90 #define ECORE_MAX_EMUL_MULTI 1
91
92 #define IRO sc->iro_array
93
94 typedef struct mtx ECORE_MUTEX;
95 #define ECORE_MUTEX_INIT(_mutex) \
96 mtx_init(_mutex, "ecore_lock", "ECORE Lock", MTX_DEF)
97 #define ECORE_MUTEX_LOCK(_mutex) mtx_lock(_mutex)
98 #define ECORE_MUTEX_UNLOCK(_mutex) mtx_unlock(_mutex)
99
100 typedef struct mtx ECORE_MUTEX_SPIN;
101 #define ECORE_SPIN_LOCK_INIT(_spin, _sc) \
102 mtx_init(_spin, "ecore_lock", "ECORE Lock", MTX_DEF)
103 #define ECORE_SPIN_LOCK_BH(_spin) mtx_lock(_spin) /* bh = bottom-half */
104 #define ECORE_SPIN_UNLOCK_BH(_spin) mtx_unlock(_spin) /* bh = bottom-half */
105
106 #define ECORE_SMP_MB_AFTER_CLEAR_BIT() mb()
107 #define ECORE_SMP_MB_BEFORE_CLEAR_BIT() mb()
108 #define ECORE_SMP_MB() mb()
109 #define ECORE_SMP_RMB() rmb()
110 #define ECORE_SMP_WMB() wmb()
111 #define ECORE_MMIOWB() wmb()
112
113 #define ECORE_SET_BIT_NA(bit, var) bit_set(var, bit) /* non-atomic */
114 #define ECORE_CLEAR_BIT_NA(bit, var) bit_clear(var, bit) /* non-atomic */
115 #define ECORE_TEST_BIT(bit, var) bxe_test_bit(bit, var)
116 #define ECORE_SET_BIT(bit, var) bxe_set_bit(bit, var)
117 #define ECORE_CLEAR_BIT(bit, var) bxe_clear_bit(bit, var)
118 #define ECORE_TEST_AND_CLEAR_BIT(bit, var) bxe_test_and_clear_bit(bit, var)
119
120 #define ECORE_ATOMIC_READ(a) atomic_load_acq_int((volatile int *)a)
121 #define ECORE_ATOMIC_SET(a, v) atomic_store_rel_int((volatile int *)a, v)
122 #define ECORE_ATOMIC_CMPXCHG(a, o, n) bxe_cmpxchg((volatile int *)a, o, n)
123
124 #define ECORE_RET_PENDING(pending_bit, pending) \
125 (ECORE_TEST_BIT(pending_bit, pending) ? ECORE_PENDING : ECORE_SUCCESS)
126
127 #define ECORE_SET_FLAG(value, mask, flag) \
128 do { \
129 (value) &= ~(mask); \
130 (value) |= ((flag) << (mask##_SHIFT)); \
131 } while (0)
132
133 #define ECORE_GET_FLAG(value, mask) \
134 (((value) &= (mask)) >> (mask##_SHIFT))
135
136 #define ECORE_MIGHT_SLEEP()
137
138 #define ECORE_FCOE_CID(sc) ((sc)->fp[FCOE_IDX(sc)].cl_id)
139
140 #define ECORE_MEMCMP(_a, _b, _s) memcmp(_a, _b, _s)
141 #define ECORE_MEMCPY(_a, _b, _s) memcpy(_a, _b, _s)
142 #define ECORE_MEMSET(_a, _c, _s) memset(_a, _c, _s)
143
144 #define ECORE_CPU_TO_LE16(x) htole16(x)
145 #define ECORE_CPU_TO_LE32(x) htole32(x)
146
147 #define ECORE_WAIT(_s, _t) DELAY(1000)
148 #define ECORE_MSLEEP(_t) DELAY((_t) * 1000)
149
150 #define ECORE_LIKELY(x) __predict_true(x)
151 #define ECORE_UNLIKELY(x) __predict_false(x)
152
153 #define ECORE_ZALLOC(_size, _flags, _sc) \
154 malloc(_size, M_TEMP, (M_NOWAIT | M_ZERO))
155
156 #define ECORE_CALLOC(_len, _size, _flags, _sc) \
157 mallocarray(_len, _size, M_TEMP, (M_NOWAIT | M_ZERO))
158
159 #define ECORE_FREE(_s, _buf, _size) free(_buf, M_TEMP)
160
161 #define SC_ILT(sc) ((sc)->ilt)
162 #define ILOG2(x) ilog2(x)
163
164 #define ECORE_ILT_ZALLOC(x, y, size) \
165 do { \
166 x = malloc(sizeof(struct bxe_dma), M_DEVBUF, (M_NOWAIT | M_ZERO)); \
167 if (x) { \
168 if (bxe_dma_alloc((struct bxe_softc *)sc, \
169 size, (struct bxe_dma *)x, \
170 "ECORE_ILT") != 0) { \
171 free(x, M_DEVBUF); \
172 x = NULL; \
173 *y = 0; \
174 } else { \
175 *y = ((struct bxe_dma *)x)->paddr; \
176 } \
177 } \
178 } while (0)
179
180 #define ECORE_ILT_FREE(x, y, size) \
181 do { \
182 if (x) { \
183 bxe_dma_free((struct bxe_softc *)sc, x); \
184 free(x, M_DEVBUF); \
185 x = NULL; \
186 y = 0; \
187 } \
188 } while (0)
189
190 #define ECORE_IS_VALID_ETHER_ADDR(_mac) TRUE
191
192 #define ECORE_IS_MF_SD_MODE IS_MF_SD_MODE
193 #define ECORE_IS_MF_SI_MODE IS_MF_SI_MODE
194 #define ECORE_IS_MF_AFEX_MODE IS_MF_AFEX_MODE
195
196 #define ECORE_SET_CTX_VALIDATION bxe_set_ctx_validation
197
198 #define ECORE_UPDATE_COALESCE_SB_INDEX bxe_update_coalesce_sb_index
199
200 #define ECORE_ALIGN(x, a) ((((x) + (a) - 1) / (a)) * (a))
201
202 #define ECORE_REG_WR_DMAE_LEN REG_WR_DMAE_LEN
203
204 #define ECORE_PATH_ID SC_PATH
205 #define ECORE_PORT_ID SC_PORT
206 #define ECORE_FUNC_ID SC_FUNC
207 #define ECORE_ABS_FUNC_ID SC_ABS_FUNC
208
209 uint32_t calc_crc32(uint8_t *crc32_packet, uint32_t crc32_length,
210 uint32_t crc32_seed, uint8_t complement);
211 static inline uint32_t
ECORE_CRC32_LE(uint32_t seed,uint8_t * mac,uint32_t len)212 ECORE_CRC32_LE(uint32_t seed, uint8_t *mac, uint32_t len)
213 {
214 uint32_t packet_buf[2] = {0};
215 memcpy(((uint8_t *)(&packet_buf[0]))+2, &mac[0], 2);
216 memcpy(&packet_buf[1], &mac[2], 4);
217 return bswap32(calc_crc32((uint8_t *)packet_buf, 8, seed, 0));
218 }
219
220 #define ecore_sp_post(_sc, _a, _b, _c, _d) \
221 bxe_sp_post(_sc, _a, _b, U64_HI(_c), U64_LO(_c), _d)
222
223 #ifdef ECORE_STOP_ON_ERROR
224
225 #define ECORE_DBG_BREAK_IF(exp) \
226 do { \
227 if (__predict_false(exp)) { \
228 panic("ECORE"); \
229 } \
230 } while (0)
231
232 #define ECORE_BUG() \
233 do { \
234 panic("BUG (%s:%d)", __FILE__, __LINE__); \
235 } while(0);
236
237 #define ECORE_BUG_ON(exp) \
238 do { \
239 if (__predict_true(exp)) { \
240 panic("BUG_ON (%s:%d)", __FILE__, __LINE__); \
241 } \
242 } while (0)
243
244 #else
245
246
247 extern unsigned long bxe_debug;
248 #define BXE_DEBUG_ECORE_DBG_BREAK_IF 0x01
249 #define BXE_DEBUG_ECORE_BUG 0x02
250 #define BXE_DEBUG_ECORE_BUG_ON 0x04
251
252 #define ECORE_DBG_BREAK_IF(exp) \
253 if (bxe_debug & BXE_DEBUG_ECORE_DBG_BREAK_IF) \
254 printf("%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__);
255
256 #define ECORE_BUG(exp) \
257 if (bxe_debug & BXE_DEBUG_ECORE_BUG) \
258 printf("%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__);
259
260 #define ECORE_BUG_ON(exp) \
261 if (bxe_debug & BXE_DEBUG_ECORE_BUG_ON) \
262 printf("%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__);
263
264
265 #endif /* #ifdef ECORE_STOP_ON_ERROR */
266
267 #define ECORE_ERR(str, ...) \
268 BLOGE(sc, "ECORE: " str, ##__VA_ARGS__)
269
270 #define DBG_SP 0x00000004 /* defined in bxe.h */
271
272 #define ECORE_MSG(sc, m, ...) \
273 BLOGD(sc, DBG_SP, "ECORE: " m, ##__VA_ARGS__)
274
275 typedef struct _ecore_list_entry_t
276 {
277 struct _ecore_list_entry_t *next, *prev;
278 } ecore_list_entry_t;
279
280 typedef struct ecore_list_t
281 {
282 ecore_list_entry_t *head, *tail;
283 unsigned long cnt;
284 } ecore_list_t;
285
286 /* initialize the list */
287 #define ECORE_LIST_INIT(_list) \
288 do { \
289 (_list)->head = NULL; \
290 (_list)->tail = NULL; \
291 (_list)->cnt = 0; \
292 } while (0)
293
294 /* return TRUE if the element is the last on the list */
295 #define ECORE_LIST_IS_LAST(_elem, _list) \
296 (_elem == (_list)->tail)
297
298 /* return TRUE if the list is empty */
299 #define ECORE_LIST_IS_EMPTY(_list) \
300 ((_list)->cnt == 0)
301
302 /* return the first element */
303 #define ECORE_LIST_FIRST_ENTRY(_list, cast, _link) \
304 (cast *)((_list)->head)
305
306 /* return the next element */
307 #define ECORE_LIST_NEXT(_elem, _link, cast) \
308 (cast *)((&((_elem)->_link))->next)
309
310 /* push an element on the head of the list */
311 #define ECORE_LIST_PUSH_HEAD(_elem, _list) \
312 do { \
313 (_elem)->prev = (ecore_list_entry_t *)0; \
314 (_elem)->next = (_list)->head; \
315 if ((_list)->tail == (ecore_list_entry_t *)0) { \
316 (_list)->tail = (_elem); \
317 } else { \
318 (_list)->head->prev = (_elem); \
319 } \
320 (_list)->head = (_elem); \
321 (_list)->cnt++; \
322 } while (0)
323
324 /* push an element on the tail of the list */
325 #define ECORE_LIST_PUSH_TAIL(_elem, _list) \
326 do { \
327 (_elem)->next = (ecore_list_entry_t *)0; \
328 (_elem)->prev = (_list)->tail; \
329 if ((_list)->tail) { \
330 (_list)->tail->next = (_elem); \
331 } else { \
332 (_list)->head = (_elem); \
333 } \
334 (_list)->tail = (_elem); \
335 (_list)->cnt++; \
336 } while (0)
337
338 /* push list1 on the head of list2 and return with list1 as empty */
339 #define ECORE_LIST_SPLICE_INIT(_list1, _list2) \
340 do { \
341 (_list1)->tail->next = (_list2)->head; \
342 if ((_list2)->head) { \
343 (_list2)->head->prev = (_list1)->tail; \
344 } else { \
345 (_list2)->tail = (_list1)->tail; \
346 } \
347 (_list2)->head = (_list1)->head; \
348 (_list2)->cnt += (_list1)->cnt; \
349 (_list1)->head = NULL; \
350 (_list1)->tail = NULL; \
351 (_list1)->cnt = 0; \
352 } while (0)
353
354 /* remove an element from the list */
355 #define ECORE_LIST_REMOVE_ENTRY(_elem, _list) \
356 do { \
357 if ((_list)->head == (_elem)) { \
358 if ((_list)->head) { \
359 (_list)->head = (_list)->head->next; \
360 if ((_list)->head) { \
361 (_list)->head->prev = (ecore_list_entry_t *)0; \
362 } else { \
363 (_list)->tail = (ecore_list_entry_t *)0; \
364 } \
365 (_list)->cnt--; \
366 } \
367 } else if ((_list)->tail == (_elem)) { \
368 if ((_list)->tail) { \
369 (_list)->tail = (_list)->tail->prev; \
370 if ((_list)->tail) { \
371 (_list)->tail->next = (ecore_list_entry_t *)0; \
372 } else { \
373 (_list)->head = (ecore_list_entry_t *)0; \
374 } \
375 (_list)->cnt--; \
376 } \
377 } else { \
378 (_elem)->prev->next = (_elem)->next; \
379 (_elem)->next->prev = (_elem)->prev; \
380 (_list)->cnt--; \
381 } \
382 } while (0)
383
384 /* walk the list */
385 #define ECORE_LIST_FOR_EACH_ENTRY(pos, _list, _link, cast) \
386 for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _link); \
387 pos; \
388 pos = ECORE_LIST_NEXT(pos, _link, cast))
389
390 /* walk the list (safely) */
391 #define ECORE_LIST_FOR_EACH_ENTRY_SAFE(pos, n, _list, _link, cast) \
392 for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _lint), \
393 n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL; \
394 pos != NULL; \
395 pos = (cast *)n, \
396 n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL)
397
398
399 /* Manipulate a bit vector defined as an array of uint64_t */
400
401 /* Number of bits in one sge_mask array element */
402 #define BIT_VEC64_ELEM_SZ 64
403 #define BIT_VEC64_ELEM_SHIFT 6
404 #define BIT_VEC64_ELEM_MASK ((uint64_t)BIT_VEC64_ELEM_SZ - 1)
405
406 #define __BIT_VEC64_SET_BIT(el, bit) \
407 do { \
408 el = ((el) | ((uint64_t)0x1 << (bit))); \
409 } while (0)
410
411 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
412 do { \
413 el = ((el) & (~((uint64_t)0x1 << (bit)))); \
414 } while (0)
415
416 #define BIT_VEC64_SET_BIT(vec64, idx) \
417 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
418 (idx) & BIT_VEC64_ELEM_MASK)
419
420 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
421 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
422 (idx) & BIT_VEC64_ELEM_MASK)
423
424 #define BIT_VEC64_TEST_BIT(vec64, idx) \
425 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
426 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
427
428 /*
429 * Creates a bitmask of all ones in less significant bits.
430 * idx - index of the most significant bit in the created mask
431 */
432 #define BIT_VEC64_ONES_MASK(idx) \
433 (((uint64_t)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
434 #define BIT_VEC64_ELEM_ONE_MASK ((uint64_t)(~0))
435
436 /* fill in a MAC address the way the FW likes it */
437 static inline void
ecore_set_fw_mac_addr(uint16_t * fw_hi,uint16_t * fw_mid,uint16_t * fw_lo,uint8_t * mac)438 ecore_set_fw_mac_addr(uint16_t *fw_hi,
439 uint16_t *fw_mid,
440 uint16_t *fw_lo,
441 uint8_t *mac)
442 {
443 ((uint8_t *)fw_hi)[0] = mac[1];
444 ((uint8_t *)fw_hi)[1] = mac[0];
445 ((uint8_t *)fw_mid)[0] = mac[3];
446 ((uint8_t *)fw_mid)[1] = mac[2];
447 ((uint8_t *)fw_lo)[0] = mac[5];
448 ((uint8_t *)fw_lo)[1] = mac[4];
449 }
450
451
452 enum ecore_status_t {
453 ECORE_EXISTS = -6,
454 ECORE_IO = -5,
455 ECORE_TIMEOUT = -4,
456 ECORE_INVAL = -3,
457 ECORE_BUSY = -2,
458 ECORE_NOMEM = -1,
459 ECORE_SUCCESS = 0,
460 /* PENDING is not an error and should be positive */
461 ECORE_PENDING = 1,
462 };
463
464 enum {
465 SWITCH_UPDATE,
466 AFEX_UPDATE,
467 };
468
469
470
471
472 struct bxe_softc;
473 struct eth_context;
474
475 /* Bits representing general command's configuration */
476 enum {
477 RAMROD_TX,
478 RAMROD_RX,
479 /* Wait until all pending commands complete */
480 RAMROD_COMP_WAIT,
481 /* Don't send a ramrod, only update a registry */
482 RAMROD_DRV_CLR_ONLY,
483 /* Configure HW according to the current object state */
484 RAMROD_RESTORE,
485 /* Execute the next command now */
486 RAMROD_EXEC,
487 /* Don't add a new command and continue execution of posponed
488 * commands. If not set a new command will be added to the
489 * pending commands list.
490 */
491 RAMROD_CONT,
492 /* If there is another pending ramrod, wait until it finishes and
493 * re-try to submit this one. This flag can be set only in sleepable
494 * context, and should not be set from the context that completes the
495 * ramrods as deadlock will occur.
496 */
497 RAMROD_RETRY,
498 };
499
500 typedef enum {
501 ECORE_OBJ_TYPE_RX,
502 ECORE_OBJ_TYPE_TX,
503 ECORE_OBJ_TYPE_RX_TX,
504 } ecore_obj_type;
505
506 /* Public slow path states */
507 enum {
508 ECORE_FILTER_MAC_PENDING,
509 ECORE_FILTER_VLAN_PENDING,
510 ECORE_FILTER_VLAN_MAC_PENDING,
511 ECORE_FILTER_RX_MODE_PENDING,
512 ECORE_FILTER_RX_MODE_SCHED,
513 ECORE_FILTER_ISCSI_ETH_START_SCHED,
514 ECORE_FILTER_ISCSI_ETH_STOP_SCHED,
515 ECORE_FILTER_FCOE_ETH_START_SCHED,
516 ECORE_FILTER_FCOE_ETH_STOP_SCHED,
517 ECORE_FILTER_BYPASS_RX_MODE_PENDING,
518 ECORE_FILTER_BYPASS_MAC_PENDING,
519 ECORE_FILTER_BYPASS_RSS_CONF_PENDING,
520 ECORE_FILTER_MCAST_PENDING,
521 ECORE_FILTER_MCAST_SCHED,
522 ECORE_FILTER_RSS_CONF_PENDING,
523 ECORE_AFEX_FCOE_Q_UPDATE_PENDING,
524 ECORE_AFEX_PENDING_VIFSET_MCP_ACK,
525 ECORE_FILTER_VXLAN_PENDING
526 };
527
528 struct ecore_raw_obj {
529 uint8_t func_id;
530
531 /* Queue params */
532 uint8_t cl_id;
533 uint32_t cid;
534
535 /* Ramrod data buffer params */
536 void *rdata;
537 ecore_dma_addr_t rdata_mapping;
538
539 /* Ramrod state params */
540 int state; /* "ramrod is pending" state bit */
541 unsigned long *pstate; /* pointer to state buffer */
542
543 ecore_obj_type obj_type;
544
545 int (*wait_comp)(struct bxe_softc *sc,
546 struct ecore_raw_obj *o);
547
548 bool (*check_pending)(struct ecore_raw_obj *o);
549 void (*clear_pending)(struct ecore_raw_obj *o);
550 void (*set_pending)(struct ecore_raw_obj *o);
551 };
552
553 /************************* VLAN-MAC commands related parameters ***************/
554 struct ecore_mac_ramrod_data {
555 uint8_t mac[ETH_ALEN];
556 uint8_t is_inner_mac;
557 };
558
559 struct ecore_vlan_ramrod_data {
560 uint16_t vlan;
561 };
562
563 struct ecore_vlan_mac_ramrod_data {
564 uint8_t mac[ETH_ALEN];
565 uint8_t is_inner_mac;
566 uint16_t vlan;
567 };
568
569 struct ecore_vxlan_fltr_ramrod_data {
570 uint8_t innermac[ETH_ALEN];
571 uint32_t vni;
572 };
573
574 union ecore_classification_ramrod_data {
575 struct ecore_mac_ramrod_data mac;
576 struct ecore_vlan_ramrod_data vlan;
577 struct ecore_vlan_mac_ramrod_data vlan_mac;
578 struct ecore_vxlan_fltr_ramrod_data vxlan_fltr;
579 };
580
581 /* VLAN_MAC commands */
582 enum ecore_vlan_mac_cmd {
583 ECORE_VLAN_MAC_ADD,
584 ECORE_VLAN_MAC_DEL,
585 ECORE_VLAN_MAC_MOVE,
586 };
587
588 struct ecore_vlan_mac_data {
589 /* Requested command: ECORE_VLAN_MAC_XX */
590 enum ecore_vlan_mac_cmd cmd;
591 /* used to contain the data related vlan_mac_flags bits from
592 * ramrod parameters.
593 */
594 unsigned long vlan_mac_flags;
595
596 /* Needed for MOVE command */
597 struct ecore_vlan_mac_obj *target_obj;
598
599 union ecore_classification_ramrod_data u;
600 };
601
602 /*************************** Exe Queue obj ************************************/
603 union ecore_exe_queue_cmd_data {
604 struct ecore_vlan_mac_data vlan_mac;
605
606 struct {
607 /* TODO */
608 } mcast;
609 };
610
611 struct ecore_exeq_elem {
612 ecore_list_entry_t link;
613
614 /* Length of this element in the exe_chunk. */
615 int cmd_len;
616
617 union ecore_exe_queue_cmd_data cmd_data;
618 };
619
620 union ecore_qable_obj;
621
622 union ecore_exeq_comp_elem {
623 union event_ring_elem *elem;
624 };
625
626 struct ecore_exe_queue_obj;
627
628 typedef int (*exe_q_validate)(struct bxe_softc *sc,
629 union ecore_qable_obj *o,
630 struct ecore_exeq_elem *elem);
631
632 typedef int (*exe_q_remove)(struct bxe_softc *sc,
633 union ecore_qable_obj *o,
634 struct ecore_exeq_elem *elem);
635
636 /* Return positive if entry was optimized, 0 - if not, negative
637 * in case of an error.
638 */
639 typedef int (*exe_q_optimize)(struct bxe_softc *sc,
640 union ecore_qable_obj *o,
641 struct ecore_exeq_elem *elem);
642 typedef int (*exe_q_execute)(struct bxe_softc *sc,
643 union ecore_qable_obj *o,
644 ecore_list_t *exe_chunk,
645 unsigned long *ramrod_flags);
646 typedef struct ecore_exeq_elem *
647 (*exe_q_get)(struct ecore_exe_queue_obj *o,
648 struct ecore_exeq_elem *elem);
649
650 struct ecore_exe_queue_obj {
651 /* Commands pending for an execution. */
652 ecore_list_t exe_queue;
653
654 /* Commands pending for an completion. */
655 ecore_list_t pending_comp;
656
657 ECORE_MUTEX_SPIN lock;
658
659 /* Maximum length of commands' list for one execution */
660 int exe_chunk_len;
661
662 union ecore_qable_obj *owner;
663
664 /****** Virtual functions ******/
665 /**
666 * Called before commands execution for commands that are really
667 * going to be executed (after 'optimize').
668 *
669 * Must run under exe_queue->lock
670 */
671 exe_q_validate validate;
672
673 /**
674 * Called before removing pending commands, cleaning allocated
675 * resources (e.g., credits from validate)
676 */
677 exe_q_remove remove;
678
679 /**
680 * This will try to cancel the current pending commands list
681 * considering the new command.
682 *
683 * Returns the number of optimized commands or a negative error code
684 *
685 * Must run under exe_queue->lock
686 */
687 exe_q_optimize optimize;
688
689 /**
690 * Run the next commands chunk (owner specific).
691 */
692 exe_q_execute execute;
693
694 /**
695 * Return the exe_queue element containing the specific command
696 * if any. Otherwise return NULL.
697 */
698 exe_q_get get;
699 };
700 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/
701 /*
702 * Element in the VLAN_MAC registry list having all current configured
703 * rules.
704 */
705 struct ecore_vlan_mac_registry_elem {
706 ecore_list_entry_t link;
707
708 /* Used to store the cam offset used for the mac/vlan/vlan-mac.
709 * Relevant for 57710 and 57711 only. VLANs and MACs share the
710 * same CAM for these chips.
711 */
712 int cam_offset;
713
714 /* Needed for DEL and RESTORE flows */
715 unsigned long vlan_mac_flags;
716
717 union ecore_classification_ramrod_data u;
718 };
719
720 /* Bits representing VLAN_MAC commands specific flags */
721 enum {
722 ECORE_UC_LIST_MAC,
723 ECORE_ETH_MAC,
724 ECORE_ISCSI_ETH_MAC,
725 ECORE_NETQ_ETH_MAC,
726 ECORE_DONT_CONSUME_CAM_CREDIT,
727 ECORE_DONT_CONSUME_CAM_CREDIT_DEST,
728 };
729 /* When looking for matching filters, some flags are not interesting */
730 #define ECORE_VLAN_MAC_CMP_MASK (1 << ECORE_UC_LIST_MAC | \
731 1 << ECORE_ETH_MAC | \
732 1 << ECORE_ISCSI_ETH_MAC | \
733 1 << ECORE_NETQ_ETH_MAC)
734 #define ECORE_VLAN_MAC_CMP_FLAGS(flags) \
735 ((flags) & ECORE_VLAN_MAC_CMP_MASK)
736
737 struct ecore_vlan_mac_ramrod_params {
738 /* Object to run the command from */
739 struct ecore_vlan_mac_obj *vlan_mac_obj;
740
741 /* General command flags: COMP_WAIT, etc. */
742 unsigned long ramrod_flags;
743
744 /* Command specific configuration request */
745 struct ecore_vlan_mac_data user_req;
746 };
747
748 struct ecore_vlan_mac_obj {
749 struct ecore_raw_obj raw;
750
751 /* Bookkeeping list: will prevent the addition of already existing
752 * entries.
753 */
754 ecore_list_t head;
755 /* Implement a simple reader/writer lock on the head list.
756 * all these fields should only be accessed under the exe_queue lock
757 */
758 uint8_t head_reader; /* Num. of readers accessing head list */
759 bool head_exe_request; /* Pending execution request. */
760 unsigned long saved_ramrod_flags; /* Ramrods of pending execution */
761
762 /* Execution queue interface instance */
763 struct ecore_exe_queue_obj exe_queue;
764
765 /* MACs credit pool */
766 struct ecore_credit_pool_obj *macs_pool;
767
768 /* VLANs credit pool */
769 struct ecore_credit_pool_obj *vlans_pool;
770
771 /* RAMROD command to be used */
772 int ramrod_cmd;
773
774 /* copy first n elements onto preallocated buffer
775 *
776 * @param n number of elements to get
777 * @param buf buffer preallocated by caller into which elements
778 * will be copied. Note elements are 4-byte aligned
779 * so buffer size must be able to accommodate the
780 * aligned elements.
781 *
782 * @return number of copied bytes
783 */
784
785 int (*get_n_elements)(struct bxe_softc *sc,
786 struct ecore_vlan_mac_obj *o, int n, uint8_t *base,
787 uint8_t stride, uint8_t size);
788
789 /**
790 * Checks if ADD-ramrod with the given params may be performed.
791 *
792 * @return zero if the element may be added
793 */
794
795 int (*check_add)(struct bxe_softc *sc,
796 struct ecore_vlan_mac_obj *o,
797 union ecore_classification_ramrod_data *data);
798
799 /**
800 * Checks if DEL-ramrod with the given params may be performed.
801 *
802 * @return TRUE if the element may be deleted
803 */
804 struct ecore_vlan_mac_registry_elem *
805 (*check_del)(struct bxe_softc *sc,
806 struct ecore_vlan_mac_obj *o,
807 union ecore_classification_ramrod_data *data);
808
809 /**
810 * Checks if DEL-ramrod with the given params may be performed.
811 *
812 * @return TRUE if the element may be deleted
813 */
814 bool (*check_move)(struct bxe_softc *sc,
815 struct ecore_vlan_mac_obj *src_o,
816 struct ecore_vlan_mac_obj *dst_o,
817 union ecore_classification_ramrod_data *data);
818
819 /**
820 * Update the relevant credit object(s) (consume/return
821 * correspondingly).
822 */
823 bool (*get_credit)(struct ecore_vlan_mac_obj *o);
824 bool (*put_credit)(struct ecore_vlan_mac_obj *o);
825 bool (*get_cam_offset)(struct ecore_vlan_mac_obj *o, int *offset);
826 bool (*put_cam_offset)(struct ecore_vlan_mac_obj *o, int offset);
827
828 /**
829 * Configures one rule in the ramrod data buffer.
830 */
831 void (*set_one_rule)(struct bxe_softc *sc,
832 struct ecore_vlan_mac_obj *o,
833 struct ecore_exeq_elem *elem, int rule_idx,
834 int cam_offset);
835
836 /**
837 * Delete all configured elements having the given
838 * vlan_mac_flags specification. Assumes no pending for
839 * execution commands. Will schedule all all currently
840 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags
841 * specification for deletion and will use the given
842 * ramrod_flags for the last DEL operation.
843 *
844 * @param sc
845 * @param o
846 * @param ramrod_flags RAMROD_XX flags
847 *
848 * @return 0 if the last operation has completed successfully
849 * and there are no more elements left, positive value
850 * if there are pending for completion commands,
851 * negative value in case of failure.
852 */
853 int (*delete_all)(struct bxe_softc *sc,
854 struct ecore_vlan_mac_obj *o,
855 unsigned long *vlan_mac_flags,
856 unsigned long *ramrod_flags);
857
858 /**
859 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously
860 * configured elements list.
861 *
862 * @param sc
863 * @param p Command parameters (RAMROD_COMP_WAIT bit in
864 * ramrod_flags is only taken into an account)
865 * @param ppos a pointer to the cookie that should be given back in the
866 * next call to make function handle the next element. If
867 * *ppos is set to NULL it will restart the iterator.
868 * If returned *ppos == NULL this means that the last
869 * element has been handled.
870 *
871 * @return int
872 */
873 int (*restore)(struct bxe_softc *sc,
874 struct ecore_vlan_mac_ramrod_params *p,
875 struct ecore_vlan_mac_registry_elem **ppos);
876
877 /**
878 * Should be called on a completion arrival.
879 *
880 * @param sc
881 * @param o
882 * @param cqe Completion element we are handling
883 * @param ramrod_flags if RAMROD_CONT is set the next bulk of
884 * pending commands will be executed.
885 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE
886 * may also be set if needed.
887 *
888 * @return 0 if there are neither pending nor waiting for
889 * completion commands. Positive value if there are
890 * pending for execution or for completion commands.
891 * Negative value in case of an error (including an
892 * error in the cqe).
893 */
894 int (*complete)(struct bxe_softc *sc, struct ecore_vlan_mac_obj *o,
895 union event_ring_elem *cqe,
896 unsigned long *ramrod_flags);
897
898 /**
899 * Wait for completion of all commands. Don't schedule new ones,
900 * just wait. It assumes that the completion code will schedule
901 * for new commands.
902 */
903 int (*wait)(struct bxe_softc *sc, struct ecore_vlan_mac_obj *o);
904 };
905
906 enum {
907 ECORE_LLH_CAM_ISCSI_ETH_LINE = 0,
908 ECORE_LLH_CAM_ETH_LINE,
909 ECORE_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2
910 };
911
912 void ecore_set_mac_in_nig(struct bxe_softc *sc,
913 bool add, unsigned char *dev_addr, int index);
914
915 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */
916
917 /* RX_MODE ramrod special flags: set in rx_mode_flags field in
918 * a ecore_rx_mode_ramrod_params.
919 */
920 enum {
921 ECORE_RX_MODE_FCOE_ETH,
922 ECORE_RX_MODE_ISCSI_ETH,
923 };
924
925 enum {
926 ECORE_ACCEPT_UNICAST,
927 ECORE_ACCEPT_MULTICAST,
928 ECORE_ACCEPT_ALL_UNICAST,
929 ECORE_ACCEPT_ALL_MULTICAST,
930 ECORE_ACCEPT_BROADCAST,
931 ECORE_ACCEPT_UNMATCHED,
932 ECORE_ACCEPT_ANY_VLAN
933 };
934
935 struct ecore_rx_mode_ramrod_params {
936 struct ecore_rx_mode_obj *rx_mode_obj;
937 unsigned long *pstate;
938 int state;
939 uint8_t cl_id;
940 uint32_t cid;
941 uint8_t func_id;
942 unsigned long ramrod_flags;
943 unsigned long rx_mode_flags;
944
945 /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to
946 * a tstorm_eth_mac_filter_config (e1x).
947 */
948 void *rdata;
949 ecore_dma_addr_t rdata_mapping;
950
951 /* Rx mode settings */
952 unsigned long rx_accept_flags;
953
954 /* internal switching settings */
955 unsigned long tx_accept_flags;
956 };
957
958 struct ecore_rx_mode_obj {
959 int (*config_rx_mode)(struct bxe_softc *sc,
960 struct ecore_rx_mode_ramrod_params *p);
961
962 int (*wait_comp)(struct bxe_softc *sc,
963 struct ecore_rx_mode_ramrod_params *p);
964 };
965
966 /********************** Set multicast group ***********************************/
967
968 struct ecore_mcast_list_elem {
969 ecore_list_entry_t link;
970 uint8_t *mac;
971 };
972
973 union ecore_mcast_config_data {
974 uint8_t *mac;
975 uint8_t bin; /* used in a RESTORE flow */
976 };
977
978 struct ecore_mcast_ramrod_params {
979 struct ecore_mcast_obj *mcast_obj;
980
981 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */
982 unsigned long ramrod_flags;
983
984 ecore_list_t mcast_list; /* list of struct ecore_mcast_list_elem */
985 /** TODO:
986 * - rename it to macs_num.
987 * - Add a new command type for handling pending commands
988 * (remove "zero semantics").
989 *
990 * Length of mcast_list. If zero and ADD_CONT command - post
991 * pending commands.
992 */
993 int mcast_list_len;
994 };
995
996 enum ecore_mcast_cmd {
997 ECORE_MCAST_CMD_ADD,
998 ECORE_MCAST_CMD_CONT,
999 ECORE_MCAST_CMD_DEL,
1000 ECORE_MCAST_CMD_RESTORE,
1001 };
1002
1003 struct ecore_mcast_obj {
1004 struct ecore_raw_obj raw;
1005
1006 union {
1007 struct {
1008 #define ECORE_MCAST_BINS_NUM 256
1009 #define ECORE_MCAST_VEC_SZ (ECORE_MCAST_BINS_NUM / 64)
1010 uint64_t vec[ECORE_MCAST_VEC_SZ];
1011
1012 /** Number of BINs to clear. Should be updated
1013 * immediately when a command arrives in order to
1014 * properly create DEL commands.
1015 */
1016 int num_bins_set;
1017 } aprox_match;
1018
1019 struct {
1020 ecore_list_t macs;
1021 int num_macs_set;
1022 } exact_match;
1023 } registry;
1024
1025 /* Pending commands */
1026 ecore_list_t pending_cmds_head;
1027
1028 /* A state that is set in raw.pstate, when there are pending commands */
1029 int sched_state;
1030
1031 /* Maximal number of mcast MACs configured in one command */
1032 int max_cmd_len;
1033
1034 /* Total number of currently pending MACs to configure: both
1035 * in the pending commands list and in the current command.
1036 */
1037 int total_pending_num;
1038
1039 uint8_t engine_id;
1040
1041 /**
1042 * @param cmd command to execute (ECORE_MCAST_CMD_X, see above)
1043 */
1044 int (*config_mcast)(struct bxe_softc *sc,
1045 struct ecore_mcast_ramrod_params *p,
1046 enum ecore_mcast_cmd cmd);
1047
1048 /**
1049 * Fills the ramrod data during the RESTORE flow.
1050 *
1051 * @param sc
1052 * @param o
1053 * @param start_idx Registry index to start from
1054 * @param rdata_idx Index in the ramrod data to start from
1055 *
1056 * @return -1 if we handled the whole registry or index of the last
1057 * handled registry element.
1058 */
1059 int (*hdl_restore)(struct bxe_softc *sc, struct ecore_mcast_obj *o,
1060 int start_bin, int *rdata_idx);
1061
1062 int (*enqueue_cmd)(struct bxe_softc *sc, struct ecore_mcast_obj *o,
1063 struct ecore_mcast_ramrod_params *p,
1064 enum ecore_mcast_cmd cmd);
1065
1066 void (*set_one_rule)(struct bxe_softc *sc,
1067 struct ecore_mcast_obj *o, int idx,
1068 union ecore_mcast_config_data *cfg_data,
1069 enum ecore_mcast_cmd cmd);
1070
1071 /** Checks if there are more mcast MACs to be set or a previous
1072 * command is still pending.
1073 */
1074 bool (*check_pending)(struct ecore_mcast_obj *o);
1075
1076 /**
1077 * Set/Clear/Check SCHEDULED state of the object
1078 */
1079 void (*set_sched)(struct ecore_mcast_obj *o);
1080 void (*clear_sched)(struct ecore_mcast_obj *o);
1081 bool (*check_sched)(struct ecore_mcast_obj *o);
1082
1083 /* Wait until all pending commands complete */
1084 int (*wait_comp)(struct bxe_softc *sc, struct ecore_mcast_obj *o);
1085
1086 /**
1087 * Handle the internal object counters needed for proper
1088 * commands handling. Checks that the provided parameters are
1089 * feasible.
1090 */
1091 int (*validate)(struct bxe_softc *sc,
1092 struct ecore_mcast_ramrod_params *p,
1093 enum ecore_mcast_cmd cmd);
1094
1095 /**
1096 * Restore the values of internal counters in case of a failure.
1097 */
1098 void (*revert)(struct bxe_softc *sc,
1099 struct ecore_mcast_ramrod_params *p,
1100 int old_num_bins);
1101
1102 int (*get_registry_size)(struct ecore_mcast_obj *o);
1103 void (*set_registry_size)(struct ecore_mcast_obj *o, int n);
1104 };
1105
1106 /*************************** Credit handling **********************************/
1107 struct ecore_credit_pool_obj {
1108
1109 /* Current amount of credit in the pool */
1110 ecore_atomic_t credit;
1111
1112 /* Maximum allowed credit. put() will check against it. */
1113 int pool_sz;
1114
1115 /* Allocate a pool table statically.
1116 *
1117 * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272)
1118 *
1119 * The set bit in the table will mean that the entry is available.
1120 */
1121 #define ECORE_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64)
1122 uint64_t pool_mirror[ECORE_POOL_VEC_SIZE];
1123
1124 /* Base pool offset (initialized differently */
1125 int base_pool_offset;
1126
1127 /**
1128 * Get the next free pool entry.
1129 *
1130 * @return TRUE if there was a free entry in the pool
1131 */
1132 bool (*get_entry)(struct ecore_credit_pool_obj *o, int *entry);
1133
1134 /**
1135 * Return the entry back to the pool.
1136 *
1137 * @return TRUE if entry is legal and has been successfully
1138 * returned to the pool.
1139 */
1140 bool (*put_entry)(struct ecore_credit_pool_obj *o, int entry);
1141
1142 /**
1143 * Get the requested amount of credit from the pool.
1144 *
1145 * @param cnt Amount of requested credit
1146 * @return TRUE if the operation is successful
1147 */
1148 bool (*get)(struct ecore_credit_pool_obj *o, int cnt);
1149
1150 /**
1151 * Returns the credit to the pool.
1152 *
1153 * @param cnt Amount of credit to return
1154 * @return TRUE if the operation is successful
1155 */
1156 bool (*put)(struct ecore_credit_pool_obj *o, int cnt);
1157
1158 /**
1159 * Reads the current amount of credit.
1160 */
1161 int (*check)(struct ecore_credit_pool_obj *o);
1162 };
1163
1164 /*************************** RSS configuration ********************************/
1165 enum {
1166 /* RSS_MODE bits are mutually exclusive */
1167 ECORE_RSS_MODE_DISABLED,
1168 ECORE_RSS_MODE_REGULAR,
1169
1170 ECORE_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */
1171
1172 ECORE_RSS_IPV4,
1173 ECORE_RSS_IPV4_TCP,
1174 ECORE_RSS_IPV4_UDP,
1175 ECORE_RSS_IPV6,
1176 ECORE_RSS_IPV6_TCP,
1177 ECORE_RSS_IPV6_UDP,
1178
1179 ECORE_RSS_IPV4_VXLAN,
1180 ECORE_RSS_IPV6_VXLAN,
1181 ECORE_RSS_TUNN_INNER_HDRS,
1182 };
1183
1184 struct ecore_config_rss_params {
1185 struct ecore_rss_config_obj *rss_obj;
1186
1187 /* may have RAMROD_COMP_WAIT set only */
1188 unsigned long ramrod_flags;
1189
1190 /* ECORE_RSS_X bits */
1191 unsigned long rss_flags;
1192
1193 /* Number hash bits to take into an account */
1194 uint8_t rss_result_mask;
1195
1196 /* Indirection table */
1197 uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
1198
1199 /* RSS hash values */
1200 uint32_t rss_key[10];
1201
1202 /* valid only iff ECORE_RSS_UPDATE_TOE is set */
1203 uint16_t toe_rss_bitmap;
1204 };
1205
1206 struct ecore_rss_config_obj {
1207 struct ecore_raw_obj raw;
1208
1209 /* RSS engine to use */
1210 uint8_t engine_id;
1211
1212 /* Last configured indirection table */
1213 uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
1214
1215 /* flags for enabling 4-tupple hash on UDP */
1216 uint8_t udp_rss_v4;
1217 uint8_t udp_rss_v6;
1218
1219 int (*config_rss)(struct bxe_softc *sc,
1220 struct ecore_config_rss_params *p);
1221 };
1222
1223 /*********************** Queue state update ***********************************/
1224
1225 /* UPDATE command options */
1226 enum {
1227 ECORE_Q_UPDATE_IN_VLAN_REM,
1228 ECORE_Q_UPDATE_IN_VLAN_REM_CHNG,
1229 ECORE_Q_UPDATE_OUT_VLAN_REM,
1230 ECORE_Q_UPDATE_OUT_VLAN_REM_CHNG,
1231 ECORE_Q_UPDATE_ANTI_SPOOF,
1232 ECORE_Q_UPDATE_ANTI_SPOOF_CHNG,
1233 ECORE_Q_UPDATE_ACTIVATE,
1234 ECORE_Q_UPDATE_ACTIVATE_CHNG,
1235 ECORE_Q_UPDATE_DEF_VLAN_EN,
1236 ECORE_Q_UPDATE_DEF_VLAN_EN_CHNG,
1237 ECORE_Q_UPDATE_SILENT_VLAN_REM_CHNG,
1238 ECORE_Q_UPDATE_SILENT_VLAN_REM,
1239 ECORE_Q_UPDATE_TX_SWITCHING_CHNG,
1240 ECORE_Q_UPDATE_TX_SWITCHING,
1241 ECORE_Q_UPDATE_PTP_PKTS_CHNG,
1242 ECORE_Q_UPDATE_PTP_PKTS,
1243 };
1244
1245 /* Allowed Queue states */
1246 enum ecore_q_state {
1247 ECORE_Q_STATE_RESET,
1248 ECORE_Q_STATE_INITIALIZED,
1249 ECORE_Q_STATE_ACTIVE,
1250 ECORE_Q_STATE_MULTI_COS,
1251 ECORE_Q_STATE_MCOS_TERMINATED,
1252 ECORE_Q_STATE_INACTIVE,
1253 ECORE_Q_STATE_STOPPED,
1254 ECORE_Q_STATE_TERMINATED,
1255 ECORE_Q_STATE_FLRED,
1256 ECORE_Q_STATE_MAX,
1257 };
1258
1259 /* Allowed Queue states */
1260 enum ecore_q_logical_state {
1261 ECORE_Q_LOGICAL_STATE_ACTIVE,
1262 ECORE_Q_LOGICAL_STATE_STOPPED,
1263 };
1264
1265 /* Allowed commands */
1266 enum ecore_queue_cmd {
1267 ECORE_Q_CMD_INIT,
1268 ECORE_Q_CMD_SETUP,
1269 ECORE_Q_CMD_SETUP_TX_ONLY,
1270 ECORE_Q_CMD_DEACTIVATE,
1271 ECORE_Q_CMD_ACTIVATE,
1272 ECORE_Q_CMD_UPDATE,
1273 ECORE_Q_CMD_UPDATE_TPA,
1274 ECORE_Q_CMD_HALT,
1275 ECORE_Q_CMD_CFC_DEL,
1276 ECORE_Q_CMD_TERMINATE,
1277 ECORE_Q_CMD_EMPTY,
1278 ECORE_Q_CMD_MAX,
1279 };
1280
1281 /* queue SETUP + INIT flags */
1282 enum {
1283 ECORE_Q_FLG_TPA,
1284 ECORE_Q_FLG_TPA_IPV6,
1285 ECORE_Q_FLG_TPA_GRO,
1286 ECORE_Q_FLG_STATS,
1287 ECORE_Q_FLG_ZERO_STATS,
1288 ECORE_Q_FLG_ACTIVE,
1289 ECORE_Q_FLG_OV,
1290 ECORE_Q_FLG_VLAN,
1291 ECORE_Q_FLG_COS,
1292 ECORE_Q_FLG_HC,
1293 ECORE_Q_FLG_HC_EN,
1294 ECORE_Q_FLG_DHC,
1295 ECORE_Q_FLG_OOO,
1296 ECORE_Q_FLG_FCOE,
1297 ECORE_Q_FLG_LEADING_RSS,
1298 ECORE_Q_FLG_MCAST,
1299 ECORE_Q_FLG_DEF_VLAN,
1300 ECORE_Q_FLG_TX_SWITCH,
1301 ECORE_Q_FLG_TX_SEC,
1302 ECORE_Q_FLG_ANTI_SPOOF,
1303 ECORE_Q_FLG_SILENT_VLAN_REM,
1304 ECORE_Q_FLG_FORCE_DEFAULT_PRI,
1305 ECORE_Q_FLG_REFUSE_OUTBAND_VLAN,
1306 ECORE_Q_FLG_PCSUM_ON_PKT,
1307 ECORE_Q_FLG_TUN_INC_INNER_IP_ID
1308 };
1309
1310 /* Queue type options: queue type may be a combination of below. */
1311 enum ecore_q_type {
1312 ECORE_Q_TYPE_FWD,
1313 /** TODO: Consider moving both these flags into the init()
1314 * ramrod params.
1315 */
1316 ECORE_Q_TYPE_HAS_RX,
1317 ECORE_Q_TYPE_HAS_TX,
1318 };
1319
1320 #define ECORE_PRIMARY_CID_INDEX 0
1321 #define ECORE_MULTI_TX_COS_E1X 3 /* QM only */
1322 #define ECORE_MULTI_TX_COS_E2_E3A0 2
1323 #define ECORE_MULTI_TX_COS_E3B0 3
1324 #define ECORE_MULTI_TX_COS 3 /* Maximum possible */
1325 #define MAC_PAD (ECORE_ALIGN(ETH_ALEN, sizeof(uint32_t)) - ETH_ALEN)
1326 /* DMAE channel to be used by FW for timesync workaroun. A driver that sends
1327 * timesync-related ramrods must not use this DMAE command ID.
1328 */
1329 #define FW_DMAE_CMD_ID 6
1330
1331 struct ecore_queue_init_params {
1332 struct {
1333 unsigned long flags;
1334 uint16_t hc_rate;
1335 uint8_t fw_sb_id;
1336 uint8_t sb_cq_index;
1337 } tx;
1338
1339 struct {
1340 unsigned long flags;
1341 uint16_t hc_rate;
1342 uint8_t fw_sb_id;
1343 uint8_t sb_cq_index;
1344 } rx;
1345
1346 /* CID context in the host memory */
1347 struct eth_context *cxts[ECORE_MULTI_TX_COS];
1348
1349 /* maximum number of cos supported by hardware */
1350 uint8_t max_cos;
1351 };
1352
1353 struct ecore_queue_terminate_params {
1354 /* index within the tx_only cids of this queue object */
1355 uint8_t cid_index;
1356 };
1357
1358 struct ecore_queue_cfc_del_params {
1359 /* index within the tx_only cids of this queue object */
1360 uint8_t cid_index;
1361 };
1362
1363 struct ecore_queue_update_params {
1364 unsigned long update_flags; /* ECORE_Q_UPDATE_XX bits */
1365 uint16_t def_vlan;
1366 uint16_t silent_removal_value;
1367 uint16_t silent_removal_mask;
1368 /* index within the tx_only cids of this queue object */
1369 uint8_t cid_index;
1370 };
1371
1372 struct ecore_queue_update_tpa_params {
1373 ecore_dma_addr_t sge_map;
1374 uint8_t update_ipv4;
1375 uint8_t update_ipv6;
1376 uint8_t max_tpa_queues;
1377 uint8_t max_sges_pkt;
1378 uint8_t complete_on_both_clients;
1379 uint8_t dont_verify_thr;
1380 uint8_t tpa_mode;
1381 uint8_t _pad;
1382
1383 uint16_t sge_buff_sz;
1384 uint16_t max_agg_sz;
1385
1386 uint16_t sge_pause_thr_low;
1387 uint16_t sge_pause_thr_high;
1388 };
1389
1390 struct rxq_pause_params {
1391 uint16_t bd_th_lo;
1392 uint16_t bd_th_hi;
1393 uint16_t rcq_th_lo;
1394 uint16_t rcq_th_hi;
1395 uint16_t sge_th_lo; /* valid iff ECORE_Q_FLG_TPA */
1396 uint16_t sge_th_hi; /* valid iff ECORE_Q_FLG_TPA */
1397 uint16_t pri_map;
1398 };
1399
1400 /* general */
1401 struct ecore_general_setup_params {
1402 /* valid iff ECORE_Q_FLG_STATS */
1403 uint8_t stat_id;
1404
1405 uint8_t spcl_id;
1406 uint16_t mtu;
1407 uint8_t cos;
1408
1409 uint8_t fp_hsi;
1410 };
1411
1412 struct ecore_rxq_setup_params {
1413 /* dma */
1414 ecore_dma_addr_t dscr_map;
1415 ecore_dma_addr_t sge_map;
1416 ecore_dma_addr_t rcq_map;
1417 ecore_dma_addr_t rcq_np_map;
1418
1419 uint16_t drop_flags;
1420 uint16_t buf_sz;
1421 uint8_t fw_sb_id;
1422 uint8_t cl_qzone_id;
1423
1424 /* valid iff ECORE_Q_FLG_TPA */
1425 uint16_t tpa_agg_sz;
1426 uint16_t sge_buf_sz;
1427 uint8_t max_sges_pkt;
1428 uint8_t max_tpa_queues;
1429 uint8_t rss_engine_id;
1430
1431 /* valid iff ECORE_Q_FLG_MCAST */
1432 uint8_t mcast_engine_id;
1433
1434 uint8_t cache_line_log;
1435
1436 uint8_t sb_cq_index;
1437
1438 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */
1439 uint16_t silent_removal_value;
1440 uint16_t silent_removal_mask;
1441 };
1442
1443 struct ecore_txq_setup_params {
1444 /* dma */
1445 ecore_dma_addr_t dscr_map;
1446
1447 uint8_t fw_sb_id;
1448 uint8_t sb_cq_index;
1449 uint8_t cos; /* valid iff ECORE_Q_FLG_COS */
1450 uint16_t traffic_type;
1451 /* equals to the leading rss client id, used for TX classification*/
1452 uint8_t tss_leading_cl_id;
1453
1454 /* valid iff ECORE_Q_FLG_DEF_VLAN */
1455 uint16_t default_vlan;
1456 };
1457
1458 struct ecore_queue_setup_params {
1459 struct ecore_general_setup_params gen_params;
1460 struct ecore_txq_setup_params txq_params;
1461 struct ecore_rxq_setup_params rxq_params;
1462 struct rxq_pause_params pause_params;
1463 unsigned long flags;
1464 };
1465
1466 struct ecore_queue_setup_tx_only_params {
1467 struct ecore_general_setup_params gen_params;
1468 struct ecore_txq_setup_params txq_params;
1469 unsigned long flags;
1470 /* index within the tx_only cids of this queue object */
1471 uint8_t cid_index;
1472 };
1473
1474 struct ecore_queue_state_params {
1475 struct ecore_queue_sp_obj *q_obj;
1476
1477 /* Current command */
1478 enum ecore_queue_cmd cmd;
1479
1480 /* may have RAMROD_COMP_WAIT set only */
1481 unsigned long ramrod_flags;
1482
1483 /* Params according to the current command */
1484 union {
1485 struct ecore_queue_update_params update;
1486 struct ecore_queue_update_tpa_params update_tpa;
1487 struct ecore_queue_setup_params setup;
1488 struct ecore_queue_init_params init;
1489 struct ecore_queue_setup_tx_only_params tx_only;
1490 struct ecore_queue_terminate_params terminate;
1491 struct ecore_queue_cfc_del_params cfc_del;
1492 } params;
1493 };
1494
1495 struct ecore_viflist_params {
1496 uint8_t echo_res;
1497 uint8_t func_bit_map_res;
1498 };
1499
1500 struct ecore_queue_sp_obj {
1501 uint32_t cids[ECORE_MULTI_TX_COS];
1502 uint8_t cl_id;
1503 uint8_t func_id;
1504
1505 /* number of traffic classes supported by queue.
1506 * The primary connection of the queue supports the first traffic
1507 * class. Any further traffic class is supported by a tx-only
1508 * connection.
1509 *
1510 * Therefore max_cos is also a number of valid entries in the cids
1511 * array.
1512 */
1513 uint8_t max_cos;
1514 uint8_t num_tx_only, next_tx_only;
1515
1516 enum ecore_q_state state, next_state;
1517
1518 /* bits from enum ecore_q_type */
1519 unsigned long type;
1520
1521 /* ECORE_Q_CMD_XX bits. This object implements "one
1522 * pending" paradigm but for debug and tracing purposes it's
1523 * more convenient to have different bits for different
1524 * commands.
1525 */
1526 unsigned long pending;
1527
1528 /* Buffer to use as a ramrod data and its mapping */
1529 void *rdata;
1530 ecore_dma_addr_t rdata_mapping;
1531
1532 /**
1533 * Performs one state change according to the given parameters.
1534 *
1535 * @return 0 in case of success and negative value otherwise.
1536 */
1537 int (*send_cmd)(struct bxe_softc *sc,
1538 struct ecore_queue_state_params *params);
1539
1540 /**
1541 * Sets the pending bit according to the requested transition.
1542 */
1543 int (*set_pending)(struct ecore_queue_sp_obj *o,
1544 struct ecore_queue_state_params *params);
1545
1546 /**
1547 * Checks that the requested state transition is legal.
1548 */
1549 int (*check_transition)(struct bxe_softc *sc,
1550 struct ecore_queue_sp_obj *o,
1551 struct ecore_queue_state_params *params);
1552
1553 /**
1554 * Completes the pending command.
1555 */
1556 int (*complete_cmd)(struct bxe_softc *sc,
1557 struct ecore_queue_sp_obj *o,
1558 enum ecore_queue_cmd);
1559
1560 int (*wait_comp)(struct bxe_softc *sc,
1561 struct ecore_queue_sp_obj *o,
1562 enum ecore_queue_cmd cmd);
1563 };
1564
1565 /********************** Function state update *********************************/
1566
1567 /* UPDATE command options */
1568 enum {
1569 ECORE_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
1570 ECORE_F_UPDATE_TX_SWITCH_SUSPEND,
1571 ECORE_F_UPDATE_SD_VLAN_TAG_CHNG,
1572 ECORE_F_UPDATE_SD_VLAN_ETH_TYPE_CHNG,
1573 ECORE_F_UPDATE_VLAN_FORCE_PRIO_CHNG,
1574 ECORE_F_UPDATE_VLAN_FORCE_PRIO_FLAG,
1575 ECORE_F_UPDATE_TUNNEL_CFG_CHNG,
1576 ECORE_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE,
1577 ECORE_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN,
1578 ECORE_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE,
1579 ECORE_F_UPDATE_TUNNEL_INNER_RSS,
1580 };
1581
1582 /* Allowed Function states */
1583 enum ecore_func_state {
1584 ECORE_F_STATE_RESET,
1585 ECORE_F_STATE_INITIALIZED,
1586 ECORE_F_STATE_STARTED,
1587 ECORE_F_STATE_TX_STOPPED,
1588 ECORE_F_STATE_MAX,
1589 };
1590
1591 /* Allowed Function commands */
1592 enum ecore_func_cmd {
1593 ECORE_F_CMD_HW_INIT,
1594 ECORE_F_CMD_START,
1595 ECORE_F_CMD_STOP,
1596 ECORE_F_CMD_HW_RESET,
1597 ECORE_F_CMD_AFEX_UPDATE,
1598 ECORE_F_CMD_AFEX_VIFLISTS,
1599 ECORE_F_CMD_TX_STOP,
1600 ECORE_F_CMD_TX_START,
1601 ECORE_F_CMD_SWITCH_UPDATE,
1602 ECORE_F_CMD_SET_TIMESYNC,
1603 ECORE_F_CMD_MAX,
1604 };
1605
1606 struct ecore_func_hw_init_params {
1607 /* A load phase returned by MCP.
1608 *
1609 * May be:
1610 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1611 * FW_MSG_CODE_DRV_LOAD_COMMON
1612 * FW_MSG_CODE_DRV_LOAD_PORT
1613 * FW_MSG_CODE_DRV_LOAD_FUNCTION
1614 */
1615 uint32_t load_phase;
1616 };
1617
1618 struct ecore_func_hw_reset_params {
1619 /* A load phase returned by MCP.
1620 *
1621 * May be:
1622 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1623 * FW_MSG_CODE_DRV_LOAD_COMMON
1624 * FW_MSG_CODE_DRV_LOAD_PORT
1625 * FW_MSG_CODE_DRV_LOAD_FUNCTION
1626 */
1627 uint32_t reset_phase;
1628 };
1629
1630 struct ecore_func_start_params {
1631 /* Multi Function mode:
1632 * - Single Function
1633 * - Switch Dependent
1634 * - Switch Independent
1635 */
1636 uint16_t mf_mode;
1637
1638 /* Switch Dependent mode outer VLAN tag */
1639 uint16_t sd_vlan_tag;
1640
1641 /* Function cos mode */
1642 uint8_t network_cos_mode;
1643
1644 /* UDP dest port for VXLAN */
1645 uint16_t vxlan_dst_port;
1646
1647 /* UDP dest port for Geneve */
1648 uint16_t geneve_dst_port;
1649
1650 /* Enable inner Rx classifications for L2GRE packets */
1651 uint8_t inner_clss_l2gre;
1652
1653 /* Enable inner Rx classifications for L2-Geneve packets */
1654 uint8_t inner_clss_l2geneve;
1655
1656 /* Enable inner Rx classification for vxlan packets */
1657 uint8_t inner_clss_vxlan;
1658
1659 /* Enable RSS according to inner header */
1660 uint8_t inner_rss;
1661
1662 /** Allows accepting of packets failing MF classification, possibly
1663 * only matching a given ethertype
1664 */
1665 uint8_t class_fail;
1666 uint16_t class_fail_ethtype;
1667
1668 /* Override priority of output packets */
1669 uint8_t sd_vlan_force_pri;
1670 uint8_t sd_vlan_force_pri_val;
1671
1672 /* Replace vlan's ethertype */
1673 uint16_t sd_vlan_eth_type;
1674
1675 /* Prevent inner vlans from being added by FW */
1676 uint8_t no_added_tags;
1677
1678 /* Inner-to-Outer vlan priority mapping */
1679 uint8_t c2s_pri[MAX_VLAN_PRIORITIES];
1680 uint8_t c2s_pri_default;
1681 uint8_t c2s_pri_valid;
1682 };
1683
1684 struct ecore_func_switch_update_params {
1685 unsigned long changes; /* ECORE_F_UPDATE_XX bits */
1686 uint16_t vlan;
1687 uint16_t vlan_eth_type;
1688 uint8_t vlan_force_prio;
1689 uint16_t vxlan_dst_port;
1690 uint16_t geneve_dst_port;
1691 };
1692
1693 struct ecore_func_afex_update_params {
1694 uint16_t vif_id;
1695 uint16_t afex_default_vlan;
1696 uint8_t allowed_priorities;
1697 };
1698
1699 struct ecore_func_afex_viflists_params {
1700 uint16_t vif_list_index;
1701 uint8_t func_bit_map;
1702 uint8_t afex_vif_list_command;
1703 uint8_t func_to_clear;
1704 };
1705
1706 struct ecore_func_tx_start_params {
1707 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
1708 uint8_t dcb_enabled;
1709 uint8_t dcb_version;
1710 uint8_t dont_add_pri_0;
1711 uint8_t dcb_outer_pri[MAX_TRAFFIC_TYPES];
1712 };
1713
1714 struct ecore_func_set_timesync_params {
1715 /* Reset, set or keep the current drift value */
1716 uint8_t drift_adjust_cmd;
1717 /* Dec, inc or keep the current offset */
1718 uint8_t offset_cmd;
1719 /* Drift value direction */
1720 uint8_t add_sub_drift_adjust_value;
1721 /* Drift, period and offset values to be used according to the commands
1722 * above.
1723 */
1724 uint8_t drift_adjust_value;
1725 uint32_t drift_adjust_period;
1726 uint64_t offset_delta;
1727 };
1728
1729 struct ecore_func_state_params {
1730 struct ecore_func_sp_obj *f_obj;
1731
1732 /* Current command */
1733 enum ecore_func_cmd cmd;
1734
1735 /* may have RAMROD_COMP_WAIT set only */
1736 unsigned long ramrod_flags;
1737
1738 /* Params according to the current command */
1739 union {
1740 struct ecore_func_hw_init_params hw_init;
1741 struct ecore_func_hw_reset_params hw_reset;
1742 struct ecore_func_start_params start;
1743 struct ecore_func_switch_update_params switch_update;
1744 struct ecore_func_afex_update_params afex_update;
1745 struct ecore_func_afex_viflists_params afex_viflists;
1746 struct ecore_func_tx_start_params tx_start;
1747 struct ecore_func_set_timesync_params set_timesync;
1748 } params;
1749 };
1750
1751 struct ecore_func_sp_drv_ops {
1752 /* Init tool + runtime initialization:
1753 * - Common Chip
1754 * - Common (per Path)
1755 * - Port
1756 * - Function phases
1757 */
1758 int (*init_hw_cmn_chip)(struct bxe_softc *sc);
1759 int (*init_hw_cmn)(struct bxe_softc *sc);
1760 int (*init_hw_port)(struct bxe_softc *sc);
1761 int (*init_hw_func)(struct bxe_softc *sc);
1762
1763 /* Reset Function HW: Common, Port, Function phases. */
1764 void (*reset_hw_cmn)(struct bxe_softc *sc);
1765 void (*reset_hw_port)(struct bxe_softc *sc);
1766 void (*reset_hw_func)(struct bxe_softc *sc);
1767
1768 /* Init/Free GUNZIP resources */
1769 int (*gunzip_init)(struct bxe_softc *sc);
1770 void (*gunzip_end)(struct bxe_softc *sc);
1771
1772 /* Prepare/Release FW resources */
1773 int (*init_fw)(struct bxe_softc *sc);
1774 void (*release_fw)(struct bxe_softc *sc);
1775 };
1776
1777 struct ecore_func_sp_obj {
1778 enum ecore_func_state state, next_state;
1779
1780 /* ECORE_FUNC_CMD_XX bits. This object implements "one
1781 * pending" paradigm but for debug and tracing purposes it's
1782 * more convenient to have different bits for different
1783 * commands.
1784 */
1785 unsigned long pending;
1786
1787 /* Buffer to use as a ramrod data and its mapping */
1788 void *rdata;
1789 ecore_dma_addr_t rdata_mapping;
1790
1791 /* Buffer to use as a afex ramrod data and its mapping.
1792 * This can't be same rdata as above because afex ramrod requests
1793 * can arrive to the object in parallel to other ramrod requests.
1794 */
1795 void *afex_rdata;
1796 ecore_dma_addr_t afex_rdata_mapping;
1797
1798 /* this mutex validates that when pending flag is taken, the next
1799 * ramrod to be sent will be the one set the pending bit
1800 */
1801 ECORE_MUTEX one_pending_mutex;
1802
1803 /* Driver interface */
1804 struct ecore_func_sp_drv_ops *drv;
1805
1806 /**
1807 * Performs one state change according to the given parameters.
1808 *
1809 * @return 0 in case of success and negative value otherwise.
1810 */
1811 int (*send_cmd)(struct bxe_softc *sc,
1812 struct ecore_func_state_params *params);
1813
1814 /**
1815 * Checks that the requested state transition is legal.
1816 */
1817 int (*check_transition)(struct bxe_softc *sc,
1818 struct ecore_func_sp_obj *o,
1819 struct ecore_func_state_params *params);
1820
1821 /**
1822 * Completes the pending command.
1823 */
1824 int (*complete_cmd)(struct bxe_softc *sc,
1825 struct ecore_func_sp_obj *o,
1826 enum ecore_func_cmd cmd);
1827
1828 int (*wait_comp)(struct bxe_softc *sc, struct ecore_func_sp_obj *o,
1829 enum ecore_func_cmd cmd);
1830 };
1831
1832 /********************** Interfaces ********************************************/
1833 /* Queueable objects set */
1834 union ecore_qable_obj {
1835 struct ecore_vlan_mac_obj vlan_mac;
1836 };
1837 /************** Function state update *********/
1838 void ecore_init_func_obj(struct bxe_softc *sc,
1839 struct ecore_func_sp_obj *obj,
1840 void *rdata, ecore_dma_addr_t rdata_mapping,
1841 void *afex_rdata, ecore_dma_addr_t afex_rdata_mapping,
1842 struct ecore_func_sp_drv_ops *drv_iface);
1843
1844 int ecore_func_state_change(struct bxe_softc *sc,
1845 struct ecore_func_state_params *params);
1846
1847 enum ecore_func_state ecore_func_get_state(struct bxe_softc *sc,
1848 struct ecore_func_sp_obj *o);
1849 /******************* Queue State **************/
1850 void ecore_init_queue_obj(struct bxe_softc *sc,
1851 struct ecore_queue_sp_obj *obj, uint8_t cl_id, uint32_t *cids,
1852 uint8_t cid_cnt, uint8_t func_id, void *rdata,
1853 ecore_dma_addr_t rdata_mapping, unsigned long type);
1854
1855 int ecore_queue_state_change(struct bxe_softc *sc,
1856 struct ecore_queue_state_params *params);
1857
1858 int ecore_get_q_logical_state(struct bxe_softc *sc,
1859 struct ecore_queue_sp_obj *obj);
1860
1861 /********************* VLAN-MAC ****************/
1862 void ecore_init_mac_obj(struct bxe_softc *sc,
1863 struct ecore_vlan_mac_obj *mac_obj,
1864 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata,
1865 ecore_dma_addr_t rdata_mapping, int state,
1866 unsigned long *pstate, ecore_obj_type type,
1867 struct ecore_credit_pool_obj *macs_pool);
1868
1869 void ecore_init_vlan_obj(struct bxe_softc *sc,
1870 struct ecore_vlan_mac_obj *vlan_obj,
1871 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata,
1872 ecore_dma_addr_t rdata_mapping, int state,
1873 unsigned long *pstate, ecore_obj_type type,
1874 struct ecore_credit_pool_obj *vlans_pool);
1875
1876 void ecore_init_vlan_mac_obj(struct bxe_softc *sc,
1877 struct ecore_vlan_mac_obj *vlan_mac_obj,
1878 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata,
1879 ecore_dma_addr_t rdata_mapping, int state,
1880 unsigned long *pstate, ecore_obj_type type,
1881 struct ecore_credit_pool_obj *macs_pool,
1882 struct ecore_credit_pool_obj *vlans_pool);
1883
1884 void ecore_init_vxlan_fltr_obj(struct bxe_softc *sc,
1885 struct ecore_vlan_mac_obj *vlan_mac_obj,
1886 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata,
1887 ecore_dma_addr_t rdata_mapping, int state,
1888 unsigned long *pstate, ecore_obj_type type,
1889 struct ecore_credit_pool_obj *macs_pool,
1890 struct ecore_credit_pool_obj *vlans_pool);
1891
1892 int ecore_vlan_mac_h_read_lock(struct bxe_softc *sc,
1893 struct ecore_vlan_mac_obj *o);
1894 void ecore_vlan_mac_h_read_unlock(struct bxe_softc *sc,
1895 struct ecore_vlan_mac_obj *o);
1896 int ecore_vlan_mac_h_write_lock(struct bxe_softc *sc,
1897 struct ecore_vlan_mac_obj *o);
1898 void ecore_vlan_mac_h_write_unlock(struct bxe_softc *sc,
1899 struct ecore_vlan_mac_obj *o);
1900 int ecore_config_vlan_mac(struct bxe_softc *sc,
1901 struct ecore_vlan_mac_ramrod_params *p);
1902
1903 int ecore_vlan_mac_move(struct bxe_softc *sc,
1904 struct ecore_vlan_mac_ramrod_params *p,
1905 struct ecore_vlan_mac_obj *dest_o);
1906
1907 /********************* RX MODE ****************/
1908
1909 void ecore_init_rx_mode_obj(struct bxe_softc *sc,
1910 struct ecore_rx_mode_obj *o);
1911
1912 /**
1913 * ecore_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters.
1914 *
1915 * @p: Command parameters
1916 *
1917 * Return: 0 - if operation was successful and there is no pending completions,
1918 * positive number - if there are pending completions,
1919 * negative - if there were errors
1920 */
1921 int ecore_config_rx_mode(struct bxe_softc *sc,
1922 struct ecore_rx_mode_ramrod_params *p);
1923
1924 /****************** MULTICASTS ****************/
1925
1926 void ecore_init_mcast_obj(struct bxe_softc *sc,
1927 struct ecore_mcast_obj *mcast_obj,
1928 uint8_t mcast_cl_id, uint32_t mcast_cid, uint8_t func_id,
1929 uint8_t engine_id, void *rdata, ecore_dma_addr_t rdata_mapping,
1930 int state, unsigned long *pstate,
1931 ecore_obj_type type);
1932
1933 /**
1934 * ecore_config_mcast - Configure multicast MACs list.
1935 *
1936 * @cmd: command to execute: BNX2X_MCAST_CMD_X
1937 *
1938 * May configure a new list
1939 * provided in p->mcast_list (ECORE_MCAST_CMD_ADD), clean up
1940 * (ECORE_MCAST_CMD_DEL) or restore (ECORE_MCAST_CMD_RESTORE) a current
1941 * configuration, continue to execute the pending commands
1942 * (ECORE_MCAST_CMD_CONT).
1943 *
1944 * If previous command is still pending or if number of MACs to
1945 * configure is more that maximum number of MACs in one command,
1946 * the current command will be enqueued to the tail of the
1947 * pending commands list.
1948 *
1949 * Return: 0 is operation was successful and there are no pending completions,
1950 * negative if there were errors, positive if there are pending
1951 * completions.
1952 */
1953 int ecore_config_mcast(struct bxe_softc *sc,
1954 struct ecore_mcast_ramrod_params *p,
1955 enum ecore_mcast_cmd cmd);
1956
1957 /****************** CREDIT POOL ****************/
1958 void ecore_init_mac_credit_pool(struct bxe_softc *sc,
1959 struct ecore_credit_pool_obj *p, uint8_t func_id,
1960 uint8_t func_num);
1961 void ecore_init_vlan_credit_pool(struct bxe_softc *sc,
1962 struct ecore_credit_pool_obj *p, uint8_t func_id,
1963 uint8_t func_num);
1964 void ecore_init_credit_pool(struct ecore_credit_pool_obj *p,
1965 int base, int credit);
1966
1967 /****************** RSS CONFIGURATION ****************/
1968 void ecore_init_rss_config_obj(struct bxe_softc *sc,
1969 struct ecore_rss_config_obj *rss_obj,
1970 uint8_t cl_id, uint32_t cid, uint8_t func_id, uint8_t engine_id,
1971 void *rdata, ecore_dma_addr_t rdata_mapping,
1972 int state, unsigned long *pstate,
1973 ecore_obj_type type);
1974
1975 /**
1976 * ecore_config_rss - Updates RSS configuration according to provided parameters
1977 *
1978 * Return: 0 in case of success
1979 */
1980 int ecore_config_rss(struct bxe_softc *sc,
1981 struct ecore_config_rss_params *p);
1982
1983 /**
1984 * ecore_get_rss_ind_table - Return the current ind_table configuration.
1985 *
1986 * @ind_table: buffer to fill with the current indirection
1987 * table content. Should be at least
1988 * T_ETH_INDIRECTION_TABLE_SIZE bytes long.
1989 */
1990 void ecore_get_rss_ind_table(struct ecore_rss_config_obj *rss_obj,
1991 uint8_t *ind_table);
1992
1993 #define PF_MAC_CREDIT_E2(sc, func_num) \
1994 ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(sc) * VF_MAC_CREDIT_CNT) / \
1995 func_num + GET_NUM_VFS_PER_PF(sc) * VF_MAC_CREDIT_CNT)
1996
1997 #define PF_VLAN_CREDIT_E2(sc, func_num) \
1998 ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(sc) * VF_VLAN_CREDIT_CNT) / \
1999 func_num + GET_NUM_VFS_PER_PF(sc) * VF_VLAN_CREDIT_CNT)
2000
2001
2002 #endif /* ECORE_SP_H */
2003
2004