1 /* $NetBSD: grf_cvreg.h,v 1.20 2014/01/22 00:25:16 christos Exp $ */
2
3 /*
4 * Copyright (c) 1995 Michael Teske
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Ezra Story, by Kari
18 * Mettinen and by Bernd Ernesti.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef _GRF_CVREG_H
35 #define _GRF_CVREG_H
36
37 #include <machine/cpu.h>
38
39 /*
40 * This is derived from Cirrus driver source
41 */
42
43 /* Extension to grfvideo_mode to support text modes.
44 * This can be passed to both text & gfx functions
45 * without worry. If gv.depth == 4, then the extended
46 * fields for a text mode are present.
47 */
48
49 struct grfcvtext_mode {
50 struct grfvideo_mode gv;
51 unsigned short fx; /* font x dimension */
52 unsigned short fy; /* font y dimension */
53 unsigned short cols; /* screen dimensions */
54 unsigned short rows;
55 void *fdata; /* font data */
56 unsigned short fdstart;
57 unsigned short fdend;
58 };
59
60
61 /* read VGA register */
62 #define vgar(ba, reg) \
63 (*(((volatile char *)ba)+reg))
64
65 /* write VGA register */
66 #define vgaw(ba, reg, val) \
67 *(((volatile char *)ba)+reg) = ((val) & 0xff); \
68 amiga_membarrier()
69
70 /* read 32 Bit VGA register */
71 #define vgar32(ba, reg) \
72 ( *((volatile unsigned long *) (((volatile char *)ba)+reg)) )
73
74 /* write 32 Bit VGA register */
75 #define vgaw32(ba, reg, val) \
76 *((unsigned long *) (((volatile char *)ba)+reg)) = val; \
77 amiga_membarrier()
78
79 /* read 16 Bit VGA register */
80 #define vgar16(ba, reg) \
81 ( *((volatile unsigned short *) (((volatile char *)ba)+reg)) )
82
83 /* write 16 Bit VGA register */
84 #define vgaw16(ba, reg, val) \
85 *((volatile unsigned short *) (((volatile char *)ba)+reg)) = val; \
86 amiga_membarrier()
87
88 #ifdef _KERNEL
89 int grfcv_cnprobe(void);
90 void grfcv_iteinit(struct grf_softc *);
91 static inline void GfxBusyWait(volatile void *);
92 static inline void GfxFifoWait(volatile void *);
93 static inline unsigned char RAttr(volatile void *, short);
94 static inline unsigned char RSeq(volatile void *, short);
95 static inline unsigned char RCrt(volatile void *, short);
96 static inline unsigned char RGfx(volatile void *, short);
97 #endif
98
99
100 /*
101 * defines for the used register addresses (mw)
102 *
103 * NOTE: there are some registers that have different addresses when
104 * in mono or color mode. We only support color mode, and thus
105 * some addresses won't work in mono-mode!
106 *
107 * General and VGA-registers taken from retina driver. Fixed a few
108 * bugs in it. (SR and GR read address is Port + 1, NOT Port)
109 *
110 */
111
112 /* General Registers: */
113 #define GREG_MISC_OUTPUT_R 0x03CC
114 #define GREG_MISC_OUTPUT_W 0x03C2
115 #define GREG_FEATURE_CONTROL_R 0x03CA
116 #define GREG_FEATURE_CONTROL_W 0x03DA
117 #define GREG_INPUT_STATUS0_R 0x03C2
118 #define GREG_INPUT_STATUS1_R 0x03DA
119
120 /* Setup Registers: */
121 #define SREG_OPTION_SELECT 0x0102
122 #define SREG_VIDEO_SUBS_ENABLE 0x46E8
123
124 /* Attribute Controller: */
125 #define ACT_ADDRESS 0x03C0
126 #define ACT_ADDRESS_R 0x03C1
127 #define ACT_ADDRESS_W 0x03C0
128 #define ACT_ADDRESS_RESET 0x03DA
129 #define ACT_ID_PALETTE0 0x00
130 #define ACT_ID_PALETTE1 0x01
131 #define ACT_ID_PALETTE2 0x02
132 #define ACT_ID_PALETTE3 0x03
133 #define ACT_ID_PALETTE4 0x04
134 #define ACT_ID_PALETTE5 0x05
135 #define ACT_ID_PALETTE6 0x06
136 #define ACT_ID_PALETTE7 0x07
137 #define ACT_ID_PALETTE8 0x08
138 #define ACT_ID_PALETTE9 0x09
139 #define ACT_ID_PALETTE10 0x0A
140 #define ACT_ID_PALETTE11 0x0B
141 #define ACT_ID_PALETTE12 0x0C
142 #define ACT_ID_PALETTE13 0x0D
143 #define ACT_ID_PALETTE14 0x0E
144 #define ACT_ID_PALETTE15 0x0F
145 #define ACT_ID_ATTR_MODE_CNTL 0x10
146 #define ACT_ID_OVERSCAN_COLOR 0x11
147 #define ACT_ID_COLOR_PLANE_ENA 0x12
148 #define ACT_ID_HOR_PEL_PANNING 0x13
149 #define ACT_ID_COLOR_SELECT 0x14
150
151 /* Graphics Controller: */
152 #define GCT_ADDRESS 0x03CE
153 #define GCT_ADDRESS_R 0x03CF
154 #define GCT_ADDRESS_W 0x03CF
155 #define GCT_ID_SET_RESET 0x00
156 #define GCT_ID_ENABLE_SET_RESET 0x01
157 #define GCT_ID_COLOR_COMPARE 0x02
158 #define GCT_ID_DATA_ROTATE 0x03
159 #define GCT_ID_READ_MAP_SELECT 0x04
160 #define GCT_ID_GRAPHICS_MODE 0x05
161 #define GCT_ID_MISC 0x06
162 #define GCT_ID_COLOR_XCARE 0x07
163 #define GCT_ID_BITMASK 0x08
164
165 /* Sequencer: */
166 #define SEQ_ADDRESS 0x03C4
167 #define SEQ_ADDRESS_R 0x03C5
168 #define SEQ_ADDRESS_W 0x03C5
169 #define SEQ_ID_RESET 0x00
170 #define SEQ_ID_CLOCKING_MODE 0x01
171 #define SEQ_ID_MAP_MASK 0x02
172 #define SEQ_ID_CHAR_MAP_SELECT 0x03
173 #define SEQ_ID_MEMORY_MODE 0x04
174 #define SEQ_ID_UNKNOWN1 0x05
175 #define SEQ_ID_UNKNOWN2 0x06
176 #define SEQ_ID_UNKNOWN3 0x07
177 /* S3 extensions */
178 #define SEQ_ID_UNLOCK_EXT 0x08
179 #define SEQ_ID_EXT_SEQ_REG9 0x09
180 #define SEQ_ID_BUS_REQ_CNTL 0x0A
181 #define SEQ_ID_EXT_MISC_SEQ 0x0B
182 #define SEQ_ID_UNKNOWN4 0x0C
183 #define SEQ_ID_EXT_SEQ 0x0D
184 #define SEQ_ID_UNKNOWN5 0x0E
185 #define SEQ_ID_UNKNOWN6 0x0F
186 #define SEQ_ID_MCLK_LO 0x10
187 #define SEQ_ID_MCLK_HI 0x11
188 #define SEQ_ID_DCLK_LO 0x12
189 #define SEQ_ID_DCLK_HI 0x13
190 #define SEQ_ID_CLKSYN_CNTL_1 0x14
191 #define SEQ_ID_CLKSYN_CNTL_2 0x15
192 #define SEQ_ID_CLKSYN_TEST_HI 0x16 /* reserved for S3 testing of the */
193 #define SEQ_ID_CLKSYN_TEST_LO 0x17 /* internal clock synthesizer */
194 #define SEQ_ID_RAMDAC_CNTL 0x18
195 #define SEQ_ID_MORE_MAGIC 0x1A
196
197 /* CRT Controller: */
198 #define CRT_ADDRESS 0x03D4
199 #define CRT_ADDRESS_R 0x03D5
200 #define CRT_ADDRESS_W 0x03D5
201 #define CRT_ID_HOR_TOTAL 0x00
202 #define CRT_ID_HOR_DISP_ENA_END 0x01
203 #define CRT_ID_START_HOR_BLANK 0x02
204 #define CRT_ID_END_HOR_BLANK 0x03
205 #define CRT_ID_START_HOR_RETR 0x04
206 #define CRT_ID_END_HOR_RETR 0x05
207 #define CRT_ID_VER_TOTAL 0x06
208 #define CRT_ID_OVERFLOW 0x07
209 #define CRT_ID_PRESET_ROW_SCAN 0x08
210 #define CRT_ID_MAX_SCAN_LINE 0x09
211 #define CRT_ID_CURSOR_START 0x0A
212 #define CRT_ID_CURSOR_END 0x0B
213 #define CRT_ID_START_ADDR_HIGH 0x0C
214 #define CRT_ID_START_ADDR_LOW 0x0D
215 #define CRT_ID_CURSOR_LOC_HIGH 0x0E
216 #define CRT_ID_CURSOR_LOC_LOW 0x0F
217 #define CRT_ID_START_VER_RETR 0x10
218 #define CRT_ID_END_VER_RETR 0x11
219 #define CRT_ID_VER_DISP_ENA_END 0x12
220 #define CRT_ID_SCREEN_OFFSET 0x13
221 #define CRT_ID_UNDERLINE_LOC 0x14
222 #define CRT_ID_START_VER_BLANK 0x15
223 #define CRT_ID_END_VER_BLANK 0x16
224 #define CRT_ID_MODE_CONTROL 0x17
225 #define CRT_ID_LINE_COMPARE 0x18
226 #define CRT_ID_GD_LATCH_RBACK 0x22
227 #define CRT_ID_ACT_TOGGLE_RBACK 0x24
228 #define CRT_ID_ACT_INDEX_RBACK 0x26
229 /* S3 extensions: S3 VGA Registers */
230 #define CRT_ID_DEVICE_HIGH 0x2D
231 #define CRT_ID_DEVICE_LOW 0x2E
232 #define CRT_ID_REVISION 0x2F
233 #define CRT_ID_CHIP_ID_REV 0x30
234 #define CRT_ID_MEMORY_CONF 0x31
235 #define CRT_ID_BACKWAD_COMP_1 0x32
236 #define CRT_ID_BACKWAD_COMP_2 0x33
237 #define CRT_ID_BACKWAD_COMP_3 0x34
238 #define CRT_ID_REGISTER_LOCK 0x35
239 #define CRT_ID_CONFIG_1 0x36
240 #define CRT_ID_CONFIG_2 0x37
241 #define CRT_ID_REGISTER_LOCK_1 0x38
242 #define CRT_ID_REGISTER_LOCK_2 0x39
243 #define CRT_ID_MISC_1 0x3A
244 #define CRT_ID_DISPLAY_FIFO 0x3B
245 #define CRT_ID_LACE_RETR_START 0x3C
246 /* S3 extensions: System Control Registers */
247 #define CRT_ID_SYSTEM_CONFIG 0x40
248 #define CRT_ID_BIOS_FLAG 0x41
249 #define CRT_ID_LACE_CONTROL 0x42
250 #define CRT_ID_EXT_MODE 0x43
251 #define CRT_ID_HWGC_MODE 0x45 /* HWGC = Hardware Graphics Cursor */
252 #define CRT_ID_HWGC_ORIGIN_X_HI 0x46
253 #define CRT_ID_HWGC_ORIGIN_X_LO 0x47
254 #define CRT_ID_HWGC_ORIGIN_Y_HI 0x48
255 #define CRT_ID_HWGC_ORIGIN_Y_LO 0x49
256 #define CRT_ID_HWGC_FG_STACK 0x4A
257 #define CRT_ID_HWGC_BG_STACK 0x4B
258 #define CRT_ID_HWGC_START_AD_HI 0x4C
259 #define CRT_ID_HWGC_START_AD_LO 0x4D
260 #define CRT_ID_HWGC_DSTART_X 0x4E
261 #define CRT_ID_HWGC_DSTART_Y 0x4F
262 /* S3 extensions: System Extension Registers */
263 #define CRT_ID_EXT_SYS_CNTL_1 0x50
264 #define CRT_ID_EXT_SYS_CNTL_2 0x51
265 #define CRT_ID_EXT_BIOS_FLAG_1 0x52
266 #define CRT_ID_EXT_MEM_CNTL_1 0x53
267 #define CRT_ID_EXT_MEM_CNTL_2 0x54
268 #define CRT_ID_EXT_DAC_CNTL 0x55
269 #define CRT_ID_EX_SYNC_1 0x56
270 #define CRT_ID_EX_SYNC_2 0x57
271 #define CRT_ID_LAW_CNTL 0x58 /* LAW = Linear Address Window */
272 #define CRT_ID_LAW_POS_HI 0x59
273 #define CRT_ID_LAW_POS_LO 0x5A
274 #define CRT_ID_GOUT_PORT 0x5C
275 #define CRT_ID_EXT_HOR_OVF 0x5D
276 #define CRT_ID_EXT_VER_OVF 0x5E
277 #define CRT_ID_EXT_MEM_CNTL_3 0x60
278 #define CRT_ID_EX_SYNC_3 0x63
279 #define CRT_ID_EXT_MISC_CNTL 0x65
280 #define CRT_ID_EXT_MISC_CNTL_1 0x66
281 #define CRT_ID_EXT_MISC_CNTL_2 0x67
282 #define CRT_ID_CONFIG_3 0x68
283 #define CRT_ID_EXT_SYS_CNTL_3 0x69
284 #define CRT_ID_EXT_SYS_CNTL_4 0x6A
285 #define CRT_ID_EXT_BIOS_FLAG_3 0x6B
286 #define CRT_ID_EXT_BIOS_FLAG_4 0x6C
287
288 /* Enhanced Commands Registers: */
289 #define ECR_SUBSYSTEM_STAT 0x42E8
290 #define ECR_SUBSYSTEM_CNTL 0x42E8
291 #define ECR_ADV_FUNC_CNTL 0x4AE8
292 #define ECR_CURRENT_Y_POS 0x82E8
293 #define ECR_CURRENT_Y_POS2 0x82EA /* Trio64 only */
294 #define ECR_CURRENT_X_POS 0x86E8
295 #define ECR_CURRENT_X_POS2 0x86EA /* Trio64 only */
296 #define ECR_DEST_Y__AX_STEP 0x8AE8
297 #define ECR_DEST_Y2__AX_STEP2 0x8AEA /* Trio64 only */
298 #define ECR_DEST_X__DIA_STEP 0x8EE8
299 #define ECR_DEST_X2__DIA_STEP2 0x8EEA /* Trio64 only */
300 #define ECR_ERR_TERM 0x92E8
301 #define ECR_ERR_TERM2 0x92EA /* Trio64 only */
302 #define ECR_MAJ_AXIS_PIX_CNT 0x96E8
303 #define ECR_MAJ_AXIS_PIX_CNT2 0x96EA /* Trio64 only */
304 #define ECR_GP_STAT 0x9AE8 /* GP = Graphics Processor */
305 #define ECR_DRAW_CMD 0x9AE8
306 #define ECR_DRAW_CMD2 0x9AEA /* Trio64 only */
307 #define ECR_SHORT_STROKE 0x9EE8
308 #define ECR_BKGD_COLOR 0xA2E8 /* BKGD = Background */
309 #define ECR_FRGD_COLOR 0xA6E8 /* FRGD = Foreground */
310 #define ECR_BITPLANE_WRITE_MASK 0xAAE8
311 #define ECR_BITPLANE_READ_MASK 0xAEE8
312 #define ECR_COLOR_COMPARE 0xB2E8
313 #define ECR_BKGD_MIX 0xB6E8
314 #define ECR_FRGD_MIX 0xBAE8
315 #define ECR_READ_REG_DATA 0xBEE8
316 #define ECR_ID_MIN_AXIS_PIX_CNT 0x00
317 #define ECR_ID_SCISSORS_TOP 0x01
318 #define ECR_ID_SCISSORS_LEFT 0x02
319 #define ECR_ID_SCISSORS_BUTTOM 0x03
320 #define ECR_ID_SCISSORS_RIGHT 0x04
321 #define ECR_ID_PIX_CNTL 0x0A
322 #define ECR_ID_MULT_CNTL_MISC_2 0x0D
323 #define ECR_ID_MULT_CNTL_MISC 0x0E
324 #define ECR_ID_READ_SEL 0x0F
325 #define ECR_PIX_TRANS 0xE2E8
326 #define ECR_PIX_TRANS_EXT 0xE2EA
327 #define ECR_PATTERN_Y 0xEAE8 /* Trio64 only */
328 #define ECR_PATTERN_X 0xEAEA /* Trio64 only */
329
330
331 /* Pass-through */
332 #define PASS_ADDRESS 0x40001
333 #define PASS_ADDRESS_W 0x40001
334
335 /* Video DAC */
336 #define VDAC_ADDRESS 0x03c8
337 #define VDAC_ADDRESS_W 0x03c8
338 #define VDAC_ADDRESS_R 0x03c7
339 #define VDAC_STATE 0x03c7
340 #define VDAC_DATA 0x03c9
341 #define VDAC_MASK 0x03c6
342
343
344 #define WGfx(ba, idx, val) \
345 do { vgaw(ba, GCT_ADDRESS, idx); vgaw(ba, GCT_ADDRESS_W , val); } while (0)
346
347 #define WSeq(ba, idx, val) \
348 do { vgaw(ba, SEQ_ADDRESS, idx); vgaw(ba, SEQ_ADDRESS_W , val); } while (0)
349
350 #define WCrt(ba, idx, val) \
351 do { vgaw(ba, CRT_ADDRESS, idx); vgaw(ba, CRT_ADDRESS_W , val); } while (0)
352
353 #define WAttr(ba, idx, val) \
354 do { \
355 unsigned char tmp;\
356 tmp = vgar(ba, ACT_ADDRESS_RESET);\
357 __USE(tmp);\
358 vgaw(ba, ACT_ADDRESS_W, idx);\
359 vgaw(ba, ACT_ADDRESS_W, val);\
360 } while (0)
361
362
363 #define SetTextPlane(ba, m) \
364 do { \
365 WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 );\
366 WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3)));\
367 } while (0)
368
369
370 /* Gfx engine busy wait */
371 #ifdef _KERNEL
372 static inline void
GfxBusyWait(volatile void * ba)373 GfxBusyWait (volatile void *ba)
374 {
375 int test;
376
377 do {
378 test = vgar16 (ba, ECR_GP_STAT);
379 amiga_cpu_sync();
380 } while (test & (1 << 9));
381 }
382
383
384 static inline void
GfxFifoWait(volatile void * ba)385 GfxFifoWait(volatile void *ba)
386 {
387 int test;
388
389 do {
390 test = vgar16 (ba, ECR_GP_STAT);
391 } while (test & 0x0f);
392 }
393
394
395 /* Special wakeup/passthrough registers on graphics boards
396 *
397 * The methods have diverged a bit for each board, so
398 * WPass(P) has been converted into a set of specific
399 * inline functions.
400 */
401
402 static inline unsigned char
RAttr(volatile void * ba,short idx)403 RAttr(volatile void *ba, short idx)
404 {
405
406 vgaw(ba, ACT_ADDRESS_W, idx);
407 delay(0);
408 return vgar(ba, ACT_ADDRESS_R);
409 }
410
411 static inline unsigned char
RSeq(volatile void * ba,short idx)412 RSeq(volatile void *ba, short idx)
413 {
414 vgaw(ba, SEQ_ADDRESS, idx);
415 return vgar(ba, SEQ_ADDRESS_R);
416 }
417
418 static inline unsigned char
RCrt(volatile void * ba,short idx)419 RCrt(volatile void *ba, short idx)
420 {
421 vgaw(ba, CRT_ADDRESS, idx);
422 return vgar(ba, CRT_ADDRESS_R);
423 }
424
425 static inline unsigned char
RGfx(volatile void * ba,short idx)426 RGfx(volatile void *ba, short idx)
427 {
428 vgaw(ba, GCT_ADDRESS, idx);
429 return vgar(ba, GCT_ADDRESS_R);
430 }
431 #endif
432
433 #endif /* _GRF_CVREG_H */
434