1 /* $OpenBSD: if_stgereg.h,v 1.11 2009/08/10 19:41:05 deraadt Exp $ */ 2 /* $NetBSD: if_stgereg.h,v 1.3 2003/02/10 21:10:07 christos Exp $ */ 3 4 /*- 5 * Copyright (c) 2001 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _DEV_PCI_IF_STGEREG_H_ 34 #define _DEV_PCI_IF_STGEREG_H_ 35 36 /* 37 * Register description for the Sundance Tech. TC9021 10/100/1000 38 * Ethernet controller. 39 * 40 * Note that while DMA addresses are all in 64-bit fields, only 41 * the lower 40 bits of a DMA address are valid. 42 */ 43 44 /* 45 * Register access macros 46 */ 47 #define CSR_WRITE_4(_sc, reg, val) \ 48 bus_space_write_4((_sc)->sc_st, (_sc)->sc_sh, (reg), (val)) 49 #define CSR_WRITE_2(_sc, reg, val) \ 50 bus_space_write_2((_sc)->sc_st, (_sc)->sc_sh, (reg), (val)) 51 #define CSR_WRITE_1(_sc, reg, val) \ 52 bus_space_write_1((_sc)->sc_st, (_sc)->sc_sh, (reg), (val)) 53 54 #define CSR_READ_4(_sc, reg) \ 55 bus_space_read_4((_sc)->sc_st, (_sc)->sc_sh, (reg)) 56 #define CSR_READ_2(_sc, reg) \ 57 bus_space_read_2((_sc)->sc_st, (_sc)->sc_sh, (reg)) 58 #define CSR_READ_1(_sc, reg) \ 59 bus_space_read_1((_sc)->sc_st, (_sc)->sc_sh, (reg)) 60 61 /* 62 * TC9021 buffer fragment descriptor. 63 */ 64 struct stge_frag { 65 uint64_t frag_word0; /* address, length */ 66 } __packed; 67 68 #define FRAG_ADDR(x) (((uint64_t)(x)) << 0) 69 #define FRAG_ADDR_MASK FRAG_ADDR(0xfffffffffULL) 70 #define FRAG_LEN(x) (((uint64_t)(x)) << 48) 71 #define FRAG_LEN_MASK FRAG_LEN(0xffffULL) 72 73 /* 74 * TC9021 Transmit Frame Descriptor. Note the number of fragments 75 * here is arbitrary, but we can't have any more than 15. 76 */ 77 #define STGE_NTXFRAGS 12 78 struct stge_tfd { 79 uint64_t tfd_next; /* next TFD in list */ 80 uint64_t tfd_control; /* control bits */ 81 /* the buffer fragments */ 82 struct stge_frag tfd_frags[STGE_NTXFRAGS]; 83 } __packed; 84 85 #define TFD_FrameId(x) ((x) << 0) 86 #define TFD_FrameId_MAX 0xffff 87 #define TFD_WordAlign(x) ((x) << 16) 88 #define TFD_WordAlign_dword 0 /* align to dword in TxFIFO */ 89 #define TFD_WordAlign_word 2 /* align to word in TxFIFO */ 90 #define TFD_WordAlign_disable 1 /* disable alignment */ 91 #define TFD_TCPChecksumEnable (1ULL << 18) 92 #define TFD_UDPChecksumEnable (1ULL << 19) 93 #define TFD_IPChecksumEnable (1ULL << 20) 94 #define TFD_FcsAppendDisable (1ULL << 21) 95 #define TFD_TxIndicate (1ULL << 22) 96 #define TFD_TxDMAIndicate (1ULL << 23) 97 #define TFD_FragCount(x) ((x) << 24) 98 #define TFD_VLANTagInsert (1ULL << 28) 99 #define TFD_TFDDone (1ULL << 31) 100 #define TFD_VID(x) (((uint64_t)(x)) << 32) 101 #define TFD_CFI (1ULL << 44) 102 #define TFD_UserPriority(x) (((uint64_t)(x)) << 45) 103 104 /* 105 * TC9021 Receive Frame Descriptor. Each RFD has a single fragment 106 * in it, and the chip tells us the beginning and end of the frame. 107 */ 108 struct stge_rfd { 109 uint64_t rfd_next; /* next RFD in list */ 110 uint64_t rfd_status; /* status bits */ 111 struct stge_frag rfd_frag; /* the buffer */ 112 } __packed; 113 114 #define RFD_RxDMAFrameLen(x) ((x) & 0xffff) 115 #define RFD_RxFIFOOverrun (1ULL << 16) 116 #define RFD_RxRuntFrame (1ULL << 17) 117 #define RFD_RxAlignmentError (1ULL << 18) 118 #define RFD_RxFCSError (1ULL << 19) 119 #define RFD_RxOversizedFrame (1ULL << 20) 120 #define RFD_RxLengthError (1ULL << 21) 121 #define RFD_VLANDetected (1ULL << 22) 122 #define RFD_TCPDetected (1ULL << 23) 123 #define RFD_TCPError (1ULL << 24) 124 #define RFD_UDPDetected (1ULL << 25) 125 #define RFD_UDPError (1ULL << 26) 126 #define RFD_IPDetected (1ULL << 27) 127 #define RFD_IPError (1ULL << 28) 128 #define RFD_FrameStart (1ULL << 29) 129 #define RFD_FrameEnd (1ULL << 30) 130 #define RFD_RFDDone (1ULL << 31) 131 #define RFD_TCI(x) ((((uint64_t)(x)) >> 32) & 0xffff) 132 133 /* 134 * PCI configuration registers used by the TC9021. 135 */ 136 137 #define STGE_PCI_IOBA (PCI_MAPREG_START + 0x00) 138 #define STGE_PCI_MMBA (PCI_MAPREG_START + 0x04) 139 140 /* 141 * EEPROM offsets. 142 */ 143 #define STGE_EEPROM_ConfigParam 0x00 144 #define STGE_EEPROM_AsicCtrl 0x01 145 #define STGE_EEPROM_SubSystemVendorId 0x02 146 #define STGE_EEPROM_SubSystemId 0x03 147 #define STGE_EEPROM_StationAddress0 0x10 148 #define STGE_EEPROM_StationAddress1 0x11 149 #define STGE_EEPROM_StationAddress2 0x12 150 151 /* 152 * The TC9021 register space. 153 */ 154 155 #define STGE_DMACtrl 0x00 156 #define DMAC_RxDMAComplete (1U << 3) 157 #define DMAC_RxDMAPollNow (1U << 4) 158 #define DMAC_TxDMAComplete (1U << 11) 159 #define DMAC_TxDMAPollNow (1U << 12) 160 #define DMAC_TxDMAInProg (1U << 15) 161 #define DMAC_RxEarlyDisable (1U << 16) 162 #define DMAC_MWIDisable (1U << 18) 163 #define DMAC_TxWiteBackDisable (1U << 19) 164 #define DMAC_TxBurstLimit(x) ((x) << 20) 165 #define DMAC_TargetAbort (1U << 30) 166 #define DMAC_MasterAbort (1U << 31) 167 168 #define STGE_RxDMAStatus 0x08 169 170 #define STGE_TFDListPtrLo 0x10 171 172 #define STGE_TFDListPtrHi 0x14 173 174 #define STGE_TxDMABurstThresh 0x18 /* 8-bit */ 175 176 #define STGE_TxDMAUrgentThresh 0x19 /* 8-bit */ 177 178 #define STGE_TxDMAPollPeriod 0x1a /* 8-bit */ 179 180 #define STGE_RFDListPtrLo 0x1c 181 182 #define STGE_RFDListPtrHi 0x20 183 184 #define STGE_RxDMABurstThresh 0x24 /* 8-bit */ 185 186 #define STGE_RxDMAUrgentThresh 0x25 /* 8-bit */ 187 188 #define STGE_RxDMAPollPeriod 0x26 /* 8-bit */ 189 190 #define STGE_RxDMAIntCtrl 0x28 191 #define RDIC_RxFrameCount(x) ((x) & 0xff) 192 #define RDIC_PriorityThresh(x) ((x) << 10) 193 #define RDIC_RxDMAWaitTime(x) ((x) << 16) 194 195 #define STGE_DebugCtrl 0x2c /* 16-bit */ 196 #define DC_GPIO0Ctrl (1U << 0) 197 #define DC_GPIO1Ctrl (1U << 1) 198 #define DC_GPIO0 (1U << 2) 199 #define DC_GPIO1 (1U << 3) 200 201 #define STGE_AsicCtrl 0x30 202 #define AC_ExpRomDisable (1U << 0) 203 #define AC_ExpRomSize (1U << 1) 204 #define AC_PhySpeed10 (1U << 4) 205 #define AC_PhySpeed100 (1U << 5) 206 #define AC_PhySpeed1000 (1U << 6) 207 #define AC_PhyMedia (1U << 7) 208 #define AC_ForcedConfig(x) ((x) << 8) 209 #define AC_ForcedConfig_MASK AC_ForcedConfig(7) 210 #define AC_D3ResetDisable (1U << 11) 211 #define AC_SpeedupMode (1U << 13) 212 #define AC_LEDMode (1U << 14) 213 #define AC_RstOutPolarity (1U << 15) 214 #define AC_GlobalReset (1U << 16) 215 #define AC_RxReset (1U << 17) 216 #define AC_TxReset (1U << 18) 217 #define AC_DMA (1U << 19) 218 #define AC_FIFO (1U << 20) 219 #define AC_Network (1U << 21) 220 #define AC_Host (1U << 22) 221 #define AC_AutoInit (1U << 23) 222 #define AC_RstOut (1U << 24) 223 #define AC_InterruptRequest (1U << 25) 224 #define AC_ResetBusy (1U << 26) 225 226 #define STGE_FIFOCtrl 0x38 /* 16-bit */ 227 #define FC_RAMTestMode (1U << 0) 228 #define FC_Transmitting (1U << 14) 229 #define FC_Receiving (1U << 15) 230 231 #define STGE_RxEarlyThresh 0x3a /* 16-bit */ 232 233 #define STGE_FlowOffThresh 0x3c /* 16-bit */ 234 235 #define STGE_FlowOnTresh 0x3e /* 16-bit */ 236 237 #define STGE_TxStartThresh 0x44 /* 16-bit */ 238 239 #define STGE_EepromData 0x48 /* 16-bit */ 240 241 #define STGE_EepromCtrl 0x4a /* 16-bit */ 242 #define EC_EepromAddress(x) ((x) & 0xff) 243 #define EC_EepromOpcode(x) ((x) << 8) 244 #define EC_OP_WE 0 245 #define EC_OP_WR 1 246 #define EC_OP_RR 2 247 #define EC_OP_ER 3 248 #define EC_EepromBusy (1U << 15) 249 250 #define STGE_ExpRomAddr 0x4c 251 252 #define STGE_ExpRomData 0x50 /* 8-bit */ 253 254 #define STGE_WakeEvent 0x51 /* 8-bit */ 255 256 #define STGE_Countdown 0x54 257 #define CD_Count(x) ((x) & 0xffff) 258 #define CD_CountdownSpeed (1U << 24) 259 #define CD_CountdownMode (1U << 25) 260 #define CD_CountdownIntEnabled (1U << 26) 261 262 #define STGE_IntStatusAck 0x5a /* 16-bit */ 263 264 #define STGE_IntStatus 0x5e /* 16-bit */ 265 266 #define STGE_IntEnable 0x5c /* 16-bit */ 267 268 #define IS_InterruptStatus (1U << 0) 269 #define IS_HostError (1U << 1) 270 #define IS_TxComplete (1U << 2) 271 #define IS_MACControlFrame (1U << 3) 272 #define IS_RxComplete (1U << 4) 273 #define IS_RxEarly (1U << 5) 274 #define IS_InRequested (1U << 6) 275 #define IS_UpdateStats (1U << 7) 276 #define IS_LinkEvent (1U << 8) 277 #define IS_TxDMAComplete (1U << 9) 278 #define IS_RxDMAComplete (1U << 10) 279 #define IS_RFDListEnd (1U << 11) 280 #define IS_RxDMAPriority (1U << 12) 281 282 #define STGE_TxStatus 0x60 283 #define TS_TxError (1U << 0) 284 #define TS_LateCollision (1U << 2) 285 #define TS_MaxCollisions (1U << 3) 286 #define TS_TxUnderrun (1U << 4) 287 #define TS_TxIndicateReqd (1U << 6) 288 #define TS_TxComplete (1U << 7) 289 #define TS_TxFrameId_get(x) ((x) >> 16) 290 291 #define STGE_MACCtrl 0x6c 292 #define MC_IFSSelect(x) ((x) & 3) 293 #define MC_DuplexSelect (1U << 5) 294 #define MC_RcvLargeFrames (1U << 6) 295 #define MC_TxFlowControlEnable (1U << 7) 296 #define MC_RxFlowControlEnable (1U << 8) 297 #define MC_RcvFCS (1U << 9) 298 #define MC_FIFOLoopback (1U << 10) 299 #define MC_MACLoopback (1U << 11) 300 #define MC_AutoVLANtagging (1U << 12) 301 #define MC_AutoVLANuntagging (1U << 13) 302 #define MC_CollisionDetect (1U << 16) 303 #define MC_CarrierSense (1U << 17) 304 #define MC_StatisticsEnable (1U << 21) 305 #define MC_StatisticsDisable (1U << 22) 306 #define MC_StatisticsEnabled (1U << 23) 307 #define MC_TxEnable (1U << 24) 308 #define MC_TxDisable (1U << 25) 309 #define MC_TxEnabled (1U << 26) 310 #define MC_RxEnable (1U << 27) 311 #define MC_RxDisable (1U << 28) 312 #define MC_RxEnabled (1U << 29) 313 #define MC_Paused (1U << 30) 314 315 #define STGE_VLANTag 0x70 316 317 #define STGE_PhyCtrl 0x76 /* 8-bit */ 318 #define PC_MgmtClk (1U << 0) 319 #define PC_MgmtData (1U << 1) 320 #define PC_MgmtDir (1U << 2) /* MAC->PHY */ 321 #define PC_PhyDuplexPolarity (1U << 3) 322 #define PC_PhyDuplexStatus (1U << 4) 323 #define PC_PhyLnkPolarity (1U << 5) 324 #define PC_LinkSpeed(x) (((x) >> 6) & 3) 325 #define PC_LinkSpeed_Down 0 326 #define PC_LinkSpeed_10 1 327 #define PC_LinkSpeed_100 2 328 #define PC_LinkSpeed_1000 3 329 330 #define STGE_StationAddress0 0x78 /* 16-bit */ 331 332 #define STGE_StationAddress1 0x7a /* 16-bit */ 333 334 #define STGE_StationAddress2 0x7c /* 16-bit */ 335 336 #define STGE_VLANHashTable 0x7e /* 16-bit */ 337 338 #define STGE_VLANId 0x80 339 340 #define STGE_MaxFrameSize 0x86 341 342 #define STGE_ReceiveMode 0x88 /* 16-bit */ 343 #define RM_ReceiveUnicast (1U << 0) 344 #define RM_ReceiveMulticast (1U << 1) 345 #define RM_ReceiveBroadcast (1U << 2) 346 #define RM_ReceiveAllFrames (1U << 3) 347 #define RM_ReceiveMulticastHash (1U << 4) 348 #define RM_ReceiveIPMulticast (1U << 5) 349 #define RM_ReceiveVLANMatch (1U << 8) 350 #define RM_ReceiveVLANHash (1U << 9) 351 352 #define STGE_HashTable0 0x8c 353 354 #define STGE_HashTable1 0x90 355 356 #define STGE_RMONStatisticsMask 0x98 /* set to disable */ 357 358 #define STGE_StatisticsMask 0x9c /* set to disable */ 359 360 #define STGE_RxJumboFrames 0xbc /* 16-bit */ 361 362 #define STGE_TCPCheckSumErrors 0xc0 /* 16-bit */ 363 364 #define STGE_IPCheckSumErrors 0xc2 /* 16-bit */ 365 366 #define STGE_UDPCheckSumErrors 0xc4 /* 16-bit */ 367 368 #define STGE_TxJumboFrames 0xf4 /* 16-bit */ 369 370 /* 371 * TC9021 statistics. Available memory and I/O mapped. 372 */ 373 374 #define STGE_OctetRcvOk 0xa8 375 376 #define STGE_McstOctetRcvdOk 0xac 377 378 #define STGE_BcstOctetRcvdOk 0xb0 379 380 #define STGE_FramesRcvdOk 0xb4 381 382 #define STGE_McstFramesRcvdOk 0xb8 383 384 #define STGE_BcstFramesRcvdOk 0xbe /* 16-bit */ 385 386 #define STGE_MacControlFramesRcvd 0xc6 /* 16-bit */ 387 388 #define STGE_FrameTooLongErrors 0xc8 /* 16-bit */ 389 390 #define STGE_InRangeLengthErrors 0xca /* 16-bit */ 391 392 #define STGE_FramesCheckSeqErrors 0xcc /* 16-bit */ 393 394 #define STGE_FramesLostRxErrors 0xce /* 16-bit */ 395 396 #define STGE_OctetXmtdOk 0xd0 397 398 #define STGE_McstOctetXmtdOk 0xd4 399 400 #define STGE_BcstOctetXmtdOk 0xd8 401 402 #define STGE_FramesXmtdOk 0xdc 403 404 #define STGE_McstFramesXmtdOk 0xe0 405 406 #define STGE_FramesWDeferredXmt 0xe4 407 408 #define STGE_LateCollisions 0xe8 409 410 #define STGE_MultiColFrames 0xec 411 412 #define STGE_SingleColFrames 0xf0 413 414 #define STGE_BcstFramesXmtdOk 0xf6 /* 16-bit */ 415 416 #define STGE_CarrierSenseErrors 0xf8 /* 16-bit */ 417 418 #define STGE_MacControlFramesXmtd 0xfa /* 16-bit */ 419 420 #define STGE_FramesAbortXSColls 0xfc /* 16-bit */ 421 422 #define STGE_FramesWEXDeferal 0xfe /* 16-bit */ 423 424 /* 425 * RMON-compatible statistics. Only accessible if memory-mapped. 426 */ 427 428 #define STGE_EtherStatsCollisions 0x100 429 430 #define STGE_EtherStatsOctetsTransmit 0x104 431 432 #define STGE_EtherStatsPktsTransmit 0x108 433 434 #define STGE_EtherStatsPkts64OctetsTransmit 0x10c 435 436 #define STGE_EtherStatsPkts64to127OctetsTransmit 0x110 437 438 #define STGE_EtherStatsPkts128to255OctetsTransmit 0x114 439 440 #define STGE_EtherStatsPkts256to511OctetsTransmit 0x118 441 442 #define STGE_EtherStatsPkts512to1023OctetsTransmit 0x11c 443 444 #define STGE_EtherStatsPkts1024to1518OctetsTransmit 0x120 445 446 #define STGE_EtherStatsCRCAlignErrors 0x124 447 448 #define STGE_EtherStatsUndersizePkts 0x128 449 450 #define STGE_EtherStatsFragments 0x12c 451 452 #define STGE_EtherStatsJabbers 0x130 453 454 #define STGE_EtherStatsOctets 0x134 455 456 #define STGE_EtherStatsPkts 0x138 457 458 #define STGE_EtherStatsPkts64Octets 0x13c 459 460 #define STGE_EtherStatsPkts65to127Octets 0x140 461 462 #define STGE_EtherStatsPkts128to255Octets 0x144 463 464 #define STGE_EtherStatsPkts256to511Octets 0x148 465 466 #define STGE_EtherStatsPkts512to1023Octets 0x14c 467 468 #define STGE_EtherStatsPkts1024to1518Octets 0x150 469 470 /* 471 * Transmit descriptor list size. 472 */ 473 #define STGE_NTXDESC 256 474 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) 475 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) 476 477 /* 478 * Receive descriptor list size. 479 */ 480 #define STGE_NRXDESC 256 481 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1) 482 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK) 483 484 /* 485 * Only interrupt every N frames. Must be a power-of-two. 486 */ 487 #define STGE_TXINTR_SPACING 16 488 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) 489 490 #define STGE_JUMBO_FRAMELEN 9022 491 #define STGE_JUMBO_MTU \ 492 (STGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 493 494 /* 495 * Control structures are DMA'd to the TC9021 chip. We allocate them in 496 * a single clump that maps to a single DMA segment to make several things 497 * easier. 498 */ 499 struct stge_control_data { 500 /* 501 * The transmit descriptors. 502 */ 503 struct stge_tfd scd_txdescs[STGE_NTXDESC]; 504 505 /* 506 * The receive descriptors. 507 */ 508 struct stge_rfd scd_rxdescs[STGE_NRXDESC]; 509 }; 510 511 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x) 512 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)]) 513 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)]) 514 515 /* 516 * Software state for transmit and receive jobs. 517 */ 518 struct stge_descsoft { 519 struct mbuf *ds_mbuf; /* head of our mbuf chain */ 520 bus_dmamap_t ds_dmamap; /* our DMA map */ 521 }; 522 523 /* 524 * Software state per device. 525 */ 526 struct stge_softc { 527 struct device sc_dev; /* generic device information */ 528 bus_space_tag_t sc_st; /* bus space tag */ 529 bus_space_handle_t sc_sh; /* bus space handle */ 530 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 531 struct arpcom sc_arpcom; /* ethernet common data */ 532 int sc_rev; /* silicon revision */ 533 void *sc_ih; /* interrupt cookie */ 534 535 struct mii_data sc_mii; /* MII/media information */ 536 537 struct timeout sc_timeout; /* tick timeout */ 538 539 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 540 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 541 542 /* 543 * Software state for transmit and receive descriptors. 544 */ 545 struct stge_descsoft sc_txsoft[STGE_NTXDESC]; 546 struct stge_descsoft sc_rxsoft[STGE_NRXDESC]; 547 548 /* 549 * Control data structures. 550 */ 551 struct stge_control_data *sc_control_data; 552 #define sc_txdescs sc_control_data->scd_txdescs 553 #define sc_rxdescs sc_control_data->scd_rxdescs 554 555 int sc_txpending; /* number of Tx requests pending */ 556 int sc_txdirty; /* first dirty Tx descriptor */ 557 int sc_txlast; /* last used Tx descriptor */ 558 559 int sc_rxptr; /* next ready Rx descriptor/descsoft */ 560 int sc_rxdiscard; 561 int sc_rxlen; 562 struct mbuf *sc_rxhead; 563 struct mbuf *sc_rxtail; 564 struct mbuf **sc_rxtailp; 565 566 int sc_txthresh; /* Tx threshold */ 567 uint32_t sc_usefiber:1; /* if we're fiber */ 568 uint32_t sc_stge1023:1; /* are we a 1023 */ 569 uint32_t sc_DMACtrl; /* prototype DMACtrl register */ 570 uint32_t sc_MACCtrl; /* prototype MacCtrl register */ 571 uint16_t sc_IntEnable; /* prototype IntEnable register */ 572 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */ 573 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */ 574 }; 575 576 #define STGE_RXCHAIN_RESET(sc) \ 577 do { \ 578 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \ 579 *(sc)->sc_rxtailp = NULL; \ 580 (sc)->sc_rxlen = 0; \ 581 } while (/*CONSTCOND*/0) 582 583 #define STGE_RXCHAIN_LINK(sc, m) \ 584 do { \ 585 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ 586 (sc)->sc_rxtailp = &(m)->m_next; \ 587 } while (/*CONSTCOND*/0) 588 589 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x))) 590 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x))) 591 592 #define STGE_CDTXSYNC(sc, x, ops) \ 593 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 594 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops)) 595 596 #define STGE_CDRXSYNC(sc, x, ops) \ 597 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 598 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops)) 599 600 #define STGE_INIT_RXDESC(sc, x) \ 601 do { \ 602 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \ 603 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \ 604 \ 605 /* \ 606 * Note: We scoot the packet forward 2 bytes in the buffer \ 607 * so that the payload after the Ethernet header is aligned \ 608 * to a 4-byte boundary. \ 609 */ \ 610 __rfd->rfd_frag.frag_word0 = \ 611 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\ 612 FRAG_LEN(MCLBYTES - 2)); \ 613 __rfd->rfd_next = \ 614 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \ 615 __rfd->rfd_status = 0; \ 616 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 617 } while (/*CONSTCOND*/0) 618 619 #define STGE_TIMEOUT 1000 620 621 #endif /* _DEV_PCI_IF_STGEREG_H_ */ 622