1 /* $OpenBSD: if_exreg.h,v 1.4 2009/05/23 15:35:10 jsg Exp $ */ 2 /* 3 * Copyright (c) 1996, Javier Mart�n Rueda (jmrueda@diatel.upm.es) 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Intel EtherExpress Pro/10 Ethernet driver 31 */ 32 33 /* 34 * Several constants. 35 */ 36 37 /* Default RAM size in board. */ 38 #define CARD_RAM_SIZE 0x8000 39 /* Number of I/O ports used. */ 40 #define EX_IOSIZE 16 41 42 /* 43 * Intel EtherExpress Pro (i82595 based) registers 44 */ 45 46 /* Common registers to all banks. */ 47 48 #define CMD_REG 0 49 #define REG1 1 50 #define REG2 2 51 #define REG3 3 52 #define REG4 4 53 #define REG5 5 54 #define REG6 6 55 #define REG7 7 56 #define REG8 8 57 #define REG9 9 58 #define REG10 10 59 #define REG11 11 60 #define REG12 12 61 #define REG13 13 62 #define REG14 14 63 #define REG15 15 64 65 /* Definitions for command register (CMD_REG). */ 66 67 #define Switch_Bank_CMD 0 68 #define MC_Setup_CMD 3 69 #define Transmit_CMD 4 70 #define Diagnose_CMD 7 71 #define Rcv_Enable_CMD 8 72 #define Rcv_Stop 11 73 #define Reset_CMD 14 74 #define Resume_XMT_List_CMD 28 75 #define Sel_Reset_CMD 30 76 #define Abort 0x20 77 #define Bank0_Sel 0x00 78 #define Bank1_Sel 0x40 79 #define Bank2_Sel 0x80 80 81 /* Bank 0 specific registers. */ 82 83 #define STATUS_REG 1 84 #define ID_REG 2 85 #define Id_Mask 0x2c 86 #define Id_Sig 0x24 87 #define Counter_bits 0xc0 88 #define MASK_REG 3 89 #define Exec_Int 0x08 90 #define Tx_Int 0x04 91 #define Rx_Int 0x02 92 #define Rx_Stp_Int 0x01 93 #define All_Int 0x0f 94 #define RCV_BAR 4 95 #define RCV_BAR_Lo 4 96 #define RCV_BAR_Hi 5 97 #define RCV_STOP_REG 6 98 #define XMT_BAR 10 99 #define HOST_ADDR_REG 12 /* 16-bit register */ 100 #define IO_PORT_REG 14 /* 16-bit register */ 101 102 /* Bank 1 specific registers. */ 103 104 #define TriST_INT 0x80 105 #define INT_NO_REG 2 106 #define RCV_LOWER_LIMIT_REG 8 107 #define RCV_UPPER_LIMIT_REG 9 108 #define XMT_LOWER_LIMIT_REG 10 109 #define XMT_UPPER_LIMIT_REG 11 110 111 /* Bank 2 specific registers. */ 112 113 #define Disc_Bad_Fr 0x80 114 #define Tx_Chn_ErStp 0x40 115 #define Tx_Chn_Int_Md 0x20 116 #define Multi_IA 0x20 117 #define No_SA_Ins 0x10 118 #define RX_CRC_InMem 0x04 119 #define Promisc_Mode 0x01 120 #define BNC_bit 0x20 121 #define TPE_bit 0x04 122 #define I_ADDR_REG0 4 123 #define EEPROM_REG 10 124 #define Trnoff_Enable 0x10 125 126 /* EEPROM memory positions (16-bit wide). */ 127 128 #define EE_W0 0x00 129 # define EE_W0_PNP 0x0001 130 # define EE_W0_BUS16 0x0004 131 # define EE_W0_FLASH_ADDR_MASK 0x0038 132 # define EE_W0_FLASH_ADDR_SHIFT 3 133 # define EE_W0_AUTO_IO 0x0040 134 # define EE_W0_FLASH 0x0100 135 # define EE_W0_AUTO_NEG 0x0200 136 # define EE_W0_IO_MASK 0xFC00 137 # define EE_W0_IO_SHIFT 10 138 139 #define EE_IRQ_No 1 140 #define IRQ_No_Mask 0x07 141 142 #define EE_W1 0x01 143 # define EE_W1_INT_SEL 0x0007 144 # define EE_W1_NO_LINK_INT 0x0008 /* Link Integrity Off */ 145 # define EE_W1_NO_POLARITY 0x0010 /* Polarity Correction Off */ 146 # define EE_W1_TPE_AUI 0x0020 /* 1 = TPE, 0 = AUI */ 147 # define EE_W1_NO_JABBER_PREV 0x0040 /* Jabber prevention Off */ 148 # define EE_W1_NO_AUTO_SELECT 0x0080 /* Auto Port Selection Off */ 149 # define EE_W1_SMOUT 0x0100 /* SMout Pin Control 0= Input */ 150 # define EE_W1_PROM 0x0200 /* Flash = 0, PROM = 1 */ 151 # define EE_W1_ALT_READY 0x2000 /* Alternate Ready, 0=normal */ 152 # define EE_W1_FULL_DUPLEX 0x8000 153 154 #define EE_W2 0x02 155 #define EE_W3 0x03 156 #define EE_W4 0x04 157 158 #define EE_Eth_Addr_Lo 2 159 #define EE_Eth_Addr_Mid 3 160 #define EE_Eth_Addr_Hi 4 161 162 #define EE_W5 0x05 163 # define EE_W5_BNC_TPE 0x0001 /* 0 = TPE, 1 = BNC */ 164 # define EE_W5_BOOT_IPX 0x0002 165 # define EE_W5_BOOT_ODI 0x0004 166 # define EE_W5_BOOT_NDIS (EE_W5_BOOT_IPX|EE_W5_BOOT_ODI) 167 # define EE_W5_NUM_CONN 0x0008 /* 0 = 2, 1 = 3 */ 168 # define EE_W5_NOFLASH 0x0010 /* No flash socket present */ 169 # define EE_W5_PORT_TPE 0x0020 /* TPE present */ 170 # define EE_W5_PORT_BNC 0x0040 /* BNC present */ 171 # define EE_W5_PORT_AUI 0x0080 /* AUI present */ 172 # define EE_W5_PWR_MGT 0x0100 /* Power Management */ 173 # define EE_W5_CP 0x0200 /* COncurrent Processing */ 174 175 #define EE_W6 0x05 176 # define EE_W6_STEP_MASK 0x000F 177 # define EE_W6_BOARD_MASK 0xF 178 179 /* EEPROM serial interface. */ 180 181 #define EESK 0x01 182 #define EECS 0x02 183 #define EEDI 0x04 184 #define EEDO 0x08 185 #define EE_READ_CMD (6 << 6) 186 187 /* Frame chain constants. */ 188 189 /* Transmit header length (in board's ring buffer). */ 190 #define XMT_HEADER_LEN 8 191 #define XMT_Chain_Point 4 192 #define XMT_Byte_Count 6 193 #define Done_bit 0x0080 194 #define Ch_bit 0x8000 195 /* Transmit result bits. */ 196 #define No_Collisions_bits 0x000f 197 #define TX_OK_bit 0x2000 198 /* Receive result bits. */ 199 #define RCV_Done 8 200 #define RCV_OK_bit 0x2000 201