xref: /openbsd/sys/dev/pci/ixgb_ee.h (revision f2ce9f98)
1 /*******************************************************************************
2 
3   Copyright (c) 2001-2005, Intel Corporation
4   All rights reserved.
5 
6   Redistribution and use in source and binary forms, with or without
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9    1. Redistributions of source code must retain the above copyright notice,
10       this list of conditions and the following disclaimer.
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12    2. Redistributions in binary form must reproduce the above copyright
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14       documentation and/or other materials provided with the distribution.
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16    3. Neither the name of the Intel Corporation nor the names of its
17       contributors may be used to endorse or promote products derived from
18       this software without specific prior written permission.
19 
20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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31 
32 *******************************************************************************/
33 
34 /* $OpenBSD: ixgb_ee.h,v 1.1 2005/11/14 23:25:43 brad Exp $ */
35 
36 #ifndef _IXGB_EE_H_
37 #define _IXGB_EE_H_
38 
39 #define IXGB_EEPROM_SIZE    64		    /* Size in words */
40 
41 #define IXGB_ETH_LENGTH_OF_ADDRESS   6
42 
43 /* EEPROM Commands */
44 #define EEPROM_READ_OPCODE  0x6		    /* EEPROM read opcode */
45 #define EEPROM_WRITE_OPCODE 0x5		    /* EEPROM write opcode */
46 #define EEPROM_ERASE_OPCODE 0x7		    /* EEPROM erase opcode */
47 #define EEPROM_EWEN_OPCODE  0x13	    /* EEPROM erase/write enable */
48 #define EEPROM_EWDS_OPCODE  0x10	    /* EEPROM erase/write disable */
49 
50 /* EEPROM MAP (Word Offsets) */
51 #define EEPROM_IA_1_2_REG        0x0000
52 #define EEPROM_IA_3_4_REG        0x0001
53 #define EEPROM_IA_5_6_REG        0x0002
54 #define EEPROM_COMPATIBILITY_REG 0x0003
55 #define EEPROM_PBA_1_2_REG       0x0008
56 #define EEPROM_PBA_3_4_REG       0x0009
57 #define EEPROM_INIT_CONTROL1_REG 0x000A
58 #define EEPROM_SUBSYS_ID_REG     0x000B
59 #define EEPROM_SUBVEND_ID_REG    0x000C
60 #define EEPROM_DEVICE_ID_REG     0x000D
61 #define EEPROM_VENDOR_ID_REG     0x000E
62 #define EEPROM_INIT_CONTROL2_REG 0x000F
63 #define EEPROM_SWDPINS_REG       0x0020
64 #define EEPROM_CIRCUIT_CTRL_REG  0x0021
65 #define EEPROM_D0_D3_POWER_REG   0x0022
66 #define EEPROM_FLASH_VERSION     0x0032
67 #define EEPROM_CHECKSUM_REG      0x003F
68 
69 /* Mask bits for fields in Word 0x0a of the EEPROM */
70 
71 #define EEPROM_ICW1_SIGNATURE_MASK  0xC000
72 #define EEPROM_ICW1_SIGNATURE_VALID 0x4000
73 #define EEPROM_ICW1_SIGNATURE_CLEAR 0x0000
74 
75 /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
76 #define EEPROM_SUM 0xBABA
77 
78 /* EEPROM Map Sizes (Byte Counts) */
79 #define PBA_SIZE 4
80 
81 /* EEPROM Map defines (WORD OFFSETS)*/
82 
83 /* EEPROM structure */
84 struct ixgb_ee_map_type {
85 	uint8_t  mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS];
86 	uint16_t compatibility;
87 	uint16_t reserved1[4];
88 	uint32_t pba_number;
89 	uint16_t init_ctrl_reg_1;
90 	uint16_t subsystem_id;
91 	uint16_t subvendor_id;
92 	uint16_t device_id;
93 	uint16_t vendor_id;
94 	uint16_t init_ctrl_reg_2;
95 	uint16_t oem_reserved[16];
96 	uint16_t swdpins_reg;
97 	uint16_t circuit_ctrl_reg;
98 	uint8_t  d3_power;
99 	uint8_t  d0_power;
100 	uint16_t reserved2[28];
101 	uint16_t checksum;
102 };
103 
104 /* EEPROM Functions */
105 uint16_t ixgb_read_eeprom(struct ixgb_hw *hw, uint16_t reg);
106 
107 boolean_t ixgb_validate_eeprom_checksum(struct ixgb_hw *hw);
108 
109 void ixgb_update_eeprom_checksum(struct ixgb_hw *hw);
110 
111 void ixgb_write_eeprom(struct ixgb_hw *hw, uint16_t reg, uint16_t data);
112 
113 #endif /* IXGB_EE_H */
114